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gerrit-public.fairphone.software / kernel / msm-5.4 / 80ea2c129c76a4159a93efeaef4385b6c964dfac / . / drivers / gpu / drm / radeon / sumo_dpm.h
blob: 561bee16039a5086cb8fbf2b0400ef101d6ecf9a [file] [log] [blame]
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame^]1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __SUMO_DPM_H__
24#define __SUMO_DPM_H__
25
26#define SUMO_MAX_HARDWARE_POWERLEVELS 5
27#define SUMO_PM_NUMBER_OF_TC 15
28
29struct sumo_pl {
30 u32 sclk;
31 u32 vddc_index;
32 u32 ds_divider_index;
33 u32 ss_divider_index;
34 u32 allow_gnb_slow;
35 u32 sclk_dpm_tdp_limit;
36};
37
38/* used for the flags field */
39#define SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE (1 << 0)
40#define SUMO_POWERSTATE_FLAGS_BOOST_STATE (1 << 1)
41
42struct sumo_ps {
43 struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
44 u32 num_levels;
45 /* flags */
46 u32 flags;
47};
48
49#define NUMBER_OF_M3ARB_PARAM_SETS 10
50#define SUMO_MAX_NUMBER_VOLTAGES 4
51
52struct sumo_disp_clock_voltage_mapping_table {
53 u32 num_max_voltage_levels;
54 u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES];
55};
56
57struct sumo_vid_mapping_entry {
58 u16 vid_2bit;
59 u16 vid_7bit;
60};
61
62struct sumo_vid_mapping_table {
63 u32 num_entries;
64 struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES];
65};
66
67struct sumo_sclk_voltage_mapping_entry {
68 u32 sclk_frequency;
69 u16 vid_2bit;
70 u16 rsv;
71};
72
73struct sumo_sclk_voltage_mapping_table {
74 u32 num_max_dpm_entries;
75 struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];
76};
77
78struct sumo_sys_info {
79 u32 bootup_sclk;
80 u32 min_sclk;
81 u32 bootup_uma_clk;
82 u16 bootup_nb_voltage_index;
83 u8 htc_tmp_lmt;
84 u8 htc_hyst_lmt;
85 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
86 struct sumo_disp_clock_voltage_mapping_table disp_clk_voltage_mapping_table;
87 struct sumo_vid_mapping_table vid_mapping_table;
88 u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];
89 u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];
90 u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];
91 u32 sclk_dpm_boost_margin;
92 u32 sclk_dpm_throttle_margin;
93 u32 sclk_dpm_tdp_limit_pg;
94 u32 gnb_tdp_limit;
95 u32 sclk_dpm_tdp_limit_boost;
96 u32 boost_sclk;
97 u32 boost_vid_2bit;
98 bool enable_boost;
99};
100
101struct sumo_power_info {
102 u32 asi;
103 u32 pasi;
104 u32 bsp;
105 u32 bsu;
106 u32 pbsp;
107 u32 pbsu;
108 u32 dsp;
109 u32 psp;
110 u32 thermal_auto_throttling;
111 u32 uvd_m3_arbiter;
112 u32 fw_version;
113 struct sumo_sys_info sys_info;
114 struct sumo_pl acpi_pl;
115 struct sumo_pl boot_pl;
116 struct sumo_pl boost_pl;
117 struct sumo_ps current_ps;
118 bool disable_gfx_power_gating_in_uvd;
119 bool driver_nbps_policy_disable;
120 bool enable_alt_vddnb;
121 bool enable_dynamic_m3_arbiter;
122 bool enable_gfx_clock_gating;
123 bool enable_gfx_power_gating;
124 bool enable_mg_clock_gating;
125 bool enable_sclk_ds;
126 bool enable_auto_thermal_throttling;
127 bool enable_dynamic_patch_ps;
128 bool enable_dpm;
129 bool enable_boost;
130};
131
132#define SUMO_UTC_DFLT_00 0x48
133#define SUMO_UTC_DFLT_01 0x44
134#define SUMO_UTC_DFLT_02 0x44
135#define SUMO_UTC_DFLT_03 0x44
136#define SUMO_UTC_DFLT_04 0x44
137#define SUMO_UTC_DFLT_05 0x44
138#define SUMO_UTC_DFLT_06 0x44
139#define SUMO_UTC_DFLT_07 0x44
140#define SUMO_UTC_DFLT_08 0x44
141#define SUMO_UTC_DFLT_09 0x44
142#define SUMO_UTC_DFLT_10 0x44
143#define SUMO_UTC_DFLT_11 0x44
144#define SUMO_UTC_DFLT_12 0x44
145#define SUMO_UTC_DFLT_13 0x44
146#define SUMO_UTC_DFLT_14 0x44
147
148#define SUMO_DTC_DFLT_00 0x48
149#define SUMO_DTC_DFLT_01 0x44
150#define SUMO_DTC_DFLT_02 0x44
151#define SUMO_DTC_DFLT_03 0x44
152#define SUMO_DTC_DFLT_04 0x44
153#define SUMO_DTC_DFLT_05 0x44
154#define SUMO_DTC_DFLT_06 0x44
155#define SUMO_DTC_DFLT_07 0x44
156#define SUMO_DTC_DFLT_08 0x44
157#define SUMO_DTC_DFLT_09 0x44
158#define SUMO_DTC_DFLT_10 0x44
159#define SUMO_DTC_DFLT_11 0x44
160#define SUMO_DTC_DFLT_12 0x44
161#define SUMO_DTC_DFLT_13 0x44
162#define SUMO_DTC_DFLT_14 0x44
163
164#define SUMO_AH_DFLT 5
165
166#define SUMO_R_DFLT0 70
167#define SUMO_R_DFLT1 70
168#define SUMO_R_DFLT2 70
169#define SUMO_R_DFLT3 70
170#define SUMO_R_DFLT4 100
171
172#define SUMO_L_DFLT0 0
173#define SUMO_L_DFLT1 20
174#define SUMO_L_DFLT2 20
175#define SUMO_L_DFLT3 20
176#define SUMO_L_DFLT4 20
177#define SUMO_VRC_DFLT 0x30033
178#define SUMO_MGCGTTLOCAL0_DFLT 0
179#define SUMO_MGCGTTLOCAL1_DFLT 0
180#define SUMO_GICST_DFLT 19
181#define SUMO_SST_DFLT 8
182#define SUMO_VOLTAGEDROPT_DFLT 1
183#define SUMO_GFXPOWERGATINGT_DFLT 100
184
185/* sumo_dpm.c */
186u32 sumo_get_xclk(struct radeon_device *rdev);
187
188
189/* sumo_smc.c */
190void sumo_initialize_m3_arb(struct radeon_device *rdev);
191void sumo_smu_pg_init(struct radeon_device *rdev);
192void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit);
193void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev,
194 bool powersaving, bool force_nbps1);
195void sumo_boost_state_enable(struct radeon_device *rdev, bool enable);
196void sumo_enable_boost_timer(struct radeon_device *rdev);
197u32 sumo_get_running_fw_version(struct radeon_device *rdev);
198
199#endif