| Philipp Zabel | 61fc413 | 2012-11-19 17:23:13 +0100 | [diff] [blame] | 1 | config ARCH_HAS_RESET_CONTROLLER |
| 2 | bool |
| 3 | |
| 4 | menuconfig RESET_CONTROLLER |
| 5 | bool "Reset Controller Support" |
| 6 | default y if ARCH_HAS_RESET_CONTROLLER |
| 7 | help |
| 8 | Generic Reset Controller support. |
| 9 | |
| 10 | This framework is designed to abstract reset handling of devices |
| 11 | via GPIOs or SoC-internal reset controller modules. |
| 12 | |
| 13 | If unsure, say no. |
| Stephen Gallimore | e5d7607 | 2013-08-07 15:53:12 +0100 | [diff] [blame] | 14 | |
| Masahiro Yamada | 998cd46 | 2016-05-03 15:29:52 +0900 | [diff] [blame] | 15 | if RESET_CONTROLLER |
| 16 | |
| Thor Thayer | 6270068 | 2017-02-22 11:10:17 -0600 | [diff] [blame] | 17 | config RESET_A10SR |
| 18 | tristate "Altera Arria10 System Resource Reset" |
| 19 | depends on MFD_ALTERA_A10SR |
| 20 | help |
| 21 | This option enables support for the external reset functions for |
| 22 | peripheral PHYs on the Altera Arria10 System Resource Chip. |
| 23 | |
| Philipp Zabel | e27b4a6 | 2016-07-28 15:30:08 +0200 | [diff] [blame] | 24 | config RESET_ATH79 |
| 25 | bool "AR71xx Reset Driver" if COMPILE_TEST |
| 26 | default ATH79 |
| 27 | help |
| 28 | This enables the ATH79 reset controller driver that supports the |
| 29 | AR71xx SoC reset controller. |
| 30 | |
| Philipp Zabel | 70d467e | 2016-07-28 15:31:12 +0200 | [diff] [blame] | 31 | config RESET_BERLIN |
| 32 | bool "Berlin Reset Driver" if COMPILE_TEST |
| 33 | default ARCH_BERLIN |
| 34 | help |
| 35 | This enables the reset controller driver for Marvell Berlin SoCs. |
| 36 | |
| Vineet Gupta | 1354122 | 2017-08-31 11:06:07 -0700 | [diff] [blame] | 37 | config RESET_HSDK |
| 38 | bool "Synopsys HSDK Reset Driver" |
| Thomas Meyer | 2d48a23 | 2017-09-09 06:02:46 +0200 | [diff] [blame] | 39 | depends on HAS_IOMEM |
| Geert Uytterhoeven | 544e3bf | 2017-09-11 14:22:08 +0200 | [diff] [blame] | 40 | depends on ARC_SOC_HSDK || COMPILE_TEST |
| Eugeniy Paltsev | e0be864 | 2017-07-19 21:45:11 +0300 | [diff] [blame] | 41 | help |
| Vineet Gupta | 1354122 | 2017-08-31 11:06:07 -0700 | [diff] [blame] | 42 | This enables the reset controller driver for HSDK board. |
| Eugeniy Paltsev | e0be864 | 2017-07-19 21:45:11 +0300 | [diff] [blame] | 43 | |
| Andrey Smirnov | abf9775 | 2017-02-21 08:13:31 -0800 | [diff] [blame] | 44 | config RESET_IMX7 |
| 45 | bool "i.MX7 Reset Driver" if COMPILE_TEST |
| 46 | default SOC_IMX7D |
| 47 | select MFD_SYSCON |
| 48 | help |
| 49 | This enables the reset controller driver for i.MX7 SoCs. |
| 50 | |
| Martin Blumenstingl | 79797b6 | 2017-08-20 00:18:17 +0200 | [diff] [blame] | 51 | config RESET_LANTIQ |
| 52 | bool "Lantiq XWAY Reset Driver" if COMPILE_TEST |
| 53 | default SOC_TYPE_XWAY |
| 54 | help |
| 55 | This enables the reset controller driver for Lantiq / Intel XWAY SoCs. |
| 56 | |
| Philipp Zabel | cd7f4b8 | 2016-07-28 15:32:01 +0200 | [diff] [blame] | 57 | config RESET_LPC18XX |
| 58 | bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST |
| 59 | default ARCH_LPC18XX |
| 60 | help |
| 61 | This enables the reset controller driver for NXP LPC18xx/43xx SoCs. |
| 62 | |
| Philipp Zabel | 44336c2 | 2016-07-28 15:32:36 +0200 | [diff] [blame] | 63 | config RESET_MESON |
| 64 | bool "Meson Reset Driver" if COMPILE_TEST |
| 65 | default ARCH_MESON |
| 66 | help |
| 67 | This enables the reset driver for Amlogic Meson SoCs. |
| 68 | |
| Neil Armstrong | 6e667fa | 2016-04-01 16:16:13 +0200 | [diff] [blame] | 69 | config RESET_OXNAS |
| 70 | bool |
| 71 | |
| Philipp Zabel | fab3f73 | 2016-07-28 15:33:07 +0200 | [diff] [blame] | 72 | config RESET_PISTACHIO |
| 73 | bool "Pistachio Reset Driver" if COMPILE_TEST |
| 74 | default MACH_PISTACHIO |
| 75 | help |
| 76 | This enables the reset driver for ImgTec Pistachio SoCs. |
| 77 | |
| Philipp Zabel | 81c22ad | 2017-08-11 12:58:43 +0200 | [diff] [blame^] | 78 | config RESET_SIMPLE |
| 79 | bool "Simple Reset Controller Driver" if COMPILE_TEST |
| 80 | default ARCH_SUNXI |
| 81 | help |
| 82 | This enables a simple reset controller driver for reset lines that |
| 83 | that can be asserted and deasserted by toggling bits in a contiguous, |
| 84 | exclusive register space. |
| 85 | |
| 86 | Currently this driver supports Allwinner SoCs. |
| 87 | |
| Philipp Zabel | 5c91407 | 2016-07-28 15:33:43 +0200 | [diff] [blame] | 88 | config RESET_SOCFPGA |
| 89 | bool "SoCFPGA Reset Driver" if COMPILE_TEST |
| Dinh Nguyen | db21f9c | 2017-09-20 10:25:41 -0500 | [diff] [blame] | 90 | default ARCH_SOCFPGA || ARCH_STRATIX10 |
| Philipp Zabel | 5c91407 | 2016-07-28 15:33:43 +0200 | [diff] [blame] | 91 | help |
| 92 | This enables the reset controller driver for Altera SoCFPGAs. |
| 93 | |
| Philipp Zabel | 7e0e901 | 2016-07-28 15:34:15 +0200 | [diff] [blame] | 94 | config RESET_STM32 |
| 95 | bool "STM32 Reset Driver" if COMPILE_TEST |
| 96 | default ARCH_STM32 |
| 97 | help |
| 98 | This enables the RCC reset controller driver for STM32 MCUs. |
| 99 | |
| Philipp Zabel | 0ae0841 | 2016-08-09 09:28:44 +0200 | [diff] [blame] | 100 | config RESET_SUNXI |
| 101 | bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI |
| 102 | default ARCH_SUNXI |
| 103 | help |
| 104 | This enables the reset driver for Allwinner SoCs. |
| 105 | |
| Andrew F. Davis | 28df169 | 2017-05-24 13:09:30 -0500 | [diff] [blame] | 106 | config RESET_TI_SCI |
| 107 | tristate "TI System Control Interface (TI-SCI) reset driver" |
| 108 | depends on TI_SCI_PROTOCOL |
| 109 | help |
| 110 | This enables the reset driver support over TI System Control Interface |
| 111 | available on some new TI's SoCs. If you wish to use reset resources |
| 112 | managed by the TI System Controller, say Y here. Otherwise, say N. |
| 113 | |
| Suman Anna | dd9bf86 | 2017-05-23 22:00:12 -0500 | [diff] [blame] | 114 | config RESET_TI_SYSCON |
| Andrew F. Davis | cc7c2bb | 2016-06-27 12:12:17 -0500 | [diff] [blame] | 115 | tristate "TI SYSCON Reset Driver" |
| 116 | depends on HAS_IOMEM |
| 117 | select MFD_SYSCON |
| 118 | help |
| 119 | This enables the reset driver support for TI devices with |
| 120 | memory-mapped reset registers as part of a syscon device node. If |
| 121 | you wish to use the reset framework for such memory-mapped devices, |
| 122 | say Y here. Otherwise, say N. |
| 123 | |
| Masahiro Yamada | 54e991b | 2016-08-02 13:18:29 +0900 | [diff] [blame] | 124 | config RESET_UNIPHIER |
| 125 | tristate "Reset controller driver for UniPhier SoCs" |
| 126 | depends on ARCH_UNIPHIER || COMPILE_TEST |
| 127 | depends on OF && MFD_SYSCON |
| 128 | default ARCH_UNIPHIER |
| 129 | help |
| 130 | Support for reset controllers on UniPhier SoCs. |
| 131 | Say Y if you want to control reset signals provided by System Control |
| 132 | block, Media I/O block, Peripheral Block. |
| 133 | |
| Baoyou Xie | b38386f | 2017-01-17 11:22:57 +0800 | [diff] [blame] | 134 | config RESET_ZX2967 |
| 135 | bool "ZTE ZX2967 Reset Driver" |
| 136 | depends on ARCH_ZX || COMPILE_TEST |
| 137 | help |
| 138 | This enables the reset controller driver for ZTE's zx2967 family. |
| 139 | |
| Philipp Zabel | 6f51b86 | 2016-08-09 09:28:54 +0200 | [diff] [blame] | 140 | config RESET_ZYNQ |
| 141 | bool "ZYNQ Reset Driver" if COMPILE_TEST |
| 142 | default ARCH_ZYNQ |
| 143 | help |
| 144 | This enables the reset controller driver for Xilinx Zynq SoCs. |
| 145 | |
| Stephen Gallimore | e5d7607 | 2013-08-07 15:53:12 +0100 | [diff] [blame] | 146 | source "drivers/reset/sti/Kconfig" |
| Chen Feng | f59d23c | 2015-11-20 10:10:05 +0800 | [diff] [blame] | 147 | source "drivers/reset/hisilicon/Kconfig" |
| Thierry Reding | dc606c5 | 2016-08-18 15:50:09 +0200 | [diff] [blame] | 148 | source "drivers/reset/tegra/Kconfig" |
| Masahiro Yamada | 998cd46 | 2016-05-03 15:29:52 +0900 | [diff] [blame] | 149 | |
| 150 | endif |