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gerrit-public.fairphone.software / kernel / msm-5.4 / 81ee8fb6b52ec69eeed37fe7943446af1dccecc5 / . / drivers / gpu / drm / radeon / radeon_asic.h
blob: 0d445e7d00d1f00a3249846806906437eb188473 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +0100[diff] [blame]36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
45/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]46 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]47 */
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]48struct r100_mc_save {
49 u32 GENMO_WT;
50 u32 CRTC_EXT_CNTL;
51 u32 CRTC_GEN_CNTL;
52 u32 CRTC2_GEN_CNTL;
53 u32 CUR_OFFSET;
54 u32 CUR2_OFFSET;
55};
56int r100_init(struct radeon_device *rdev);
57void r100_fini(struct radeon_device *rdev);
58int r100_suspend(struct radeon_device *rdev);
59int r100_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]60void r100_vga_set_state(struct radeon_device *rdev, bool state);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]61bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]62int r100_asic_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]63u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]64void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
65int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]66void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]67int r100_irq_set(struct radeon_device *rdev);
68int r100_irq_process(struct radeon_device *rdev);
69void r100_fence_ring_emit(struct radeon_device *rdev,
70 struct radeon_fence *fence);
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]71void r100_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]72 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]73 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]74 bool emit_wait);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]75int r100_cs_parse(struct radeon_cs_parser *p);
76void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
77uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
78int r100_copy_blit(struct radeon_device *rdev,
79 uint64_t src_offset,
80 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]81 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]82 struct radeon_fence **fence);
Dave Airliee024e112009-06-24 09:48:08 +1000[diff] [blame]83int r100_set_surface_reg(struct radeon_device *rdev, int reg,
84 uint32_t tiling_flags, uint32_t pitch,
85 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]86void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]87void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]88void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]89int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]90void r100_hpd_init(struct radeon_device *rdev);
91void r100_hpd_fini(struct radeon_device *rdev);
92bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
93void r100_hpd_set_polarity(struct radeon_device *rdev,
94 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]95int r100_debugfs_rbbm_init(struct radeon_device *rdev);
96int r100_debugfs_cp_init(struct radeon_device *rdev);
97void r100_cp_disable(struct radeon_device *rdev);
98int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
99void r100_cp_fini(struct radeon_device *rdev);
100int r100_pci_gart_init(struct radeon_device *rdev);
101void r100_pci_gart_fini(struct radeon_device *rdev);
102int r100_pci_gart_enable(struct radeon_device *rdev);
103void r100_pci_gart_disable(struct radeon_device *rdev);
104int r100_debugfs_mc_info_init(struct radeon_device *rdev);
105int r100_gui_wait_for_idle(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]106int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]107void r100_irq_disable(struct radeon_device *rdev);
108void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
109void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
110void r100_vram_init_sizes(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]111int r100_cp_reset(struct radeon_device *rdev);
112void r100_vga_render_disable(struct radeon_device *rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000[diff] [blame]113void r100_restore_sanity(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]114int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
115 struct radeon_cs_packet *pkt,
116 struct radeon_bo *robj);
117int r100_cs_parse_packet0(struct radeon_cs_parser *p,
118 struct radeon_cs_packet *pkt,
119 const unsigned *auth, unsigned n,
120 radeon_packet0_check_t check);
121int r100_cs_packet_parse(struct radeon_cs_parser *p,
122 struct radeon_cs_packet *pkt,
123 unsigned idx);
124void r100_enable_bm(struct radeon_device *rdev);
125void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]126void r100_bm_disable(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]127extern bool r100_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]128extern void r100_pm_misc(struct radeon_device *rdev);
129extern void r100_pm_prepare(struct radeon_device *rdev);
130extern void r100_pm_finish(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]131extern void r100_pm_init_profile(struct radeon_device *rdev);
132extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]133extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
134extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
135extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]136extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]137extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucherbae6b5622010-04-22 13:38:05 -0400[diff] [blame]138
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]139/*
140 * r200,rv250,rs300,rv280
141 */
142extern int r200_copy_dma(struct radeon_device *rdev,
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]143 uint64_t src_offset,
144 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]145 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]146 struct radeon_fence **fence);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]147void r200_set_safe_registers(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]148
149/*
150 * r300,r350,rv350,rv380
151 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]152extern int r300_init(struct radeon_device *rdev);
153extern void r300_fini(struct radeon_device *rdev);
154extern int r300_suspend(struct radeon_device *rdev);
155extern int r300_resume(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]156extern int r300_asic_reset(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]157extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]158extern void r300_fence_ring_emit(struct radeon_device *rdev,
159 struct radeon_fence *fence);
160extern int r300_cs_parse(struct radeon_cs_parser *p);
161extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
162extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]163extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500[diff] [blame]164extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]165extern void r300_set_reg_safe(struct radeon_device *rdev);
166extern void r300_mc_program(struct radeon_device *rdev);
167extern void r300_mc_init(struct radeon_device *rdev);
168extern void r300_clock_startup(struct radeon_device *rdev);
169extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
170extern int rv370_pcie_gart_init(struct radeon_device *rdev);
171extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
172extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
173extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]174extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]175
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]176/*
177 * r420,r423,rv410
178 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200[diff] [blame]179extern int r420_init(struct radeon_device *rdev);
180extern void r420_fini(struct radeon_device *rdev);
181extern int r420_suspend(struct radeon_device *rdev);
182extern int r420_resume(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]183extern void r420_pm_init_profile(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]184extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
185extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
186extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
187extern void r420_pipes_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]188
189/*
190 * rs400,rs480
191 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200[diff] [blame]192extern int rs400_init(struct radeon_device *rdev);
193extern void rs400_fini(struct radeon_device *rdev);
194extern int rs400_suspend(struct radeon_device *rdev);
195extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]196void rs400_gart_tlb_flush(struct radeon_device *rdev);
197int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
198uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
199void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]200int rs400_gart_init(struct radeon_device *rdev);
201int rs400_gart_enable(struct radeon_device *rdev);
202void rs400_gart_adjust_size(struct radeon_device *rdev);
203void rs400_gart_disable(struct radeon_device *rdev);
204void rs400_gart_fini(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]205extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]206
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]207/*
208 * rs600.
209 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]210extern int rs600_asic_reset(struct radeon_device *rdev);
Jerome Glissec010f802009-09-30 22:09:06 +0200[diff] [blame]211extern int rs600_init(struct radeon_device *rdev);
212extern void rs600_fini(struct radeon_device *rdev);
213extern int rs600_suspend(struct radeon_device *rdev);
214extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]215int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]216int rs600_irq_process(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]217void rs600_irq_disable(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]218u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]219void rs600_gart_tlb_flush(struct radeon_device *rdev);
220int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
221uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
222void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]223void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]224void rs600_hpd_init(struct radeon_device *rdev);
225void rs600_hpd_fini(struct radeon_device *rdev);
226bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
227void rs600_hpd_set_polarity(struct radeon_device *rdev,
228 enum radeon_hpd_id hpd);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]229extern void rs600_pm_misc(struct radeon_device *rdev);
230extern void rs600_pm_prepare(struct radeon_device *rdev);
231extern void rs600_pm_finish(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]232extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
233extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
234extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]235void rs600_set_safe_registers(struct radeon_device *rdev);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]236extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]237extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]238
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]239/*
240 * rs690,rs740
241 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200[diff] [blame]242int rs690_init(struct radeon_device *rdev);
243void rs690_fini(struct radeon_device *rdev);
244int rs690_resume(struct radeon_device *rdev);
245int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]246uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
247void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]248void rs690_bandwidth_update(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]249void rs690_line_buffer_adjust(struct radeon_device *rdev,
250 struct drm_display_mode *mode1,
251 struct drm_display_mode *mode2);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]252extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]253
254/*
255 * rv515
256 */
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]257struct rv515_mc_save {
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]258 u32 vga_render_control;
259 u32 vga_hdp_control;
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]260};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame^]261
Jerome Glisse068a1172009-06-17 13:28:30 +0200[diff] [blame]262int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]263void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]264uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
265void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]266void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]267void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]268int rv515_resume(struct radeon_device *rdev);
269int rv515_suspend(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]270void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
271void rv515_vga_render_disable(struct radeon_device *rdev);
272void rv515_set_safe_registers(struct radeon_device *rdev);
273void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
274void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
275void rv515_clock_startup(struct radeon_device *rdev);
276void rv515_debugfs(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]277int rv515_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]278
279/*
280 * r520,rv530,rv560,rv570,r580
281 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]282int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200[diff] [blame]283int r520_resume(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]284int r520_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]285
286/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]287 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]288 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]289int r600_init(struct radeon_device *rdev);
290void r600_fini(struct radeon_device *rdev);
291int r600_suspend(struct radeon_device *rdev);
292int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]293void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]294int r600_wb_init(struct radeon_device *rdev);
295void r600_wb_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]296void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]297uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
298void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]299int r600_cs_parse(struct radeon_cs_parser *p);
300void r600_fence_ring_emit(struct radeon_device *rdev,
301 struct radeon_fence *fence);
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]302void r600_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]303 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]304 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]305 bool emit_wait);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]306bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]307int r600_asic_reset(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]308int r600_set_surface_reg(struct radeon_device *rdev, int reg,
309 uint32_t tiling_flags, uint32_t pitch,
310 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]311void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]312int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]313void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]314int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]315int r600_copy_blit(struct radeon_device *rdev,
316 uint64_t src_offset, uint64_t dst_offset,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]317 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]318void r600_hpd_init(struct radeon_device *rdev);
319void r600_hpd_fini(struct radeon_device *rdev);
320bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
321void r600_hpd_set_polarity(struct radeon_device *rdev,
322 enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]323extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]324extern bool r600_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]325extern void r600_pm_misc(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]326extern void r600_pm_init_profile(struct radeon_device *rdev);
327extern void rs780_pm_init_profile(struct radeon_device *rdev);
328extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]329extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
330extern int r600_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]331bool r600_card_posted(struct radeon_device *rdev);
332void r600_cp_stop(struct radeon_device *rdev);
333int r600_cp_start(struct radeon_device *rdev);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]334void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]335int r600_cp_resume(struct radeon_device *rdev);
336void r600_cp_fini(struct radeon_device *rdev);
337int r600_count_pipe_bits(uint32_t val);
338int r600_mc_wait_for_idle(struct radeon_device *rdev);
339int r600_pcie_gart_init(struct radeon_device *rdev);
340void r600_scratch_init(struct radeon_device *rdev);
341int r600_blit_init(struct radeon_device *rdev);
342void r600_blit_fini(struct radeon_device *rdev);
343int r600_init_microcode(struct radeon_device *rdev);
344/* r600 irq */
345int r600_irq_process(struct radeon_device *rdev);
346int r600_irq_init(struct radeon_device *rdev);
347void r600_irq_fini(struct radeon_device *rdev);
348void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
349int r600_irq_set(struct radeon_device *rdev);
350void r600_irq_suspend(struct radeon_device *rdev);
351void r600_disable_interrupts(struct radeon_device *rdev);
352void r600_rlc_stop(struct radeon_device *rdev);
353/* r600 audio */
354int r600_audio_init(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]355void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
Rafał Miłecki3299de92012-05-14 21:25:57 +0200[diff] [blame]356struct r600_audio r600_audio_status(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]357void r600_audio_fini(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]358int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
359void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]360/* r600 blit */
Christian Königf2377502012-05-09 15:35:01 +0200[diff] [blame]361int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
Christian König220907d2012-05-10 16:46:43 +0200[diff] [blame]362 struct radeon_fence **fence, struct radeon_sa_bo **vb,
363 struct radeon_semaphore **sem);
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]364void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
Christian König220907d2012-05-10 16:46:43 +0200[diff] [blame]365 struct radeon_sa_bo *vb, struct radeon_semaphore *sem);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]366void r600_kms_blit_copy(struct radeon_device *rdev,
367 u64 src_gpu_addr, u64 dst_gpu_addr,
Christian Königf2377502012-05-09 15:35:01 +0200[diff] [blame]368 unsigned num_gpu_pages,
369 struct radeon_sa_bo *vb);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]370int r600_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]371
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]372/*
373 * rv770,rv730,rv710,rv740
374 */
375int rv770_init(struct radeon_device *rdev);
376void rv770_fini(struct radeon_device *rdev);
377int rv770_suspend(struct radeon_device *rdev);
378int rv770_resume(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]379void rv770_pm_misc(struct radeon_device *rdev);
380u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
381void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
382void r700_cp_stop(struct radeon_device *rdev);
383void r700_cp_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]384
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]385/*
386 * evergreen
387 */
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]388struct evergreen_mc_save {
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]389 u32 vga_render_control;
390 u32 vga_hdp_control;
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]391};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame^]392
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]393void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]394int evergreen_init(struct radeon_device *rdev);
395void evergreen_fini(struct radeon_device *rdev);
396int evergreen_suspend(struct radeon_device *rdev);
397int evergreen_resume(struct radeon_device *rdev);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]398bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]399int evergreen_asic_reset(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]400void evergreen_bandwidth_update(struct radeon_device *rdev);
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]401void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]402void evergreen_hpd_init(struct radeon_device *rdev);
403void evergreen_hpd_fini(struct radeon_device *rdev);
404bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
405void evergreen_hpd_set_polarity(struct radeon_device *rdev,
406 enum radeon_hpd_id hpd);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]407u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
408int evergreen_irq_set(struct radeon_device *rdev);
409int evergreen_irq_process(struct radeon_device *rdev);
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]410extern int evergreen_cs_parse(struct radeon_cs_parser *p);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]411extern void evergreen_pm_misc(struct radeon_device *rdev);
412extern void evergreen_pm_prepare(struct radeon_device *rdev);
413extern void evergreen_pm_finish(struct radeon_device *rdev);
Alex Deuchera4c9e2e2011-11-04 10:09:41 -0400[diff] [blame]414extern void sumo_pm_init_profile(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]415extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
416extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
417extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]418extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]419void evergreen_disable_interrupt_state(struct radeon_device *rdev);
420int evergreen_blit_init(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]421int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]422
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]423/*
424 * cayman
425 */
Alex Deucherb40e7e12011-11-17 14:57:50 -0500[diff] [blame]426void cayman_fence_ring_emit(struct radeon_device *rdev,
427 struct radeon_fence *fence);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]428void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
429int cayman_init(struct radeon_device *rdev);
430void cayman_fini(struct radeon_device *rdev);
431int cayman_suspend(struct radeon_device *rdev);
432int cayman_resume(struct radeon_device *rdev);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]433int cayman_asic_reset(struct radeon_device *rdev);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]434void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
435int cayman_vm_init(struct radeon_device *rdev);
436void cayman_vm_fini(struct radeon_device *rdev);
437int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id);
438void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
439void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm);
440uint32_t cayman_vm_page_flags(struct radeon_device *rdev,
441 struct radeon_vm *vm,
442 uint32_t flags);
443void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
444 unsigned pfn, uint64_t addr, uint32_t flags);
445int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]446
Alex Deucher43b3cd92012-03-20 17:18:00 -0400[diff] [blame]447/* DCE6 - SI */
448void dce6_bandwidth_update(struct radeon_device *rdev);
449
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]450/*
451 * si
452 */
453void si_fence_ring_emit(struct radeon_device *rdev,
454 struct radeon_fence *fence);
455void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
456int si_init(struct radeon_device *rdev);
457void si_fini(struct radeon_device *rdev);
458int si_suspend(struct radeon_device *rdev);
459int si_resume(struct radeon_device *rdev);
460bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
461int si_asic_reset(struct radeon_device *rdev);
462void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
463int si_irq_set(struct radeon_device *rdev);
464int si_irq_process(struct radeon_device *rdev);
465int si_vm_init(struct radeon_device *rdev);
466void si_vm_fini(struct radeon_device *rdev);
467int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id);
468void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
469void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm);
470int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
471
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]472#endif