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AnilKumar Ch32bb00e2012-06-22 15:10:49 +05301/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
Florian Vaussardeb33ef662013-06-03 16:12:22 +020010#include "am33xx.dtsi"
AnilKumar Ch32bb00e2012-06-22 15:10:49 +053011
12/ {
13 model = "TI AM335x EVM";
14 compatible = "ti,am335x-evm", "ti,am33xx";
15
AnilKumar Chefeedcf2012-08-31 15:07:20 +053016 cpus {
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
19 };
20 };
21
AnilKumar Ch32bb00e2012-06-22 15:10:49 +053022 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 };
Vaibhav Hiremath53d91032012-08-15 16:53:25 +053026
27 ocp {
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +053028 uart0: serial@44e09000 {
Vaibhav Hiremath9f2fbe12013-03-27 16:31:34 +053029 pinctrl-names = "default";
30 pinctrl-0 = <&uart0_pins>;
31
Vaibhav Hiremath53d91032012-08-15 16:53:25 +053032 status = "okay";
33 };
AnilKumar Ch1b2a9702012-08-21 16:47:29 +053034
AnilKumar Chb918e2c2012-11-21 17:22:17 +053035 i2c0: i2c@44e0b000 {
Vaibhav Hiremath3f866442013-03-26 14:14:01 +053036 pinctrl-names = "default";
37 pinctrl-0 = <&i2c0_pins>;
38
AnilKumar Ch1b2a9702012-08-21 16:47:29 +053039 status = "okay";
40 clock-frequency = <400000>;
41
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +053042 tps: tps@2d {
43 reg = <0x2d>;
AnilKumar Ch1b2a9702012-08-21 16:47:29 +053044 };
45 };
AnilKumar Ch492dd022012-09-20 02:49:29 +053046
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +020047 musb: usb@47400000 {
48 status = "okay";
49
50 control@44e10000 {
51 status = "okay";
52 };
53
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +020054 usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +020055 status = "okay";
56 };
57
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +020058 usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +020059 status = "okay";
60 };
61
62 usb@47401000 {
63 status = "okay";
64 };
65
66 usb@47401800 {
67 status = "okay";
Sebastian Andrzej Siewior781f1792013-08-20 18:35:49 +020068 dr_mode = "host";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +020069 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +020070
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +020071 dma-controller@07402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +020072 status = "okay";
73 };
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +020074 };
75
AnilKumar Chb918e2c2012-11-21 17:22:17 +053076 i2c1: i2c@4802a000 {
Vaibhav Hiremath3f866442013-03-26 14:14:01 +053077 pinctrl-names = "default";
78 pinctrl-0 = <&i2c1_pins>;
79
AnilKumar Ch492dd022012-09-20 02:49:29 +053080 status = "okay";
AnilKumar Chcd5cfac2012-09-21 21:19:11 +053081 clock-frequency = <100000>;
AnilKumar Ch492dd022012-09-20 02:49:29 +053082
83 lis331dlh: lis331dlh@18 {
84 compatible = "st,lis331dlh", "st,lis3lv02d";
85 reg = <0x18>;
86 Vdd-supply = <&lis3_reg>;
87 Vdd_IO-supply = <&lis3_reg>;
88
89 st,click-single-x;
90 st,click-single-y;
91 st,click-single-z;
92 st,click-thresh-x = <10>;
93 st,click-thresh-y = <10>;
94 st,click-thresh-z = <10>;
95 st,irq1-click;
96 st,irq2-click;
97 st,wakeup-x-lo;
98 st,wakeup-x-hi;
99 st,wakeup-y-lo;
100 st,wakeup-y-hi;
101 st,wakeup-z-lo;
102 st,wakeup-z-hi;
103 st,min-limit-x = <120>;
104 st,min-limit-y = <120>;
105 st,min-limit-z = <140>;
106 st,max-limit-x = <550>;
107 st,max-limit-y = <550>;
108 st,max-limit-z = <750>;
109 };
AnilKumar Chbf078552012-09-20 02:49:30 +0530110
AnilKumar Chcd5cfac2012-09-21 21:19:11 +0530111 tsl2550: tsl2550@39 {
112 compatible = "taos,tsl2550";
113 reg = <0x39>;
114 };
115
AnilKumar Chbf078552012-09-20 02:49:30 +0530116 tmp275: tmp275@48 {
117 compatible = "ti,tmp275";
118 reg = <0x48>;
119 };
AnilKumar Ch492dd022012-09-20 02:49:29 +0530120 };
Philip Avinashfdc6a2d2013-05-31 13:19:05 +0530121
122 elm: elm@48080000 {
123 status = "okay";
124 };
125
Philip Avinash6993fd02013-06-06 15:52:38 +0200126 epwmss0: epwmss@48300000 {
127 status = "okay";
128
129 ecap0: ecap@48300100 {
130 status = "okay";
131 pinctrl-names = "default";
132 pinctrl-0 = <&ecap0_pins>;
133 };
134 };
135
Philip Avinashfdc6a2d2013-05-31 13:19:05 +0530136 gpmc: gpmc@50000000 {
137 status = "okay";
138 pinctrl-names = "default";
139 pinctrl-0 = <&nandflash_pins_s0>;
140 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
141 nand@0,0 {
142 reg = <0 0 0>; /* CS0, offset 0 */
143 nand-bus-width = <8>;
144 ti,nand-ecc-opt = "bch8";
145 gpmc,device-nand = "true";
146 gpmc,device-width = <1>;
147 gpmc,sync-clk-ps = <0>;
148 gpmc,cs-on-ns = <0>;
149 gpmc,cs-rd-off-ns = <44>;
150 gpmc,cs-wr-off-ns = <44>;
151 gpmc,adv-on-ns = <6>;
152 gpmc,adv-rd-off-ns = <34>;
153 gpmc,adv-wr-off-ns = <44>;
154 gpmc,we-on-ns = <0>;
155 gpmc,we-off-ns = <40>;
156 gpmc,oe-on-ns = <0>;
157 gpmc,oe-off-ns = <54>;
158 gpmc,access-ns = <64>;
159 gpmc,rd-cycle-ns = <82>;
160 gpmc,wr-cycle-ns = <82>;
161 gpmc,wait-on-read = "true";
162 gpmc,wait-on-write = "true";
163 gpmc,bus-turnaround-ns = <0>;
164 gpmc,cycle2cycle-delay-ns = <0>;
165 gpmc,clk-activation-ns = <0>;
166 gpmc,wait-monitoring-ns = <0>;
167 gpmc,wr-access-ns = <40>;
168 gpmc,wr-data-mux-bus-ns = <0>;
169
170 #address-cells = <1>;
171 #size-cells = <1>;
172 elm_id = <&elm>;
173
174 /* MTD partition table */
175 partition@0 {
176 label = "SPL1";
177 reg = <0x00000000 0x000020000>;
178 };
179
180 partition@1 {
181 label = "SPL2";
182 reg = <0x00020000 0x00020000>;
183 };
184
185 partition@2 {
186 label = "SPL3";
187 reg = <0x00040000 0x00020000>;
188 };
189
190 partition@3 {
191 label = "SPL4";
192 reg = <0x00060000 0x00020000>;
193 };
194
195 partition@4 {
196 label = "U-boot";
197 reg = <0x00080000 0x001e0000>;
198 };
199
200 partition@5 {
201 label = "environment";
202 reg = <0x00260000 0x00020000>;
203 };
204
205 partition@6 {
206 label = "Kernel";
207 reg = <0x00280000 0x00500000>;
208 };
209
210 partition@7 {
211 label = "File-System";
212 reg = <0x00780000 0x0F880000>;
213 };
214 };
215 };
AnilKumar Ch1b2a9702012-08-21 16:47:29 +0530216 };
217
218 vbat: fixedregulator@0 {
219 compatible = "regulator-fixed";
220 regulator-name = "vbat";
221 regulator-min-microvolt = <5000000>;
222 regulator-max-microvolt = <5000000>;
223 regulator-boot-on;
224 };
AnilKumar Ch492dd022012-09-20 02:49:29 +0530225
226 lis3_reg: fixedregulator@1 {
227 compatible = "regulator-fixed";
228 regulator-name = "lis3_reg";
229 regulator-boot-on;
230 };
AnilKumar Ch2ca1d312012-11-06 19:18:30 +0530231
232 matrix_keypad: matrix_keypad@0 {
233 compatible = "gpio-matrix-keypad";
234 debounce-delay-ms = <5>;
235 col-scan-delay-us = <2>;
236
Florian Vaussarde94233c2013-06-03 16:12:23 +0200237 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
238 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
239 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
AnilKumar Ch2ca1d312012-11-06 19:18:30 +0530240
Florian Vaussarde94233c2013-06-03 16:12:23 +0200241 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
242 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
AnilKumar Ch2ca1d312012-11-06 19:18:30 +0530243
244 linux,keymap = <0x0000008b /* MENU */
245 0x0100009e /* BACK */
246 0x02000069 /* LEFT */
247 0x0001006a /* RIGHT */
248 0x0101001c /* ENTER */
249 0x0201006c>; /* DOWN */
250 };
AnilKumar Ch822c9932012-11-06 19:18:32 +0530251
252 gpio_keys: volume_keys@0 {
253 compatible = "gpio-keys";
254 #address-cells = <1>;
255 #size-cells = <0>;
256 autorepeat;
257
258 switch@9 {
259 label = "volume-up";
260 linux,code = <115>;
Florian Vaussarde94233c2013-06-03 16:12:23 +0200261 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
AnilKumar Ch822c9932012-11-06 19:18:32 +0530262 gpio-key,wakeup;
263 };
264
265 switch@10 {
266 label = "volume-down";
267 linux,code = <114>;
Florian Vaussarde94233c2013-06-03 16:12:23 +0200268 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
AnilKumar Ch822c9932012-11-06 19:18:32 +0530269 gpio-key,wakeup;
270 };
271 };
Philip Avinash6993fd02013-06-06 15:52:38 +0200272
273 backlight {
274 compatible = "pwm-backlight";
275 pwms = <&ecap0 0 50000 0>;
276 brightness-levels = <0 51 53 56 62 75 101 152 255>;
277 default-brightness-level = <8>;
278 };
AnilKumar Ch1b2a9702012-08-21 16:47:29 +0530279};
280
Javier Martinez Canillas82d75af2013-09-20 17:00:00 +0200281&am33xx_pinmux {
282 pinctrl-names = "default";
283 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
284
285 matrix_keypad_s0: matrix_keypad_s0 {
286 pinctrl-single,pins = <
287 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
288 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
289 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
290 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
291 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
292 >;
293 };
294
295 volume_keys_s0: volume_keys_s0 {
296 pinctrl-single,pins = <
297 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
298 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
299 >;
300 };
301
302 i2c0_pins: pinmux_i2c0_pins {
303 pinctrl-single,pins = <
304 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
305 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
306 >;
307 };
308
309 i2c1_pins: pinmux_i2c1_pins {
310 pinctrl-single,pins = <
311 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
312 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
313 >;
314 };
315
316 uart0_pins: pinmux_uart0_pins {
317 pinctrl-single,pins = <
318 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
319 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
320 >;
321 };
322
323 clkout2_pin: pinmux_clkout2_pin {
324 pinctrl-single,pins = <
325 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
326 >;
327 };
328
329 nandflash_pins_s0: nandflash_pins_s0 {
330 pinctrl-single,pins = <
331 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
332 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
333 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
334 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
335 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
336 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
337 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
338 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
339 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
340 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
341 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
342 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
343 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
344 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
345 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
346 >;
347 };
348
349 ecap0_pins: backlight_pins {
350 pinctrl-single,pins = <
351 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
352 >;
353 };
354
355 cpsw_default: cpsw_default {
356 pinctrl-single,pins = <
357 /* Slave 1 */
358 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
359 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
360 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
361 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
362 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
363 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
364 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
365 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
366 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
367 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
368 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
369 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
370 >;
371 };
372
373 cpsw_sleep: cpsw_sleep {
374 pinctrl-single,pins = <
375 /* Slave 1 reset value */
376 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
377 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
378 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
379 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
380 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
381 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
382 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
383 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
384 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
385 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
386 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
387 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
388 >;
389 };
390
391 davinci_mdio_default: davinci_mdio_default {
392 pinctrl-single,pins = <
393 /* MDIO */
394 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
395 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
396 >;
397 };
398
399 davinci_mdio_sleep: davinci_mdio_sleep {
400 pinctrl-single,pins = <
401 /* MDIO reset value */
402 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
403 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
404 >;
405 };
406};
407
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200408#include "tps65910.dtsi"
AnilKumar Ch1b2a9702012-08-21 16:47:29 +0530409
410&tps {
411 vcc1-supply = <&vbat>;
412 vcc2-supply = <&vbat>;
413 vcc3-supply = <&vbat>;
414 vcc4-supply = <&vbat>;
415 vcc5-supply = <&vbat>;
416 vcc6-supply = <&vbat>;
417 vcc7-supply = <&vbat>;
418 vccio-supply = <&vbat>;
419
420 regulators {
421 vrtc_reg: regulator@0 {
422 regulator-always-on;
423 };
424
425 vio_reg: regulator@1 {
426 regulator-always-on;
427 };
428
429 vdd1_reg: regulator@2 {
430 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
431 regulator-name = "vdd_mpu";
432 regulator-min-microvolt = <912500>;
433 regulator-max-microvolt = <1312500>;
434 regulator-boot-on;
435 regulator-always-on;
436 };
437
438 vdd2_reg: regulator@3 {
439 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
440 regulator-name = "vdd_core";
441 regulator-min-microvolt = <912500>;
442 regulator-max-microvolt = <1150000>;
443 regulator-boot-on;
444 regulator-always-on;
445 };
446
447 vdd3_reg: regulator@4 {
448 regulator-always-on;
449 };
450
451 vdig1_reg: regulator@5 {
452 regulator-always-on;
453 };
454
455 vdig2_reg: regulator@6 {
456 regulator-always-on;
457 };
458
459 vpll_reg: regulator@7 {
460 regulator-always-on;
461 };
462
463 vdac_reg: regulator@8 {
464 regulator-always-on;
465 };
466
467 vaux1_reg: regulator@9 {
468 regulator-always-on;
469 };
470
471 vaux2_reg: regulator@10 {
472 regulator-always-on;
473 };
474
475 vaux33_reg: regulator@11 {
476 regulator-always-on;
477 };
478
479 vmmc_reg: regulator@12 {
Matt Porter55b44522013-09-10 14:24:39 -0500480 regulator-min-microvolt = <1800000>;
481 regulator-max-microvolt = <3300000>;
AnilKumar Ch1b2a9702012-08-21 16:47:29 +0530482 regulator-always-on;
483 };
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530484 };
AnilKumar Ch32bb00e2012-06-22 15:10:49 +0530485};
Mugunthan V N1a39a652012-11-14 09:08:00 +0000486
Mugunthan V N50c7d2bd2013-06-07 17:02:54 +0530487&mac {
488 pinctrl-names = "default", "sleep";
489 pinctrl-0 = <&cpsw_default>;
490 pinctrl-1 = <&cpsw_sleep>;
491};
492
493&davinci_mdio {
494 pinctrl-names = "default", "sleep";
495 pinctrl-0 = <&davinci_mdio_default>;
496 pinctrl-1 = <&davinci_mdio_sleep>;
497};
498
Mugunthan V N1a39a652012-11-14 09:08:00 +0000499&cpsw_emac0 {
500 phy_id = <&davinci_mdio>, <0>;
Mugunthan V N6d75afe2013-06-03 20:10:11 +0000501 phy-mode = "rgmii-txid";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000502};
503
504&cpsw_emac1 {
505 phy_id = <&davinci_mdio>, <1>;
Mugunthan V N6d75afe2013-06-03 20:10:11 +0000506 phy-mode = "rgmii-txid";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000507};
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000508
509&tscadc {
510 status = "okay";
511 tsc {
512 ti,wires = <4>;
513 ti,x-plate-resistance = <200>;
514 ti,coordiante-readouts = <5>;
515 ti,wire-config = <0x00 0x11 0x22 0x33>;
516 };
517
518 adc {
Sebastian Andrzej Siewior18926ed2013-05-29 17:39:02 +0200519 ti,adc-channels = <4 5 6 7>;
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000520 };
521};
Matt Porter55b44522013-09-10 14:24:39 -0500522
523&mmc1 {
524 status = "okay";
525 vmmc-supply = <&vmmc_reg>;
526};