Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 1 | /* |
| 2 | * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | * |
| 16 | * Copyright (C) 2013 ARM Limited |
| 17 | * Copyright (C) 2017 Red Hat |
| 18 | */ |
| 19 | |
| 20 | #include <linux/atomic.h> |
| 21 | #include <linux/clk.h> |
| 22 | #include <linux/delay.h> |
| 23 | #include <linux/dma-iommu.h> |
| 24 | #include <linux/dma-mapping.h> |
| 25 | #include <linux/err.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/io.h> |
| 28 | #include <linux/io-64-nonatomic-hi-lo.h> |
| 29 | #include <linux/iommu.h> |
| 30 | #include <linux/iopoll.h> |
| 31 | #include <linux/kconfig.h> |
| 32 | #include <linux/module.h> |
| 33 | #include <linux/mutex.h> |
| 34 | #include <linux/of.h> |
| 35 | #include <linux/of_address.h> |
| 36 | #include <linux/of_device.h> |
| 37 | #include <linux/of_iommu.h> |
| 38 | #include <linux/platform_device.h> |
| 39 | #include <linux/pm.h> |
| 40 | #include <linux/pm_runtime.h> |
| 41 | #include <linux/qcom_scm.h> |
| 42 | #include <linux/slab.h> |
| 43 | #include <linux/spinlock.h> |
| 44 | |
| 45 | #include "io-pgtable.h" |
| 46 | #include "arm-smmu-regs.h" |
| 47 | |
| 48 | #define SMMU_INTR_SEL_NS 0x2000 |
| 49 | |
| 50 | struct qcom_iommu_ctx; |
| 51 | |
| 52 | struct qcom_iommu_dev { |
| 53 | /* IOMMU core code handle */ |
| 54 | struct iommu_device iommu; |
| 55 | struct device *dev; |
| 56 | struct clk *iface_clk; |
| 57 | struct clk *bus_clk; |
| 58 | void __iomem *local_base; |
| 59 | u32 sec_id; |
| 60 | u8 num_ctxs; |
| 61 | struct qcom_iommu_ctx *ctxs[0]; /* indexed by asid-1 */ |
| 62 | }; |
| 63 | |
| 64 | struct qcom_iommu_ctx { |
| 65 | struct device *dev; |
| 66 | void __iomem *base; |
| 67 | bool secure_init; |
| 68 | u8 asid; /* asid and ctx bank # are 1:1 */ |
Rob Clark | 049541e | 2017-11-03 10:50:33 -0600 | [diff] [blame] | 69 | struct iommu_domain *domain; |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | struct qcom_iommu_domain { |
| 73 | struct io_pgtable_ops *pgtbl_ops; |
| 74 | spinlock_t pgtbl_lock; |
| 75 | struct mutex init_mutex; /* Protects iommu pointer */ |
| 76 | struct iommu_domain domain; |
| 77 | struct qcom_iommu_dev *iommu; |
| 78 | }; |
| 79 | |
| 80 | static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom) |
| 81 | { |
| 82 | return container_of(dom, struct qcom_iommu_domain, domain); |
| 83 | } |
| 84 | |
| 85 | static const struct iommu_ops qcom_iommu_ops; |
| 86 | |
| 87 | static struct qcom_iommu_dev * to_iommu(struct iommu_fwspec *fwspec) |
| 88 | { |
| 89 | if (!fwspec || fwspec->ops != &qcom_iommu_ops) |
| 90 | return NULL; |
| 91 | return fwspec->iommu_priv; |
| 92 | } |
| 93 | |
| 94 | static struct qcom_iommu_ctx * to_ctx(struct iommu_fwspec *fwspec, unsigned asid) |
| 95 | { |
| 96 | struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec); |
| 97 | if (!qcom_iommu) |
| 98 | return NULL; |
| 99 | return qcom_iommu->ctxs[asid - 1]; |
| 100 | } |
| 101 | |
| 102 | static inline void |
| 103 | iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val) |
| 104 | { |
| 105 | writel_relaxed(val, ctx->base + reg); |
| 106 | } |
| 107 | |
| 108 | static inline void |
| 109 | iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val) |
| 110 | { |
| 111 | writeq_relaxed(val, ctx->base + reg); |
| 112 | } |
| 113 | |
| 114 | static inline u32 |
| 115 | iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg) |
| 116 | { |
| 117 | return readl_relaxed(ctx->base + reg); |
| 118 | } |
| 119 | |
| 120 | static inline u64 |
| 121 | iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg) |
| 122 | { |
| 123 | return readq_relaxed(ctx->base + reg); |
| 124 | } |
| 125 | |
| 126 | static void qcom_iommu_tlb_sync(void *cookie) |
| 127 | { |
| 128 | struct iommu_fwspec *fwspec = cookie; |
| 129 | unsigned i; |
| 130 | |
| 131 | for (i = 0; i < fwspec->num_ids; i++) { |
| 132 | struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); |
| 133 | unsigned int val, ret; |
| 134 | |
| 135 | iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0); |
| 136 | |
| 137 | ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val, |
| 138 | (val & 0x1) == 0, 0, 5000000); |
| 139 | if (ret) |
| 140 | dev_err(ctx->dev, "timeout waiting for TLB SYNC\n"); |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | static void qcom_iommu_tlb_inv_context(void *cookie) |
| 145 | { |
| 146 | struct iommu_fwspec *fwspec = cookie; |
| 147 | unsigned i; |
| 148 | |
| 149 | for (i = 0; i < fwspec->num_ids; i++) { |
| 150 | struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); |
| 151 | iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid); |
| 152 | } |
| 153 | |
| 154 | qcom_iommu_tlb_sync(cookie); |
| 155 | } |
| 156 | |
| 157 | static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size, |
| 158 | size_t granule, bool leaf, void *cookie) |
| 159 | { |
| 160 | struct iommu_fwspec *fwspec = cookie; |
| 161 | unsigned i, reg; |
| 162 | |
| 163 | reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; |
| 164 | |
| 165 | for (i = 0; i < fwspec->num_ids; i++) { |
| 166 | struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); |
| 167 | size_t s = size; |
| 168 | |
| 169 | iova &= ~12UL; |
| 170 | iova |= ctx->asid; |
| 171 | do { |
| 172 | iommu_writel(ctx, reg, iova); |
| 173 | iova += granule; |
| 174 | } while (s -= granule); |
| 175 | } |
| 176 | } |
| 177 | |
| 178 | static const struct iommu_gather_ops qcom_gather_ops = { |
| 179 | .tlb_flush_all = qcom_iommu_tlb_inv_context, |
| 180 | .tlb_add_flush = qcom_iommu_tlb_inv_range_nosync, |
| 181 | .tlb_sync = qcom_iommu_tlb_sync, |
| 182 | }; |
| 183 | |
| 184 | static irqreturn_t qcom_iommu_fault(int irq, void *dev) |
| 185 | { |
| 186 | struct qcom_iommu_ctx *ctx = dev; |
| 187 | u32 fsr, fsynr; |
| 188 | u64 iova; |
| 189 | |
| 190 | fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR); |
| 191 | |
| 192 | if (!(fsr & FSR_FAULT)) |
| 193 | return IRQ_NONE; |
| 194 | |
| 195 | fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0); |
| 196 | iova = iommu_readq(ctx, ARM_SMMU_CB_FAR); |
| 197 | |
Rob Clark | 049541e | 2017-11-03 10:50:33 -0600 | [diff] [blame] | 198 | if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) { |
| 199 | dev_err_ratelimited(ctx->dev, |
| 200 | "Unhandled context fault: fsr=0x%x, " |
| 201 | "iova=0x%016llx, fsynr=0x%x, cb=%d\n", |
| 202 | fsr, iova, fsynr, ctx->asid); |
| 203 | } |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 204 | |
| 205 | iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr); |
Rob Clark | 049541e | 2017-11-03 10:50:33 -0600 | [diff] [blame] | 206 | iommu_writel(ctx, ARM_SMMU_CB_RESUME, RESUME_TERMINATE); |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 207 | |
| 208 | return IRQ_HANDLED; |
| 209 | } |
| 210 | |
| 211 | static int qcom_iommu_init_domain(struct iommu_domain *domain, |
| 212 | struct qcom_iommu_dev *qcom_iommu, |
| 213 | struct iommu_fwspec *fwspec) |
| 214 | { |
| 215 | struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); |
| 216 | struct io_pgtable_ops *pgtbl_ops; |
| 217 | struct io_pgtable_cfg pgtbl_cfg; |
| 218 | int i, ret = 0; |
| 219 | u32 reg; |
| 220 | |
| 221 | mutex_lock(&qcom_domain->init_mutex); |
| 222 | if (qcom_domain->iommu) |
| 223 | goto out_unlock; |
| 224 | |
| 225 | pgtbl_cfg = (struct io_pgtable_cfg) { |
| 226 | .pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap, |
| 227 | .ias = 32, |
| 228 | .oas = 40, |
| 229 | .tlb = &qcom_gather_ops, |
| 230 | .iommu_dev = qcom_iommu->dev, |
| 231 | }; |
| 232 | |
| 233 | qcom_domain->iommu = qcom_iommu; |
| 234 | pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, fwspec); |
| 235 | if (!pgtbl_ops) { |
| 236 | dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n"); |
| 237 | ret = -ENOMEM; |
| 238 | goto out_clear_iommu; |
| 239 | } |
| 240 | |
| 241 | /* Update the domain's page sizes to reflect the page table format */ |
| 242 | domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; |
| 243 | domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1; |
| 244 | domain->geometry.force_aperture = true; |
| 245 | |
| 246 | for (i = 0; i < fwspec->num_ids; i++) { |
| 247 | struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); |
| 248 | |
| 249 | if (!ctx->secure_init) { |
| 250 | ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid); |
| 251 | if (ret) { |
| 252 | dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret); |
| 253 | goto out_clear_iommu; |
| 254 | } |
| 255 | ctx->secure_init = true; |
| 256 | } |
| 257 | |
| 258 | /* TTBRs */ |
| 259 | iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, |
| 260 | pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] | |
| 261 | ((u64)ctx->asid << TTBRn_ASID_SHIFT)); |
| 262 | iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, |
| 263 | pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] | |
| 264 | ((u64)ctx->asid << TTBRn_ASID_SHIFT)); |
| 265 | |
| 266 | /* TTBCR */ |
| 267 | iommu_writel(ctx, ARM_SMMU_CB_TTBCR2, |
| 268 | (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) | |
| 269 | TTBCR2_SEP_UPSTREAM); |
| 270 | iommu_writel(ctx, ARM_SMMU_CB_TTBCR, |
| 271 | pgtbl_cfg.arm_lpae_s1_cfg.tcr); |
| 272 | |
| 273 | /* MAIRs (stage-1 only) */ |
| 274 | iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, |
| 275 | pgtbl_cfg.arm_lpae_s1_cfg.mair[0]); |
| 276 | iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, |
| 277 | pgtbl_cfg.arm_lpae_s1_cfg.mair[1]); |
| 278 | |
| 279 | /* SCTLR */ |
| 280 | reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE | |
Rob Clark | 049541e | 2017-11-03 10:50:33 -0600 | [diff] [blame] | 281 | SCTLR_M | SCTLR_S1_ASIDPNE | SCTLR_CFCFG; |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 282 | |
| 283 | if (IS_ENABLED(CONFIG_BIG_ENDIAN)) |
| 284 | reg |= SCTLR_E; |
| 285 | |
| 286 | iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg); |
Rob Clark | 049541e | 2017-11-03 10:50:33 -0600 | [diff] [blame] | 287 | |
| 288 | ctx->domain = domain; |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 289 | } |
| 290 | |
| 291 | mutex_unlock(&qcom_domain->init_mutex); |
| 292 | |
| 293 | /* Publish page table ops for map/unmap */ |
| 294 | qcom_domain->pgtbl_ops = pgtbl_ops; |
| 295 | |
| 296 | return 0; |
| 297 | |
| 298 | out_clear_iommu: |
| 299 | qcom_domain->iommu = NULL; |
| 300 | out_unlock: |
| 301 | mutex_unlock(&qcom_domain->init_mutex); |
| 302 | return ret; |
| 303 | } |
| 304 | |
| 305 | static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type) |
| 306 | { |
| 307 | struct qcom_iommu_domain *qcom_domain; |
| 308 | |
| 309 | if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) |
| 310 | return NULL; |
| 311 | /* |
| 312 | * Allocate the domain and initialise some of its data structures. |
| 313 | * We can't really do anything meaningful until we've added a |
| 314 | * master. |
| 315 | */ |
| 316 | qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL); |
| 317 | if (!qcom_domain) |
| 318 | return NULL; |
| 319 | |
| 320 | if (type == IOMMU_DOMAIN_DMA && |
| 321 | iommu_get_dma_cookie(&qcom_domain->domain)) { |
| 322 | kfree(qcom_domain); |
| 323 | return NULL; |
| 324 | } |
| 325 | |
| 326 | mutex_init(&qcom_domain->init_mutex); |
| 327 | spin_lock_init(&qcom_domain->pgtbl_lock); |
| 328 | |
| 329 | return &qcom_domain->domain; |
| 330 | } |
| 331 | |
| 332 | static void qcom_iommu_domain_free(struct iommu_domain *domain) |
| 333 | { |
| 334 | struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); |
| 335 | |
| 336 | if (WARN_ON(qcom_domain->iommu)) /* forgot to detach? */ |
| 337 | return; |
| 338 | |
| 339 | iommu_put_dma_cookie(domain); |
| 340 | |
| 341 | /* NOTE: unmap can be called after client device is powered off, |
| 342 | * for example, with GPUs or anything involving dma-buf. So we |
| 343 | * cannot rely on the device_link. Make sure the IOMMU is on to |
| 344 | * avoid unclocked accesses in the TLB inv path: |
| 345 | */ |
| 346 | pm_runtime_get_sync(qcom_domain->iommu->dev); |
| 347 | |
| 348 | free_io_pgtable_ops(qcom_domain->pgtbl_ops); |
| 349 | |
| 350 | pm_runtime_put_sync(qcom_domain->iommu->dev); |
| 351 | |
| 352 | kfree(qcom_domain); |
| 353 | } |
| 354 | |
| 355 | static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) |
| 356 | { |
| 357 | struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec); |
| 358 | struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); |
| 359 | int ret; |
| 360 | |
| 361 | if (!qcom_iommu) { |
| 362 | dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n"); |
| 363 | return -ENXIO; |
| 364 | } |
| 365 | |
| 366 | /* Ensure that the domain is finalized */ |
| 367 | pm_runtime_get_sync(qcom_iommu->dev); |
| 368 | ret = qcom_iommu_init_domain(domain, qcom_iommu, dev->iommu_fwspec); |
| 369 | pm_runtime_put_sync(qcom_iommu->dev); |
| 370 | if (ret < 0) |
| 371 | return ret; |
| 372 | |
| 373 | /* |
| 374 | * Sanity check the domain. We don't support domains across |
| 375 | * different IOMMUs. |
| 376 | */ |
| 377 | if (qcom_domain->iommu != qcom_iommu) { |
| 378 | dev_err(dev, "cannot attach to IOMMU %s while already " |
| 379 | "attached to domain on IOMMU %s\n", |
| 380 | dev_name(qcom_domain->iommu->dev), |
| 381 | dev_name(qcom_iommu->dev)); |
| 382 | return -EINVAL; |
| 383 | } |
| 384 | |
| 385 | return 0; |
| 386 | } |
| 387 | |
| 388 | static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *dev) |
| 389 | { |
| 390 | struct iommu_fwspec *fwspec = dev->iommu_fwspec; |
| 391 | struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec); |
| 392 | struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); |
| 393 | unsigned i; |
| 394 | |
| 395 | if (!qcom_domain->iommu) |
| 396 | return; |
| 397 | |
| 398 | pm_runtime_get_sync(qcom_iommu->dev); |
| 399 | for (i = 0; i < fwspec->num_ids; i++) { |
| 400 | struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); |
| 401 | |
| 402 | /* Disable the context bank: */ |
| 403 | iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); |
Rob Clark | 049541e | 2017-11-03 10:50:33 -0600 | [diff] [blame] | 404 | |
| 405 | ctx->domain = NULL; |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 406 | } |
| 407 | pm_runtime_put_sync(qcom_iommu->dev); |
| 408 | |
| 409 | qcom_domain->iommu = NULL; |
| 410 | } |
| 411 | |
| 412 | static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova, |
| 413 | phys_addr_t paddr, size_t size, int prot) |
| 414 | { |
| 415 | int ret; |
| 416 | unsigned long flags; |
| 417 | struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); |
| 418 | struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; |
| 419 | |
| 420 | if (!ops) |
| 421 | return -ENODEV; |
| 422 | |
| 423 | spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); |
| 424 | ret = ops->map(ops, iova, paddr, size, prot); |
| 425 | spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); |
| 426 | return ret; |
| 427 | } |
| 428 | |
| 429 | static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova, |
| 430 | size_t size) |
| 431 | { |
| 432 | size_t ret; |
| 433 | unsigned long flags; |
| 434 | struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); |
| 435 | struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; |
| 436 | |
| 437 | if (!ops) |
| 438 | return 0; |
| 439 | |
| 440 | /* NOTE: unmap can be called after client device is powered off, |
| 441 | * for example, with GPUs or anything involving dma-buf. So we |
| 442 | * cannot rely on the device_link. Make sure the IOMMU is on to |
| 443 | * avoid unclocked accesses in the TLB inv path: |
| 444 | */ |
| 445 | pm_runtime_get_sync(qcom_domain->iommu->dev); |
| 446 | spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); |
| 447 | ret = ops->unmap(ops, iova, size); |
| 448 | spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); |
| 449 | pm_runtime_put_sync(qcom_domain->iommu->dev); |
| 450 | |
| 451 | return ret; |
| 452 | } |
| 453 | |
Robin Murphy | 4d689b6 | 2017-09-28 15:55:02 +0100 | [diff] [blame] | 454 | static void qcom_iommu_iotlb_sync(struct iommu_domain *domain) |
| 455 | { |
| 456 | struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); |
| 457 | struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops, |
| 458 | struct io_pgtable, ops); |
| 459 | if (!qcom_domain->pgtbl_ops) |
| 460 | return; |
| 461 | |
| 462 | pm_runtime_get_sync(qcom_domain->iommu->dev); |
| 463 | qcom_iommu_tlb_sync(pgtable->cookie); |
| 464 | pm_runtime_put_sync(qcom_domain->iommu->dev); |
| 465 | } |
| 466 | |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 467 | static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain, |
| 468 | dma_addr_t iova) |
| 469 | { |
| 470 | phys_addr_t ret; |
| 471 | unsigned long flags; |
| 472 | struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); |
| 473 | struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; |
| 474 | |
| 475 | if (!ops) |
| 476 | return 0; |
| 477 | |
| 478 | spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); |
| 479 | ret = ops->iova_to_phys(ops, iova); |
| 480 | spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); |
| 481 | |
| 482 | return ret; |
| 483 | } |
| 484 | |
| 485 | static bool qcom_iommu_capable(enum iommu_cap cap) |
| 486 | { |
| 487 | switch (cap) { |
| 488 | case IOMMU_CAP_CACHE_COHERENCY: |
| 489 | /* |
| 490 | * Return true here as the SMMU can always send out coherent |
| 491 | * requests. |
| 492 | */ |
| 493 | return true; |
| 494 | case IOMMU_CAP_NOEXEC: |
| 495 | return true; |
| 496 | default: |
| 497 | return false; |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | static int qcom_iommu_add_device(struct device *dev) |
| 502 | { |
| 503 | struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec); |
| 504 | struct iommu_group *group; |
| 505 | struct device_link *link; |
| 506 | |
| 507 | if (!qcom_iommu) |
| 508 | return -ENODEV; |
| 509 | |
| 510 | /* |
| 511 | * Establish the link between iommu and master, so that the |
| 512 | * iommu gets runtime enabled/disabled as per the master's |
| 513 | * needs. |
| 514 | */ |
| 515 | link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME); |
| 516 | if (!link) { |
| 517 | dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n", |
| 518 | dev_name(qcom_iommu->dev), dev_name(dev)); |
| 519 | return -ENODEV; |
| 520 | } |
| 521 | |
| 522 | group = iommu_group_get_for_dev(dev); |
| 523 | if (IS_ERR_OR_NULL(group)) |
| 524 | return PTR_ERR_OR_ZERO(group); |
| 525 | |
| 526 | iommu_group_put(group); |
| 527 | iommu_device_link(&qcom_iommu->iommu, dev); |
| 528 | |
| 529 | return 0; |
| 530 | } |
| 531 | |
| 532 | static void qcom_iommu_remove_device(struct device *dev) |
| 533 | { |
| 534 | struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec); |
| 535 | |
| 536 | if (!qcom_iommu) |
| 537 | return; |
| 538 | |
| 539 | iommu_device_unlink(&qcom_iommu->iommu, dev); |
| 540 | iommu_group_remove_device(dev); |
| 541 | iommu_fwspec_free(dev); |
| 542 | } |
| 543 | |
| 544 | static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) |
| 545 | { |
| 546 | struct qcom_iommu_dev *qcom_iommu; |
| 547 | struct platform_device *iommu_pdev; |
| 548 | unsigned asid = args->args[0]; |
| 549 | |
| 550 | if (args->args_count != 1) { |
| 551 | dev_err(dev, "incorrect number of iommu params found for %s " |
| 552 | "(found %d, expected 1)\n", |
| 553 | args->np->full_name, args->args_count); |
| 554 | return -EINVAL; |
| 555 | } |
| 556 | |
| 557 | iommu_pdev = of_find_device_by_node(args->np); |
| 558 | if (WARN_ON(!iommu_pdev)) |
| 559 | return -EINVAL; |
| 560 | |
| 561 | qcom_iommu = platform_get_drvdata(iommu_pdev); |
| 562 | |
| 563 | /* make sure the asid specified in dt is valid, so we don't have |
| 564 | * to sanity check this elsewhere, since 'asid - 1' is used to |
| 565 | * index into qcom_iommu->ctxs: |
| 566 | */ |
| 567 | if (WARN_ON(asid < 1) || |
| 568 | WARN_ON(asid > qcom_iommu->num_ctxs)) |
| 569 | return -EINVAL; |
| 570 | |
| 571 | if (!dev->iommu_fwspec->iommu_priv) { |
| 572 | dev->iommu_fwspec->iommu_priv = qcom_iommu; |
| 573 | } else { |
| 574 | /* make sure devices iommus dt node isn't referring to |
| 575 | * multiple different iommu devices. Multiple context |
| 576 | * banks are ok, but multiple devices are not: |
| 577 | */ |
| 578 | if (WARN_ON(qcom_iommu != dev->iommu_fwspec->iommu_priv)) |
| 579 | return -EINVAL; |
| 580 | } |
| 581 | |
| 582 | return iommu_fwspec_add_ids(dev, &asid, 1); |
| 583 | } |
| 584 | |
| 585 | static const struct iommu_ops qcom_iommu_ops = { |
| 586 | .capable = qcom_iommu_capable, |
| 587 | .domain_alloc = qcom_iommu_domain_alloc, |
| 588 | .domain_free = qcom_iommu_domain_free, |
| 589 | .attach_dev = qcom_iommu_attach_dev, |
| 590 | .detach_dev = qcom_iommu_detach_dev, |
| 591 | .map = qcom_iommu_map, |
| 592 | .unmap = qcom_iommu_unmap, |
Robin Murphy | 4d689b6 | 2017-09-28 15:55:02 +0100 | [diff] [blame] | 593 | .flush_iotlb_all = qcom_iommu_iotlb_sync, |
| 594 | .iotlb_sync = qcom_iommu_iotlb_sync, |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 595 | .iova_to_phys = qcom_iommu_iova_to_phys, |
| 596 | .add_device = qcom_iommu_add_device, |
| 597 | .remove_device = qcom_iommu_remove_device, |
| 598 | .device_group = generic_device_group, |
| 599 | .of_xlate = qcom_iommu_of_xlate, |
| 600 | .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, |
| 601 | }; |
| 602 | |
| 603 | static int qcom_iommu_enable_clocks(struct qcom_iommu_dev *qcom_iommu) |
| 604 | { |
| 605 | int ret; |
| 606 | |
| 607 | ret = clk_prepare_enable(qcom_iommu->iface_clk); |
| 608 | if (ret) { |
| 609 | dev_err(qcom_iommu->dev, "Couldn't enable iface_clk\n"); |
| 610 | return ret; |
| 611 | } |
| 612 | |
| 613 | ret = clk_prepare_enable(qcom_iommu->bus_clk); |
| 614 | if (ret) { |
| 615 | dev_err(qcom_iommu->dev, "Couldn't enable bus_clk\n"); |
| 616 | clk_disable_unprepare(qcom_iommu->iface_clk); |
| 617 | return ret; |
| 618 | } |
| 619 | |
| 620 | return 0; |
| 621 | } |
| 622 | |
| 623 | static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu) |
| 624 | { |
| 625 | clk_disable_unprepare(qcom_iommu->bus_clk); |
| 626 | clk_disable_unprepare(qcom_iommu->iface_clk); |
| 627 | } |
| 628 | |
Stanimir Varbanov | d051f28 | 2017-08-09 10:43:05 -0400 | [diff] [blame] | 629 | static int qcom_iommu_sec_ptbl_init(struct device *dev) |
| 630 | { |
| 631 | size_t psize = 0; |
| 632 | unsigned int spare = 0; |
| 633 | void *cpu_addr; |
| 634 | dma_addr_t paddr; |
| 635 | unsigned long attrs; |
| 636 | static bool allocated = false; |
| 637 | int ret; |
| 638 | |
| 639 | if (allocated) |
| 640 | return 0; |
| 641 | |
| 642 | ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize); |
| 643 | if (ret) { |
| 644 | dev_err(dev, "failed to get iommu secure pgtable size (%d)\n", |
| 645 | ret); |
| 646 | return ret; |
| 647 | } |
| 648 | |
| 649 | dev_info(dev, "iommu sec: pgtable size: %zu\n", psize); |
| 650 | |
| 651 | attrs = DMA_ATTR_NO_KERNEL_MAPPING; |
| 652 | |
| 653 | cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs); |
| 654 | if (!cpu_addr) { |
| 655 | dev_err(dev, "failed to allocate %zu bytes for pgtable\n", |
| 656 | psize); |
| 657 | return -ENOMEM; |
| 658 | } |
| 659 | |
| 660 | ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare); |
| 661 | if (ret) { |
| 662 | dev_err(dev, "failed to init iommu pgtable (%d)\n", ret); |
| 663 | goto free_mem; |
| 664 | } |
| 665 | |
| 666 | allocated = true; |
| 667 | return 0; |
| 668 | |
| 669 | free_mem: |
| 670 | dma_free_attrs(dev, psize, cpu_addr, paddr, attrs); |
| 671 | return ret; |
| 672 | } |
| 673 | |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 674 | static int get_asid(const struct device_node *np) |
| 675 | { |
| 676 | u32 reg; |
| 677 | |
| 678 | /* read the "reg" property directly to get the relative address |
| 679 | * of the context bank, and calculate the asid from that: |
| 680 | */ |
| 681 | if (of_property_read_u32_index(np, "reg", 0, ®)) |
| 682 | return -ENODEV; |
| 683 | |
| 684 | return reg / 0x1000; /* context banks are 0x1000 apart */ |
| 685 | } |
| 686 | |
| 687 | static int qcom_iommu_ctx_probe(struct platform_device *pdev) |
| 688 | { |
| 689 | struct qcom_iommu_ctx *ctx; |
| 690 | struct device *dev = &pdev->dev; |
| 691 | struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent); |
| 692 | struct resource *res; |
| 693 | int ret, irq; |
| 694 | |
| 695 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
| 696 | if (!ctx) |
| 697 | return -ENOMEM; |
| 698 | |
| 699 | ctx->dev = dev; |
| 700 | platform_set_drvdata(pdev, ctx); |
| 701 | |
| 702 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 703 | ctx->base = devm_ioremap_resource(dev, res); |
| 704 | if (IS_ERR(ctx->base)) |
| 705 | return PTR_ERR(ctx->base); |
| 706 | |
| 707 | irq = platform_get_irq(pdev, 0); |
| 708 | if (irq < 0) { |
| 709 | dev_err(dev, "failed to get irq\n"); |
| 710 | return -ENODEV; |
| 711 | } |
| 712 | |
| 713 | /* clear IRQs before registering fault handler, just in case the |
| 714 | * boot-loader left us a surprise: |
| 715 | */ |
| 716 | iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR)); |
| 717 | |
| 718 | ret = devm_request_irq(dev, irq, |
| 719 | qcom_iommu_fault, |
| 720 | IRQF_SHARED, |
| 721 | "qcom-iommu-fault", |
| 722 | ctx); |
| 723 | if (ret) { |
| 724 | dev_err(dev, "failed to request IRQ %u\n", irq); |
| 725 | return ret; |
| 726 | } |
| 727 | |
| 728 | ret = get_asid(dev->of_node); |
| 729 | if (ret < 0) { |
| 730 | dev_err(dev, "missing reg property\n"); |
| 731 | return ret; |
| 732 | } |
| 733 | |
| 734 | ctx->asid = ret; |
| 735 | |
| 736 | dev_dbg(dev, "found asid %u\n", ctx->asid); |
| 737 | |
| 738 | qcom_iommu->ctxs[ctx->asid - 1] = ctx; |
| 739 | |
| 740 | return 0; |
| 741 | } |
| 742 | |
| 743 | static int qcom_iommu_ctx_remove(struct platform_device *pdev) |
| 744 | { |
| 745 | struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent); |
| 746 | struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev); |
| 747 | |
| 748 | platform_set_drvdata(pdev, NULL); |
| 749 | |
| 750 | qcom_iommu->ctxs[ctx->asid - 1] = NULL; |
| 751 | |
| 752 | return 0; |
| 753 | } |
| 754 | |
| 755 | static const struct of_device_id ctx_of_match[] = { |
| 756 | { .compatible = "qcom,msm-iommu-v1-ns" }, |
| 757 | { .compatible = "qcom,msm-iommu-v1-sec" }, |
| 758 | { /* sentinel */ } |
| 759 | }; |
| 760 | |
| 761 | static struct platform_driver qcom_iommu_ctx_driver = { |
| 762 | .driver = { |
| 763 | .name = "qcom-iommu-ctx", |
| 764 | .of_match_table = of_match_ptr(ctx_of_match), |
| 765 | }, |
| 766 | .probe = qcom_iommu_ctx_probe, |
| 767 | .remove = qcom_iommu_ctx_remove, |
| 768 | }; |
| 769 | |
Stanimir Varbanov | d051f28 | 2017-08-09 10:43:05 -0400 | [diff] [blame] | 770 | static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu) |
| 771 | { |
| 772 | struct device_node *child; |
| 773 | |
| 774 | for_each_child_of_node(qcom_iommu->dev->of_node, child) |
| 775 | if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) |
| 776 | return true; |
| 777 | |
| 778 | return false; |
| 779 | } |
| 780 | |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 781 | static int qcom_iommu_device_probe(struct platform_device *pdev) |
| 782 | { |
| 783 | struct device_node *child; |
| 784 | struct qcom_iommu_dev *qcom_iommu; |
| 785 | struct device *dev = &pdev->dev; |
| 786 | struct resource *res; |
| 787 | int ret, sz, max_asid = 0; |
| 788 | |
| 789 | /* find the max asid (which is 1:1 to ctx bank idx), so we know how |
| 790 | * many child ctx devices we have: |
| 791 | */ |
| 792 | for_each_child_of_node(dev->of_node, child) |
| 793 | max_asid = max(max_asid, get_asid(child)); |
| 794 | |
| 795 | sz = sizeof(*qcom_iommu) + (max_asid * sizeof(qcom_iommu->ctxs[0])); |
| 796 | |
| 797 | qcom_iommu = devm_kzalloc(dev, sz, GFP_KERNEL); |
| 798 | if (!qcom_iommu) |
| 799 | return -ENOMEM; |
| 800 | qcom_iommu->num_ctxs = max_asid; |
| 801 | qcom_iommu->dev = dev; |
| 802 | |
| 803 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 804 | if (res) |
| 805 | qcom_iommu->local_base = devm_ioremap_resource(dev, res); |
| 806 | |
| 807 | qcom_iommu->iface_clk = devm_clk_get(dev, "iface"); |
| 808 | if (IS_ERR(qcom_iommu->iface_clk)) { |
| 809 | dev_err(dev, "failed to get iface clock\n"); |
| 810 | return PTR_ERR(qcom_iommu->iface_clk); |
| 811 | } |
| 812 | |
| 813 | qcom_iommu->bus_clk = devm_clk_get(dev, "bus"); |
| 814 | if (IS_ERR(qcom_iommu->bus_clk)) { |
| 815 | dev_err(dev, "failed to get bus clock\n"); |
| 816 | return PTR_ERR(qcom_iommu->bus_clk); |
| 817 | } |
| 818 | |
| 819 | if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id", |
| 820 | &qcom_iommu->sec_id)) { |
| 821 | dev_err(dev, "missing qcom,iommu-secure-id property\n"); |
| 822 | return -ENODEV; |
| 823 | } |
| 824 | |
Stanimir Varbanov | d051f28 | 2017-08-09 10:43:05 -0400 | [diff] [blame] | 825 | if (qcom_iommu_has_secure_context(qcom_iommu)) { |
| 826 | ret = qcom_iommu_sec_ptbl_init(dev); |
| 827 | if (ret) { |
| 828 | dev_err(dev, "cannot init secure pg table(%d)\n", ret); |
| 829 | return ret; |
| 830 | } |
| 831 | } |
| 832 | |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 833 | platform_set_drvdata(pdev, qcom_iommu); |
| 834 | |
| 835 | pm_runtime_enable(dev); |
| 836 | |
| 837 | /* register context bank devices, which are child nodes: */ |
| 838 | ret = devm_of_platform_populate(dev); |
| 839 | if (ret) { |
| 840 | dev_err(dev, "Failed to populate iommu contexts\n"); |
| 841 | return ret; |
| 842 | } |
| 843 | |
| 844 | ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL, |
| 845 | dev_name(dev)); |
| 846 | if (ret) { |
| 847 | dev_err(dev, "Failed to register iommu in sysfs\n"); |
| 848 | return ret; |
| 849 | } |
| 850 | |
| 851 | iommu_device_set_ops(&qcom_iommu->iommu, &qcom_iommu_ops); |
| 852 | iommu_device_set_fwnode(&qcom_iommu->iommu, dev->fwnode); |
| 853 | |
| 854 | ret = iommu_device_register(&qcom_iommu->iommu); |
| 855 | if (ret) { |
| 856 | dev_err(dev, "Failed to register iommu\n"); |
| 857 | return ret; |
| 858 | } |
| 859 | |
| 860 | bus_set_iommu(&platform_bus_type, &qcom_iommu_ops); |
| 861 | |
| 862 | if (qcom_iommu->local_base) { |
| 863 | pm_runtime_get_sync(dev); |
| 864 | writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS); |
| 865 | pm_runtime_put_sync(dev); |
| 866 | } |
| 867 | |
| 868 | return 0; |
| 869 | } |
| 870 | |
| 871 | static int qcom_iommu_device_remove(struct platform_device *pdev) |
| 872 | { |
| 873 | struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev); |
| 874 | |
| 875 | bus_set_iommu(&platform_bus_type, NULL); |
| 876 | |
| 877 | pm_runtime_force_suspend(&pdev->dev); |
| 878 | platform_set_drvdata(pdev, NULL); |
| 879 | iommu_device_sysfs_remove(&qcom_iommu->iommu); |
| 880 | iommu_device_unregister(&qcom_iommu->iommu); |
| 881 | |
| 882 | return 0; |
| 883 | } |
| 884 | |
Arnd Bergmann | 6ce5b0f | 2017-08-23 15:42:45 +0200 | [diff] [blame] | 885 | static int __maybe_unused qcom_iommu_resume(struct device *dev) |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 886 | { |
Wolfram Sang | 7d1bf14 | 2018-04-19 16:05:54 +0200 | [diff] [blame] | 887 | struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev); |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 888 | |
| 889 | return qcom_iommu_enable_clocks(qcom_iommu); |
| 890 | } |
| 891 | |
Arnd Bergmann | 6ce5b0f | 2017-08-23 15:42:45 +0200 | [diff] [blame] | 892 | static int __maybe_unused qcom_iommu_suspend(struct device *dev) |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 893 | { |
Wolfram Sang | 7d1bf14 | 2018-04-19 16:05:54 +0200 | [diff] [blame] | 894 | struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev); |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 895 | |
| 896 | qcom_iommu_disable_clocks(qcom_iommu); |
| 897 | |
| 898 | return 0; |
| 899 | } |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 900 | |
| 901 | static const struct dev_pm_ops qcom_iommu_pm_ops = { |
| 902 | SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL) |
| 903 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
| 904 | pm_runtime_force_resume) |
| 905 | }; |
| 906 | |
| 907 | static const struct of_device_id qcom_iommu_of_match[] = { |
| 908 | { .compatible = "qcom,msm-iommu-v1" }, |
| 909 | { /* sentinel */ } |
| 910 | }; |
| 911 | MODULE_DEVICE_TABLE(of, qcom_iommu_of_match); |
| 912 | |
| 913 | static struct platform_driver qcom_iommu_driver = { |
| 914 | .driver = { |
| 915 | .name = "qcom-iommu", |
| 916 | .of_match_table = of_match_ptr(qcom_iommu_of_match), |
| 917 | .pm = &qcom_iommu_pm_ops, |
| 918 | }, |
| 919 | .probe = qcom_iommu_device_probe, |
| 920 | .remove = qcom_iommu_device_remove, |
| 921 | }; |
| 922 | |
| 923 | static int __init qcom_iommu_init(void) |
| 924 | { |
| 925 | int ret; |
| 926 | |
| 927 | ret = platform_driver_register(&qcom_iommu_ctx_driver); |
| 928 | if (ret) |
| 929 | return ret; |
| 930 | |
| 931 | ret = platform_driver_register(&qcom_iommu_driver); |
| 932 | if (ret) |
| 933 | platform_driver_unregister(&qcom_iommu_ctx_driver); |
| 934 | |
| 935 | return ret; |
| 936 | } |
| 937 | |
| 938 | static void __exit qcom_iommu_exit(void) |
| 939 | { |
| 940 | platform_driver_unregister(&qcom_iommu_driver); |
| 941 | platform_driver_unregister(&qcom_iommu_ctx_driver); |
| 942 | } |
| 943 | |
| 944 | module_init(qcom_iommu_init); |
| 945 | module_exit(qcom_iommu_exit); |
| 946 | |
Rob Clark | 0ae349a | 2017-08-09 10:43:04 -0400 | [diff] [blame] | 947 | MODULE_DESCRIPTION("IOMMU API for QCOM IOMMU v1 implementations"); |
| 948 | MODULE_LICENSE("GPL v2"); |