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Catalin Marinas60ffc302012-03-05 11:49:27 +00001/*
2 * Based on arch/arm/include/asm/ptrace.h
3 *
4 * Copyright (C) 1996-2003 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#ifndef __ASM_PTRACE_H
20#define __ASM_PTRACE_H
21
David Howells4262a722012-10-11 11:05:13 +010022#include <uapi/asm/ptrace.h>
Catalin Marinas60ffc302012-03-05 11:49:27 +000023
Catalin Marinas60ffc302012-03-05 11:49:27 +000024/* AArch32-specific ptrace requests */
Will Deacon27aa55c2012-09-27 11:38:12 +010025#define COMPAT_PTRACE_GETREGS 12
26#define COMPAT_PTRACE_SETREGS 13
27#define COMPAT_PTRACE_GET_THREAD_AREA 22
28#define COMPAT_PTRACE_SET_SYSCALL 23
Catalin Marinas60ffc302012-03-05 11:49:27 +000029#define COMPAT_PTRACE_GETVFPREGS 27
30#define COMPAT_PTRACE_SETVFPREGS 28
Will Deacon27aa55c2012-09-27 11:38:12 +010031#define COMPAT_PTRACE_GETHBPREGS 29
32#define COMPAT_PTRACE_SETHBPREGS 30
Catalin Marinas60ffc302012-03-05 11:49:27 +000033#define COMPAT_PSR_MODE_USR 0x00000010
34#define COMPAT_PSR_T_BIT 0x00000020
35#define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
Catalin Marinas60ffc302012-03-05 11:49:27 +000036/*
37 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
38 * process is located in memory.
39 */
Catalin Marinas7606c372012-10-10 15:50:03 +010040#define COMPAT_PT_TEXT_ADDR 0x10000
41#define COMPAT_PT_DATA_ADDR 0x10004
42#define COMPAT_PT_TEXT_END_ADDR 0x10008
Catalin Marinas60ffc302012-03-05 11:49:27 +000043#ifndef __ASSEMBLY__
44
Catalin Marinas60ffc302012-03-05 11:49:27 +000045/* sizeof(struct user) for AArch32 */
46#define COMPAT_USER_SZ 296
Marc Zyngier88483ec2012-10-03 15:54:09 +010047
48/* Architecturally defined mapping between AArch32 and AArch64 registers */
49#define compat_usr(x) regs[(x)]
Catalin Marinas60ffc302012-03-05 11:49:27 +000050#define compat_sp regs[13]
Catalin Marinas60ffc302012-03-05 11:49:27 +000051#define compat_lr regs[14]
Marc Zyngier88483ec2012-10-03 15:54:09 +010052#define compat_sp_hyp regs[15]
53#define compat_sp_irq regs[16]
54#define compat_lr_irq regs[17]
55#define compat_sp_svc regs[18]
56#define compat_lr_svc regs[19]
57#define compat_sp_abt regs[20]
58#define compat_lr_abt regs[21]
59#define compat_sp_und regs[22]
60#define compat_lr_und regs[23]
61#define compat_r8_fiq regs[24]
62#define compat_r9_fiq regs[25]
63#define compat_r10_fiq regs[26]
64#define compat_r11_fiq regs[27]
65#define compat_r12_fiq regs[28]
66#define compat_sp_fiq regs[29]
67#define compat_lr_fiq regs[30]
Catalin Marinas60ffc302012-03-05 11:49:27 +000068
69/*
70 * This struct defines the way the registers are stored on the stack during an
71 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
72 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
73 */
74struct pt_regs {
75 union {
76 struct user_pt_regs user_regs;
77 struct {
78 u64 regs[31];
79 u64 sp;
80 u64 pc;
81 u64 pstate;
82 };
83 };
84 u64 orig_x0;
85 u64 syscallno;
86};
87
88#define arch_has_single_step() (1)
89
90#ifdef CONFIG_COMPAT
91#define compat_thumb_mode(regs) \
92 (((regs)->pstate & COMPAT_PSR_T_BIT))
93#else
94#define compat_thumb_mode(regs) (0)
95#endif
96
97#define user_mode(regs) \
98 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
99
100#define compat_user_mode(regs) \
101 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
102 (PSR_MODE32_BIT | PSR_MODE_EL0t))
103
104#define processor_mode(regs) \
105 ((regs)->pstate & PSR_MODE_MASK)
106
107#define interrupts_enabled(regs) \
108 (!((regs)->pstate & PSR_I_BIT))
109
110#define fast_interrupts_enabled(regs) \
111 (!((regs)->pstate & PSR_F_BIT))
112
113#define user_stack_pointer(regs) \
114 ((regs)->sp)
115
116/*
117 * Are the current registers suitable for user mode? (used to maintain
118 * security in signal handlers)
119 */
120static inline int valid_user_regs(struct user_pt_regs *regs)
121{
122 if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) {
123 regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT);
124
125 /* The T bit is reserved for AArch64 */
126 if (!(regs->pstate & PSR_MODE32_BIT))
127 regs->pstate &= ~COMPAT_PSR_T_BIT;
128
129 return 1;
130 }
131
132 /*
133 * Force PSR to something logical...
134 */
135 regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \
136 COMPAT_PSR_T_BIT | PSR_MODE32_BIT;
137
138 if (!(regs->pstate & PSR_MODE32_BIT)) {
139 regs->pstate &= ~COMPAT_PSR_T_BIT;
140 regs->pstate |= PSR_MODE_EL0t;
141 }
142
143 return 0;
144}
145
146#define instruction_pointer(regs) (regs)->pc
147
148#ifdef CONFIG_SMP
149extern unsigned long profile_pc(struct pt_regs *regs);
150#else
151#define profile_pc(regs) instruction_pointer(regs)
152#endif
153
154extern int aarch32_break_trap(struct pt_regs *regs);
155
Catalin Marinas60ffc302012-03-05 11:49:27 +0000156#endif /* __ASSEMBLY__ */
Catalin Marinas60ffc302012-03-05 11:49:27 +0000157#endif