Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 3 | * redistributing this file, you may do so under either license. |
| 4 | * |
| 5 | * GPL LICENSE SUMMARY |
| 6 | * |
| 7 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms and conditions of the GNU General Public License, |
| 11 | * version 2, as published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 16 | * more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along with |
| 19 | * this program; if not, write to the Free Software Foundation, Inc., |
| 20 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 21 | * |
| 22 | * The full GNU General Public License is included in this distribution in |
| 23 | * the file called "COPYING". |
| 24 | * |
| 25 | * BSD LICENSE |
| 26 | * |
| 27 | * Copyright(c) 2004-2009 Intel Corporation. All rights reserved. |
| 28 | * |
| 29 | * Redistribution and use in source and binary forms, with or without |
| 30 | * modification, are permitted provided that the following conditions are met: |
| 31 | * |
| 32 | * * Redistributions of source code must retain the above copyright |
| 33 | * notice, this list of conditions and the following disclaimer. |
| 34 | * * Redistributions in binary form must reproduce the above copyright |
| 35 | * notice, this list of conditions and the following disclaimer in |
| 36 | * the documentation and/or other materials provided with the |
| 37 | * distribution. |
| 38 | * * Neither the name of Intel Corporation nor the names of its |
| 39 | * contributors may be used to endorse or promote products derived |
| 40 | * from this software without specific prior written permission. |
| 41 | * |
| 42 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 43 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 44 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 45 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 46 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 47 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 48 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 49 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 50 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 51 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 52 | * POSSIBILITY OF SUCH DAMAGE. |
| 53 | */ |
| 54 | |
| 55 | /* |
| 56 | * Support routines for v3+ hardware |
| 57 | */ |
| 58 | |
| 59 | #include <linux/pci.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 60 | #include <linux/gfp.h> |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 61 | #include <linux/dmaengine.h> |
| 62 | #include <linux/dma-mapping.h> |
Paul Gortmaker | 70c7160 | 2011-05-22 16:47:17 -0400 | [diff] [blame] | 63 | #include <linux/prefetch.h> |
Vinod Koul | 949ff5b | 2012-03-13 11:58:12 +0530 | [diff] [blame] | 64 | #include "../dmaengine.h" |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 65 | #include "registers.h" |
| 66 | #include "hw.h" |
| 67 | #include "dma.h" |
| 68 | #include "dma_v2.h" |
| 69 | |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 70 | /* ioat hardware assumes at least two sources for raid operations */ |
| 71 | #define src_cnt_to_sw(x) ((x) + 2) |
| 72 | #define src_cnt_to_hw(x) ((x) - 2) |
| 73 | |
| 74 | /* provide a lookup table for setting the source address in the base or |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 75 | * extended descriptor of an xor or pq descriptor |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 76 | */ |
Dan Williams | d0b0c8c | 2011-07-22 14:20:46 -0700 | [diff] [blame] | 77 | static const u8 xor_idx_to_desc = 0xe0; |
Andi Kleen | 9b487ce | 2011-06-07 15:26:33 -0700 | [diff] [blame] | 78 | static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 }; |
| 79 | static const u8 pq_idx_to_desc = 0xf8; |
| 80 | static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 }; |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 81 | |
| 82 | static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
| 83 | { |
| 84 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; |
| 85 | |
| 86 | return raw->field[xor_idx_to_field[idx]]; |
| 87 | } |
| 88 | |
| 89 | static void xor_set_src(struct ioat_raw_descriptor *descs[2], |
| 90 | dma_addr_t addr, u32 offset, int idx) |
| 91 | { |
| 92 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; |
| 93 | |
| 94 | raw->field[xor_idx_to_field[idx]] = addr + offset; |
| 95 | } |
| 96 | |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 97 | static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
| 98 | { |
| 99 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; |
| 100 | |
| 101 | return raw->field[pq_idx_to_field[idx]]; |
| 102 | } |
| 103 | |
| 104 | static void pq_set_src(struct ioat_raw_descriptor *descs[2], |
| 105 | dma_addr_t addr, u32 offset, u8 coef, int idx) |
| 106 | { |
| 107 | struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0]; |
| 108 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; |
| 109 | |
| 110 | raw->field[pq_idx_to_field[idx]] = addr + offset; |
| 111 | pq->coef[idx] = coef; |
| 112 | } |
| 113 | |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame^] | 114 | static bool is_jf_ioat(struct pci_dev *pdev) |
| 115 | { |
| 116 | switch (pdev->device) { |
| 117 | case PCI_DEVICE_ID_INTEL_IOAT_JSF0: |
| 118 | case PCI_DEVICE_ID_INTEL_IOAT_JSF1: |
| 119 | case PCI_DEVICE_ID_INTEL_IOAT_JSF2: |
| 120 | case PCI_DEVICE_ID_INTEL_IOAT_JSF3: |
| 121 | case PCI_DEVICE_ID_INTEL_IOAT_JSF4: |
| 122 | case PCI_DEVICE_ID_INTEL_IOAT_JSF5: |
| 123 | case PCI_DEVICE_ID_INTEL_IOAT_JSF6: |
| 124 | case PCI_DEVICE_ID_INTEL_IOAT_JSF7: |
| 125 | case PCI_DEVICE_ID_INTEL_IOAT_JSF8: |
| 126 | case PCI_DEVICE_ID_INTEL_IOAT_JSF9: |
| 127 | return true; |
| 128 | default: |
| 129 | return false; |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | static bool is_snb_ioat(struct pci_dev *pdev) |
| 134 | { |
| 135 | switch (pdev->device) { |
| 136 | case PCI_DEVICE_ID_INTEL_IOAT_SNB0: |
| 137 | case PCI_DEVICE_ID_INTEL_IOAT_SNB1: |
| 138 | case PCI_DEVICE_ID_INTEL_IOAT_SNB2: |
| 139 | case PCI_DEVICE_ID_INTEL_IOAT_SNB3: |
| 140 | case PCI_DEVICE_ID_INTEL_IOAT_SNB4: |
| 141 | case PCI_DEVICE_ID_INTEL_IOAT_SNB5: |
| 142 | case PCI_DEVICE_ID_INTEL_IOAT_SNB6: |
| 143 | case PCI_DEVICE_ID_INTEL_IOAT_SNB7: |
| 144 | case PCI_DEVICE_ID_INTEL_IOAT_SNB8: |
| 145 | case PCI_DEVICE_ID_INTEL_IOAT_SNB9: |
| 146 | return true; |
| 147 | default: |
| 148 | return false; |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | static bool is_ivb_ioat(struct pci_dev *pdev) |
| 153 | { |
| 154 | switch (pdev->device) { |
| 155 | case PCI_DEVICE_ID_INTEL_IOAT_IVB0: |
| 156 | case PCI_DEVICE_ID_INTEL_IOAT_IVB1: |
| 157 | case PCI_DEVICE_ID_INTEL_IOAT_IVB2: |
| 158 | case PCI_DEVICE_ID_INTEL_IOAT_IVB3: |
| 159 | case PCI_DEVICE_ID_INTEL_IOAT_IVB4: |
| 160 | case PCI_DEVICE_ID_INTEL_IOAT_IVB5: |
| 161 | case PCI_DEVICE_ID_INTEL_IOAT_IVB6: |
| 162 | case PCI_DEVICE_ID_INTEL_IOAT_IVB7: |
| 163 | case PCI_DEVICE_ID_INTEL_IOAT_IVB8: |
| 164 | case PCI_DEVICE_ID_INTEL_IOAT_IVB9: |
| 165 | return true; |
| 166 | default: |
| 167 | return false; |
| 168 | } |
| 169 | |
| 170 | } |
| 171 | |
| 172 | static bool is_hsw_ioat(struct pci_dev *pdev) |
| 173 | { |
| 174 | switch (pdev->device) { |
| 175 | case PCI_DEVICE_ID_INTEL_IOAT_HSW0: |
| 176 | case PCI_DEVICE_ID_INTEL_IOAT_HSW1: |
| 177 | case PCI_DEVICE_ID_INTEL_IOAT_HSW2: |
| 178 | case PCI_DEVICE_ID_INTEL_IOAT_HSW3: |
| 179 | case PCI_DEVICE_ID_INTEL_IOAT_HSW4: |
| 180 | case PCI_DEVICE_ID_INTEL_IOAT_HSW5: |
| 181 | case PCI_DEVICE_ID_INTEL_IOAT_HSW6: |
| 182 | case PCI_DEVICE_ID_INTEL_IOAT_HSW7: |
| 183 | case PCI_DEVICE_ID_INTEL_IOAT_HSW8: |
| 184 | case PCI_DEVICE_ID_INTEL_IOAT_HSW9: |
| 185 | return true; |
| 186 | default: |
| 187 | return false; |
| 188 | } |
| 189 | |
| 190 | } |
| 191 | |
| 192 | static bool is_xeon_cb32(struct pci_dev *pdev) |
| 193 | { |
| 194 | return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || |
| 195 | is_hsw_ioat(pdev); |
| 196 | } |
| 197 | |
| 198 | static bool is_bwd_ioat(struct pci_dev *pdev) |
| 199 | { |
| 200 | switch (pdev->device) { |
| 201 | case PCI_DEVICE_ID_INTEL_IOAT_BWD0: |
| 202 | case PCI_DEVICE_ID_INTEL_IOAT_BWD1: |
| 203 | case PCI_DEVICE_ID_INTEL_IOAT_BWD2: |
| 204 | case PCI_DEVICE_ID_INTEL_IOAT_BWD3: |
| 205 | return true; |
| 206 | default: |
| 207 | return false; |
| 208 | } |
| 209 | } |
| 210 | |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 211 | static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 212 | struct ioat_ring_ent *desc, int idx) |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 213 | { |
| 214 | struct ioat_chan_common *chan = &ioat->base; |
| 215 | struct pci_dev *pdev = chan->device->pdev; |
| 216 | size_t len = desc->len; |
| 217 | size_t offset = len - desc->hw->size; |
| 218 | struct dma_async_tx_descriptor *tx = &desc->txd; |
| 219 | enum dma_ctrl_flags flags = tx->flags; |
| 220 | |
| 221 | switch (desc->hw->ctl_f.op) { |
| 222 | case IOAT_OP_COPY: |
Dan Williams | 58c8649 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 223 | if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */ |
| 224 | ioat_dma_unmap(chan, flags, len, desc->hw); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 225 | break; |
| 226 | case IOAT_OP_FILL: { |
| 227 | struct ioat_fill_descriptor *hw = desc->fill; |
| 228 | |
| 229 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) |
| 230 | ioat_unmap(pdev, hw->dst_addr - offset, len, |
| 231 | PCI_DMA_FROMDEVICE, flags, 1); |
| 232 | break; |
| 233 | } |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 234 | case IOAT_OP_XOR_VAL: |
| 235 | case IOAT_OP_XOR: { |
| 236 | struct ioat_xor_descriptor *xor = desc->xor; |
| 237 | struct ioat_ring_ent *ext; |
| 238 | struct ioat_xor_ext_descriptor *xor_ex = NULL; |
| 239 | int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt); |
| 240 | struct ioat_raw_descriptor *descs[2]; |
| 241 | int i; |
| 242 | |
| 243 | if (src_cnt > 5) { |
| 244 | ext = ioat2_get_ring_ent(ioat, idx + 1); |
| 245 | xor_ex = ext->xor_ex; |
| 246 | } |
| 247 | |
| 248 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { |
| 249 | descs[0] = (struct ioat_raw_descriptor *) xor; |
| 250 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; |
| 251 | for (i = 0; i < src_cnt; i++) { |
| 252 | dma_addr_t src = xor_get_src(descs, i); |
| 253 | |
| 254 | ioat_unmap(pdev, src - offset, len, |
| 255 | PCI_DMA_TODEVICE, flags, 0); |
| 256 | } |
| 257 | |
| 258 | /* dest is a source in xor validate operations */ |
| 259 | if (xor->ctl_f.op == IOAT_OP_XOR_VAL) { |
| 260 | ioat_unmap(pdev, xor->dst_addr - offset, len, |
| 261 | PCI_DMA_TODEVICE, flags, 1); |
| 262 | break; |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) |
| 267 | ioat_unmap(pdev, xor->dst_addr - offset, len, |
| 268 | PCI_DMA_FROMDEVICE, flags, 1); |
| 269 | break; |
| 270 | } |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 271 | case IOAT_OP_PQ_VAL: |
| 272 | case IOAT_OP_PQ: { |
| 273 | struct ioat_pq_descriptor *pq = desc->pq; |
| 274 | struct ioat_ring_ent *ext; |
| 275 | struct ioat_pq_ext_descriptor *pq_ex = NULL; |
| 276 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); |
| 277 | struct ioat_raw_descriptor *descs[2]; |
| 278 | int i; |
| 279 | |
| 280 | if (src_cnt > 3) { |
| 281 | ext = ioat2_get_ring_ent(ioat, idx + 1); |
| 282 | pq_ex = ext->pq_ex; |
| 283 | } |
| 284 | |
| 285 | /* in the 'continue' case don't unmap the dests as sources */ |
| 286 | if (dmaf_p_disabled_continue(flags)) |
| 287 | src_cnt--; |
| 288 | else if (dmaf_continue(flags)) |
| 289 | src_cnt -= 3; |
| 290 | |
| 291 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { |
| 292 | descs[0] = (struct ioat_raw_descriptor *) pq; |
| 293 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; |
| 294 | for (i = 0; i < src_cnt; i++) { |
| 295 | dma_addr_t src = pq_get_src(descs, i); |
| 296 | |
| 297 | ioat_unmap(pdev, src - offset, len, |
| 298 | PCI_DMA_TODEVICE, flags, 0); |
| 299 | } |
| 300 | |
| 301 | /* the dests are sources in pq validate operations */ |
| 302 | if (pq->ctl_f.op == IOAT_OP_XOR_VAL) { |
| 303 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) |
| 304 | ioat_unmap(pdev, pq->p_addr - offset, |
| 305 | len, PCI_DMA_TODEVICE, flags, 0); |
| 306 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) |
| 307 | ioat_unmap(pdev, pq->q_addr - offset, |
| 308 | len, PCI_DMA_TODEVICE, flags, 0); |
| 309 | break; |
| 310 | } |
| 311 | } |
| 312 | |
| 313 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { |
| 314 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) |
| 315 | ioat_unmap(pdev, pq->p_addr - offset, len, |
| 316 | PCI_DMA_BIDIRECTIONAL, flags, 1); |
| 317 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) |
| 318 | ioat_unmap(pdev, pq->q_addr - offset, len, |
| 319 | PCI_DMA_BIDIRECTIONAL, flags, 1); |
| 320 | } |
| 321 | break; |
| 322 | } |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 323 | default: |
| 324 | dev_err(&pdev->dev, "%s: unknown op type: %#x\n", |
| 325 | __func__, desc->hw->ctl_f.op); |
| 326 | } |
| 327 | } |
| 328 | |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 329 | static bool desc_has_ext(struct ioat_ring_ent *desc) |
| 330 | { |
| 331 | struct ioat_dma_descriptor *hw = desc->hw; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 332 | |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 333 | if (hw->ctl_f.op == IOAT_OP_XOR || |
| 334 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { |
| 335 | struct ioat_xor_descriptor *xor = desc->xor; |
| 336 | |
| 337 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) |
| 338 | return true; |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 339 | } else if (hw->ctl_f.op == IOAT_OP_PQ || |
| 340 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { |
| 341 | struct ioat_pq_descriptor *pq = desc->pq; |
| 342 | |
| 343 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) |
| 344 | return true; |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 345 | } |
| 346 | |
| 347 | return false; |
| 348 | } |
| 349 | |
| 350 | /** |
| 351 | * __cleanup - reclaim used descriptors |
| 352 | * @ioat: channel (ring) to clean |
| 353 | * |
| 354 | * The difference from the dma_v2.c __cleanup() is that this routine |
| 355 | * handles extended descriptors and dma-unmapping raid operations. |
| 356 | */ |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 357 | static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete) |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 358 | { |
| 359 | struct ioat_chan_common *chan = &ioat->base; |
| 360 | struct ioat_ring_ent *desc; |
| 361 | bool seen_current = false; |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 362 | int idx = ioat->tail, i; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 363 | u16 active; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 364 | |
| 365 | dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", |
| 366 | __func__, ioat->head, ioat->tail, ioat->issued); |
| 367 | |
| 368 | active = ioat2_ring_active(ioat); |
| 369 | for (i = 0; i < active && !seen_current; i++) { |
| 370 | struct dma_async_tx_descriptor *tx; |
| 371 | |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 372 | smp_read_barrier_depends(); |
| 373 | prefetch(ioat2_get_ring_ent(ioat, idx + i + 1)); |
| 374 | desc = ioat2_get_ring_ent(ioat, idx + i); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 375 | dump_desc_dbg(ioat, desc); |
| 376 | tx = &desc->txd; |
| 377 | if (tx->cookie) { |
Russell King - ARM Linux | f7fbce0 | 2012-03-06 22:35:07 +0000 | [diff] [blame] | 378 | dma_cookie_complete(tx); |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 379 | ioat3_dma_unmap(ioat, desc, idx + i); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 380 | if (tx->callback) { |
| 381 | tx->callback(tx->callback_param); |
| 382 | tx->callback = NULL; |
| 383 | } |
| 384 | } |
| 385 | |
| 386 | if (tx->phys == phys_complete) |
| 387 | seen_current = true; |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 388 | |
| 389 | /* skip extended descriptors */ |
| 390 | if (desc_has_ext(desc)) { |
| 391 | BUG_ON(i + 1 >= active); |
| 392 | i++; |
| 393 | } |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 394 | } |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 395 | smp_mb(); /* finish all descriptor reads before incrementing tail */ |
| 396 | ioat->tail = idx + i; |
Dan Williams | aa75db0 | 2010-03-03 21:21:10 -0700 | [diff] [blame] | 397 | BUG_ON(active && !seen_current); /* no active descs have written a completion? */ |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 398 | chan->last_completion = phys_complete; |
Dan Williams | b9cc986 | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 399 | |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 400 | if (active - i == 0) { |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 401 | dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", |
| 402 | __func__); |
| 403 | clear_bit(IOAT_COMPLETION_PENDING, &chan->state); |
| 404 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); |
| 405 | } |
Dan Williams | b9cc986 | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 406 | /* 5 microsecond delay per pending descriptor */ |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 407 | writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK), |
Dan Williams | b9cc986 | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 408 | chan->device->reg_base + IOAT_INTRDELAY_OFFSET); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 409 | } |
| 410 | |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 411 | static void ioat3_cleanup(struct ioat2_dma_chan *ioat) |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 412 | { |
| 413 | struct ioat_chan_common *chan = &ioat->base; |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 414 | dma_addr_t phys_complete; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 415 | |
Dan Williams | b9cc986 | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 416 | spin_lock_bh(&chan->cleanup_lock); |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 417 | if (ioat_cleanup_preamble(chan, &phys_complete)) |
| 418 | __cleanup(ioat, phys_complete); |
Dan Williams | b9cc986 | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 419 | spin_unlock_bh(&chan->cleanup_lock); |
| 420 | } |
| 421 | |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 422 | static void ioat3_cleanup_event(unsigned long data) |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 423 | { |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 424 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 425 | |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 426 | ioat3_cleanup(ioat); |
Dan Williams | 773d9e2 | 2010-03-03 11:47:42 -0700 | [diff] [blame] | 427 | writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) |
| 431 | { |
| 432 | struct ioat_chan_common *chan = &ioat->base; |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 433 | dma_addr_t phys_complete; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 434 | |
Dan Williams | b372ec2 | 2010-03-03 11:47:42 -0700 | [diff] [blame] | 435 | ioat2_quiesce(chan, 0); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 436 | if (ioat_cleanup_preamble(chan, &phys_complete)) |
| 437 | __cleanup(ioat, phys_complete); |
| 438 | |
| 439 | __ioat2_restart_chan(ioat); |
| 440 | } |
| 441 | |
Dave Jiang | 4dec23d | 2013-02-07 14:38:32 -0700 | [diff] [blame] | 442 | static void check_active(struct ioat2_dma_chan *ioat) |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 443 | { |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 444 | struct ioat_chan_common *chan = &ioat->base; |
| 445 | |
Dave Jiang | 4dec23d | 2013-02-07 14:38:32 -0700 | [diff] [blame] | 446 | if (ioat2_ring_active(ioat)) { |
| 447 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 448 | return; |
| 449 | } |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 450 | |
Dave Jiang | 4dec23d | 2013-02-07 14:38:32 -0700 | [diff] [blame] | 451 | if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &chan->state)) |
| 452 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); |
| 453 | else if (ioat->alloc_order > ioat_get_alloc_order()) { |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 454 | /* if the ring is idle, empty, and oversized try to step |
| 455 | * down the size |
| 456 | */ |
Dave Jiang | 4dec23d | 2013-02-07 14:38:32 -0700 | [diff] [blame] | 457 | reshape_ring(ioat, ioat->alloc_order - 1); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 458 | |
| 459 | /* keep shrinking until we get back to our minimum |
| 460 | * default size |
| 461 | */ |
| 462 | if (ioat->alloc_order > ioat_get_alloc_order()) |
| 463 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); |
| 464 | } |
Dave Jiang | 4dec23d | 2013-02-07 14:38:32 -0700 | [diff] [blame] | 465 | |
| 466 | } |
| 467 | |
Fengguang Wu | a20702b | 2013-02-13 09:40:03 +0800 | [diff] [blame] | 468 | static void ioat3_timer_event(unsigned long data) |
Dave Jiang | 4dec23d | 2013-02-07 14:38:32 -0700 | [diff] [blame] | 469 | { |
| 470 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); |
| 471 | struct ioat_chan_common *chan = &ioat->base; |
| 472 | dma_addr_t phys_complete; |
| 473 | u64 status; |
| 474 | |
| 475 | status = ioat_chansts(chan); |
| 476 | |
| 477 | /* when halted due to errors check for channel |
| 478 | * programming errors before advancing the completion state |
| 479 | */ |
| 480 | if (is_ioat_halted(status)) { |
| 481 | u32 chanerr; |
| 482 | |
| 483 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); |
| 484 | dev_err(to_dev(chan), "%s: Channel halted (%x)\n", |
| 485 | __func__, chanerr); |
| 486 | if (test_bit(IOAT_RUN, &chan->state)) |
| 487 | BUG_ON(is_ioat_bug(chanerr)); |
| 488 | else /* we never got off the ground */ |
| 489 | return; |
| 490 | } |
| 491 | |
| 492 | /* if we haven't made progress and we have already |
| 493 | * acknowledged a pending completion once, then be more |
| 494 | * forceful with a restart |
| 495 | */ |
| 496 | spin_lock_bh(&chan->cleanup_lock); |
| 497 | if (ioat_cleanup_preamble(chan, &phys_complete)) |
| 498 | __cleanup(ioat, phys_complete); |
| 499 | else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) { |
| 500 | spin_lock_bh(&ioat->prep_lock); |
| 501 | ioat3_restart_channel(ioat); |
| 502 | spin_unlock_bh(&ioat->prep_lock); |
| 503 | spin_unlock_bh(&chan->cleanup_lock); |
| 504 | return; |
| 505 | } else { |
| 506 | set_bit(IOAT_COMPLETION_ACK, &chan->state); |
| 507 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 508 | } |
| 509 | |
| 510 | |
| 511 | if (ioat2_ring_active(ioat)) |
| 512 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 513 | else { |
| 514 | spin_lock_bh(&ioat->prep_lock); |
| 515 | check_active(ioat); |
| 516 | spin_unlock_bh(&ioat->prep_lock); |
| 517 | } |
| 518 | spin_unlock_bh(&chan->cleanup_lock); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 519 | } |
| 520 | |
| 521 | static enum dma_status |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 522 | ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie, |
| 523 | struct dma_tx_state *txstate) |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 524 | { |
| 525 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 526 | enum dma_status ret; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 527 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 528 | ret = dma_cookie_status(c, cookie, txstate); |
| 529 | if (ret == DMA_SUCCESS) |
| 530 | return ret; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 531 | |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 532 | ioat3_cleanup(ioat); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 533 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 534 | return dma_cookie_status(c, cookie, txstate); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 535 | } |
| 536 | |
| 537 | static struct dma_async_tx_descriptor * |
| 538 | ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value, |
| 539 | size_t len, unsigned long flags) |
| 540 | { |
| 541 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
| 542 | struct ioat_ring_ent *desc; |
| 543 | size_t total_len = len; |
| 544 | struct ioat_fill_descriptor *fill; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 545 | u64 src_data = (0x0101010101010101ULL) * (value & 0xff); |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 546 | int num_descs, idx, i; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 547 | |
| 548 | num_descs = ioat2_xferlen_to_descs(ioat, len); |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 549 | if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs) == 0) |
| 550 | idx = ioat->head; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 551 | else |
| 552 | return NULL; |
Dan Williams | cdef57d | 2009-09-21 09:22:29 -0700 | [diff] [blame] | 553 | i = 0; |
| 554 | do { |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 555 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); |
| 556 | |
| 557 | desc = ioat2_get_ring_ent(ioat, idx + i); |
| 558 | fill = desc->fill; |
| 559 | |
| 560 | fill->size = xfer_size; |
| 561 | fill->src_data = src_data; |
| 562 | fill->dst_addr = dest; |
| 563 | fill->ctl = 0; |
| 564 | fill->ctl_f.op = IOAT_OP_FILL; |
| 565 | |
| 566 | len -= xfer_size; |
| 567 | dest += xfer_size; |
| 568 | dump_desc_dbg(ioat, desc); |
Dan Williams | cdef57d | 2009-09-21 09:22:29 -0700 | [diff] [blame] | 569 | } while (++i < num_descs); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 570 | |
| 571 | desc->txd.flags = flags; |
| 572 | desc->len = total_len; |
| 573 | fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); |
| 574 | fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE); |
| 575 | fill->ctl_f.compl_write = 1; |
| 576 | dump_desc_dbg(ioat, desc); |
| 577 | |
| 578 | /* we leave the channel locked to ensure in order submission */ |
| 579 | return &desc->txd; |
| 580 | } |
| 581 | |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 582 | static struct dma_async_tx_descriptor * |
| 583 | __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result, |
| 584 | dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, |
| 585 | size_t len, unsigned long flags) |
| 586 | { |
| 587 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
| 588 | struct ioat_ring_ent *compl_desc; |
| 589 | struct ioat_ring_ent *desc; |
| 590 | struct ioat_ring_ent *ext; |
| 591 | size_t total_len = len; |
| 592 | struct ioat_xor_descriptor *xor; |
| 593 | struct ioat_xor_ext_descriptor *xor_ex = NULL; |
| 594 | struct ioat_dma_descriptor *hw; |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 595 | int num_descs, with_ext, idx, i; |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 596 | u32 offset = 0; |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 597 | u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR; |
| 598 | |
| 599 | BUG_ON(src_cnt < 2); |
| 600 | |
| 601 | num_descs = ioat2_xferlen_to_descs(ioat, len); |
| 602 | /* we need 2x the number of descriptors to cover greater than 5 |
| 603 | * sources |
| 604 | */ |
| 605 | if (src_cnt > 5) { |
| 606 | with_ext = 1; |
| 607 | num_descs *= 2; |
| 608 | } else |
| 609 | with_ext = 0; |
| 610 | |
| 611 | /* completion writes from the raid engine may pass completion |
| 612 | * writes from the legacy engine, so we need one extra null |
| 613 | * (legacy) descriptor to ensure all completion writes arrive in |
| 614 | * order. |
| 615 | */ |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 616 | if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs+1) == 0) |
| 617 | idx = ioat->head; |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 618 | else |
| 619 | return NULL; |
Dan Williams | cdef57d | 2009-09-21 09:22:29 -0700 | [diff] [blame] | 620 | i = 0; |
| 621 | do { |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 622 | struct ioat_raw_descriptor *descs[2]; |
| 623 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); |
| 624 | int s; |
| 625 | |
| 626 | desc = ioat2_get_ring_ent(ioat, idx + i); |
| 627 | xor = desc->xor; |
| 628 | |
| 629 | /* save a branch by unconditionally retrieving the |
| 630 | * extended descriptor xor_set_src() knows to not write |
| 631 | * to it in the single descriptor case |
| 632 | */ |
| 633 | ext = ioat2_get_ring_ent(ioat, idx + i + 1); |
| 634 | xor_ex = ext->xor_ex; |
| 635 | |
| 636 | descs[0] = (struct ioat_raw_descriptor *) xor; |
| 637 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; |
| 638 | for (s = 0; s < src_cnt; s++) |
| 639 | xor_set_src(descs, src[s], offset, s); |
| 640 | xor->size = xfer_size; |
| 641 | xor->dst_addr = dest + offset; |
| 642 | xor->ctl = 0; |
| 643 | xor->ctl_f.op = op; |
| 644 | xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt); |
| 645 | |
| 646 | len -= xfer_size; |
| 647 | offset += xfer_size; |
| 648 | dump_desc_dbg(ioat, desc); |
Dan Williams | cdef57d | 2009-09-21 09:22:29 -0700 | [diff] [blame] | 649 | } while ((i += 1 + with_ext) < num_descs); |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 650 | |
| 651 | /* last xor descriptor carries the unmap parameters and fence bit */ |
| 652 | desc->txd.flags = flags; |
| 653 | desc->len = total_len; |
| 654 | if (result) |
| 655 | desc->result = result; |
| 656 | xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE); |
| 657 | |
| 658 | /* completion descriptor carries interrupt bit */ |
| 659 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); |
| 660 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; |
| 661 | hw = compl_desc->hw; |
| 662 | hw->ctl = 0; |
| 663 | hw->ctl_f.null = 1; |
| 664 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); |
| 665 | hw->ctl_f.compl_write = 1; |
| 666 | hw->size = NULL_DESC_BUFFER_SIZE; |
| 667 | dump_desc_dbg(ioat, compl_desc); |
| 668 | |
| 669 | /* we leave the channel locked to ensure in order submission */ |
Dan Williams | 49954c1 | 2009-11-19 17:11:03 -0700 | [diff] [blame] | 670 | return &compl_desc->txd; |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 671 | } |
| 672 | |
| 673 | static struct dma_async_tx_descriptor * |
| 674 | ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
| 675 | unsigned int src_cnt, size_t len, unsigned long flags) |
| 676 | { |
| 677 | return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags); |
| 678 | } |
| 679 | |
| 680 | struct dma_async_tx_descriptor * |
| 681 | ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, |
| 682 | unsigned int src_cnt, size_t len, |
| 683 | enum sum_check_flags *result, unsigned long flags) |
| 684 | { |
| 685 | /* the cleanup routine only sets bits on validate failure, it |
| 686 | * does not clear bits on validate success... so clear it here |
| 687 | */ |
| 688 | *result = 0; |
| 689 | |
| 690 | return __ioat3_prep_xor_lock(chan, result, src[0], &src[1], |
| 691 | src_cnt - 1, len, flags); |
| 692 | } |
| 693 | |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 694 | static void |
| 695 | dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext) |
| 696 | { |
| 697 | struct device *dev = to_dev(&ioat->base); |
| 698 | struct ioat_pq_descriptor *pq = desc->pq; |
| 699 | struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL; |
| 700 | struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex }; |
| 701 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); |
| 702 | int i; |
| 703 | |
| 704 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" |
Dave Jiang | 50f9f97 | 2013-03-04 10:59:54 -0700 | [diff] [blame] | 705 | " sz: %#10.8x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s' src_cnt: %d)\n", |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 706 | desc_id(desc), (unsigned long long) desc->txd.phys, |
| 707 | (unsigned long long) (pq_ex ? pq_ex->next : pq->next), |
| 708 | desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en, |
| 709 | pq->ctl_f.compl_write, |
| 710 | pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", |
| 711 | pq->ctl_f.src_cnt); |
| 712 | for (i = 0; i < src_cnt; i++) |
| 713 | dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, |
| 714 | (unsigned long long) pq_get_src(descs, i), pq->coef[i]); |
| 715 | dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); |
| 716 | dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); |
Dave Jiang | 50f9f97 | 2013-03-04 10:59:54 -0700 | [diff] [blame] | 717 | dev_dbg(dev, "\tNEXT: %#llx\n", pq->next); |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 718 | } |
| 719 | |
| 720 | static struct dma_async_tx_descriptor * |
| 721 | __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result, |
| 722 | const dma_addr_t *dst, const dma_addr_t *src, |
| 723 | unsigned int src_cnt, const unsigned char *scf, |
| 724 | size_t len, unsigned long flags) |
| 725 | { |
| 726 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
| 727 | struct ioat_chan_common *chan = &ioat->base; |
| 728 | struct ioat_ring_ent *compl_desc; |
| 729 | struct ioat_ring_ent *desc; |
| 730 | struct ioat_ring_ent *ext; |
| 731 | size_t total_len = len; |
| 732 | struct ioat_pq_descriptor *pq; |
| 733 | struct ioat_pq_ext_descriptor *pq_ex = NULL; |
| 734 | struct ioat_dma_descriptor *hw; |
| 735 | u32 offset = 0; |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 736 | u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ; |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 737 | int i, s, idx, with_ext, num_descs; |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 738 | |
| 739 | dev_dbg(to_dev(chan), "%s\n", __func__); |
| 740 | /* the engine requires at least two sources (we provide |
| 741 | * at least 1 implied source in the DMA_PREP_CONTINUE case) |
| 742 | */ |
| 743 | BUG_ON(src_cnt + dmaf_continue(flags) < 2); |
| 744 | |
| 745 | num_descs = ioat2_xferlen_to_descs(ioat, len); |
| 746 | /* we need 2x the number of descriptors to cover greater than 3 |
Dan Williams | cd78809 | 2009-12-17 13:52:39 -0700 | [diff] [blame] | 747 | * sources (we need 1 extra source in the q-only continuation |
| 748 | * case and 3 extra sources in the p+q continuation case. |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 749 | */ |
Dan Williams | cd78809 | 2009-12-17 13:52:39 -0700 | [diff] [blame] | 750 | if (src_cnt + dmaf_p_disabled_continue(flags) > 3 || |
| 751 | (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) { |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 752 | with_ext = 1; |
| 753 | num_descs *= 2; |
| 754 | } else |
| 755 | with_ext = 0; |
| 756 | |
| 757 | /* completion writes from the raid engine may pass completion |
| 758 | * writes from the legacy engine, so we need one extra null |
| 759 | * (legacy) descriptor to ensure all completion writes arrive in |
| 760 | * order. |
| 761 | */ |
| 762 | if (likely(num_descs) && |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 763 | ioat2_check_space_lock(ioat, num_descs+1) == 0) |
| 764 | idx = ioat->head; |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 765 | else |
| 766 | return NULL; |
Dan Williams | cdef57d | 2009-09-21 09:22:29 -0700 | [diff] [blame] | 767 | i = 0; |
| 768 | do { |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 769 | struct ioat_raw_descriptor *descs[2]; |
| 770 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); |
| 771 | |
| 772 | desc = ioat2_get_ring_ent(ioat, idx + i); |
| 773 | pq = desc->pq; |
| 774 | |
| 775 | /* save a branch by unconditionally retrieving the |
| 776 | * extended descriptor pq_set_src() knows to not write |
| 777 | * to it in the single descriptor case |
| 778 | */ |
| 779 | ext = ioat2_get_ring_ent(ioat, idx + i + with_ext); |
| 780 | pq_ex = ext->pq_ex; |
| 781 | |
| 782 | descs[0] = (struct ioat_raw_descriptor *) pq; |
| 783 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; |
| 784 | |
| 785 | for (s = 0; s < src_cnt; s++) |
| 786 | pq_set_src(descs, src[s], offset, scf[s], s); |
| 787 | |
| 788 | /* see the comment for dma_maxpq in include/linux/dmaengine.h */ |
| 789 | if (dmaf_p_disabled_continue(flags)) |
| 790 | pq_set_src(descs, dst[1], offset, 1, s++); |
| 791 | else if (dmaf_continue(flags)) { |
| 792 | pq_set_src(descs, dst[0], offset, 0, s++); |
| 793 | pq_set_src(descs, dst[1], offset, 1, s++); |
| 794 | pq_set_src(descs, dst[1], offset, 0, s++); |
| 795 | } |
| 796 | pq->size = xfer_size; |
| 797 | pq->p_addr = dst[0] + offset; |
| 798 | pq->q_addr = dst[1] + offset; |
| 799 | pq->ctl = 0; |
| 800 | pq->ctl_f.op = op; |
| 801 | pq->ctl_f.src_cnt = src_cnt_to_hw(s); |
| 802 | pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); |
| 803 | pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); |
| 804 | |
| 805 | len -= xfer_size; |
| 806 | offset += xfer_size; |
Dan Williams | cdef57d | 2009-09-21 09:22:29 -0700 | [diff] [blame] | 807 | } while ((i += 1 + with_ext) < num_descs); |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 808 | |
| 809 | /* last pq descriptor carries the unmap parameters and fence bit */ |
| 810 | desc->txd.flags = flags; |
| 811 | desc->len = total_len; |
| 812 | if (result) |
| 813 | desc->result = result; |
| 814 | pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); |
| 815 | dump_pq_desc_dbg(ioat, desc, ext); |
| 816 | |
| 817 | /* completion descriptor carries interrupt bit */ |
| 818 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); |
| 819 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; |
| 820 | hw = compl_desc->hw; |
| 821 | hw->ctl = 0; |
| 822 | hw->ctl_f.null = 1; |
| 823 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); |
| 824 | hw->ctl_f.compl_write = 1; |
| 825 | hw->size = NULL_DESC_BUFFER_SIZE; |
| 826 | dump_desc_dbg(ioat, compl_desc); |
| 827 | |
| 828 | /* we leave the channel locked to ensure in order submission */ |
Dan Williams | 49954c1 | 2009-11-19 17:11:03 -0700 | [diff] [blame] | 829 | return &compl_desc->txd; |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 830 | } |
| 831 | |
| 832 | static struct dma_async_tx_descriptor * |
| 833 | ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, |
| 834 | unsigned int src_cnt, const unsigned char *scf, size_t len, |
| 835 | unsigned long flags) |
| 836 | { |
Dan Williams | de581b6 | 2009-11-19 17:08:45 -0700 | [diff] [blame] | 837 | /* specify valid address for disabled result */ |
| 838 | if (flags & DMA_PREP_PQ_DISABLE_P) |
| 839 | dst[0] = dst[1]; |
| 840 | if (flags & DMA_PREP_PQ_DISABLE_Q) |
| 841 | dst[1] = dst[0]; |
| 842 | |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 843 | /* handle the single source multiply case from the raid6 |
| 844 | * recovery path |
| 845 | */ |
Dan Williams | de581b6 | 2009-11-19 17:08:45 -0700 | [diff] [blame] | 846 | if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) { |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 847 | dma_addr_t single_source[2]; |
| 848 | unsigned char single_source_coef[2]; |
| 849 | |
| 850 | BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q); |
| 851 | single_source[0] = src[0]; |
| 852 | single_source[1] = src[0]; |
| 853 | single_source_coef[0] = scf[0]; |
| 854 | single_source_coef[1] = 0; |
| 855 | |
| 856 | return __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2, |
| 857 | single_source_coef, len, flags); |
| 858 | } else |
| 859 | return __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, scf, |
| 860 | len, flags); |
| 861 | } |
| 862 | |
| 863 | struct dma_async_tx_descriptor * |
| 864 | ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, |
| 865 | unsigned int src_cnt, const unsigned char *scf, size_t len, |
| 866 | enum sum_check_flags *pqres, unsigned long flags) |
| 867 | { |
Dan Williams | de581b6 | 2009-11-19 17:08:45 -0700 | [diff] [blame] | 868 | /* specify valid address for disabled result */ |
| 869 | if (flags & DMA_PREP_PQ_DISABLE_P) |
| 870 | pq[0] = pq[1]; |
| 871 | if (flags & DMA_PREP_PQ_DISABLE_Q) |
| 872 | pq[1] = pq[0]; |
| 873 | |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 874 | /* the cleanup routine only sets bits on validate failure, it |
| 875 | * does not clear bits on validate success... so clear it here |
| 876 | */ |
| 877 | *pqres = 0; |
| 878 | |
| 879 | return __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len, |
| 880 | flags); |
| 881 | } |
| 882 | |
Dan Williams | ae78662 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 883 | static struct dma_async_tx_descriptor * |
| 884 | ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, |
| 885 | unsigned int src_cnt, size_t len, unsigned long flags) |
| 886 | { |
| 887 | unsigned char scf[src_cnt]; |
| 888 | dma_addr_t pq[2]; |
| 889 | |
| 890 | memset(scf, 0, src_cnt); |
Dan Williams | ae78662 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 891 | pq[0] = dst; |
Dan Williams | de581b6 | 2009-11-19 17:08:45 -0700 | [diff] [blame] | 892 | flags |= DMA_PREP_PQ_DISABLE_Q; |
| 893 | pq[1] = dst; /* specify valid address for disabled result */ |
Dan Williams | ae78662 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 894 | |
| 895 | return __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len, |
| 896 | flags); |
| 897 | } |
| 898 | |
| 899 | struct dma_async_tx_descriptor * |
| 900 | ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, |
| 901 | unsigned int src_cnt, size_t len, |
| 902 | enum sum_check_flags *result, unsigned long flags) |
| 903 | { |
| 904 | unsigned char scf[src_cnt]; |
| 905 | dma_addr_t pq[2]; |
| 906 | |
| 907 | /* the cleanup routine only sets bits on validate failure, it |
| 908 | * does not clear bits on validate success... so clear it here |
| 909 | */ |
| 910 | *result = 0; |
| 911 | |
| 912 | memset(scf, 0, src_cnt); |
Dan Williams | ae78662 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 913 | pq[0] = src[0]; |
Dan Williams | de581b6 | 2009-11-19 17:08:45 -0700 | [diff] [blame] | 914 | flags |= DMA_PREP_PQ_DISABLE_Q; |
| 915 | pq[1] = pq[0]; /* specify valid address for disabled result */ |
Dan Williams | ae78662 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 916 | |
| 917 | return __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, scf, |
| 918 | len, flags); |
| 919 | } |
| 920 | |
Dan Williams | 58c8649 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 921 | static struct dma_async_tx_descriptor * |
| 922 | ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags) |
| 923 | { |
| 924 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
| 925 | struct ioat_ring_ent *desc; |
| 926 | struct ioat_dma_descriptor *hw; |
Dan Williams | 58c8649 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 927 | |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 928 | if (ioat2_check_space_lock(ioat, 1) == 0) |
| 929 | desc = ioat2_get_ring_ent(ioat, ioat->head); |
Dan Williams | 58c8649 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 930 | else |
| 931 | return NULL; |
| 932 | |
| 933 | hw = desc->hw; |
| 934 | hw->ctl = 0; |
| 935 | hw->ctl_f.null = 1; |
| 936 | hw->ctl_f.int_en = 1; |
| 937 | hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); |
| 938 | hw->ctl_f.compl_write = 1; |
| 939 | hw->size = NULL_DESC_BUFFER_SIZE; |
| 940 | hw->src_addr = 0; |
| 941 | hw->dst_addr = 0; |
| 942 | |
| 943 | desc->txd.flags = flags; |
| 944 | desc->len = 1; |
| 945 | |
| 946 | dump_desc_dbg(ioat, desc); |
| 947 | |
| 948 | /* we leave the channel locked to ensure in order submission */ |
| 949 | return &desc->txd; |
| 950 | } |
| 951 | |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 952 | static void ioat3_dma_test_callback(void *dma_async_param) |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 953 | { |
| 954 | struct completion *cmp = dma_async_param; |
| 955 | |
| 956 | complete(cmp); |
| 957 | } |
| 958 | |
| 959 | #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 960 | static int ioat_xor_val_self_test(struct ioatdma_device *device) |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 961 | { |
| 962 | int i, src_idx; |
| 963 | struct page *dest; |
| 964 | struct page *xor_srcs[IOAT_NUM_SRC_TEST]; |
| 965 | struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; |
| 966 | dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; |
| 967 | dma_addr_t dma_addr, dest_dma; |
| 968 | struct dma_async_tx_descriptor *tx; |
| 969 | struct dma_chan *dma_chan; |
| 970 | dma_cookie_t cookie; |
| 971 | u8 cmp_byte = 0; |
| 972 | u32 cmp_word; |
| 973 | u32 xor_val_result; |
| 974 | int err = 0; |
| 975 | struct completion cmp; |
| 976 | unsigned long tmo; |
| 977 | struct device *dev = &device->pdev->dev; |
| 978 | struct dma_device *dma = &device->common; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 979 | u8 op = 0; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 980 | |
| 981 | dev_dbg(dev, "%s\n", __func__); |
| 982 | |
| 983 | if (!dma_has_cap(DMA_XOR, dma->cap_mask)) |
| 984 | return 0; |
| 985 | |
| 986 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { |
| 987 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
| 988 | if (!xor_srcs[src_idx]) { |
| 989 | while (src_idx--) |
| 990 | __free_page(xor_srcs[src_idx]); |
| 991 | return -ENOMEM; |
| 992 | } |
| 993 | } |
| 994 | |
| 995 | dest = alloc_page(GFP_KERNEL); |
| 996 | if (!dest) { |
| 997 | while (src_idx--) |
| 998 | __free_page(xor_srcs[src_idx]); |
| 999 | return -ENOMEM; |
| 1000 | } |
| 1001 | |
| 1002 | /* Fill in src buffers */ |
| 1003 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { |
| 1004 | u8 *ptr = page_address(xor_srcs[src_idx]); |
| 1005 | for (i = 0; i < PAGE_SIZE; i++) |
| 1006 | ptr[i] = (1 << src_idx); |
| 1007 | } |
| 1008 | |
| 1009 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) |
| 1010 | cmp_byte ^= (u8) (1 << src_idx); |
| 1011 | |
| 1012 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | |
| 1013 | (cmp_byte << 8) | cmp_byte; |
| 1014 | |
| 1015 | memset(page_address(dest), 0, PAGE_SIZE); |
| 1016 | |
| 1017 | dma_chan = container_of(dma->channels.next, struct dma_chan, |
| 1018 | device_node); |
| 1019 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { |
| 1020 | err = -ENODEV; |
| 1021 | goto out; |
| 1022 | } |
| 1023 | |
| 1024 | /* test xor */ |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1025 | op = IOAT_OP_XOR; |
| 1026 | |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1027 | dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); |
| 1028 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) |
| 1029 | dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, |
| 1030 | DMA_TO_DEVICE); |
| 1031 | tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, |
| 1032 | IOAT_NUM_SRC_TEST, PAGE_SIZE, |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1033 | DMA_PREP_INTERRUPT | |
| 1034 | DMA_COMPL_SKIP_SRC_UNMAP | |
| 1035 | DMA_COMPL_SKIP_DEST_UNMAP); |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1036 | |
| 1037 | if (!tx) { |
| 1038 | dev_err(dev, "Self-test xor prep failed\n"); |
| 1039 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1040 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1041 | } |
| 1042 | |
| 1043 | async_tx_ack(tx); |
| 1044 | init_completion(&cmp); |
| 1045 | tx->callback = ioat3_dma_test_callback; |
| 1046 | tx->callback_param = &cmp; |
| 1047 | cookie = tx->tx_submit(tx); |
| 1048 | if (cookie < 0) { |
| 1049 | dev_err(dev, "Self-test xor setup failed\n"); |
| 1050 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1051 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1052 | } |
| 1053 | dma->device_issue_pending(dma_chan); |
| 1054 | |
| 1055 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
| 1056 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1057 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1058 | dev_err(dev, "Self-test xor timed out\n"); |
| 1059 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1060 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1061 | } |
| 1062 | |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1063 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
| 1064 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) |
| 1065 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); |
| 1066 | |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1067 | dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
| 1068 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { |
| 1069 | u32 *ptr = page_address(dest); |
| 1070 | if (ptr[i] != cmp_word) { |
| 1071 | dev_err(dev, "Self-test xor failed compare\n"); |
| 1072 | err = -ENODEV; |
| 1073 | goto free_resources; |
| 1074 | } |
| 1075 | } |
Shuah Khan | ac49898 | 2012-10-25 10:22:32 -0600 | [diff] [blame] | 1076 | dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1077 | |
| 1078 | /* skip validate if the capability is not present */ |
| 1079 | if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) |
| 1080 | goto free_resources; |
| 1081 | |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1082 | op = IOAT_OP_XOR_VAL; |
| 1083 | |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1084 | /* validate the sources with the destintation page */ |
| 1085 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) |
| 1086 | xor_val_srcs[i] = xor_srcs[i]; |
| 1087 | xor_val_srcs[i] = dest; |
| 1088 | |
| 1089 | xor_val_result = 1; |
| 1090 | |
| 1091 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
| 1092 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, |
| 1093 | DMA_TO_DEVICE); |
| 1094 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, |
| 1095 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1096 | &xor_val_result, DMA_PREP_INTERRUPT | |
| 1097 | DMA_COMPL_SKIP_SRC_UNMAP | |
| 1098 | DMA_COMPL_SKIP_DEST_UNMAP); |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1099 | if (!tx) { |
| 1100 | dev_err(dev, "Self-test zero prep failed\n"); |
| 1101 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1102 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1103 | } |
| 1104 | |
| 1105 | async_tx_ack(tx); |
| 1106 | init_completion(&cmp); |
| 1107 | tx->callback = ioat3_dma_test_callback; |
| 1108 | tx->callback_param = &cmp; |
| 1109 | cookie = tx->tx_submit(tx); |
| 1110 | if (cookie < 0) { |
| 1111 | dev_err(dev, "Self-test zero setup failed\n"); |
| 1112 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1113 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1114 | } |
| 1115 | dma->device_issue_pending(dma_chan); |
| 1116 | |
| 1117 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
| 1118 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1119 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1120 | dev_err(dev, "Self-test validate timed out\n"); |
| 1121 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1122 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1123 | } |
| 1124 | |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1125 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
| 1126 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); |
| 1127 | |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1128 | if (xor_val_result != 0) { |
| 1129 | dev_err(dev, "Self-test validate failed compare\n"); |
| 1130 | err = -ENODEV; |
| 1131 | goto free_resources; |
| 1132 | } |
| 1133 | |
| 1134 | /* skip memset if the capability is not present */ |
| 1135 | if (!dma_has_cap(DMA_MEMSET, dma_chan->device->cap_mask)) |
| 1136 | goto free_resources; |
| 1137 | |
| 1138 | /* test memset */ |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1139 | op = IOAT_OP_FILL; |
| 1140 | |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1141 | dma_addr = dma_map_page(dev, dest, 0, |
| 1142 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 1143 | tx = dma->device_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1144 | DMA_PREP_INTERRUPT | |
| 1145 | DMA_COMPL_SKIP_SRC_UNMAP | |
| 1146 | DMA_COMPL_SKIP_DEST_UNMAP); |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1147 | if (!tx) { |
| 1148 | dev_err(dev, "Self-test memset prep failed\n"); |
| 1149 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1150 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1151 | } |
| 1152 | |
| 1153 | async_tx_ack(tx); |
| 1154 | init_completion(&cmp); |
| 1155 | tx->callback = ioat3_dma_test_callback; |
| 1156 | tx->callback_param = &cmp; |
| 1157 | cookie = tx->tx_submit(tx); |
| 1158 | if (cookie < 0) { |
| 1159 | dev_err(dev, "Self-test memset setup failed\n"); |
| 1160 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1161 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1162 | } |
| 1163 | dma->device_issue_pending(dma_chan); |
| 1164 | |
| 1165 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
| 1166 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1167 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1168 | dev_err(dev, "Self-test memset timed out\n"); |
| 1169 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1170 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1171 | } |
| 1172 | |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1173 | dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); |
| 1174 | |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1175 | for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) { |
| 1176 | u32 *ptr = page_address(dest); |
| 1177 | if (ptr[i]) { |
| 1178 | dev_err(dev, "Self-test memset failed compare\n"); |
| 1179 | err = -ENODEV; |
| 1180 | goto free_resources; |
| 1181 | } |
| 1182 | } |
| 1183 | |
| 1184 | /* test for non-zero parity sum */ |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1185 | op = IOAT_OP_XOR_VAL; |
| 1186 | |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1187 | xor_val_result = 0; |
| 1188 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
| 1189 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, |
| 1190 | DMA_TO_DEVICE); |
| 1191 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, |
| 1192 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1193 | &xor_val_result, DMA_PREP_INTERRUPT | |
| 1194 | DMA_COMPL_SKIP_SRC_UNMAP | |
| 1195 | DMA_COMPL_SKIP_DEST_UNMAP); |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1196 | if (!tx) { |
| 1197 | dev_err(dev, "Self-test 2nd zero prep failed\n"); |
| 1198 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1199 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1200 | } |
| 1201 | |
| 1202 | async_tx_ack(tx); |
| 1203 | init_completion(&cmp); |
| 1204 | tx->callback = ioat3_dma_test_callback; |
| 1205 | tx->callback_param = &cmp; |
| 1206 | cookie = tx->tx_submit(tx); |
| 1207 | if (cookie < 0) { |
| 1208 | dev_err(dev, "Self-test 2nd zero setup failed\n"); |
| 1209 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1210 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1211 | } |
| 1212 | dma->device_issue_pending(dma_chan); |
| 1213 | |
| 1214 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
| 1215 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1216 | if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1217 | dev_err(dev, "Self-test 2nd validate timed out\n"); |
| 1218 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1219 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1220 | } |
| 1221 | |
| 1222 | if (xor_val_result != SUM_CHECK_P_RESULT) { |
| 1223 | dev_err(dev, "Self-test validate failed compare\n"); |
| 1224 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1225 | goto dma_unmap; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1226 | } |
| 1227 | |
Bartlomiej Zolnierkiewicz | 7369f56 | 2012-11-05 10:00:19 +0000 | [diff] [blame] | 1228 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
| 1229 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); |
| 1230 | |
| 1231 | goto free_resources; |
| 1232 | dma_unmap: |
| 1233 | if (op == IOAT_OP_XOR) { |
| 1234 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
| 1235 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) |
| 1236 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, |
| 1237 | DMA_TO_DEVICE); |
| 1238 | } else if (op == IOAT_OP_XOR_VAL) { |
| 1239 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
| 1240 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, |
| 1241 | DMA_TO_DEVICE); |
| 1242 | } else if (op == IOAT_OP_FILL) |
| 1243 | dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1244 | free_resources: |
| 1245 | dma->device_free_chan_resources(dma_chan); |
| 1246 | out: |
| 1247 | src_idx = IOAT_NUM_SRC_TEST; |
| 1248 | while (src_idx--) |
| 1249 | __free_page(xor_srcs[src_idx]); |
| 1250 | __free_page(dest); |
| 1251 | return err; |
| 1252 | } |
| 1253 | |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 1254 | static int ioat3_dma_self_test(struct ioatdma_device *device) |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1255 | { |
| 1256 | int rc = ioat_dma_self_test(device); |
| 1257 | |
| 1258 | if (rc) |
| 1259 | return rc; |
| 1260 | |
| 1261 | rc = ioat_xor_val_self_test(device); |
| 1262 | if (rc) |
| 1263 | return rc; |
| 1264 | |
| 1265 | return 0; |
| 1266 | } |
| 1267 | |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame^] | 1268 | static int ioat3_irq_reinit(struct ioatdma_device *device) |
| 1269 | { |
| 1270 | int msixcnt = device->common.chancnt; |
| 1271 | struct pci_dev *pdev = device->pdev; |
| 1272 | int i; |
| 1273 | struct msix_entry *msix; |
| 1274 | struct ioat_chan_common *chan; |
| 1275 | int err = 0; |
| 1276 | |
| 1277 | switch (device->irq_mode) { |
| 1278 | case IOAT_MSIX: |
| 1279 | |
| 1280 | for (i = 0; i < msixcnt; i++) { |
| 1281 | msix = &device->msix_entries[i]; |
| 1282 | chan = ioat_chan_by_index(device, i); |
| 1283 | devm_free_irq(&pdev->dev, msix->vector, chan); |
| 1284 | } |
| 1285 | |
| 1286 | pci_disable_msix(pdev); |
| 1287 | break; |
| 1288 | |
| 1289 | case IOAT_MSIX_SINGLE: |
| 1290 | msix = &device->msix_entries[0]; |
| 1291 | chan = ioat_chan_by_index(device, 0); |
| 1292 | devm_free_irq(&pdev->dev, msix->vector, chan); |
| 1293 | pci_disable_msix(pdev); |
| 1294 | break; |
| 1295 | |
| 1296 | case IOAT_MSI: |
| 1297 | chan = ioat_chan_by_index(device, 0); |
| 1298 | devm_free_irq(&pdev->dev, pdev->irq, chan); |
| 1299 | pci_disable_msi(pdev); |
| 1300 | break; |
| 1301 | |
| 1302 | case IOAT_INTX: |
| 1303 | chan = ioat_chan_by_index(device, 0); |
| 1304 | devm_free_irq(&pdev->dev, pdev->irq, chan); |
| 1305 | break; |
| 1306 | |
| 1307 | default: |
| 1308 | return 0; |
| 1309 | } |
| 1310 | |
| 1311 | device->irq_mode = IOAT_NOIRQ; |
| 1312 | |
| 1313 | err = ioat_dma_setup_interrupts(device); |
| 1314 | |
| 1315 | return err; |
| 1316 | } |
| 1317 | |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 1318 | static int ioat3_reset_hw(struct ioat_chan_common *chan) |
| 1319 | { |
| 1320 | /* throw away whatever the channel was doing and get it |
| 1321 | * initialized, with ioat3 specific workarounds |
| 1322 | */ |
| 1323 | struct ioatdma_device *device = chan->device; |
| 1324 | struct pci_dev *pdev = device->pdev; |
| 1325 | u32 chanerr; |
| 1326 | u16 dev_id; |
| 1327 | int err; |
| 1328 | |
| 1329 | ioat2_quiesce(chan, msecs_to_jiffies(100)); |
| 1330 | |
| 1331 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); |
| 1332 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); |
| 1333 | |
Dave Jiang | 6decffd | 2012-11-27 15:16:08 -0700 | [diff] [blame] | 1334 | /* clear any pending errors */ |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 1335 | err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); |
| 1336 | if (err) { |
| 1337 | dev_err(&pdev->dev, "channel error register unreachable\n"); |
| 1338 | return err; |
| 1339 | } |
| 1340 | pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr); |
| 1341 | |
| 1342 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit |
| 1343 | * (workaround for spurious config parity error after restart) |
| 1344 | */ |
| 1345 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); |
| 1346 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) |
| 1347 | pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10); |
| 1348 | |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame^] | 1349 | err = ioat2_reset_sync(chan, msecs_to_jiffies(200)); |
| 1350 | if (err) { |
| 1351 | dev_err(&pdev->dev, "Failed to reset!\n"); |
| 1352 | return err; |
Dave Jiang | 1a36306 | 2012-12-03 16:08:37 -0700 | [diff] [blame] | 1353 | } |
| 1354 | |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame^] | 1355 | if (device->irq_mode != IOAT_NOIRQ && is_bwd_ioat(pdev)) |
| 1356 | err = ioat3_irq_reinit(device); |
Dave Jiang | 1a36306 | 2012-12-03 16:08:37 -0700 | [diff] [blame] | 1357 | |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame^] | 1358 | return err; |
Dave Jiang | 570727b | 2013-03-25 14:37:31 -0700 | [diff] [blame] | 1359 | } |
| 1360 | |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 1361 | int ioat3_dma_probe(struct ioatdma_device *device, int dca) |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 1362 | { |
| 1363 | struct pci_dev *pdev = device->pdev; |
Dan Williams | 228c4f5 | 2009-11-19 17:07:10 -0700 | [diff] [blame] | 1364 | int dca_en = system_has_dca_enabled(pdev); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 1365 | struct dma_device *dma; |
| 1366 | struct dma_chan *c; |
| 1367 | struct ioat_chan_common *chan; |
Dan Williams | e323271 | 2009-09-08 17:43:02 -0700 | [diff] [blame] | 1368 | bool is_raid_device = false; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 1369 | int err; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 1370 | u32 cap; |
| 1371 | |
| 1372 | device->enumerate_channels = ioat2_enumerate_channels; |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 1373 | device->reset_hw = ioat3_reset_hw; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1374 | device->self_test = ioat3_dma_self_test; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 1375 | dma = &device->common; |
| 1376 | dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; |
| 1377 | dma->device_issue_pending = ioat2_issue_pending; |
| 1378 | dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; |
| 1379 | dma->device_free_chan_resources = ioat2_free_chan_resources; |
Dan Williams | 58c8649 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 1380 | |
Dave Jiang | 570727b | 2013-03-25 14:37:31 -0700 | [diff] [blame] | 1381 | if (is_xeon_cb32(pdev)) |
Dave Jiang | f26df1a | 2012-04-04 16:10:41 -0700 | [diff] [blame] | 1382 | dma->copy_align = 6; |
| 1383 | |
Dan Williams | 58c8649 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 1384 | dma_cap_set(DMA_INTERRUPT, dma->cap_mask); |
| 1385 | dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock; |
| 1386 | |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 1387 | cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET); |
Dan Williams | 228c4f5 | 2009-11-19 17:07:10 -0700 | [diff] [blame] | 1388 | |
| 1389 | /* dca is incompatible with raid operations */ |
| 1390 | if (dca_en && (cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) |
| 1391 | cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); |
| 1392 | |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 1393 | if (cap & IOAT_CAP_XOR) { |
Dan Williams | e323271 | 2009-09-08 17:43:02 -0700 | [diff] [blame] | 1394 | is_raid_device = true; |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 1395 | dma->max_xor = 8; |
Dan Williams | 2adfc55 | 2010-05-01 15:22:56 -0700 | [diff] [blame] | 1396 | dma->xor_align = 6; |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 1397 | |
| 1398 | dma_cap_set(DMA_XOR, dma->cap_mask); |
| 1399 | dma->device_prep_dma_xor = ioat3_prep_xor; |
| 1400 | |
| 1401 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); |
| 1402 | dma->device_prep_dma_xor_val = ioat3_prep_xor_val; |
| 1403 | } |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 1404 | if (cap & IOAT_CAP_PQ) { |
Dan Williams | e323271 | 2009-09-08 17:43:02 -0700 | [diff] [blame] | 1405 | is_raid_device = true; |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 1406 | dma_set_maxpq(dma, 8, 0); |
Dan Williams | 2adfc55 | 2010-05-01 15:22:56 -0700 | [diff] [blame] | 1407 | dma->pq_align = 6; |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 1408 | |
| 1409 | dma_cap_set(DMA_PQ, dma->cap_mask); |
| 1410 | dma->device_prep_dma_pq = ioat3_prep_pq; |
| 1411 | |
| 1412 | dma_cap_set(DMA_PQ_VAL, dma->cap_mask); |
| 1413 | dma->device_prep_dma_pq_val = ioat3_prep_pq_val; |
Dan Williams | ae78662 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 1414 | |
| 1415 | if (!(cap & IOAT_CAP_XOR)) { |
| 1416 | dma->max_xor = 8; |
Dan Williams | 2adfc55 | 2010-05-01 15:22:56 -0700 | [diff] [blame] | 1417 | dma->xor_align = 6; |
Dan Williams | ae78662 | 2009-09-08 17:43:00 -0700 | [diff] [blame] | 1418 | |
| 1419 | dma_cap_set(DMA_XOR, dma->cap_mask); |
| 1420 | dma->device_prep_dma_xor = ioat3_prep_pqxor; |
| 1421 | |
| 1422 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); |
| 1423 | dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val; |
| 1424 | } |
Dan Williams | d69d235b | 2009-09-08 17:42:59 -0700 | [diff] [blame] | 1425 | } |
Dan Williams | e323271 | 2009-09-08 17:43:02 -0700 | [diff] [blame] | 1426 | if (is_raid_device && (cap & IOAT_CAP_FILL_BLOCK)) { |
| 1427 | dma_cap_set(DMA_MEMSET, dma->cap_mask); |
| 1428 | dma->device_prep_dma_memset = ioat3_prep_memset_lock; |
| 1429 | } |
| 1430 | |
| 1431 | |
Dave Jiang | 9a37f64 | 2013-02-26 09:20:36 -0700 | [diff] [blame] | 1432 | dma->device_tx_status = ioat3_tx_status; |
| 1433 | device->cleanup_fn = ioat3_cleanup_event; |
| 1434 | device->timer_fn = ioat3_timer_event; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 1435 | |
Dan Williams | 7b3cc2b | 2009-11-19 17:10:37 -0700 | [diff] [blame] | 1436 | #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA |
| 1437 | dma_cap_clear(DMA_PQ_VAL, dma->cap_mask); |
| 1438 | dma->device_prep_dma_pq_val = NULL; |
| 1439 | #endif |
| 1440 | |
| 1441 | #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA |
| 1442 | dma_cap_clear(DMA_XOR_VAL, dma->cap_mask); |
| 1443 | dma->device_prep_dma_xor_val = NULL; |
| 1444 | #endif |
| 1445 | |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 1446 | err = ioat_probe(device); |
| 1447 | if (err) |
| 1448 | return err; |
| 1449 | ioat_set_tcp_copy_break(262144); |
| 1450 | |
| 1451 | list_for_each_entry(c, &dma->channels, device_node) { |
| 1452 | chan = to_chan_common(c); |
| 1453 | writel(IOAT_DMA_DCA_ANY_CPU, |
| 1454 | chan->reg_base + IOAT_DCACTRL_OFFSET); |
| 1455 | } |
| 1456 | |
| 1457 | err = ioat_register(device); |
| 1458 | if (err) |
| 1459 | return err; |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 1460 | |
| 1461 | ioat_kobject_add(device, &ioat2_ktype); |
| 1462 | |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 1463 | if (dca) |
| 1464 | device->dca = ioat3_dca_init(pdev, device->reg_base); |
| 1465 | |
| 1466 | return 0; |
| 1467 | } |