Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * mtu3_dr.c - dual role switch and host glue layer |
| 3 | * |
| 4 | * Copyright (C) 2016 MediaTek Inc. |
| 5 | * |
| 6 | * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> |
| 7 | * |
| 8 | * This software is licensed under the terms of the GNU General Public |
| 9 | * License version 2, as published by the Free Software Foundation, and |
| 10 | * may be copied, distributed, and modified under those terms. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | */ |
| 18 | |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/iopoll.h> |
| 21 | #include <linux/irq.h> |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/mfd/syscon.h> |
| 24 | #include <linux/of_device.h> |
| 25 | #include <linux/regmap.h> |
| 26 | |
| 27 | #include "mtu3.h" |
| 28 | #include "mtu3_dr.h" |
| 29 | |
| 30 | #define PERI_WK_CTRL1 0x404 |
| 31 | #define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26) |
| 32 | #define UWK_CTL1_IS_E BIT(25) |
| 33 | #define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */ |
| 34 | #define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */ |
| 35 | #define UWK_CTL1_IDDIG_P BIT(9) /* polarity */ |
| 36 | #define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */ |
| 37 | |
| 38 | /* |
| 39 | * ip-sleep wakeup mode: |
| 40 | * all clocks can be turn off, but power domain should be kept on |
| 41 | */ |
| 42 | static void ssusb_wakeup_ip_sleep_en(struct ssusb_mtk *ssusb) |
| 43 | { |
| 44 | u32 tmp; |
| 45 | struct regmap *pericfg = ssusb->pericfg; |
| 46 | |
| 47 | regmap_read(pericfg, PERI_WK_CTRL1, &tmp); |
| 48 | tmp &= ~UWK_CTL1_IS_P; |
| 49 | tmp &= ~(UWK_CTL1_IS_C(0xf)); |
| 50 | tmp |= UWK_CTL1_IS_C(0x8); |
| 51 | regmap_write(pericfg, PERI_WK_CTRL1, tmp); |
| 52 | regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E); |
| 53 | |
| 54 | regmap_read(pericfg, PERI_WK_CTRL1, &tmp); |
| 55 | dev_dbg(ssusb->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n", |
| 56 | __func__, tmp); |
| 57 | } |
| 58 | |
| 59 | static void ssusb_wakeup_ip_sleep_dis(struct ssusb_mtk *ssusb) |
| 60 | { |
| 61 | u32 tmp; |
| 62 | |
| 63 | regmap_read(ssusb->pericfg, PERI_WK_CTRL1, &tmp); |
| 64 | tmp &= ~UWK_CTL1_IS_E; |
| 65 | regmap_write(ssusb->pericfg, PERI_WK_CTRL1, tmp); |
| 66 | } |
| 67 | |
| 68 | int ssusb_wakeup_of_property_parse(struct ssusb_mtk *ssusb, |
| 69 | struct device_node *dn) |
| 70 | { |
| 71 | struct device *dev = ssusb->dev; |
| 72 | |
| 73 | /* |
| 74 | * Wakeup function is optional, so it is not an error if this property |
| 75 | * does not exist, and in such case, no need to get relative |
| 76 | * properties anymore. |
| 77 | */ |
| 78 | ssusb->wakeup_en = of_property_read_bool(dn, "mediatek,enable-wakeup"); |
| 79 | if (!ssusb->wakeup_en) |
| 80 | return 0; |
| 81 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 82 | ssusb->pericfg = syscon_regmap_lookup_by_phandle(dn, |
| 83 | "mediatek,syscon-wakeup"); |
| 84 | if (IS_ERR(ssusb->pericfg)) { |
| 85 | dev_err(dev, "fail to get pericfg regs\n"); |
| 86 | return PTR_ERR(ssusb->pericfg); |
| 87 | } |
| 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 92 | static void host_ports_num_get(struct ssusb_mtk *ssusb) |
| 93 | { |
| 94 | u32 xhci_cap; |
| 95 | |
| 96 | xhci_cap = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_XHCI_CAP); |
| 97 | ssusb->u2_ports = SSUSB_IP_XHCI_U2_PORT_NUM(xhci_cap); |
| 98 | ssusb->u3_ports = SSUSB_IP_XHCI_U3_PORT_NUM(xhci_cap); |
| 99 | |
| 100 | dev_dbg(ssusb->dev, "host - u2_ports:%d, u3_ports:%d\n", |
| 101 | ssusb->u2_ports, ssusb->u3_ports); |
| 102 | } |
| 103 | |
| 104 | /* only configure ports will be used later */ |
| 105 | int ssusb_host_enable(struct ssusb_mtk *ssusb) |
| 106 | { |
| 107 | void __iomem *ibase = ssusb->ippc_base; |
| 108 | int num_u3p = ssusb->u3_ports; |
| 109 | int num_u2p = ssusb->u2_ports; |
Chunfeng Yun | 076f1a8 | 2017-10-13 17:10:38 +0800 | [diff] [blame] | 110 | int u3_ports_disabed; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 111 | u32 check_clk; |
| 112 | u32 value; |
| 113 | int i; |
| 114 | |
| 115 | /* power on host ip */ |
| 116 | mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN); |
| 117 | |
Chunfeng Yun | 076f1a8 | 2017-10-13 17:10:38 +0800 | [diff] [blame] | 118 | /* power on and enable u3 ports except skipped ones */ |
| 119 | u3_ports_disabed = 0; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 120 | for (i = 0; i < num_u3p; i++) { |
Chunfeng Yun | 076f1a8 | 2017-10-13 17:10:38 +0800 | [diff] [blame] | 121 | if ((0x1 << i) & ssusb->u3p_dis_msk) { |
| 122 | u3_ports_disabed++; |
| 123 | continue; |
| 124 | } |
| 125 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 126 | value = mtu3_readl(ibase, SSUSB_U3_CTRL(i)); |
| 127 | value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS); |
| 128 | value |= SSUSB_U3_PORT_HOST_SEL; |
| 129 | mtu3_writel(ibase, SSUSB_U3_CTRL(i), value); |
| 130 | } |
| 131 | |
| 132 | /* power on and enable all u2 ports */ |
| 133 | for (i = 0; i < num_u2p; i++) { |
| 134 | value = mtu3_readl(ibase, SSUSB_U2_CTRL(i)); |
| 135 | value &= ~(SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS); |
| 136 | value |= SSUSB_U2_PORT_HOST_SEL; |
| 137 | mtu3_writel(ibase, SSUSB_U2_CTRL(i), value); |
| 138 | } |
| 139 | |
| 140 | check_clk = SSUSB_XHCI_RST_B_STS; |
Chunfeng Yun | 076f1a8 | 2017-10-13 17:10:38 +0800 | [diff] [blame] | 141 | if (num_u3p > u3_ports_disabed) |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 142 | check_clk = SSUSB_U3_MAC_RST_B_STS; |
| 143 | |
| 144 | return ssusb_check_clocks(ssusb, check_clk); |
| 145 | } |
| 146 | |
| 147 | int ssusb_host_disable(struct ssusb_mtk *ssusb, bool suspend) |
| 148 | { |
| 149 | void __iomem *ibase = ssusb->ippc_base; |
| 150 | int num_u3p = ssusb->u3_ports; |
| 151 | int num_u2p = ssusb->u2_ports; |
| 152 | u32 value; |
| 153 | int ret; |
| 154 | int i; |
| 155 | |
Chunfeng Yun | 076f1a8 | 2017-10-13 17:10:38 +0800 | [diff] [blame] | 156 | /* power down and disable u3 ports except skipped ones */ |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 157 | for (i = 0; i < num_u3p; i++) { |
Chunfeng Yun | 076f1a8 | 2017-10-13 17:10:38 +0800 | [diff] [blame] | 158 | if ((0x1 << i) & ssusb->u3p_dis_msk) |
| 159 | continue; |
| 160 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 161 | value = mtu3_readl(ibase, SSUSB_U3_CTRL(i)); |
| 162 | value |= SSUSB_U3_PORT_PDN; |
| 163 | value |= suspend ? 0 : SSUSB_U3_PORT_DIS; |
| 164 | mtu3_writel(ibase, SSUSB_U3_CTRL(i), value); |
| 165 | } |
| 166 | |
| 167 | /* power down and disable all u2 ports */ |
| 168 | for (i = 0; i < num_u2p; i++) { |
| 169 | value = mtu3_readl(ibase, SSUSB_U2_CTRL(i)); |
| 170 | value |= SSUSB_U2_PORT_PDN; |
| 171 | value |= suspend ? 0 : SSUSB_U2_PORT_DIS; |
| 172 | mtu3_writel(ibase, SSUSB_U2_CTRL(i), value); |
| 173 | } |
| 174 | |
| 175 | /* power down host ip */ |
| 176 | mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN); |
| 177 | |
| 178 | if (!suspend) |
| 179 | return 0; |
| 180 | |
| 181 | /* wait for host ip to sleep */ |
| 182 | ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value, |
| 183 | (value & SSUSB_IP_SLEEP_STS), 100, 100000); |
| 184 | if (ret) |
| 185 | dev_err(ssusb->dev, "ip sleep failed!!!\n"); |
| 186 | |
| 187 | return ret; |
| 188 | } |
| 189 | |
| 190 | static void ssusb_host_setup(struct ssusb_mtk *ssusb) |
| 191 | { |
Chunfeng Yun | c776f2c | 2017-10-13 17:10:42 +0800 | [diff] [blame] | 192 | struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; |
| 193 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 194 | host_ports_num_get(ssusb); |
| 195 | |
| 196 | /* |
| 197 | * power on host and power on/enable all ports |
| 198 | * if support OTG, gadget driver will switch port0 to device mode |
| 199 | */ |
| 200 | ssusb_host_enable(ssusb); |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 201 | |
Chunfeng Yun | c776f2c | 2017-10-13 17:10:42 +0800 | [diff] [blame] | 202 | if (otg_sx->manual_drd_enabled) |
| 203 | ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST); |
| 204 | |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 205 | /* if port0 supports dual-role, works as host mode by default */ |
| 206 | ssusb_set_vbus(&ssusb->otg_switch, 1); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | static void ssusb_host_cleanup(struct ssusb_mtk *ssusb) |
| 210 | { |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 211 | if (ssusb->is_host) |
| 212 | ssusb_set_vbus(&ssusb->otg_switch, 0); |
| 213 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 214 | ssusb_host_disable(ssusb, false); |
| 215 | } |
| 216 | |
| 217 | /* |
| 218 | * If host supports multiple ports, the VBUSes(5V) of ports except port0 |
| 219 | * which supports OTG are better to be enabled by default in DTS. |
| 220 | * Because the host driver will keep link with devices attached when system |
| 221 | * enters suspend mode, so no need to control VBUSes after initialization. |
| 222 | */ |
| 223 | int ssusb_host_init(struct ssusb_mtk *ssusb, struct device_node *parent_dn) |
| 224 | { |
| 225 | struct device *parent_dev = ssusb->dev; |
| 226 | int ret; |
| 227 | |
| 228 | ssusb_host_setup(ssusb); |
| 229 | |
| 230 | ret = of_platform_populate(parent_dn, NULL, NULL, parent_dev); |
| 231 | if (ret) { |
Rob Herring | d9241ff | 2017-07-18 16:43:35 -0500 | [diff] [blame] | 232 | dev_dbg(parent_dev, "failed to create child devices at %pOF\n", |
| 233 | parent_dn); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 234 | return ret; |
| 235 | } |
| 236 | |
| 237 | dev_info(parent_dev, "xHCI platform device register success...\n"); |
| 238 | |
| 239 | return 0; |
| 240 | } |
| 241 | |
| 242 | void ssusb_host_exit(struct ssusb_mtk *ssusb) |
| 243 | { |
| 244 | of_platform_depopulate(ssusb->dev); |
| 245 | ssusb_host_cleanup(ssusb); |
| 246 | } |
| 247 | |
| 248 | int ssusb_wakeup_enable(struct ssusb_mtk *ssusb) |
| 249 | { |
Chunfeng Yun | d90223a | 2017-10-13 17:10:39 +0800 | [diff] [blame] | 250 | if (ssusb->wakeup_en) |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 251 | ssusb_wakeup_ip_sleep_en(ssusb); |
Chunfeng Yun | d90223a | 2017-10-13 17:10:39 +0800 | [diff] [blame] | 252 | |
| 253 | return 0; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | void ssusb_wakeup_disable(struct ssusb_mtk *ssusb) |
| 257 | { |
Chunfeng Yun | d90223a | 2017-10-13 17:10:39 +0800 | [diff] [blame] | 258 | if (ssusb->wakeup_en) |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 259 | ssusb_wakeup_ip_sleep_dis(ssusb); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 260 | } |