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gerrit-public.fairphone.software / kernel / msm-5.4 / 8b24e69fc47e43679bb29ddb481aa0e8dce2a3c5 / . / arch / powerpc / kvm / book3s_hv_interrupts.S
blob: dc54373c878010b6419f02568ad8626b53c474c8 [file] [log] [blame]
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
16 *
17 * Derived from book3s_interrupts.S, which is:
18 * Copyright SUSE Linux Products GmbH 2009
19 *
20 * Authors: Alexander Graf <agraf@suse.de>
21 */
22
23#include <asm/ppc_asm.h>
24#include <asm/kvm_asm.h>
25#include <asm/reg.h>
26#include <asm/page.h>
27#include <asm/asm-offsets.h>
28#include <asm/exception-64s.h>
29#include <asm/ppc-opcode.h>
30
31/*****************************************************************************
32 * *
33 * Guest entry / exit code that is in kernel module memory (vmalloc) *
34 * *
35 ****************************************************************************/
36
37/* Registers:
Paul Mackerrase0b7ec02014-01-08 21:25:20 +1100[diff] [blame]38 * none
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]39 */
40_GLOBAL(__kvmppc_vcore_entry)
41
42 /* Write correct stack frame */
43 mflr r0
44 std r0,PPC_LR_STKOFF(r1)
45
46 /* Save host state to the stack */
47 stdu r1, -SWITCH_FRAME_SIZE(r1)
48
Paul Mackerrasa5ddea02012-02-03 00:53:21 +0000[diff] [blame]49 /* Save non-volatile registers (r14 - r31) and CR */
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]50 SAVE_NVGPRS(r1)
Paul Mackerrasa5ddea02012-02-03 00:53:21 +0000[diff] [blame]51 mfcr r3
52 std r3, _CCR(r1)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]53
54 /* Save host DSCR */
55 mfspr r3, SPRN_DSCR
56 std r3, HSTATE_DSCR(r13)
57
Michael Neulingeee7ff92014-01-08 21:25:19 +1100[diff] [blame]58BEGIN_FTR_SECTION
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]59 /* Save host DABR */
60 mfspr r3, SPRN_DABR
61 std r3, HSTATE_DABR(r13)
Michael Neulingeee7ff92014-01-08 21:25:19 +1100[diff] [blame]62END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]63
Paul Mackerras89436332012-03-02 01:38:23 +0000[diff] [blame]64 /* Save host PMU registers */
Paul Mackerras72cde5a2014-03-25 10:47:08 +1100[diff] [blame]65BEGIN_FTR_SECTION
66 /* Work around P8 PMAE bug */
67 li r3, -1
68 clrrdi r3, r3, 10
69 mfspr r8, SPRN_MMCR2
70 mtspr SPRN_MMCR2, r3 /* freeze all counters using MMCR2 */
71 isync
72END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]73 li r3, 1
74 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
75 mfspr r7, SPRN_MMCR0 /* save MMCR0 */
76 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
Paul Mackerras89436332012-03-02 01:38:23 +0000[diff] [blame]77 mfspr r6, SPRN_MMCRA
Paul Mackerrasc17b98c2014-12-03 13:30:38 +1100[diff] [blame]78 /* Clear MMCRA in order to disable SDAR updates */
Paul Mackerras89436332012-03-02 01:38:23 +0000[diff] [blame]79 li r5, 0
80 mtspr SPRN_MMCRA, r5
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]81 isync
82 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
83 lbz r5, LPPACA_PMCINUSE(r3)
84 cmpwi r5, 0
85 beq 31f /* skip if not */
86 mfspr r5, SPRN_MMCR1
Paul Mackerras72cde5a2014-03-25 10:47:08 +1100[diff] [blame]87 mfspr r9, SPRN_SIAR
88 mfspr r10, SPRN_SDAR
Michael Ellerman9a4fc4e2014-07-10 19:34:31 +1000[diff] [blame]89 std r7, HSTATE_MMCR0(r13)
90 std r5, HSTATE_MMCR1(r13)
91 std r6, HSTATE_MMCRA(r13)
92 std r9, HSTATE_SIAR(r13)
93 std r10, HSTATE_SDAR(r13)
Paul Mackerras72cde5a2014-03-25 10:47:08 +1100[diff] [blame]94BEGIN_FTR_SECTION
95 mfspr r9, SPRN_SIER
Michael Ellerman9a4fc4e2014-07-10 19:34:31 +1000[diff] [blame]96 std r8, HSTATE_MMCR2(r13)
97 std r9, HSTATE_SIER(r13)
Paul Mackerras72cde5a2014-03-25 10:47:08 +1100[diff] [blame]98END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]99 mfspr r3, SPRN_PMC1
100 mfspr r5, SPRN_PMC2
101 mfspr r6, SPRN_PMC3
102 mfspr r7, SPRN_PMC4
103 mfspr r8, SPRN_PMC5
104 mfspr r9, SPRN_PMC6
Michael Ellerman9a4fc4e2014-07-10 19:34:31 +1000[diff] [blame]105 stw r3, HSTATE_PMC1(r13)
106 stw r5, HSTATE_PMC2(r13)
107 stw r6, HSTATE_PMC3(r13)
108 stw r7, HSTATE_PMC4(r13)
109 stw r8, HSTATE_PMC5(r13)
110 stw r9, HSTATE_PMC6(r13)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]11131:
112
113 /*
114 * Put whatever is in the decrementer into the
115 * hypervisor decrementer.
116 */
Paul Mackerras2f272462017-05-22 16:25:14 +1000[diff] [blame]117BEGIN_FTR_SECTION
118 ld r5, HSTATE_KVM_VCORE(r13)
119 ld r6, VCORE_KVM(r5)
120 ld r9, KVM_HOST_LPCR(r6)
121 andis. r9, r9, LPCR_LD@h
122END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]123 mfspr r8,SPRN_DEC
124 mftb r7
Paul Mackerras2f272462017-05-22 16:25:14 +1000[diff] [blame]125BEGIN_FTR_SECTION
126 /* On POWER9, don't sign-extend if host LPCR[LD] bit is set */
127 bne 32f
128END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]129 extsw r8,r8
Paul Mackerras2f272462017-05-22 16:25:14 +1000[diff] [blame]13032: mtspr SPRN_HDEC,r8
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]131 add r8,r8,r7
132 std r8,HSTATE_DECEXP(r13)
133
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]134 /* Jump to partition switch code */
Anton Blanchardb1576fe2014-02-04 16:04:35 +1100[diff] [blame]135 bl kvmppc_hv_entry_trampoline
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]136 nop
137
138/*
139 * We return here in virtual mode after the guest exits
140 * with something that we can't handle in real mode.
141 * Interrupts are enabled again at this point.
142 */
143
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]144 /*
145 * Register usage at this point:
146 *
147 * R1 = host R1
148 * R2 = host R2
Paul Mackerras8b24e692017-06-26 15:45:51 +1000[diff] [blame^]149 * R3 = trap number on this thread
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]150 * R12 = exit handler id
151 * R13 = PACA
152 */
153
Paul Mackerrasa5ddea02012-02-03 00:53:21 +0000[diff] [blame]154 /* Restore non-volatile host registers (r14 - r31) and CR */
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]155 REST_NVGPRS(r1)
Paul Mackerrasa5ddea02012-02-03 00:53:21 +0000[diff] [blame]156 ld r4, _CCR(r1)
157 mtcr r4
Paul Mackerrasde56a942011-06-29 00:21:34 +0000[diff] [blame]158
159 addi r1, r1, SWITCH_FRAME_SIZE
160 ld r0, PPC_LR_STKOFF(r1)
161 mtlr r0
162 blr