Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 1 | /* |
Gertjan van Wingerde | 9c9a0d1 | 2009-11-08 16:39:55 +0100 | [diff] [blame] | 2 | Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> |
Gertjan van Wingerde | cce5fc4 | 2009-11-10 22:42:40 +0100 | [diff] [blame] | 3 | Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 4 | |
Gertjan van Wingerde | 9c9a0d1 | 2009-11-08 16:39:55 +0100 | [diff] [blame] | 5 | Based on the original rt2800pci.c and rt2800usb.c. |
| 6 | Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com> |
| 7 | Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> |
| 8 | Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> |
| 9 | Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> |
| 10 | Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> |
| 11 | Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> |
| 12 | Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 13 | <http://rt2x00.serialmonkey.com> |
| 14 | |
| 15 | This program is free software; you can redistribute it and/or modify |
| 16 | it under the terms of the GNU General Public License as published by |
| 17 | the Free Software Foundation; either version 2 of the License, or |
| 18 | (at your option) any later version. |
| 19 | |
| 20 | This program is distributed in the hope that it will be useful, |
| 21 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | GNU General Public License for more details. |
| 24 | |
| 25 | You should have received a copy of the GNU General Public License |
| 26 | along with this program; if not, write to the |
| 27 | Free Software Foundation, Inc., |
| 28 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 29 | */ |
| 30 | |
| 31 | /* |
| 32 | Module: rt2800lib |
| 33 | Abstract: rt2800 generic device routines. |
| 34 | */ |
| 35 | |
| 36 | #include <linux/kernel.h> |
| 37 | #include <linux/module.h> |
| 38 | |
| 39 | #include "rt2x00.h" |
Gertjan van Wingerde | ac39491 | 2009-12-23 00:03:23 +0100 | [diff] [blame] | 40 | #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE) |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 41 | #include "rt2x00usb.h" |
| 42 | #endif |
Gertjan van Wingerde | 714fa66 | 2010-02-13 20:55:48 +0100 | [diff] [blame] | 43 | #if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE) |
| 44 | #include "rt2x00pci.h" |
| 45 | #endif |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 46 | #include "rt2800lib.h" |
| 47 | #include "rt2800.h" |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 48 | #include "rt2800usb.h" |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 49 | |
| 50 | MODULE_AUTHOR("Bartlomiej Zolnierkiewicz"); |
| 51 | MODULE_DESCRIPTION("rt2800 library"); |
| 52 | MODULE_LICENSE("GPL"); |
| 53 | |
| 54 | /* |
| 55 | * Register access. |
| 56 | * All access to the CSR registers will go through the methods |
| 57 | * rt2800_register_read and rt2800_register_write. |
| 58 | * BBP and RF register require indirect register access, |
| 59 | * and use the CSR registers BBPCSR and RFCSR to achieve this. |
| 60 | * These indirect registers work with busy bits, |
| 61 | * and we will try maximal REGISTER_BUSY_COUNT times to access |
| 62 | * the register while taking a REGISTER_BUSY_DELAY us delay |
| 63 | * between each attampt. When the busy bit is still set at that time, |
| 64 | * the access attempt is considered to have failed, |
| 65 | * and we will print an error. |
| 66 | * The _lock versions must be used if you already hold the csr_mutex |
| 67 | */ |
| 68 | #define WAIT_FOR_BBP(__dev, __reg) \ |
| 69 | rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) |
| 70 | #define WAIT_FOR_RFCSR(__dev, __reg) \ |
| 71 | rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) |
| 72 | #define WAIT_FOR_RF(__dev, __reg) \ |
| 73 | rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) |
| 74 | #define WAIT_FOR_MCU(__dev, __reg) \ |
| 75 | rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ |
| 76 | H2M_MAILBOX_CSR_OWNER, (__reg)) |
| 77 | |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 78 | static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, |
| 79 | const unsigned int word, const u8 value) |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 80 | { |
| 81 | u32 reg; |
| 82 | |
| 83 | mutex_lock(&rt2x00dev->csr_mutex); |
| 84 | |
| 85 | /* |
| 86 | * Wait until the BBP becomes available, afterwards we |
| 87 | * can safely write the new data into the register. |
| 88 | */ |
| 89 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
| 90 | reg = 0; |
| 91 | rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); |
| 92 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); |
| 93 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); |
| 94 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 95 | if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 96 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); |
| 97 | |
| 98 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); |
| 99 | } |
| 100 | |
| 101 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 102 | } |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 103 | |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 104 | static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, |
| 105 | const unsigned int word, u8 *value) |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 106 | { |
| 107 | u32 reg; |
| 108 | |
| 109 | mutex_lock(&rt2x00dev->csr_mutex); |
| 110 | |
| 111 | /* |
| 112 | * Wait until the BBP becomes available, afterwards we |
| 113 | * can safely write the read request into the register. |
| 114 | * After the data has been written, we wait until hardware |
| 115 | * returns the correct value, if at any time the register |
| 116 | * doesn't become available in time, reg will be 0xffffffff |
| 117 | * which means we return 0xff to the caller. |
| 118 | */ |
| 119 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
| 120 | reg = 0; |
| 121 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); |
| 122 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); |
| 123 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 124 | if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 125 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); |
| 126 | |
| 127 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); |
| 128 | |
| 129 | WAIT_FOR_BBP(rt2x00dev, ®); |
| 130 | } |
| 131 | |
| 132 | *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); |
| 133 | |
| 134 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 135 | } |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 136 | |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 137 | static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, |
| 138 | const unsigned int word, const u8 value) |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 139 | { |
| 140 | u32 reg; |
| 141 | |
| 142 | mutex_lock(&rt2x00dev->csr_mutex); |
| 143 | |
| 144 | /* |
| 145 | * Wait until the RFCSR becomes available, afterwards we |
| 146 | * can safely write the new data into the register. |
| 147 | */ |
| 148 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { |
| 149 | reg = 0; |
| 150 | rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); |
| 151 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); |
| 152 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); |
| 153 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); |
| 154 | |
| 155 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); |
| 156 | } |
| 157 | |
| 158 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 159 | } |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 160 | |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 161 | static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, |
| 162 | const unsigned int word, u8 *value) |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 163 | { |
| 164 | u32 reg; |
| 165 | |
| 166 | mutex_lock(&rt2x00dev->csr_mutex); |
| 167 | |
| 168 | /* |
| 169 | * Wait until the RFCSR becomes available, afterwards we |
| 170 | * can safely write the read request into the register. |
| 171 | * After the data has been written, we wait until hardware |
| 172 | * returns the correct value, if at any time the register |
| 173 | * doesn't become available in time, reg will be 0xffffffff |
| 174 | * which means we return 0xff to the caller. |
| 175 | */ |
| 176 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { |
| 177 | reg = 0; |
| 178 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); |
| 179 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); |
| 180 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); |
| 181 | |
| 182 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); |
| 183 | |
| 184 | WAIT_FOR_RFCSR(rt2x00dev, ®); |
| 185 | } |
| 186 | |
| 187 | *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); |
| 188 | |
| 189 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 190 | } |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 191 | |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 192 | static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, |
| 193 | const unsigned int word, const u32 value) |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 194 | { |
| 195 | u32 reg; |
| 196 | |
| 197 | mutex_lock(&rt2x00dev->csr_mutex); |
| 198 | |
| 199 | /* |
| 200 | * Wait until the RF becomes available, afterwards we |
| 201 | * can safely write the new data into the register. |
| 202 | */ |
| 203 | if (WAIT_FOR_RF(rt2x00dev, ®)) { |
| 204 | reg = 0; |
| 205 | rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); |
| 206 | rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); |
| 207 | rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); |
| 208 | rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); |
| 209 | |
| 210 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); |
| 211 | rt2x00_rf_write(rt2x00dev, word, value); |
| 212 | } |
| 213 | |
| 214 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 215 | } |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 216 | |
| 217 | void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, |
| 218 | const u8 command, const u8 token, |
| 219 | const u8 arg0, const u8 arg1) |
| 220 | { |
| 221 | u32 reg; |
| 222 | |
Gertjan van Wingerde | ee303e5 | 2009-11-23 22:44:49 +0100 | [diff] [blame] | 223 | /* |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 224 | * SOC devices don't support MCU requests. |
Gertjan van Wingerde | ee303e5 | 2009-11-23 22:44:49 +0100 | [diff] [blame] | 225 | */ |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 226 | if (rt2x00_is_soc(rt2x00dev)) |
Gertjan van Wingerde | ee303e5 | 2009-11-23 22:44:49 +0100 | [diff] [blame] | 227 | return; |
Bartlomiej Zolnierkiewicz | 8929742 | 2009-11-04 18:36:24 +0100 | [diff] [blame] | 228 | |
| 229 | mutex_lock(&rt2x00dev->csr_mutex); |
| 230 | |
| 231 | /* |
| 232 | * Wait until the MCU becomes available, afterwards we |
| 233 | * can safely write the new data into the register. |
| 234 | */ |
| 235 | if (WAIT_FOR_MCU(rt2x00dev, ®)) { |
| 236 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); |
| 237 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); |
| 238 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); |
| 239 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); |
| 240 | rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); |
| 241 | |
| 242 | reg = 0; |
| 243 | rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); |
| 244 | rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); |
| 245 | } |
| 246 | |
| 247 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 248 | } |
| 249 | EXPORT_SYMBOL_GPL(rt2800_mcu_request); |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 250 | |
Gertjan van Wingerde | 67a4c1e | 2009-12-30 11:36:32 +0100 | [diff] [blame] | 251 | int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) |
| 252 | { |
| 253 | unsigned int i; |
| 254 | u32 reg; |
| 255 | |
| 256 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
| 257 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); |
| 258 | if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && |
| 259 | !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) |
| 260 | return 0; |
| 261 | |
| 262 | msleep(1); |
| 263 | } |
| 264 | |
| 265 | ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n"); |
| 266 | return -EACCES; |
| 267 | } |
| 268 | EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); |
| 269 | |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 270 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
| 271 | const struct rt2x00debug rt2800_rt2x00debug = { |
| 272 | .owner = THIS_MODULE, |
| 273 | .csr = { |
| 274 | .read = rt2800_register_read, |
| 275 | .write = rt2800_register_write, |
| 276 | .flags = RT2X00DEBUGFS_OFFSET, |
| 277 | .word_base = CSR_REG_BASE, |
| 278 | .word_size = sizeof(u32), |
| 279 | .word_count = CSR_REG_SIZE / sizeof(u32), |
| 280 | }, |
| 281 | .eeprom = { |
| 282 | .read = rt2x00_eeprom_read, |
| 283 | .write = rt2x00_eeprom_write, |
| 284 | .word_base = EEPROM_BASE, |
| 285 | .word_size = sizeof(u16), |
| 286 | .word_count = EEPROM_SIZE / sizeof(u16), |
| 287 | }, |
| 288 | .bbp = { |
| 289 | .read = rt2800_bbp_read, |
| 290 | .write = rt2800_bbp_write, |
| 291 | .word_base = BBP_BASE, |
| 292 | .word_size = sizeof(u8), |
| 293 | .word_count = BBP_SIZE / sizeof(u8), |
| 294 | }, |
| 295 | .rf = { |
| 296 | .read = rt2x00_rf_read, |
| 297 | .write = rt2800_rf_write, |
| 298 | .word_base = RF_BASE, |
| 299 | .word_size = sizeof(u32), |
| 300 | .word_count = RF_SIZE / sizeof(u32), |
| 301 | }, |
| 302 | }; |
| 303 | EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); |
| 304 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 305 | |
| 306 | int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
| 307 | { |
| 308 | u32 reg; |
| 309 | |
| 310 | rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®); |
| 311 | return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2); |
| 312 | } |
| 313 | EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); |
| 314 | |
| 315 | #ifdef CONFIG_RT2X00_LIB_LEDS |
| 316 | static void rt2800_brightness_set(struct led_classdev *led_cdev, |
| 317 | enum led_brightness brightness) |
| 318 | { |
| 319 | struct rt2x00_led *led = |
| 320 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 321 | unsigned int enabled = brightness != LED_OFF; |
| 322 | unsigned int bg_mode = |
| 323 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); |
| 324 | unsigned int polarity = |
| 325 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, |
| 326 | EEPROM_FREQ_LED_POLARITY); |
| 327 | unsigned int ledmode = |
| 328 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, |
| 329 | EEPROM_FREQ_LED_MODE); |
| 330 | |
| 331 | if (led->type == LED_TYPE_RADIO) { |
| 332 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, |
| 333 | enabled ? 0x20 : 0); |
| 334 | } else if (led->type == LED_TYPE_ASSOC) { |
| 335 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, |
| 336 | enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); |
| 337 | } else if (led->type == LED_TYPE_QUALITY) { |
| 338 | /* |
| 339 | * The brightness is divided into 6 levels (0 - 5), |
| 340 | * The specs tell us the following levels: |
| 341 | * 0, 1 ,3, 7, 15, 31 |
| 342 | * to determine the level in a simple way we can simply |
| 343 | * work with bitshifting: |
| 344 | * (1 << level) - 1 |
| 345 | */ |
| 346 | rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, |
| 347 | (1 << brightness / (LED_FULL / 6)) - 1, |
| 348 | polarity); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | static int rt2800_blink_set(struct led_classdev *led_cdev, |
| 353 | unsigned long *delay_on, unsigned long *delay_off) |
| 354 | { |
| 355 | struct rt2x00_led *led = |
| 356 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 357 | u32 reg; |
| 358 | |
| 359 | rt2800_register_read(led->rt2x00dev, LED_CFG, ®); |
| 360 | rt2x00_set_field32(®, LED_CFG_ON_PERIOD, *delay_on); |
| 361 | rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, *delay_off); |
| 362 | rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); |
| 363 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); |
Gertjan van Wingerde | 301a823 | 2009-12-30 11:36:33 +0100 | [diff] [blame] | 364 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 365 | rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); |
| 366 | rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); |
| 367 | rt2800_register_write(led->rt2x00dev, LED_CFG, reg); |
| 368 | |
| 369 | return 0; |
| 370 | } |
| 371 | |
Gertjan van Wingerde | b3579d6 | 2009-12-30 11:36:34 +0100 | [diff] [blame] | 372 | static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 373 | struct rt2x00_led *led, enum led_type type) |
| 374 | { |
| 375 | led->rt2x00dev = rt2x00dev; |
| 376 | led->type = type; |
| 377 | led->led_dev.brightness_set = rt2800_brightness_set; |
| 378 | led->led_dev.blink_set = rt2800_blink_set; |
| 379 | led->flags = LED_INITIALIZED; |
| 380 | } |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 381 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
| 382 | |
| 383 | /* |
| 384 | * Configuration handlers. |
| 385 | */ |
| 386 | static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev, |
| 387 | struct rt2x00lib_crypto *crypto, |
| 388 | struct ieee80211_key_conf *key) |
| 389 | { |
| 390 | struct mac_wcid_entry wcid_entry; |
| 391 | struct mac_iveiv_entry iveiv_entry; |
| 392 | u32 offset; |
| 393 | u32 reg; |
| 394 | |
| 395 | offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); |
| 396 | |
| 397 | rt2800_register_read(rt2x00dev, offset, ®); |
| 398 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, |
| 399 | !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); |
| 400 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, |
| 401 | (crypto->cmd == SET_KEY) * crypto->cipher); |
| 402 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, |
| 403 | (crypto->cmd == SET_KEY) * crypto->bssidx); |
| 404 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); |
| 405 | rt2800_register_write(rt2x00dev, offset, reg); |
| 406 | |
| 407 | offset = MAC_IVEIV_ENTRY(key->hw_key_idx); |
| 408 | |
| 409 | memset(&iveiv_entry, 0, sizeof(iveiv_entry)); |
| 410 | if ((crypto->cipher == CIPHER_TKIP) || |
| 411 | (crypto->cipher == CIPHER_TKIP_NO_MIC) || |
| 412 | (crypto->cipher == CIPHER_AES)) |
| 413 | iveiv_entry.iv[3] |= 0x20; |
| 414 | iveiv_entry.iv[3] |= key->keyidx << 6; |
| 415 | rt2800_register_multiwrite(rt2x00dev, offset, |
| 416 | &iveiv_entry, sizeof(iveiv_entry)); |
| 417 | |
| 418 | offset = MAC_WCID_ENTRY(key->hw_key_idx); |
| 419 | |
| 420 | memset(&wcid_entry, 0, sizeof(wcid_entry)); |
| 421 | if (crypto->cmd == SET_KEY) |
| 422 | memcpy(&wcid_entry, crypto->address, ETH_ALEN); |
| 423 | rt2800_register_multiwrite(rt2x00dev, offset, |
| 424 | &wcid_entry, sizeof(wcid_entry)); |
| 425 | } |
| 426 | |
| 427 | int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, |
| 428 | struct rt2x00lib_crypto *crypto, |
| 429 | struct ieee80211_key_conf *key) |
| 430 | { |
| 431 | struct hw_key_entry key_entry; |
| 432 | struct rt2x00_field32 field; |
| 433 | u32 offset; |
| 434 | u32 reg; |
| 435 | |
| 436 | if (crypto->cmd == SET_KEY) { |
| 437 | key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; |
| 438 | |
| 439 | memcpy(key_entry.key, crypto->key, |
| 440 | sizeof(key_entry.key)); |
| 441 | memcpy(key_entry.tx_mic, crypto->tx_mic, |
| 442 | sizeof(key_entry.tx_mic)); |
| 443 | memcpy(key_entry.rx_mic, crypto->rx_mic, |
| 444 | sizeof(key_entry.rx_mic)); |
| 445 | |
| 446 | offset = SHARED_KEY_ENTRY(key->hw_key_idx); |
| 447 | rt2800_register_multiwrite(rt2x00dev, offset, |
| 448 | &key_entry, sizeof(key_entry)); |
| 449 | } |
| 450 | |
| 451 | /* |
| 452 | * The cipher types are stored over multiple registers |
| 453 | * starting with SHARED_KEY_MODE_BASE each word will have |
| 454 | * 32 bits and contains the cipher types for 2 bssidx each. |
| 455 | * Using the correct defines correctly will cause overhead, |
| 456 | * so just calculate the correct offset. |
| 457 | */ |
| 458 | field.bit_offset = 4 * (key->hw_key_idx % 8); |
| 459 | field.bit_mask = 0x7 << field.bit_offset; |
| 460 | |
| 461 | offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); |
| 462 | |
| 463 | rt2800_register_read(rt2x00dev, offset, ®); |
| 464 | rt2x00_set_field32(®, field, |
| 465 | (crypto->cmd == SET_KEY) * crypto->cipher); |
| 466 | rt2800_register_write(rt2x00dev, offset, reg); |
| 467 | |
| 468 | /* |
| 469 | * Update WCID information |
| 470 | */ |
| 471 | rt2800_config_wcid_attr(rt2x00dev, crypto, key); |
| 472 | |
| 473 | return 0; |
| 474 | } |
| 475 | EXPORT_SYMBOL_GPL(rt2800_config_shared_key); |
| 476 | |
| 477 | int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, |
| 478 | struct rt2x00lib_crypto *crypto, |
| 479 | struct ieee80211_key_conf *key) |
| 480 | { |
| 481 | struct hw_key_entry key_entry; |
| 482 | u32 offset; |
| 483 | |
| 484 | if (crypto->cmd == SET_KEY) { |
| 485 | /* |
| 486 | * 1 pairwise key is possible per AID, this means that the AID |
| 487 | * equals our hw_key_idx. Make sure the WCID starts _after_ the |
| 488 | * last possible shared key entry. |
| 489 | */ |
| 490 | if (crypto->aid > (256 - 32)) |
| 491 | return -ENOSPC; |
| 492 | |
| 493 | key->hw_key_idx = 32 + crypto->aid; |
| 494 | |
| 495 | memcpy(key_entry.key, crypto->key, |
| 496 | sizeof(key_entry.key)); |
| 497 | memcpy(key_entry.tx_mic, crypto->tx_mic, |
| 498 | sizeof(key_entry.tx_mic)); |
| 499 | memcpy(key_entry.rx_mic, crypto->rx_mic, |
| 500 | sizeof(key_entry.rx_mic)); |
| 501 | |
| 502 | offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); |
| 503 | rt2800_register_multiwrite(rt2x00dev, offset, |
| 504 | &key_entry, sizeof(key_entry)); |
| 505 | } |
| 506 | |
| 507 | /* |
| 508 | * Update WCID information |
| 509 | */ |
| 510 | rt2800_config_wcid_attr(rt2x00dev, crypto, key); |
| 511 | |
| 512 | return 0; |
| 513 | } |
| 514 | EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); |
| 515 | |
| 516 | void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, |
| 517 | const unsigned int filter_flags) |
| 518 | { |
| 519 | u32 reg; |
| 520 | |
| 521 | /* |
| 522 | * Start configuration steps. |
| 523 | * Note that the version error will always be dropped |
| 524 | * and broadcast frames will always be accepted since |
| 525 | * there is no filter for it at this time. |
| 526 | */ |
| 527 | rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); |
| 528 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, |
| 529 | !(filter_flags & FIF_FCSFAIL)); |
| 530 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, |
| 531 | !(filter_flags & FIF_PLCPFAIL)); |
| 532 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, |
| 533 | !(filter_flags & FIF_PROMISC_IN_BSS)); |
| 534 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); |
| 535 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); |
| 536 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, |
| 537 | !(filter_flags & FIF_ALLMULTI)); |
| 538 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); |
| 539 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); |
| 540 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, |
| 541 | !(filter_flags & FIF_CONTROL)); |
| 542 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, |
| 543 | !(filter_flags & FIF_CONTROL)); |
| 544 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, |
| 545 | !(filter_flags & FIF_CONTROL)); |
| 546 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, |
| 547 | !(filter_flags & FIF_CONTROL)); |
| 548 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, |
| 549 | !(filter_flags & FIF_CONTROL)); |
| 550 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, |
| 551 | !(filter_flags & FIF_PSPOLL)); |
| 552 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 1); |
| 553 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 0); |
| 554 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, |
| 555 | !(filter_flags & FIF_CONTROL)); |
| 556 | rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); |
| 557 | } |
| 558 | EXPORT_SYMBOL_GPL(rt2800_config_filter); |
| 559 | |
| 560 | void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, |
| 561 | struct rt2x00intf_conf *conf, const unsigned int flags) |
| 562 | { |
| 563 | unsigned int beacon_base; |
| 564 | u32 reg; |
| 565 | |
| 566 | if (flags & CONFIG_UPDATE_TYPE) { |
| 567 | /* |
| 568 | * Clear current synchronisation setup. |
| 569 | * For the Beacon base registers we only need to clear |
| 570 | * the first byte since that byte contains the VALID and OWNER |
| 571 | * bits which (when set to 0) will invalidate the entire beacon. |
| 572 | */ |
| 573 | beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); |
| 574 | rt2800_register_write(rt2x00dev, beacon_base, 0); |
| 575 | |
| 576 | /* |
| 577 | * Enable synchronisation. |
| 578 | */ |
| 579 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); |
| 580 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1); |
| 581 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); |
Josef Bacik | 6a62e5e | 2009-11-15 21:33:18 -0500 | [diff] [blame] | 582 | rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, |
| 583 | (conf->sync == TSF_SYNC_BEACON)); |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 584 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
| 585 | } |
| 586 | |
| 587 | if (flags & CONFIG_UPDATE_MAC) { |
| 588 | reg = le32_to_cpu(conf->mac[1]); |
| 589 | rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); |
| 590 | conf->mac[1] = cpu_to_le32(reg); |
| 591 | |
| 592 | rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, |
| 593 | conf->mac, sizeof(conf->mac)); |
| 594 | } |
| 595 | |
| 596 | if (flags & CONFIG_UPDATE_BSSID) { |
| 597 | reg = le32_to_cpu(conf->bssid[1]); |
| 598 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 0); |
| 599 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); |
| 600 | conf->bssid[1] = cpu_to_le32(reg); |
| 601 | |
| 602 | rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, |
| 603 | conf->bssid, sizeof(conf->bssid)); |
| 604 | } |
| 605 | } |
| 606 | EXPORT_SYMBOL_GPL(rt2800_config_intf); |
| 607 | |
| 608 | void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp) |
| 609 | { |
| 610 | u32 reg; |
| 611 | |
| 612 | rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); |
| 613 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20); |
| 614 | rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); |
| 615 | |
| 616 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); |
| 617 | rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, |
| 618 | !!erp->short_preamble); |
| 619 | rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, |
| 620 | !!erp->short_preamble); |
| 621 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); |
| 622 | |
| 623 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); |
| 624 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, |
| 625 | erp->cts_protection ? 2 : 0); |
| 626 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); |
| 627 | |
| 628 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, |
| 629 | erp->basic_rates); |
| 630 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); |
| 631 | |
| 632 | rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); |
| 633 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); |
| 634 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); |
| 635 | rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); |
| 636 | |
| 637 | rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); |
| 638 | rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs); |
| 639 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs); |
| 640 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); |
| 641 | rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); |
| 642 | rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); |
| 643 | rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); |
| 644 | |
| 645 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); |
| 646 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, |
| 647 | erp->beacon_int * 16); |
| 648 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
| 649 | } |
| 650 | EXPORT_SYMBOL_GPL(rt2800_config_erp); |
| 651 | |
| 652 | void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) |
| 653 | { |
| 654 | u8 r1; |
| 655 | u8 r3; |
| 656 | |
| 657 | rt2800_bbp_read(rt2x00dev, 1, &r1); |
| 658 | rt2800_bbp_read(rt2x00dev, 3, &r3); |
| 659 | |
| 660 | /* |
| 661 | * Configure the TX antenna. |
| 662 | */ |
| 663 | switch ((int)ant->tx) { |
| 664 | case 1: |
| 665 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 666 | if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 667 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); |
| 668 | break; |
| 669 | case 2: |
| 670 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); |
| 671 | break; |
| 672 | case 3: |
| 673 | /* Do nothing */ |
| 674 | break; |
| 675 | } |
| 676 | |
| 677 | /* |
| 678 | * Configure the RX antenna. |
| 679 | */ |
| 680 | switch ((int)ant->rx) { |
| 681 | case 1: |
| 682 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); |
| 683 | break; |
| 684 | case 2: |
| 685 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); |
| 686 | break; |
| 687 | case 3: |
| 688 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); |
| 689 | break; |
| 690 | } |
| 691 | |
| 692 | rt2800_bbp_write(rt2x00dev, 3, r3); |
| 693 | rt2800_bbp_write(rt2x00dev, 1, r1); |
| 694 | } |
| 695 | EXPORT_SYMBOL_GPL(rt2800_config_ant); |
| 696 | |
| 697 | static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, |
| 698 | struct rt2x00lib_conf *libconf) |
| 699 | { |
| 700 | u16 eeprom; |
| 701 | short lna_gain; |
| 702 | |
| 703 | if (libconf->rf.channel <= 14) { |
| 704 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); |
| 705 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); |
| 706 | } else if (libconf->rf.channel <= 64) { |
| 707 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); |
| 708 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); |
| 709 | } else if (libconf->rf.channel <= 128) { |
| 710 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); |
| 711 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1); |
| 712 | } else { |
| 713 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); |
| 714 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2); |
| 715 | } |
| 716 | |
| 717 | rt2x00dev->lna_gain = lna_gain; |
| 718 | } |
| 719 | |
Gertjan van Wingerde | 06855ef | 2010-04-11 14:31:07 +0200 | [diff] [blame] | 720 | static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, |
| 721 | struct ieee80211_conf *conf, |
| 722 | struct rf_channel *rf, |
| 723 | struct channel_info *info) |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 724 | { |
| 725 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); |
| 726 | |
| 727 | if (rt2x00dev->default_ant.tx == 1) |
| 728 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); |
| 729 | |
| 730 | if (rt2x00dev->default_ant.rx == 1) { |
| 731 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); |
| 732 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); |
| 733 | } else if (rt2x00dev->default_ant.rx == 2) |
| 734 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); |
| 735 | |
| 736 | if (rf->channel > 14) { |
| 737 | /* |
| 738 | * When TX power is below 0, we should increase it by 7 to |
| 739 | * make it a positive value (Minumum value is -7). |
| 740 | * However this means that values between 0 and 7 have |
| 741 | * double meaning, and we should set a 7DBm boost flag. |
| 742 | */ |
| 743 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, |
| 744 | (info->tx_power1 >= 0)); |
| 745 | |
| 746 | if (info->tx_power1 < 0) |
| 747 | info->tx_power1 += 7; |
| 748 | |
| 749 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, |
| 750 | TXPOWER_A_TO_DEV(info->tx_power1)); |
| 751 | |
| 752 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, |
| 753 | (info->tx_power2 >= 0)); |
| 754 | |
| 755 | if (info->tx_power2 < 0) |
| 756 | info->tx_power2 += 7; |
| 757 | |
| 758 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, |
| 759 | TXPOWER_A_TO_DEV(info->tx_power2)); |
| 760 | } else { |
| 761 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, |
| 762 | TXPOWER_G_TO_DEV(info->tx_power1)); |
| 763 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, |
| 764 | TXPOWER_G_TO_DEV(info->tx_power2)); |
| 765 | } |
| 766 | |
| 767 | rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); |
| 768 | |
| 769 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); |
| 770 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); |
| 771 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); |
| 772 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); |
| 773 | |
| 774 | udelay(200); |
| 775 | |
| 776 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); |
| 777 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); |
| 778 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); |
| 779 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); |
| 780 | |
| 781 | udelay(200); |
| 782 | |
| 783 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); |
| 784 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); |
| 785 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); |
| 786 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); |
| 787 | } |
| 788 | |
Gertjan van Wingerde | 06855ef | 2010-04-11 14:31:07 +0200 | [diff] [blame] | 789 | static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, |
| 790 | struct ieee80211_conf *conf, |
| 791 | struct rf_channel *rf, |
| 792 | struct channel_info *info) |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 793 | { |
| 794 | u8 rfcsr; |
| 795 | |
| 796 | rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); |
Gertjan van Wingerde | 41a2617 | 2009-11-09 22:59:04 +0100 | [diff] [blame] | 797 | rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 798 | |
| 799 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); |
Gertjan van Wingerde | fab799c | 2010-04-11 14:31:08 +0200 | [diff] [blame] | 800 | rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 801 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); |
| 802 | |
| 803 | rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); |
| 804 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, |
| 805 | TXPOWER_G_TO_DEV(info->tx_power1)); |
| 806 | rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); |
| 807 | |
| 808 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); |
| 809 | rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); |
| 810 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); |
| 811 | |
| 812 | rt2800_rfcsr_write(rt2x00dev, 24, |
| 813 | rt2x00dev->calibration[conf_is_ht40(conf)]); |
| 814 | |
Gertjan van Wingerde | 7197690 | 2010-03-24 21:42:36 +0100 | [diff] [blame] | 815 | rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 816 | rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); |
Gertjan van Wingerde | 7197690 | 2010-03-24 21:42:36 +0100 | [diff] [blame] | 817 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 818 | } |
| 819 | |
| 820 | static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, |
| 821 | struct ieee80211_conf *conf, |
| 822 | struct rf_channel *rf, |
| 823 | struct channel_info *info) |
| 824 | { |
| 825 | u32 reg; |
| 826 | unsigned int tx_pin; |
| 827 | u8 bbp; |
| 828 | |
Gertjan van Wingerde | 06855ef | 2010-04-11 14:31:07 +0200 | [diff] [blame] | 829 | if (rt2x00_rf(rt2x00dev, RF2020) || |
| 830 | rt2x00_rf(rt2x00dev, RF3020) || |
| 831 | rt2x00_rf(rt2x00dev, RF3021) || |
| 832 | rt2x00_rf(rt2x00dev, RF3022)) |
| 833 | rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); |
Gertjan van Wingerde | fa6f632 | 2009-11-09 22:59:58 +0100 | [diff] [blame] | 834 | else |
Gertjan van Wingerde | 06855ef | 2010-04-11 14:31:07 +0200 | [diff] [blame] | 835 | rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 836 | |
| 837 | /* |
| 838 | * Change BBP settings |
| 839 | */ |
| 840 | rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); |
| 841 | rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); |
| 842 | rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); |
| 843 | rt2800_bbp_write(rt2x00dev, 86, 0); |
| 844 | |
| 845 | if (rf->channel <= 14) { |
| 846 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { |
| 847 | rt2800_bbp_write(rt2x00dev, 82, 0x62); |
| 848 | rt2800_bbp_write(rt2x00dev, 75, 0x46); |
| 849 | } else { |
| 850 | rt2800_bbp_write(rt2x00dev, 82, 0x84); |
| 851 | rt2800_bbp_write(rt2x00dev, 75, 0x50); |
| 852 | } |
| 853 | } else { |
| 854 | rt2800_bbp_write(rt2x00dev, 82, 0xf2); |
| 855 | |
| 856 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) |
| 857 | rt2800_bbp_write(rt2x00dev, 75, 0x46); |
| 858 | else |
| 859 | rt2800_bbp_write(rt2x00dev, 75, 0x50); |
| 860 | } |
| 861 | |
| 862 | rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); |
| 863 | rt2x00_set_field32(®, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf)); |
| 864 | rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); |
| 865 | rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); |
| 866 | rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); |
| 867 | |
| 868 | tx_pin = 0; |
| 869 | |
| 870 | /* Turn on unused PA or LNA when not using 1T or 1R */ |
| 871 | if (rt2x00dev->default_ant.tx != 1) { |
| 872 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); |
| 873 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); |
| 874 | } |
| 875 | |
| 876 | /* Turn on unused PA or LNA when not using 1T or 1R */ |
| 877 | if (rt2x00dev->default_ant.rx != 1) { |
| 878 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); |
| 879 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); |
| 880 | } |
| 881 | |
| 882 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); |
| 883 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); |
| 884 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); |
| 885 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); |
| 886 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14); |
| 887 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14); |
| 888 | |
| 889 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); |
| 890 | |
| 891 | rt2800_bbp_read(rt2x00dev, 4, &bbp); |
| 892 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); |
| 893 | rt2800_bbp_write(rt2x00dev, 4, bbp); |
| 894 | |
| 895 | rt2800_bbp_read(rt2x00dev, 3, &bbp); |
| 896 | rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf)); |
| 897 | rt2800_bbp_write(rt2x00dev, 3, bbp); |
| 898 | |
Gertjan van Wingerde | 8d0c9b6 | 2010-04-11 14:31:10 +0200 | [diff] [blame^] | 899 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 900 | if (conf_is_ht40(conf)) { |
| 901 | rt2800_bbp_write(rt2x00dev, 69, 0x1a); |
| 902 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); |
| 903 | rt2800_bbp_write(rt2x00dev, 73, 0x16); |
| 904 | } else { |
| 905 | rt2800_bbp_write(rt2x00dev, 69, 0x16); |
| 906 | rt2800_bbp_write(rt2x00dev, 70, 0x08); |
| 907 | rt2800_bbp_write(rt2x00dev, 73, 0x11); |
| 908 | } |
| 909 | } |
| 910 | |
| 911 | msleep(1); |
| 912 | } |
| 913 | |
| 914 | static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, |
| 915 | const int txpower) |
| 916 | { |
| 917 | u32 reg; |
| 918 | u32 value = TXPOWER_G_TO_DEV(txpower); |
| 919 | u8 r1; |
| 920 | |
| 921 | rt2800_bbp_read(rt2x00dev, 1, &r1); |
| 922 | rt2x00_set_field8(®, BBP1_TX_POWER, 0); |
| 923 | rt2800_bbp_write(rt2x00dev, 1, r1); |
| 924 | |
| 925 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, ®); |
| 926 | rt2x00_set_field32(®, TX_PWR_CFG_0_1MBS, value); |
| 927 | rt2x00_set_field32(®, TX_PWR_CFG_0_2MBS, value); |
| 928 | rt2x00_set_field32(®, TX_PWR_CFG_0_55MBS, value); |
| 929 | rt2x00_set_field32(®, TX_PWR_CFG_0_11MBS, value); |
| 930 | rt2x00_set_field32(®, TX_PWR_CFG_0_6MBS, value); |
| 931 | rt2x00_set_field32(®, TX_PWR_CFG_0_9MBS, value); |
| 932 | rt2x00_set_field32(®, TX_PWR_CFG_0_12MBS, value); |
| 933 | rt2x00_set_field32(®, TX_PWR_CFG_0_18MBS, value); |
| 934 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg); |
| 935 | |
| 936 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, ®); |
| 937 | rt2x00_set_field32(®, TX_PWR_CFG_1_24MBS, value); |
| 938 | rt2x00_set_field32(®, TX_PWR_CFG_1_36MBS, value); |
| 939 | rt2x00_set_field32(®, TX_PWR_CFG_1_48MBS, value); |
| 940 | rt2x00_set_field32(®, TX_PWR_CFG_1_54MBS, value); |
| 941 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS0, value); |
| 942 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS1, value); |
| 943 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS2, value); |
| 944 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS3, value); |
| 945 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg); |
| 946 | |
| 947 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, ®); |
| 948 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS4, value); |
| 949 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS5, value); |
| 950 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS6, value); |
| 951 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS7, value); |
| 952 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS8, value); |
| 953 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS9, value); |
| 954 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS10, value); |
| 955 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS11, value); |
| 956 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg); |
| 957 | |
| 958 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, ®); |
| 959 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS12, value); |
| 960 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS13, value); |
| 961 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS14, value); |
| 962 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS15, value); |
| 963 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN1, value); |
| 964 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN2, value); |
| 965 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN3, value); |
| 966 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN4, value); |
| 967 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg); |
| 968 | |
| 969 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, ®); |
| 970 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN5, value); |
| 971 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN6, value); |
| 972 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN7, value); |
| 973 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN8, value); |
| 974 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg); |
| 975 | } |
| 976 | |
| 977 | static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, |
| 978 | struct rt2x00lib_conf *libconf) |
| 979 | { |
| 980 | u32 reg; |
| 981 | |
| 982 | rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); |
| 983 | rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, |
| 984 | libconf->conf->short_frame_max_tx_count); |
| 985 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, |
| 986 | libconf->conf->long_frame_max_tx_count); |
| 987 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); |
| 988 | rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); |
| 989 | rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); |
| 990 | rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); |
| 991 | rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); |
| 992 | } |
| 993 | |
| 994 | static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, |
| 995 | struct rt2x00lib_conf *libconf) |
| 996 | { |
| 997 | enum dev_state state = |
| 998 | (libconf->conf->flags & IEEE80211_CONF_PS) ? |
| 999 | STATE_SLEEP : STATE_AWAKE; |
| 1000 | u32 reg; |
| 1001 | |
| 1002 | if (state == STATE_SLEEP) { |
| 1003 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); |
| 1004 | |
| 1005 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); |
| 1006 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); |
| 1007 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, |
| 1008 | libconf->conf->listen_interval - 1); |
| 1009 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); |
| 1010 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); |
| 1011 | |
| 1012 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); |
| 1013 | } else { |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 1014 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); |
| 1015 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); |
| 1016 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); |
| 1017 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); |
| 1018 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); |
Gertjan van Wingerde | 5731858 | 2010-03-30 23:50:23 +0200 | [diff] [blame] | 1019 | |
| 1020 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 1021 | } |
| 1022 | } |
| 1023 | |
| 1024 | void rt2800_config(struct rt2x00_dev *rt2x00dev, |
| 1025 | struct rt2x00lib_conf *libconf, |
| 1026 | const unsigned int flags) |
| 1027 | { |
| 1028 | /* Always recalculate LNA gain before changing configuration */ |
| 1029 | rt2800_config_lna_gain(rt2x00dev, libconf); |
| 1030 | |
| 1031 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
| 1032 | rt2800_config_channel(rt2x00dev, libconf->conf, |
| 1033 | &libconf->rf, &libconf->channel); |
| 1034 | if (flags & IEEE80211_CONF_CHANGE_POWER) |
| 1035 | rt2800_config_txpower(rt2x00dev, libconf->conf->power_level); |
| 1036 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
| 1037 | rt2800_config_retry_limit(rt2x00dev, libconf); |
| 1038 | if (flags & IEEE80211_CONF_CHANGE_PS) |
| 1039 | rt2800_config_ps(rt2x00dev, libconf); |
| 1040 | } |
| 1041 | EXPORT_SYMBOL_GPL(rt2800_config); |
| 1042 | |
| 1043 | /* |
| 1044 | * Link tuning |
| 1045 | */ |
| 1046 | void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) |
| 1047 | { |
| 1048 | u32 reg; |
| 1049 | |
| 1050 | /* |
| 1051 | * Update FCS error count from register. |
| 1052 | */ |
| 1053 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); |
| 1054 | qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); |
| 1055 | } |
| 1056 | EXPORT_SYMBOL_GPL(rt2800_link_stats); |
| 1057 | |
| 1058 | static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) |
| 1059 | { |
| 1060 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1061 | if (rt2x00_is_usb(rt2x00dev) && |
Gertjan van Wingerde | 8d0c9b6 | 2010-04-11 14:31:10 +0200 | [diff] [blame^] | 1062 | rt2x00_rt_rev(rt2x00dev, RT3070, REV_RT3070E)) |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 1063 | return 0x1c + (2 * rt2x00dev->lna_gain); |
| 1064 | else |
| 1065 | return 0x2e + rt2x00dev->lna_gain; |
| 1066 | } |
| 1067 | |
| 1068 | if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) |
| 1069 | return 0x32 + (rt2x00dev->lna_gain * 5) / 3; |
| 1070 | else |
| 1071 | return 0x3a + (rt2x00dev->lna_gain * 5) / 3; |
| 1072 | } |
| 1073 | |
| 1074 | static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, |
| 1075 | struct link_qual *qual, u8 vgc_level) |
| 1076 | { |
| 1077 | if (qual->vgc_level != vgc_level) { |
| 1078 | rt2800_bbp_write(rt2x00dev, 66, vgc_level); |
| 1079 | qual->vgc_level = vgc_level; |
| 1080 | qual->vgc_level_reg = vgc_level; |
| 1081 | } |
| 1082 | } |
| 1083 | |
| 1084 | void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) |
| 1085 | { |
| 1086 | rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); |
| 1087 | } |
| 1088 | EXPORT_SYMBOL_GPL(rt2800_reset_tuner); |
| 1089 | |
| 1090 | void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, |
| 1091 | const u32 count) |
| 1092 | { |
Gertjan van Wingerde | 8d0c9b6 | 2010-04-11 14:31:10 +0200 | [diff] [blame^] | 1093 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) |
Bartlomiej Zolnierkiewicz | f445061 | 2009-11-04 18:36:40 +0100 | [diff] [blame] | 1094 | return; |
| 1095 | |
| 1096 | /* |
| 1097 | * When RSSI is better then -80 increase VGC level with 0x10 |
| 1098 | */ |
| 1099 | rt2800_set_vgc(rt2x00dev, qual, |
| 1100 | rt2800_get_default_vgc(rt2x00dev) + |
| 1101 | ((qual->rssi > -80) * 0x10)); |
| 1102 | } |
| 1103 | EXPORT_SYMBOL_GPL(rt2800_link_tuner); |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1104 | |
| 1105 | /* |
| 1106 | * Initialization functions. |
| 1107 | */ |
| 1108 | int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) |
| 1109 | { |
| 1110 | u32 reg; |
| 1111 | unsigned int i; |
| 1112 | |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1113 | if (rt2x00_is_usb(rt2x00dev)) { |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1114 | /* |
Thadeu Lima de Souza Cascardo | 235faf9 | 2009-11-12 20:04:52 +0100 | [diff] [blame] | 1115 | * Wait until BBP and RF are ready. |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1116 | */ |
| 1117 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
| 1118 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); |
| 1119 | if (reg && reg != ~0) |
| 1120 | break; |
| 1121 | msleep(1); |
| 1122 | } |
| 1123 | |
| 1124 | if (i == REGISTER_BUSY_COUNT) { |
| 1125 | ERROR(rt2x00dev, "Unstable hardware.\n"); |
| 1126 | return -EBUSY; |
| 1127 | } |
| 1128 | |
| 1129 | rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); |
| 1130 | rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, |
| 1131 | reg & ~0x00002000); |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1132 | } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1133 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); |
| 1134 | |
| 1135 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); |
| 1136 | rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1); |
| 1137 | rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1); |
| 1138 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); |
| 1139 | |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1140 | if (rt2x00_is_usb(rt2x00dev)) { |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1141 | rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000); |
Gertjan van Wingerde | ac39491 | 2009-12-23 00:03:23 +0100 | [diff] [blame] | 1142 | #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE) |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1143 | rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, |
| 1144 | USB_MODE_RESET, REGISTER_TIMEOUT); |
| 1145 | #endif |
| 1146 | } |
| 1147 | |
| 1148 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); |
| 1149 | |
| 1150 | rt2800_register_read(rt2x00dev, BCN_OFFSET0, ®); |
| 1151 | rt2x00_set_field32(®, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */ |
| 1152 | rt2x00_set_field32(®, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */ |
| 1153 | rt2x00_set_field32(®, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */ |
| 1154 | rt2x00_set_field32(®, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */ |
| 1155 | rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg); |
| 1156 | |
| 1157 | rt2800_register_read(rt2x00dev, BCN_OFFSET1, ®); |
| 1158 | rt2x00_set_field32(®, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */ |
| 1159 | rt2x00_set_field32(®, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */ |
| 1160 | rt2x00_set_field32(®, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */ |
| 1161 | rt2x00_set_field32(®, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */ |
| 1162 | rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg); |
| 1163 | |
| 1164 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); |
| 1165 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); |
| 1166 | |
| 1167 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); |
| 1168 | |
| 1169 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); |
| 1170 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 0); |
| 1171 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); |
| 1172 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); |
| 1173 | rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); |
| 1174 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); |
| 1175 | rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); |
| 1176 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
| 1177 | |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1178 | if (rt2x00_is_usb(rt2x00dev) && |
Gertjan van Wingerde | 8d0c9b6 | 2010-04-11 14:31:10 +0200 | [diff] [blame^] | 1179 | rt2x00_rt_rev(rt2x00dev, RT3070, REV_RT3070E)) { |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1180 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); |
| 1181 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); |
| 1182 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); |
| 1183 | } else { |
| 1184 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); |
| 1185 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); |
| 1186 | } |
| 1187 | |
| 1188 | rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); |
| 1189 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); |
| 1190 | rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); |
| 1191 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); |
| 1192 | rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); |
| 1193 | rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); |
| 1194 | rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); |
| 1195 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); |
| 1196 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); |
| 1197 | rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); |
| 1198 | |
| 1199 | rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); |
| 1200 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); |
| 1201 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); |
| 1202 | rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); |
| 1203 | |
| 1204 | rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); |
| 1205 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); |
Gertjan van Wingerde | 8d0c9b6 | 2010-04-11 14:31:10 +0200 | [diff] [blame^] | 1206 | if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1207 | rt2x00_rt(rt2x00dev, RT2883) || |
Gertjan van Wingerde | 8d0c9b6 | 2010-04-11 14:31:10 +0200 | [diff] [blame^] | 1208 | rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1209 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); |
| 1210 | else |
| 1211 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); |
| 1212 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0); |
| 1213 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0); |
| 1214 | rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); |
| 1215 | |
| 1216 | rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); |
| 1217 | |
| 1218 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); |
| 1219 | rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); |
| 1220 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0); |
| 1221 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); |
| 1222 | rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); |
| 1223 | rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); |
| 1224 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); |
| 1225 | |
| 1226 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); |
| 1227 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 8); |
| 1228 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); |
| 1229 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV, 1); |
| 1230 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1231 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1232 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1233 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1); |
| 1234 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1235 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1); |
| 1236 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); |
| 1237 | |
| 1238 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); |
| 1239 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 8); |
| 1240 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); |
| 1241 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV, 1); |
| 1242 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1243 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1244 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1245 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1); |
| 1246 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1247 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1); |
| 1248 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); |
| 1249 | |
| 1250 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); |
| 1251 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); |
| 1252 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0); |
| 1253 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV, 1); |
| 1254 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1255 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1256 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1257 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); |
| 1258 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1259 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); |
| 1260 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); |
| 1261 | |
| 1262 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); |
| 1263 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); |
| 1264 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0); |
| 1265 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV, 1); |
| 1266 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1267 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1268 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1269 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); |
| 1270 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1271 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); |
| 1272 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); |
| 1273 | |
| 1274 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); |
| 1275 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); |
| 1276 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0); |
| 1277 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV, 1); |
| 1278 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1279 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1280 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1281 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); |
| 1282 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1283 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); |
| 1284 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); |
| 1285 | |
| 1286 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); |
| 1287 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); |
| 1288 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0); |
| 1289 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV, 1); |
| 1290 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1291 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1292 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1293 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); |
| 1294 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1295 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); |
| 1296 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); |
| 1297 | |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1298 | if (rt2x00_is_usb(rt2x00dev)) { |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1299 | rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); |
| 1300 | |
| 1301 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); |
| 1302 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); |
| 1303 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); |
| 1304 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); |
| 1305 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); |
| 1306 | rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); |
| 1307 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); |
| 1308 | rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); |
| 1309 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); |
| 1310 | rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); |
| 1311 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); |
| 1312 | } |
| 1313 | |
| 1314 | rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f); |
| 1315 | rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002); |
| 1316 | |
| 1317 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); |
| 1318 | rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); |
| 1319 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, |
| 1320 | IEEE80211_MAX_RTS_THRESHOLD); |
| 1321 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); |
| 1322 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); |
| 1323 | |
| 1324 | rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); |
| 1325 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); |
| 1326 | |
| 1327 | /* |
| 1328 | * ASIC will keep garbage value after boot, clear encryption keys. |
| 1329 | */ |
| 1330 | for (i = 0; i < 4; i++) |
| 1331 | rt2800_register_write(rt2x00dev, |
| 1332 | SHARED_KEY_MODE_ENTRY(i), 0); |
| 1333 | |
| 1334 | for (i = 0; i < 256; i++) { |
| 1335 | u32 wcid[2] = { 0xffffffff, 0x00ffffff }; |
| 1336 | rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i), |
| 1337 | wcid, sizeof(wcid)); |
| 1338 | |
| 1339 | rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1); |
| 1340 | rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); |
| 1341 | } |
| 1342 | |
| 1343 | /* |
| 1344 | * Clear all beacons |
| 1345 | * For the Beacon base registers we only need to clear |
| 1346 | * the first byte since that byte contains the VALID and OWNER |
| 1347 | * bits which (when set to 0) will invalidate the entire beacon. |
| 1348 | */ |
| 1349 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0); |
| 1350 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0); |
| 1351 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0); |
| 1352 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0); |
| 1353 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0); |
| 1354 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0); |
| 1355 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0); |
| 1356 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0); |
| 1357 | |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1358 | if (rt2x00_is_usb(rt2x00dev)) { |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1359 | rt2800_register_read(rt2x00dev, USB_CYC_CFG, ®); |
| 1360 | rt2x00_set_field32(®, USB_CYC_CFG_CLOCK_CYCLE, 30); |
| 1361 | rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg); |
| 1362 | } |
| 1363 | |
| 1364 | rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); |
| 1365 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); |
| 1366 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); |
| 1367 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); |
| 1368 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); |
| 1369 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); |
| 1370 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); |
| 1371 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); |
| 1372 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); |
| 1373 | rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); |
| 1374 | |
| 1375 | rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); |
| 1376 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); |
| 1377 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); |
| 1378 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); |
| 1379 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); |
| 1380 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); |
| 1381 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); |
| 1382 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); |
| 1383 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); |
| 1384 | rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); |
| 1385 | |
| 1386 | rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); |
| 1387 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); |
| 1388 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); |
| 1389 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); |
| 1390 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); |
| 1391 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); |
| 1392 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); |
| 1393 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); |
| 1394 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); |
| 1395 | rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); |
| 1396 | |
| 1397 | rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); |
| 1398 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); |
| 1399 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); |
| 1400 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); |
| 1401 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); |
| 1402 | rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); |
| 1403 | |
| 1404 | /* |
| 1405 | * We must clear the error counters. |
| 1406 | * These registers are cleared on read, |
| 1407 | * so we may pass a useless variable to store the value. |
| 1408 | */ |
| 1409 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); |
| 1410 | rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); |
| 1411 | rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); |
| 1412 | rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); |
| 1413 | rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); |
| 1414 | rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); |
| 1415 | |
| 1416 | return 0; |
| 1417 | } |
| 1418 | EXPORT_SYMBOL_GPL(rt2800_init_registers); |
| 1419 | |
| 1420 | static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) |
| 1421 | { |
| 1422 | unsigned int i; |
| 1423 | u32 reg; |
| 1424 | |
| 1425 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
| 1426 | rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); |
| 1427 | if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) |
| 1428 | return 0; |
| 1429 | |
| 1430 | udelay(REGISTER_BUSY_DELAY); |
| 1431 | } |
| 1432 | |
| 1433 | ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n"); |
| 1434 | return -EACCES; |
| 1435 | } |
| 1436 | |
| 1437 | static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
| 1438 | { |
| 1439 | unsigned int i; |
| 1440 | u8 value; |
| 1441 | |
| 1442 | /* |
| 1443 | * BBP was enabled after firmware was loaded, |
| 1444 | * but we need to reactivate it now. |
| 1445 | */ |
| 1446 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); |
| 1447 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); |
| 1448 | msleep(1); |
| 1449 | |
| 1450 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
| 1451 | rt2800_bbp_read(rt2x00dev, 0, &value); |
| 1452 | if ((value != 0xff) && (value != 0x00)) |
| 1453 | return 0; |
| 1454 | udelay(REGISTER_BUSY_DELAY); |
| 1455 | } |
| 1456 | |
| 1457 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); |
| 1458 | return -EACCES; |
| 1459 | } |
| 1460 | |
| 1461 | int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) |
| 1462 | { |
| 1463 | unsigned int i; |
| 1464 | u16 eeprom; |
| 1465 | u8 reg_id; |
| 1466 | u8 value; |
| 1467 | |
| 1468 | if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) || |
| 1469 | rt2800_wait_bbp_ready(rt2x00dev))) |
| 1470 | return -EACCES; |
| 1471 | |
| 1472 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); |
| 1473 | rt2800_bbp_write(rt2x00dev, 66, 0x38); |
| 1474 | rt2800_bbp_write(rt2x00dev, 69, 0x12); |
| 1475 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); |
| 1476 | rt2800_bbp_write(rt2x00dev, 73, 0x10); |
| 1477 | rt2800_bbp_write(rt2x00dev, 81, 0x37); |
| 1478 | rt2800_bbp_write(rt2x00dev, 82, 0x62); |
| 1479 | rt2800_bbp_write(rt2x00dev, 83, 0x6a); |
| 1480 | rt2800_bbp_write(rt2x00dev, 84, 0x99); |
| 1481 | rt2800_bbp_write(rt2x00dev, 86, 0x00); |
| 1482 | rt2800_bbp_write(rt2x00dev, 91, 0x04); |
| 1483 | rt2800_bbp_write(rt2x00dev, 92, 0x00); |
| 1484 | rt2800_bbp_write(rt2x00dev, 103, 0x00); |
| 1485 | rt2800_bbp_write(rt2x00dev, 105, 0x05); |
| 1486 | |
Gertjan van Wingerde | 8d0c9b6 | 2010-04-11 14:31:10 +0200 | [diff] [blame^] | 1487 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1488 | rt2800_bbp_write(rt2x00dev, 69, 0x16); |
| 1489 | rt2800_bbp_write(rt2x00dev, 73, 0x12); |
| 1490 | } |
| 1491 | |
Gertjan van Wingerde | 8d0c9b6 | 2010-04-11 14:31:10 +0200 | [diff] [blame^] | 1492 | if (rt2x00_rt_rev_gte(rt2x00dev, RT2860, REV_RT2860D)) |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1493 | rt2800_bbp_write(rt2x00dev, 84, 0x19); |
| 1494 | |
Gertjan van Wingerde | e148b4c | 2010-04-11 14:31:09 +0200 | [diff] [blame] | 1495 | if (rt2x00_rt(rt2x00dev, RT2872)) { |
| 1496 | rt2800_bbp_write(rt2x00dev, 31, 0x08); |
| 1497 | rt2800_bbp_write(rt2x00dev, 78, 0x0e); |
| 1498 | rt2800_bbp_write(rt2x00dev, 80, 0x08); |
| 1499 | } |
| 1500 | |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1501 | if (rt2x00_is_usb(rt2x00dev) && |
Gertjan van Wingerde | 8d0c9b6 | 2010-04-11 14:31:10 +0200 | [diff] [blame^] | 1502 | rt2x00_rt_rev(rt2x00dev, RT3070, REV_RT3070E)) { |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1503 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); |
| 1504 | rt2800_bbp_write(rt2x00dev, 84, 0x99); |
| 1505 | rt2800_bbp_write(rt2x00dev, 105, 0x05); |
| 1506 | } |
| 1507 | |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1508 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
| 1509 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); |
| 1510 | |
| 1511 | if (eeprom != 0xffff && eeprom != 0x0000) { |
| 1512 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); |
| 1513 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); |
| 1514 | rt2800_bbp_write(rt2x00dev, reg_id, value); |
| 1515 | } |
| 1516 | } |
| 1517 | |
| 1518 | return 0; |
| 1519 | } |
| 1520 | EXPORT_SYMBOL_GPL(rt2800_init_bbp); |
| 1521 | |
| 1522 | static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, |
| 1523 | bool bw40, u8 rfcsr24, u8 filter_target) |
| 1524 | { |
| 1525 | unsigned int i; |
| 1526 | u8 bbp; |
| 1527 | u8 rfcsr; |
| 1528 | u8 passband; |
| 1529 | u8 stopband; |
| 1530 | u8 overtuned = 0; |
| 1531 | |
| 1532 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); |
| 1533 | |
| 1534 | rt2800_bbp_read(rt2x00dev, 4, &bbp); |
| 1535 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); |
| 1536 | rt2800_bbp_write(rt2x00dev, 4, bbp); |
| 1537 | |
| 1538 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); |
| 1539 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); |
| 1540 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); |
| 1541 | |
| 1542 | /* |
| 1543 | * Set power & frequency of passband test tone |
| 1544 | */ |
| 1545 | rt2800_bbp_write(rt2x00dev, 24, 0); |
| 1546 | |
| 1547 | for (i = 0; i < 100; i++) { |
| 1548 | rt2800_bbp_write(rt2x00dev, 25, 0x90); |
| 1549 | msleep(1); |
| 1550 | |
| 1551 | rt2800_bbp_read(rt2x00dev, 55, &passband); |
| 1552 | if (passband) |
| 1553 | break; |
| 1554 | } |
| 1555 | |
| 1556 | /* |
| 1557 | * Set power & frequency of stopband test tone |
| 1558 | */ |
| 1559 | rt2800_bbp_write(rt2x00dev, 24, 0x06); |
| 1560 | |
| 1561 | for (i = 0; i < 100; i++) { |
| 1562 | rt2800_bbp_write(rt2x00dev, 25, 0x90); |
| 1563 | msleep(1); |
| 1564 | |
| 1565 | rt2800_bbp_read(rt2x00dev, 55, &stopband); |
| 1566 | |
| 1567 | if ((passband - stopband) <= filter_target) { |
| 1568 | rfcsr24++; |
| 1569 | overtuned += ((passband - stopband) == filter_target); |
| 1570 | } else |
| 1571 | break; |
| 1572 | |
| 1573 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); |
| 1574 | } |
| 1575 | |
| 1576 | rfcsr24 -= !!overtuned; |
| 1577 | |
| 1578 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); |
| 1579 | return rfcsr24; |
| 1580 | } |
| 1581 | |
| 1582 | int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) |
| 1583 | { |
| 1584 | u8 rfcsr; |
| 1585 | u8 bbp; |
| 1586 | |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1587 | if (rt2x00_is_usb(rt2x00dev) && |
Gertjan van Wingerde | 8d0c9b6 | 2010-04-11 14:31:10 +0200 | [diff] [blame^] | 1588 | !rt2x00_rt_rev(rt2x00dev, RT3070, REV_RT3070E)) |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1589 | return 0; |
| 1590 | |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1591 | if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) { |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 1592 | if (!rt2x00_rf(rt2x00dev, RF3020) && |
| 1593 | !rt2x00_rf(rt2x00dev, RF3021) && |
| 1594 | !rt2x00_rf(rt2x00dev, RF3022)) |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1595 | return 0; |
| 1596 | } |
| 1597 | |
| 1598 | /* |
| 1599 | * Init RF calibration. |
| 1600 | */ |
| 1601 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); |
| 1602 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); |
| 1603 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); |
| 1604 | msleep(1); |
| 1605 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); |
| 1606 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); |
| 1607 | |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1608 | if (rt2x00_is_usb(rt2x00dev)) { |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1609 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); |
| 1610 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); |
| 1611 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); |
| 1612 | rt2800_rfcsr_write(rt2x00dev, 7, 0x70); |
| 1613 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); |
| 1614 | rt2800_rfcsr_write(rt2x00dev, 10, 0x71); |
| 1615 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); |
| 1616 | rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); |
| 1617 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); |
| 1618 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); |
| 1619 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); |
| 1620 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); |
| 1621 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); |
| 1622 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); |
| 1623 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); |
| 1624 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); |
| 1625 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); |
| 1626 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); |
| 1627 | rt2800_rfcsr_write(rt2x00dev, 27, 0x03); |
| 1628 | rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 1629 | } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) { |
Bartlomiej Zolnierkiewicz | fcf5154 | 2009-11-04 18:36:57 +0100 | [diff] [blame] | 1630 | rt2800_rfcsr_write(rt2x00dev, 0, 0x50); |
| 1631 | rt2800_rfcsr_write(rt2x00dev, 1, 0x01); |
| 1632 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); |
| 1633 | rt2800_rfcsr_write(rt2x00dev, 3, 0x75); |
| 1634 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); |
| 1635 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); |
| 1636 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); |
| 1637 | rt2800_rfcsr_write(rt2x00dev, 7, 0x50); |
| 1638 | rt2800_rfcsr_write(rt2x00dev, 8, 0x39); |
| 1639 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); |
| 1640 | rt2800_rfcsr_write(rt2x00dev, 10, 0x60); |
| 1641 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); |
| 1642 | rt2800_rfcsr_write(rt2x00dev, 12, 0x75); |
| 1643 | rt2800_rfcsr_write(rt2x00dev, 13, 0x75); |
| 1644 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); |
| 1645 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); |
| 1646 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); |
| 1647 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); |
| 1648 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); |
| 1649 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); |
| 1650 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); |
| 1651 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); |
| 1652 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); |
| 1653 | rt2800_rfcsr_write(rt2x00dev, 23, 0x31); |
| 1654 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); |
| 1655 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); |
| 1656 | rt2800_rfcsr_write(rt2x00dev, 26, 0x25); |
| 1657 | rt2800_rfcsr_write(rt2x00dev, 27, 0x23); |
| 1658 | rt2800_rfcsr_write(rt2x00dev, 28, 0x13); |
| 1659 | rt2800_rfcsr_write(rt2x00dev, 29, 0x83); |
| 1660 | } |
| 1661 | |
| 1662 | /* |
| 1663 | * Set RX Filter calibration for 20MHz and 40MHz |
| 1664 | */ |
| 1665 | rt2x00dev->calibration[0] = |
| 1666 | rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16); |
| 1667 | rt2x00dev->calibration[1] = |
| 1668 | rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); |
| 1669 | |
| 1670 | /* |
| 1671 | * Set back to initial state |
| 1672 | */ |
| 1673 | rt2800_bbp_write(rt2x00dev, 24, 0); |
| 1674 | |
| 1675 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); |
| 1676 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); |
| 1677 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); |
| 1678 | |
| 1679 | /* |
| 1680 | * set BBP back to BW20 |
| 1681 | */ |
| 1682 | rt2800_bbp_read(rt2x00dev, 4, &bbp); |
| 1683 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); |
| 1684 | rt2800_bbp_write(rt2x00dev, 4, bbp); |
| 1685 | |
| 1686 | return 0; |
| 1687 | } |
| 1688 | EXPORT_SYMBOL_GPL(rt2800_init_rfcsr); |
Bartlomiej Zolnierkiewicz | 2ce3399 | 2009-11-04 18:37:05 +0100 | [diff] [blame] | 1689 | |
Bartlomiej Zolnierkiewicz | 30e8403 | 2009-11-08 14:39:48 +0100 | [diff] [blame] | 1690 | int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) |
| 1691 | { |
| 1692 | u32 reg; |
| 1693 | |
| 1694 | rt2800_register_read(rt2x00dev, EFUSE_CTRL, ®); |
| 1695 | |
| 1696 | return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); |
| 1697 | } |
| 1698 | EXPORT_SYMBOL_GPL(rt2800_efuse_detect); |
| 1699 | |
| 1700 | static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) |
| 1701 | { |
| 1702 | u32 reg; |
| 1703 | |
Gertjan van Wingerde | 31a4cf1 | 2009-11-14 20:20:36 +0100 | [diff] [blame] | 1704 | mutex_lock(&rt2x00dev->csr_mutex); |
| 1705 | |
| 1706 | rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, ®); |
Bartlomiej Zolnierkiewicz | 30e8403 | 2009-11-08 14:39:48 +0100 | [diff] [blame] | 1707 | rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); |
| 1708 | rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); |
| 1709 | rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); |
Gertjan van Wingerde | 31a4cf1 | 2009-11-14 20:20:36 +0100 | [diff] [blame] | 1710 | rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg); |
Bartlomiej Zolnierkiewicz | 30e8403 | 2009-11-08 14:39:48 +0100 | [diff] [blame] | 1711 | |
| 1712 | /* Wait until the EEPROM has been loaded */ |
| 1713 | rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, ®); |
| 1714 | |
| 1715 | /* Apparently the data is read from end to start */ |
Gertjan van Wingerde | 31a4cf1 | 2009-11-14 20:20:36 +0100 | [diff] [blame] | 1716 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, |
| 1717 | (u32 *)&rt2x00dev->eeprom[i]); |
| 1718 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, |
| 1719 | (u32 *)&rt2x00dev->eeprom[i + 2]); |
| 1720 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, |
| 1721 | (u32 *)&rt2x00dev->eeprom[i + 4]); |
| 1722 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, |
| 1723 | (u32 *)&rt2x00dev->eeprom[i + 6]); |
| 1724 | |
| 1725 | mutex_unlock(&rt2x00dev->csr_mutex); |
Bartlomiej Zolnierkiewicz | 30e8403 | 2009-11-08 14:39:48 +0100 | [diff] [blame] | 1726 | } |
| 1727 | |
| 1728 | void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) |
| 1729 | { |
| 1730 | unsigned int i; |
| 1731 | |
| 1732 | for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) |
| 1733 | rt2800_efuse_read(rt2x00dev, i); |
| 1734 | } |
| 1735 | EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); |
| 1736 | |
Bartlomiej Zolnierkiewicz | 38bd7b8 | 2009-11-08 14:39:01 +0100 | [diff] [blame] | 1737 | int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) |
| 1738 | { |
| 1739 | u16 word; |
| 1740 | u8 *mac; |
| 1741 | u8 default_lna_gain; |
| 1742 | |
| 1743 | /* |
| 1744 | * Start validation of the data that has been read. |
| 1745 | */ |
| 1746 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); |
| 1747 | if (!is_valid_ether_addr(mac)) { |
| 1748 | random_ether_addr(mac); |
| 1749 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); |
| 1750 | } |
| 1751 | |
| 1752 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); |
| 1753 | if (word == 0xffff) { |
| 1754 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2); |
| 1755 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1); |
| 1756 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820); |
| 1757 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); |
| 1758 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1759 | } else if (rt2x00_rt(rt2x00dev, RT2860) || |
| 1760 | rt2x00_rt(rt2x00dev, RT2870) || |
| 1761 | rt2x00_rt(rt2x00dev, RT2872) || |
Gertjan van Wingerde | e148b4c | 2010-04-11 14:31:09 +0200 | [diff] [blame] | 1762 | rt2x00_rt(rt2x00dev, RT2872)) { |
Bartlomiej Zolnierkiewicz | 38bd7b8 | 2009-11-08 14:39:01 +0100 | [diff] [blame] | 1763 | /* |
| 1764 | * There is a max of 2 RX streams for RT28x0 series |
| 1765 | */ |
| 1766 | if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2) |
| 1767 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2); |
| 1768 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); |
| 1769 | } |
| 1770 | |
| 1771 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); |
| 1772 | if (word == 0xffff) { |
| 1773 | rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0); |
| 1774 | rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0); |
| 1775 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0); |
| 1776 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0); |
| 1777 | rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); |
| 1778 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0); |
| 1779 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0); |
| 1780 | rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0); |
| 1781 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0); |
| 1782 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0); |
| 1783 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); |
| 1784 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); |
| 1785 | } |
| 1786 | |
| 1787 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); |
| 1788 | if ((word & 0x00ff) == 0x00ff) { |
| 1789 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); |
| 1790 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, |
| 1791 | LED_MODE_TXRX_ACTIVITY); |
| 1792 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); |
| 1793 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); |
| 1794 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555); |
| 1795 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221); |
| 1796 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8); |
| 1797 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); |
| 1798 | } |
| 1799 | |
| 1800 | /* |
| 1801 | * During the LNA validation we are going to use |
| 1802 | * lna0 as correct value. Note that EEPROM_LNA |
| 1803 | * is never validated. |
| 1804 | */ |
| 1805 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word); |
| 1806 | default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); |
| 1807 | |
| 1808 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word); |
| 1809 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) |
| 1810 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); |
| 1811 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) |
| 1812 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); |
| 1813 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); |
| 1814 | |
| 1815 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word); |
| 1816 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) |
| 1817 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); |
| 1818 | if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || |
| 1819 | rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) |
| 1820 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, |
| 1821 | default_lna_gain); |
| 1822 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); |
| 1823 | |
| 1824 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word); |
| 1825 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) |
| 1826 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); |
| 1827 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) |
| 1828 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); |
| 1829 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); |
| 1830 | |
| 1831 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word); |
| 1832 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) |
| 1833 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); |
| 1834 | if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || |
| 1835 | rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) |
| 1836 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, |
| 1837 | default_lna_gain); |
| 1838 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); |
| 1839 | |
| 1840 | return 0; |
| 1841 | } |
| 1842 | EXPORT_SYMBOL_GPL(rt2800_validate_eeprom); |
| 1843 | |
| 1844 | int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) |
| 1845 | { |
| 1846 | u32 reg; |
| 1847 | u16 value; |
| 1848 | u16 eeprom; |
| 1849 | |
| 1850 | /* |
| 1851 | * Read EEPROM word for configuration. |
| 1852 | */ |
| 1853 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); |
| 1854 | |
| 1855 | /* |
| 1856 | * Identify RF chipset. |
| 1857 | */ |
| 1858 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); |
| 1859 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); |
| 1860 | |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1861 | rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), |
| 1862 | value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); |
Gertjan van Wingerde | 714fa66 | 2010-02-13 20:55:48 +0100 | [diff] [blame] | 1863 | |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1864 | if (!rt2x00_rt(rt2x00dev, RT2860) && |
| 1865 | !rt2x00_rt(rt2x00dev, RT2870) && |
| 1866 | !rt2x00_rt(rt2x00dev, RT2872) && |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1867 | !rt2x00_rt(rt2x00dev, RT2883) && |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1868 | !rt2x00_rt(rt2x00dev, RT3070) && |
| 1869 | !rt2x00_rt(rt2x00dev, RT3071) && |
| 1870 | !rt2x00_rt(rt2x00dev, RT3090) && |
| 1871 | !rt2x00_rt(rt2x00dev, RT3390) && |
| 1872 | !rt2x00_rt(rt2x00dev, RT3572)) { |
| 1873 | ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); |
| 1874 | return -ENODEV; |
| 1875 | } |
Bartlomiej Zolnierkiewicz | 38bd7b8 | 2009-11-08 14:39:01 +0100 | [diff] [blame] | 1876 | |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 1877 | if (!rt2x00_rf(rt2x00dev, RF2820) && |
| 1878 | !rt2x00_rf(rt2x00dev, RF2850) && |
| 1879 | !rt2x00_rf(rt2x00dev, RF2720) && |
| 1880 | !rt2x00_rf(rt2x00dev, RF2750) && |
| 1881 | !rt2x00_rf(rt2x00dev, RF3020) && |
| 1882 | !rt2x00_rf(rt2x00dev, RF2020) && |
| 1883 | !rt2x00_rf(rt2x00dev, RF3021) && |
Gertjan van Wingerde | 6c0fe26 | 2009-12-30 11:36:31 +0100 | [diff] [blame] | 1884 | !rt2x00_rf(rt2x00dev, RF3022) && |
| 1885 | !rt2x00_rf(rt2x00dev, RF3052)) { |
Bartlomiej Zolnierkiewicz | 38bd7b8 | 2009-11-08 14:39:01 +0100 | [diff] [blame] | 1886 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
| 1887 | return -ENODEV; |
| 1888 | } |
| 1889 | |
| 1890 | /* |
| 1891 | * Identify default antenna configuration. |
| 1892 | */ |
| 1893 | rt2x00dev->default_ant.tx = |
| 1894 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH); |
| 1895 | rt2x00dev->default_ant.rx = |
| 1896 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH); |
| 1897 | |
| 1898 | /* |
| 1899 | * Read frequency offset and RF programming sequence. |
| 1900 | */ |
| 1901 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); |
| 1902 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); |
| 1903 | |
| 1904 | /* |
| 1905 | * Read external LNA informations. |
| 1906 | */ |
| 1907 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); |
| 1908 | |
| 1909 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) |
| 1910 | __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); |
| 1911 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) |
| 1912 | __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); |
| 1913 | |
| 1914 | /* |
| 1915 | * Detect if this device has an hardware controlled radio. |
| 1916 | */ |
| 1917 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO)) |
| 1918 | __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); |
| 1919 | |
| 1920 | /* |
| 1921 | * Store led settings, for correct led behaviour. |
| 1922 | */ |
| 1923 | #ifdef CONFIG_RT2X00_LIB_LEDS |
| 1924 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
| 1925 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); |
| 1926 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); |
| 1927 | |
| 1928 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg); |
| 1929 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
| 1930 | |
| 1931 | return 0; |
| 1932 | } |
| 1933 | EXPORT_SYMBOL_GPL(rt2800_init_eeprom); |
| 1934 | |
Bartlomiej Zolnierkiewicz | 2ce3399 | 2009-11-04 18:37:05 +0100 | [diff] [blame] | 1935 | /* |
Bartlomiej Zolnierkiewicz | 4da2933 | 2009-11-08 14:39:32 +0100 | [diff] [blame] | 1936 | * RF value list for rt28x0 |
| 1937 | * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) |
| 1938 | */ |
| 1939 | static const struct rf_channel rf_vals[] = { |
| 1940 | { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, |
| 1941 | { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, |
| 1942 | { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, |
| 1943 | { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, |
| 1944 | { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, |
| 1945 | { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, |
| 1946 | { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, |
| 1947 | { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, |
| 1948 | { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, |
| 1949 | { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, |
| 1950 | { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, |
| 1951 | { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, |
| 1952 | { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, |
| 1953 | { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, |
| 1954 | |
| 1955 | /* 802.11 UNI / HyperLan 2 */ |
| 1956 | { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, |
| 1957 | { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, |
| 1958 | { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, |
| 1959 | { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, |
| 1960 | { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, |
| 1961 | { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, |
| 1962 | { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, |
| 1963 | { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, |
| 1964 | { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, |
| 1965 | { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, |
| 1966 | { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, |
| 1967 | { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, |
| 1968 | |
| 1969 | /* 802.11 HyperLan 2 */ |
| 1970 | { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, |
| 1971 | { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, |
| 1972 | { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, |
| 1973 | { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, |
| 1974 | { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, |
| 1975 | { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, |
| 1976 | { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, |
| 1977 | { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, |
| 1978 | { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, |
| 1979 | { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, |
| 1980 | { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, |
| 1981 | { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, |
| 1982 | { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, |
| 1983 | { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, |
| 1984 | { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, |
| 1985 | { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, |
| 1986 | |
| 1987 | /* 802.11 UNII */ |
| 1988 | { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, |
| 1989 | { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, |
| 1990 | { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, |
| 1991 | { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, |
| 1992 | { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, |
| 1993 | { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, |
| 1994 | { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, |
| 1995 | { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, |
| 1996 | { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, |
| 1997 | { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, |
| 1998 | { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, |
| 1999 | |
| 2000 | /* 802.11 Japan */ |
| 2001 | { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, |
| 2002 | { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, |
| 2003 | { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, |
| 2004 | { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, |
| 2005 | { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, |
| 2006 | { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, |
| 2007 | { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, |
| 2008 | }; |
| 2009 | |
| 2010 | /* |
| 2011 | * RF value list for rt3070 |
| 2012 | * Supports: 2.4 GHz |
| 2013 | */ |
Gertjan van Wingerde | cce5fc4 | 2009-11-10 22:42:40 +0100 | [diff] [blame] | 2014 | static const struct rf_channel rf_vals_302x[] = { |
Bartlomiej Zolnierkiewicz | 4da2933 | 2009-11-08 14:39:32 +0100 | [diff] [blame] | 2015 | {1, 241, 2, 2 }, |
| 2016 | {2, 241, 2, 7 }, |
| 2017 | {3, 242, 2, 2 }, |
| 2018 | {4, 242, 2, 7 }, |
| 2019 | {5, 243, 2, 2 }, |
| 2020 | {6, 243, 2, 7 }, |
| 2021 | {7, 244, 2, 2 }, |
| 2022 | {8, 244, 2, 7 }, |
| 2023 | {9, 245, 2, 2 }, |
| 2024 | {10, 245, 2, 7 }, |
| 2025 | {11, 246, 2, 2 }, |
| 2026 | {12, 246, 2, 7 }, |
| 2027 | {13, 247, 2, 2 }, |
| 2028 | {14, 248, 2, 4 }, |
| 2029 | }; |
| 2030 | |
| 2031 | int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
| 2032 | { |
Bartlomiej Zolnierkiewicz | 4da2933 | 2009-11-08 14:39:32 +0100 | [diff] [blame] | 2033 | struct hw_mode_spec *spec = &rt2x00dev->spec; |
| 2034 | struct channel_info *info; |
| 2035 | char *tx_power1; |
| 2036 | char *tx_power2; |
| 2037 | unsigned int i; |
| 2038 | u16 eeprom; |
| 2039 | |
| 2040 | /* |
Gertjan van Wingerde | 93b6bd2 | 2009-12-14 20:33:55 +0100 | [diff] [blame] | 2041 | * Disable powersaving as default on PCI devices. |
| 2042 | */ |
Gertjan van Wingerde | cea90e5 | 2010-02-13 20:55:47 +0100 | [diff] [blame] | 2043 | if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) |
Gertjan van Wingerde | 93b6bd2 | 2009-12-14 20:33:55 +0100 | [diff] [blame] | 2044 | rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
| 2045 | |
| 2046 | /* |
Bartlomiej Zolnierkiewicz | 4da2933 | 2009-11-08 14:39:32 +0100 | [diff] [blame] | 2047 | * Initialize all hw fields. |
| 2048 | */ |
| 2049 | rt2x00dev->hw->flags = |
| 2050 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
| 2051 | IEEE80211_HW_SIGNAL_DBM | |
| 2052 | IEEE80211_HW_SUPPORTS_PS | |
| 2053 | IEEE80211_HW_PS_NULLFUNC_STACK; |
| 2054 | |
Bartlomiej Zolnierkiewicz | 4da2933 | 2009-11-08 14:39:32 +0100 | [diff] [blame] | 2055 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
| 2056 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
| 2057 | rt2x00_eeprom_addr(rt2x00dev, |
| 2058 | EEPROM_MAC_ADDR_0)); |
| 2059 | |
| 2060 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); |
| 2061 | |
| 2062 | /* |
| 2063 | * Initialize hw_mode information. |
| 2064 | */ |
| 2065 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
| 2066 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; |
| 2067 | |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 2068 | if (rt2x00_rf(rt2x00dev, RF2820) || |
| 2069 | rt2x00_rf(rt2x00dev, RF2720) || |
Gertjan van Wingerde | 6c0fe26 | 2009-12-30 11:36:31 +0100 | [diff] [blame] | 2070 | rt2x00_rf(rt2x00dev, RF3052)) { |
Bartlomiej Zolnierkiewicz | 4da2933 | 2009-11-08 14:39:32 +0100 | [diff] [blame] | 2071 | spec->num_channels = 14; |
| 2072 | spec->channels = rf_vals; |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 2073 | } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) { |
Bartlomiej Zolnierkiewicz | 4da2933 | 2009-11-08 14:39:32 +0100 | [diff] [blame] | 2074 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
| 2075 | spec->num_channels = ARRAY_SIZE(rf_vals); |
| 2076 | spec->channels = rf_vals; |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 2077 | } else if (rt2x00_rf(rt2x00dev, RF3020) || |
| 2078 | rt2x00_rf(rt2x00dev, RF2020) || |
| 2079 | rt2x00_rf(rt2x00dev, RF3021) || |
| 2080 | rt2x00_rf(rt2x00dev, RF3022)) { |
Gertjan van Wingerde | cce5fc4 | 2009-11-10 22:42:40 +0100 | [diff] [blame] | 2081 | spec->num_channels = ARRAY_SIZE(rf_vals_302x); |
| 2082 | spec->channels = rf_vals_302x; |
Bartlomiej Zolnierkiewicz | 4da2933 | 2009-11-08 14:39:32 +0100 | [diff] [blame] | 2083 | } |
| 2084 | |
| 2085 | /* |
| 2086 | * Initialize HT information. |
| 2087 | */ |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 2088 | if (!rt2x00_rf(rt2x00dev, RF2020)) |
Gertjan van Wingerde | 38a522e | 2009-11-23 22:44:47 +0100 | [diff] [blame] | 2089 | spec->ht.ht_supported = true; |
| 2090 | else |
| 2091 | spec->ht.ht_supported = false; |
| 2092 | |
Bartlomiej Zolnierkiewicz | 4da2933 | 2009-11-08 14:39:32 +0100 | [diff] [blame] | 2093 | spec->ht.cap = |
| 2094 | IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
| 2095 | IEEE80211_HT_CAP_GRN_FLD | |
| 2096 | IEEE80211_HT_CAP_SGI_20 | |
| 2097 | IEEE80211_HT_CAP_SGI_40 | |
| 2098 | IEEE80211_HT_CAP_TX_STBC | |
Johannes Berg | 9a418af | 2009-12-17 13:55:48 +0100 | [diff] [blame] | 2099 | IEEE80211_HT_CAP_RX_STBC; |
Bartlomiej Zolnierkiewicz | 4da2933 | 2009-11-08 14:39:32 +0100 | [diff] [blame] | 2100 | spec->ht.ampdu_factor = 3; |
| 2101 | spec->ht.ampdu_density = 4; |
| 2102 | spec->ht.mcs.tx_params = |
| 2103 | IEEE80211_HT_MCS_TX_DEFINED | |
| 2104 | IEEE80211_HT_MCS_TX_RX_DIFF | |
| 2105 | ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) << |
| 2106 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); |
| 2107 | |
| 2108 | switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) { |
| 2109 | case 3: |
| 2110 | spec->ht.mcs.rx_mask[2] = 0xff; |
| 2111 | case 2: |
| 2112 | spec->ht.mcs.rx_mask[1] = 0xff; |
| 2113 | case 1: |
| 2114 | spec->ht.mcs.rx_mask[0] = 0xff; |
| 2115 | spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ |
| 2116 | break; |
| 2117 | } |
| 2118 | |
| 2119 | /* |
| 2120 | * Create channel information array |
| 2121 | */ |
| 2122 | info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); |
| 2123 | if (!info) |
| 2124 | return -ENOMEM; |
| 2125 | |
| 2126 | spec->channels_info = info; |
| 2127 | |
| 2128 | tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); |
| 2129 | tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); |
| 2130 | |
| 2131 | for (i = 0; i < 14; i++) { |
| 2132 | info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]); |
| 2133 | info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]); |
| 2134 | } |
| 2135 | |
| 2136 | if (spec->num_channels > 14) { |
| 2137 | tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1); |
| 2138 | tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2); |
| 2139 | |
| 2140 | for (i = 14; i < spec->num_channels; i++) { |
| 2141 | info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]); |
| 2142 | info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]); |
| 2143 | } |
| 2144 | } |
| 2145 | |
| 2146 | return 0; |
| 2147 | } |
| 2148 | EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode); |
| 2149 | |
| 2150 | /* |
Bartlomiej Zolnierkiewicz | 2ce3399 | 2009-11-04 18:37:05 +0100 | [diff] [blame] | 2151 | * IEEE80211 stack callback functions. |
| 2152 | */ |
| 2153 | static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, |
| 2154 | u32 *iv32, u16 *iv16) |
| 2155 | { |
| 2156 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 2157 | struct mac_iveiv_entry iveiv_entry; |
| 2158 | u32 offset; |
| 2159 | |
| 2160 | offset = MAC_IVEIV_ENTRY(hw_key_idx); |
| 2161 | rt2800_register_multiread(rt2x00dev, offset, |
| 2162 | &iveiv_entry, sizeof(iveiv_entry)); |
| 2163 | |
Julia Lawall | 855da5e | 2009-12-13 17:07:45 +0100 | [diff] [blame] | 2164 | memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16)); |
| 2165 | memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32)); |
Bartlomiej Zolnierkiewicz | 2ce3399 | 2009-11-04 18:37:05 +0100 | [diff] [blame] | 2166 | } |
| 2167 | |
| 2168 | static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) |
| 2169 | { |
| 2170 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 2171 | u32 reg; |
| 2172 | bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); |
| 2173 | |
| 2174 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); |
| 2175 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); |
| 2176 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); |
| 2177 | |
| 2178 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); |
| 2179 | rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); |
| 2180 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); |
| 2181 | |
| 2182 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); |
| 2183 | rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); |
| 2184 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); |
| 2185 | |
| 2186 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); |
| 2187 | rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); |
| 2188 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); |
| 2189 | |
| 2190 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); |
| 2191 | rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); |
| 2192 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); |
| 2193 | |
| 2194 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); |
| 2195 | rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); |
| 2196 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); |
| 2197 | |
| 2198 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); |
| 2199 | rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); |
| 2200 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); |
| 2201 | |
| 2202 | return 0; |
| 2203 | } |
| 2204 | |
| 2205 | static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, |
| 2206 | const struct ieee80211_tx_queue_params *params) |
| 2207 | { |
| 2208 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 2209 | struct data_queue *queue; |
| 2210 | struct rt2x00_field32 field; |
| 2211 | int retval; |
| 2212 | u32 reg; |
| 2213 | u32 offset; |
| 2214 | |
| 2215 | /* |
| 2216 | * First pass the configuration through rt2x00lib, that will |
| 2217 | * update the queue settings and validate the input. After that |
| 2218 | * we are free to update the registers based on the value |
| 2219 | * in the queue parameter. |
| 2220 | */ |
| 2221 | retval = rt2x00mac_conf_tx(hw, queue_idx, params); |
| 2222 | if (retval) |
| 2223 | return retval; |
| 2224 | |
| 2225 | /* |
| 2226 | * We only need to perform additional register initialization |
| 2227 | * for WMM queues/ |
| 2228 | */ |
| 2229 | if (queue_idx >= 4) |
| 2230 | return 0; |
| 2231 | |
| 2232 | queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); |
| 2233 | |
| 2234 | /* Update WMM TXOP register */ |
| 2235 | offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); |
| 2236 | field.bit_offset = (queue_idx & 1) * 16; |
| 2237 | field.bit_mask = 0xffff << field.bit_offset; |
| 2238 | |
| 2239 | rt2800_register_read(rt2x00dev, offset, ®); |
| 2240 | rt2x00_set_field32(®, field, queue->txop); |
| 2241 | rt2800_register_write(rt2x00dev, offset, reg); |
| 2242 | |
| 2243 | /* Update WMM registers */ |
| 2244 | field.bit_offset = queue_idx * 4; |
| 2245 | field.bit_mask = 0xf << field.bit_offset; |
| 2246 | |
| 2247 | rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); |
| 2248 | rt2x00_set_field32(®, field, queue->aifs); |
| 2249 | rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); |
| 2250 | |
| 2251 | rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); |
| 2252 | rt2x00_set_field32(®, field, queue->cw_min); |
| 2253 | rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); |
| 2254 | |
| 2255 | rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); |
| 2256 | rt2x00_set_field32(®, field, queue->cw_max); |
| 2257 | rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); |
| 2258 | |
| 2259 | /* Update EDCA registers */ |
| 2260 | offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); |
| 2261 | |
| 2262 | rt2800_register_read(rt2x00dev, offset, ®); |
| 2263 | rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); |
| 2264 | rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); |
| 2265 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); |
| 2266 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); |
| 2267 | rt2800_register_write(rt2x00dev, offset, reg); |
| 2268 | |
| 2269 | return 0; |
| 2270 | } |
| 2271 | |
| 2272 | static u64 rt2800_get_tsf(struct ieee80211_hw *hw) |
| 2273 | { |
| 2274 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 2275 | u64 tsf; |
| 2276 | u32 reg; |
| 2277 | |
| 2278 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); |
| 2279 | tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; |
| 2280 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); |
| 2281 | tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); |
| 2282 | |
| 2283 | return tsf; |
| 2284 | } |
| 2285 | |
| 2286 | const struct ieee80211_ops rt2800_mac80211_ops = { |
| 2287 | .tx = rt2x00mac_tx, |
| 2288 | .start = rt2x00mac_start, |
| 2289 | .stop = rt2x00mac_stop, |
| 2290 | .add_interface = rt2x00mac_add_interface, |
| 2291 | .remove_interface = rt2x00mac_remove_interface, |
| 2292 | .config = rt2x00mac_config, |
| 2293 | .configure_filter = rt2x00mac_configure_filter, |
| 2294 | .set_tim = rt2x00mac_set_tim, |
| 2295 | .set_key = rt2x00mac_set_key, |
| 2296 | .get_stats = rt2x00mac_get_stats, |
| 2297 | .get_tkip_seq = rt2800_get_tkip_seq, |
| 2298 | .set_rts_threshold = rt2800_set_rts_threshold, |
| 2299 | .bss_info_changed = rt2x00mac_bss_info_changed, |
| 2300 | .conf_tx = rt2800_conf_tx, |
Bartlomiej Zolnierkiewicz | 2ce3399 | 2009-11-04 18:37:05 +0100 | [diff] [blame] | 2301 | .get_tsf = rt2800_get_tsf, |
| 2302 | .rfkill_poll = rt2x00mac_rfkill_poll, |
| 2303 | }; |
| 2304 | EXPORT_SYMBOL_GPL(rt2800_mac80211_ops); |