blob: c0bfd59a7a368f1dde18c428a5c9aa41df5a6087 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +04002 * Copyright 2002, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
Sergei Shtylyovce28f942008-04-23 22:43:55 +040025
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#include <linux/delay.h>
28
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <asm/mach-au1x00/au1000.h>
30#include <asm/mach-pb1x00/pb1100.h>
31
Ralf Baechle49a89ef2007-10-11 23:46:15 +010032void board_reset(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070033{
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040034 /* Hit BCSR.RST_VDDI[SOFT_RESET] */
35 au_writel(0x00000000, PB1100_RST_VDDI);
Linus Torvalds1da177e2005-04-16 15:20:36 -070036}
37
38void __init board_setup(void)
39{
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040040 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040042 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
Linus Torvalds1da177e2005-04-16 15:20:36 -070043 au_writel(8, SYS_AUXPLL);
44 au_writel(0, SYS_PININPUTEN);
45 udelay(100);
46
Florian Fainellif7086312007-09-25 17:07:24 +020047#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
Ralf Baechle3f21cde2006-11-07 10:19:05 +000048 {
49 u32 pin_func, sys_freqctrl, sys_clksrc;
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040051 /* Configure pins GPIO[14:9] as GPIO */
52 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040054 /* Zero and disable FREQ2 */
Ralf Baechle3f21cde2006-11-07 10:19:05 +000055 sys_freqctrl = au_readl(SYS_FREQCTRL0);
56 sys_freqctrl &= ~0xFFF00000;
57 au_writel(sys_freqctrl, SYS_FREQCTRL0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040059 /* Zero and disable USBH/USBD/IrDA clock */
Ralf Baechle3f21cde2006-11-07 10:19:05 +000060 sys_clksrc = au_readl(SYS_CLKSRC);
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040061 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
Ralf Baechle3f21cde2006-11-07 10:19:05 +000062 au_writel(sys_clksrc, SYS_CLKSRC);
Linus Torvalds1da177e2005-04-16 15:20:36 -070063
Ralf Baechle3f21cde2006-11-07 10:19:05 +000064 sys_freqctrl = au_readl(SYS_FREQCTRL0);
65 sys_freqctrl &= ~0xFFF00000;
Linus Torvalds1da177e2005-04-16 15:20:36 -070066
Ralf Baechle3f21cde2006-11-07 10:19:05 +000067 sys_clksrc = au_readl(SYS_CLKSRC);
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040068 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040070 /* FREQ2 = aux / 2 = 48 MHz */
71 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
72 SYS_FC_FE2 | SYS_FC_FS2;
Ralf Baechle3f21cde2006-11-07 10:19:05 +000073 au_writel(sys_freqctrl, SYS_FREQCTRL0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
Ralf Baechle3f21cde2006-11-07 10:19:05 +000075 /*
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040076 * Route 48 MHz FREQ2 into USBH/USBD/IrDA
Ralf Baechle3f21cde2006-11-07 10:19:05 +000077 */
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040078 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
Ralf Baechle3f21cde2006-11-07 10:19:05 +000079 au_writel(sys_clksrc, SYS_CLKSRC);
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040081 /* Setup the static bus controller */
Ralf Baechle3f21cde2006-11-07 10:19:05 +000082 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
83 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
84 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
85
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040086 /*
87 * Get USB Functionality pin state (device vs host drive pins).
88 */
89 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
90 /* 2nd USB port is USB host. */
91 pin_func |= SYS_PF_USB;
Ralf Baechle3f21cde2006-11-07 10:19:05 +000092 au_writel(pin_func, SYS_PINFUNC);
93 }
Florian Fainellif7086312007-09-25 17:07:24 +020094#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
Linus Torvalds1da177e2005-04-16 15:20:36 -070095
96 /* Enable sys bus clock divider when IDLE state or no bus activity. */
97 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
98
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +040099 /* Enable the RTC if not already enabled. */
Ralf Baechle3f21cde2006-11-07 10:19:05 +0000100 if (!(readb(base + 0x28) & 0x20)) {
101 writeb(readb(base + 0x28) | 0x20, base + 0x28);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102 au_sync();
103 }
Sergei Shtylyovbe1c3c12008-04-30 23:26:28 +0400104 /* Put the clock in BCD mode. */
Ralf Baechle3f21cde2006-11-07 10:19:05 +0000105 if (readb(base + 0x2C) & 0x4) { /* reg B */
106 writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107 au_sync();
108 }
109}