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John Crispin85639912013-01-21 18:25:59 +01001/*
2 * Ralink SoC register definitions
3 *
John Crispin97b92102016-05-05 09:57:56 +02004 * Copyright (C) 2013 John Crispin <john@phrozen.org>
John Crispin85639912013-01-21 18:25:59 +01005 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#ifndef _RALINK_REGS_H_
14#define _RALINK_REGS_H_
15
John Crispin418d29c2015-11-04 11:50:07 +010016enum ralink_soc_type {
17 RALINK_UNKNOWN = 0,
18 RT2880_SOC,
19 RT3883_SOC,
20 RT305X_SOC_RT3050,
21 RT305X_SOC_RT3052,
22 RT305X_SOC_RT3350,
23 RT305X_SOC_RT3352,
24 RT305X_SOC_RT5350,
25 MT762X_SOC_MT7620A,
26 MT762X_SOC_MT7620N,
27 MT762X_SOC_MT7621AT,
28 MT762X_SOC_MT7628AN,
29 MT762X_SOC_MT7688,
30};
31extern enum ralink_soc_type ralink_soc;
32
John Crispin85639912013-01-21 18:25:59 +010033extern __iomem void *rt_sysc_membase;
34extern __iomem void *rt_memc_membase;
35
36static inline void rt_sysc_w32(u32 val, unsigned reg)
37{
38 __raw_writel(val, rt_sysc_membase + reg);
39}
40
41static inline u32 rt_sysc_r32(unsigned reg)
42{
43 return __raw_readl(rt_sysc_membase + reg);
44}
45
John Crispin47e14d62013-05-19 00:42:23 +020046static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
47{
48 u32 val = rt_sysc_r32(reg) & ~clr;
49
50 __raw_writel(val | set, rt_sysc_membase + reg);
51}
52
John Crispin85639912013-01-21 18:25:59 +010053static inline void rt_memc_w32(u32 val, unsigned reg)
54{
55 __raw_writel(val, rt_memc_membase + reg);
56}
57
58static inline u32 rt_memc_r32(unsigned reg)
59{
60 return __raw_readl(rt_memc_membase + reg);
61}
62
63#endif /* _RALINK_REGS_H_ */