blob: f91273912eb89718ec27bdf7e88c0e3f27beef87 [file] [log] [blame]
Christian Koenigdafc3bd2009-10-11 23:49:13 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 */
Thierry Redinge3b2e032013-01-14 13:36:30 +010026#include <linux/hdmi.h>
Pierre Ossmana2098252013-11-06 20:09:08 +010027#include <linux/gcd.h>
David Howells760285e2012-10-02 18:01:07 +010028#include <drm/drmP.h>
29#include <drm/radeon_drm.h>
Christian Koenigdafc3bd2009-10-11 23:49:13 +020030#include "radeon.h"
Daniel Vetter3574dda2011-02-18 17:59:19 +010031#include "radeon_asic.h"
Slava Grigorev3cdde022014-12-02 15:22:43 -050032#include "radeon_audio.h"
Rafał Miłeckic6543a62012-04-28 23:35:24 +020033#include "r600d.h"
Christian Koenigdafc3bd2009-10-11 23:49:13 +020034#include "atom.h"
35
36/*
37 * HDMI color format
38 */
39enum r600_hdmi_color_format {
40 RGB = 0,
41 YCC_422 = 1,
42 YCC_444 = 2
43};
44
45/*
46 * IEC60958 status bits
47 */
48enum r600_hdmi_iec_status_bits {
49 AUDIO_STATUS_DIG_ENABLE = 0x01,
Rafał Miłecki3fe373d2010-03-06 13:03:38 +000050 AUDIO_STATUS_V = 0x02,
51 AUDIO_STATUS_VCFG = 0x04,
Christian Koenigdafc3bd2009-10-11 23:49:13 +020052 AUDIO_STATUS_EMPHASIS = 0x08,
53 AUDIO_STATUS_COPYRIGHT = 0x10,
54 AUDIO_STATUS_NONAUDIO = 0x20,
55 AUDIO_STATUS_PROFESSIONAL = 0x40,
Rafał Miłecki3fe373d2010-03-06 13:03:38 +000056 AUDIO_STATUS_LEVEL = 0x80
Christian Koenigdafc3bd2009-10-11 23:49:13 +020057};
58
Alex Deucher72156672014-09-18 16:36:08 -040059static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
60{
61 struct r600_audio_pin status;
62 uint32_t value;
63
64 value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
65
66 /* number of channels */
67 status.channels = (value & 0x7) + 1;
68
69 /* bits per sample */
70 switch ((value & 0xF0) >> 4) {
71 case 0x0:
72 status.bits_per_sample = 8;
73 break;
74 case 0x1:
75 status.bits_per_sample = 16;
76 break;
77 case 0x2:
78 status.bits_per_sample = 20;
79 break;
80 case 0x3:
81 status.bits_per_sample = 24;
82 break;
83 case 0x4:
84 status.bits_per_sample = 32;
85 break;
86 default:
87 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
88 (int)value);
89 status.bits_per_sample = 16;
90 }
91
92 /* current sampling rate in HZ */
93 if (value & 0x4000)
94 status.rate = 44100;
95 else
96 status.rate = 48000;
97 status.rate *= ((value >> 11) & 0x7) + 1;
98 status.rate /= ((value >> 8) & 0x7) + 1;
99
100 value = RREG32(R600_AUDIO_STATUS_BITS);
101
102 /* iec 60958 status bits */
103 status.status_bits = value & 0xff;
104
105 /* iec 60958 category code */
106 status.category_code = (value >> 8) & 0xff;
107
108 return status;
109}
110
111/*
112 * update all hdmi interfaces with current audio parameters
113 */
114void r600_audio_update_hdmi(struct work_struct *work)
115{
116 struct radeon_device *rdev = container_of(work, struct radeon_device,
117 audio_work);
118 struct drm_device *dev = rdev->ddev;
119 struct r600_audio_pin audio_status = r600_audio_status(rdev);
120 struct drm_encoder *encoder;
121 bool changed = false;
122
123 if (rdev->audio.pin[0].channels != audio_status.channels ||
124 rdev->audio.pin[0].rate != audio_status.rate ||
125 rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
126 rdev->audio.pin[0].status_bits != audio_status.status_bits ||
127 rdev->audio.pin[0].category_code != audio_status.category_code) {
128 rdev->audio.pin[0] = audio_status;
129 changed = true;
130 }
131
132 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
133 if (!radeon_encoder_is_digital(encoder))
134 continue;
135 if (changed || r600_hdmi_buffer_status_changed(encoder))
136 r600_hdmi_update_audio_settings(encoder);
137 }
138}
139
140/* enable the audio stream */
141void r600_audio_enable(struct radeon_device *rdev,
142 struct r600_audio_pin *pin,
Alex Deucherd3d8c142014-09-18 17:26:39 -0400143 u8 enable_mask)
Alex Deucher72156672014-09-18 16:36:08 -0400144{
Alex Deucherd3d8c142014-09-18 17:26:39 -0400145 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
Alex Deucher72156672014-09-18 16:36:08 -0400146
147 if (!pin)
148 return;
149
Alex Deucherd3d8c142014-09-18 17:26:39 -0400150 if (enable_mask) {
151 tmp |= AUDIO_ENABLED;
152 if (enable_mask & 1)
153 tmp |= PIN0_AUDIO_ENABLED;
154 if (enable_mask & 2)
155 tmp |= PIN1_AUDIO_ENABLED;
156 if (enable_mask & 4)
157 tmp |= PIN2_AUDIO_ENABLED;
158 if (enable_mask & 8)
159 tmp |= PIN3_AUDIO_ENABLED;
Alex Deucher72156672014-09-18 16:36:08 -0400160 } else {
Alex Deucherd3d8c142014-09-18 17:26:39 -0400161 tmp &= ~(AUDIO_ENABLED |
162 PIN0_AUDIO_ENABLED |
163 PIN1_AUDIO_ENABLED |
164 PIN2_AUDIO_ENABLED |
165 PIN3_AUDIO_ENABLED);
Alex Deucher72156672014-09-18 16:36:08 -0400166 }
Alex Deucherd3d8c142014-09-18 17:26:39 -0400167
168 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
Alex Deucher72156672014-09-18 16:36:08 -0400169}
170
Alex Deucher72156672014-09-18 16:36:08 -0400171struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
172{
173 /* only one pin on 6xx-NI */
174 return &rdev->audio.pin[0];
175}
176
Slava Grigorev64424d6e2014-12-06 20:19:16 -0500177void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset,
178 const struct radeon_hdmi_acr *acr)
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200179{
180 struct drm_device *dev = encoder->dev;
181 struct radeon_device *rdev = dev->dev_private;
Slava Grigorev64424d6e2014-12-06 20:19:16 -0500182
183 /* DCE 3.0 uses register that's normally for CRC_CONTROL */
184 uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
185 HDMI0_ACR_PACKET_CONTROL;
186 WREG32_P(acr_ctl + offset,
187 HDMI0_ACR_SOURCE | /* select SW CTS value */
188 HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
189 ~(HDMI0_ACR_SOURCE |
190 HDMI0_ACR_AUTO_SEND));
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200191
Rafał Miłecki68706332014-05-16 11:10:30 +0200192 WREG32_P(HDMI0_ACR_32_0 + offset,
Slava Grigorev64424d6e2014-12-06 20:19:16 -0500193 HDMI0_ACR_CTS_32(acr->cts_32khz),
194 ~HDMI0_ACR_CTS_32_MASK);
Rafał Miłecki68706332014-05-16 11:10:30 +0200195 WREG32_P(HDMI0_ACR_32_1 + offset,
Slava Grigorev64424d6e2014-12-06 20:19:16 -0500196 HDMI0_ACR_N_32(acr->n_32khz),
197 ~HDMI0_ACR_N_32_MASK);
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200198
Rafał Miłecki68706332014-05-16 11:10:30 +0200199 WREG32_P(HDMI0_ACR_44_0 + offset,
Slava Grigorev64424d6e2014-12-06 20:19:16 -0500200 HDMI0_ACR_CTS_44(acr->cts_44_1khz),
201 ~HDMI0_ACR_CTS_44_MASK);
Rafał Miłecki68706332014-05-16 11:10:30 +0200202 WREG32_P(HDMI0_ACR_44_1 + offset,
Slava Grigorev64424d6e2014-12-06 20:19:16 -0500203 HDMI0_ACR_N_44(acr->n_44_1khz),
204 ~HDMI0_ACR_N_44_MASK);
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200205
Rafał Miłecki68706332014-05-16 11:10:30 +0200206 WREG32_P(HDMI0_ACR_48_0 + offset,
Slava Grigorev64424d6e2014-12-06 20:19:16 -0500207 HDMI0_ACR_CTS_48(acr->cts_48khz),
208 ~HDMI0_ACR_CTS_48_MASK);
Rafał Miłecki68706332014-05-16 11:10:30 +0200209 WREG32_P(HDMI0_ACR_48_1 + offset,
Slava Grigorev64424d6e2014-12-06 20:19:16 -0500210 HDMI0_ACR_N_48(acr->n_48khz),
211 ~HDMI0_ACR_N_48_MASK);
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200212}
213
214/*
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200215 * build a HDMI Video Info Frame
216 */
Slava Grigorev96ea7af2014-12-05 17:59:56 -0500217void r600_update_avi_infoframe(struct radeon_device *rdev, u32 offset,
218 unsigned char *buffer, size_t size)
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200219{
Thierry Redinge3b2e032013-01-14 13:36:30 +0100220 uint8_t *frame = buffer + 3;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200221
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200222 WREG32(HDMI0_AVI_INFO0 + offset,
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200223 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200224 WREG32(HDMI0_AVI_INFO1 + offset,
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200225 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200226 WREG32(HDMI0_AVI_INFO2 + offset,
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200227 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200228 WREG32(HDMI0_AVI_INFO3 + offset,
Slava Grigorev96ea7af2014-12-05 17:59:56 -0500229 frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200230}
231
232/*
233 * build a Audio Info Frame
234 */
Thierry Redinge3b2e032013-01-14 13:36:30 +0100235static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
236 const void *buffer, size_t size)
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200237{
238 struct drm_device *dev = encoder->dev;
239 struct radeon_device *rdev = dev->dev_private;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200240 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
241 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
242 uint32_t offset = dig->afmt->offset;
Thierry Redinge3b2e032013-01-14 13:36:30 +0100243 const u8 *frame = buffer + 3;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200244
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200245 WREG32(HDMI0_AUDIO_INFO0 + offset,
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200246 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200247 WREG32(HDMI0_AUDIO_INFO1 + offset,
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200248 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
249}
250
251/*
252 * test if audio buffer is filled enough to start playing
253 */
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200254static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200255{
256 struct drm_device *dev = encoder->dev;
257 struct radeon_device *rdev = dev->dev_private;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200258 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
259 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
260 uint32_t offset = dig->afmt->offset;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200261
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200262 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200263}
264
265/*
266 * have buffer status changed since last call?
267 */
268int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
269{
270 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200271 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200272 int status, result;
273
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200274 if (!dig->afmt || !dig->afmt->enabled)
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200275 return 0;
276
277 status = r600_hdmi_is_audio_buffer_filled(encoder);
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200278 result = dig->afmt->last_buffer_filled_status != status;
279 dig->afmt->last_buffer_filled_status = status;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200280
281 return result;
282}
283
284/*
285 * write the audio workaround status to the hardware
286 */
Rafał Miłecki8f33a152014-05-16 11:36:24 +0200287void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200288{
289 struct drm_device *dev = encoder->dev;
290 struct radeon_device *rdev = dev->dev_private;
291 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200292 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
293 uint32_t offset = dig->afmt->offset;
294 bool hdmi_audio_workaround = false; /* FIXME */
295 u32 value;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200296
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200297 if (!hdmi_audio_workaround ||
298 r600_hdmi_is_audio_buffer_filled(encoder))
299 value = 0; /* disable workaround */
300 else
301 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
302 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
303 value, ~HDMI0_AUDIO_TEST_EN);
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200304}
305
Slava Grigoreva85d6822014-12-05 13:38:31 -0500306void r600_hdmi_audio_set_dto(struct radeon_device *rdev,
307 struct radeon_crtc *crtc, unsigned int clock)
Alex Deucherb1f6f472013-04-18 10:50:55 -0400308{
Slava Grigoreva85d6822014-12-05 13:38:31 -0500309 struct radeon_encoder *radeon_encoder;
310 struct radeon_encoder_atom_dig *dig;
Alex Deucherb1f6f472013-04-18 10:50:55 -0400311
Slava Grigoreva85d6822014-12-05 13:38:31 -0500312 if (!crtc)
Alex Deucherb1f6f472013-04-18 10:50:55 -0400313 return;
314
Slava Grigoreva85d6822014-12-05 13:38:31 -0500315 radeon_encoder = to_radeon_encoder(crtc->encoder);
316 dig = radeon_encoder->enc_priv;
Alex Deucher1518dd82013-07-30 17:31:07 -0400317
Slava Grigoreva85d6822014-12-05 13:38:31 -0500318 if (!dig)
319 return;
320
321 if (dig->dig_encoder == 0) {
322 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100);
323 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
324 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
Alex Deucher55d4e022013-11-25 13:20:59 -0500325 } else {
Slava Grigoreva85d6822014-12-05 13:38:31 -0500326 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100);
327 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
328 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
Alex Deucher15865052013-04-22 09:42:07 -0400329 }
Alex Deucherb1f6f472013-04-18 10:50:55 -0400330}
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200331
332/*
333 * update the info frames with the data from the current display mode
334 */
335void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
336{
337 struct drm_device *dev = encoder->dev;
338 struct radeon_device *rdev = dev->dev_private;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
340 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
Thierry Redinge3b2e032013-01-14 13:36:30 +0100341 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
342 struct hdmi_avi_infoframe frame;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200343 uint32_t offset;
Thierry Redinge3b2e032013-01-14 13:36:30 +0100344 ssize_t err;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200345
Alex Deucherc2b4cacf2013-07-08 18:16:56 -0400346 if (!dig || !dig->afmt)
347 return;
348
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200349 /* Silent, r600_hdmi_enable will raise WARN for us */
350 if (!dig->afmt->enabled)
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200351 return;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200352 offset = dig->afmt->offset;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200353
Alex Deucher832eafa2014-02-18 11:07:55 -0500354 /* disable audio prior to setting up hw */
Slava Grigorev3cdde022014-12-02 15:22:43 -0500355 dig->afmt->pin = radeon_audio_get_pin(encoder);
Slava Grigorev8bf59822014-12-03 15:29:53 -0500356 radeon_audio_enable(rdev, dig->afmt->pin, 0);
Alex Deucher832eafa2014-02-18 11:07:55 -0500357
Slava Grigoreva85d6822014-12-05 13:38:31 -0500358 radeon_audio_set_dto(encoder, mode->clock);
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200359
Rafał Miłecki68706332014-05-16 11:10:30 +0200360 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
361 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
362 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
363 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
364 HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */
365 ~(HDMI0_AUDIO_SAMPLE_SEND |
366 HDMI0_AUDIO_DELAY_EN_MASK |
367 HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
368 HDMI0_60958_CS_UPDATE));
Alex Deucher0ffae602013-08-15 12:03:37 -0400369
Rafał Miłecki68706332014-05-16 11:10:30 +0200370 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
371 HDMI0_NULL_SEND | /* send null packets when required */
372 HDMI0_GC_SEND | /* send general control packets */
373 HDMI0_GC_CONT); /* send general control packets every frame */
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200374
Rafał Miłecki68706332014-05-16 11:10:30 +0200375 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
376 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
377 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
378 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
379 HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200380
Rafał Miłecki68706332014-05-16 11:10:30 +0200381 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
382 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
383 HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */
384 ~(HDMI0_AVI_INFO_LINE_MASK |
385 HDMI0_AUDIO_INFO_LINE_MASK));
Rafał Miłecki1c3439f2012-05-06 17:29:45 +0200386
Rafał Miłecki68706332014-05-16 11:10:30 +0200387 WREG32_AND(HDMI0_GC + offset,
388 ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200389
Thierry Redinge3b2e032013-01-14 13:36:30 +0100390 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
391 if (err < 0) {
392 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
393 return;
394 }
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200395
Thierry Redinge3b2e032013-01-14 13:36:30 +0100396 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
397 if (err < 0) {
398 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
399 return;
400 }
401
Slava Grigorev96ea7af2014-12-05 17:59:56 -0500402 radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer));
Rafał Miłecki68706332014-05-16 11:10:30 +0200403
404 /* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */
405
406 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
407 ~(HDMI0_GENERIC0_SEND |
408 HDMI0_GENERIC0_CONT |
409 HDMI0_GENERIC0_UPDATE |
410 HDMI0_GENERIC1_SEND |
411 HDMI0_GENERIC1_CONT |
412 HDMI0_GENERIC0_LINE_MASK |
413 HDMI0_GENERIC1_LINE_MASK));
414
Slava Grigorev64424d6e2014-12-06 20:19:16 -0500415 radeon_audio_update_acr(encoder, mode->clock);
Rafał Miłecki1c3439f2012-05-06 17:29:45 +0200416
Rafał Miłecki68706332014-05-16 11:10:30 +0200417 WREG32_P(HDMI0_60958_0 + offset,
418 HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
419 ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
420 HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
421
422 WREG32_P(HDMI0_60958_1 + offset,
423 HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
424 ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
425
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300426 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
Rafał Miłeckic6543a62012-04-28 23:35:24 +0200427 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
428 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
429 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
430 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200431
Alex Deucher832eafa2014-02-18 11:07:55 -0500432 /* enable audio after to setting up hw */
Slava Grigorev8bf59822014-12-03 15:29:53 -0500433 radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200434}
435
Rafał Miłecki8e4d9f82014-05-16 11:10:31 +0200436/**
437 * r600_hdmi_update_audio_settings - Update audio infoframe
438 *
439 * @encoder: drm encoder
440 *
441 * Gets info about current audio stream and updates audio infoframe.
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200442 */
Christian König58bd0862010-04-05 22:14:55 +0200443void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200444{
445 struct drm_device *dev = encoder->dev;
446 struct radeon_device *rdev = dev->dev_private;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200447 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
448 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
Alex Deucherb5306022013-07-31 16:51:33 -0400449 struct r600_audio_pin audio = r600_audio_status(rdev);
Thierry Redinge3b2e032013-01-14 13:36:30 +0100450 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
451 struct hdmi_audio_infoframe frame;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200452 uint32_t offset;
Rafał Miłecki8e4d9f82014-05-16 11:10:31 +0200453 uint32_t value;
Thierry Redinge3b2e032013-01-14 13:36:30 +0100454 ssize_t err;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200455
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200456 if (!dig->afmt || !dig->afmt->enabled)
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200457 return;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200458 offset = dig->afmt->offset;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200459
460 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
461 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
Rafał Miłecki3299de92012-05-14 21:25:57 +0200462 audio.channels, audio.rate, audio.bits_per_sample);
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200463 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
Rafał Miłecki3299de92012-05-14 21:25:57 +0200464 (int)audio.status_bits, (int)audio.category_code);
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200465
Thierry Redinge3b2e032013-01-14 13:36:30 +0100466 err = hdmi_audio_infoframe_init(&frame);
467 if (err < 0) {
468 DRM_ERROR("failed to setup audio infoframe\n");
469 return;
470 }
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200471
Thierry Redinge3b2e032013-01-14 13:36:30 +0100472 frame.channels = audio.channels;
473
474 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
475 if (err < 0) {
476 DRM_ERROR("failed to pack audio infoframe\n");
477 return;
478 }
479
Rafał Miłecki8e4d9f82014-05-16 11:10:31 +0200480 value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
481 if (value & HDMI0_AUDIO_TEST_EN)
482 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
483 value & ~HDMI0_AUDIO_TEST_EN);
484
485 WREG32_OR(HDMI0_CONTROL + offset,
486 HDMI0_ERROR_ACK);
487
488 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
489 ~HDMI0_AUDIO_INFO_SOURCE);
490
Thierry Redinge3b2e032013-01-14 13:36:30 +0100491 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
Rafał Miłecki8e4d9f82014-05-16 11:10:31 +0200492
493 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
494 HDMI0_AUDIO_INFO_CONT |
495 HDMI0_AUDIO_INFO_UPDATE);
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200496}
497
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200498/*
Rafał Miłecki2cd62182010-03-08 22:14:01 +0000499 * enable the HDMI engine
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200500 */
Alex Deuchera973bea2013-04-18 11:32:16 -0400501void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200502{
Rafał Miłecki2cd62182010-03-08 22:14:01 +0000503 struct drm_device *dev = encoder->dev;
504 struct radeon_device *rdev = dev->dev_private;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200505 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200506 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
Alex Deuchera973bea2013-04-18 11:32:16 -0400507 u32 hdmi = HDMI0_ERROR_ACK;
Alex Deucher16823d12010-04-16 11:35:30 -0400508
Alex Deucherc2b4cacf2013-07-08 18:16:56 -0400509 if (!dig || !dig->afmt)
510 return;
511
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200512 /* Silent, r600_hdmi_enable will raise WARN for us */
Alex Deuchera973bea2013-04-18 11:32:16 -0400513 if (enable && dig->afmt->enabled)
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200514 return;
Alex Deuchera973bea2013-04-18 11:32:16 -0400515 if (!enable && !dig->afmt->enabled)
516 return;
Rafał Miłecki64fb4fb2012-04-30 15:44:53 +0200517
Alex Deucher4adb34e2014-09-18 18:07:08 -0400518 if (!enable && dig->afmt->pin) {
Slava Grigorev8bf59822014-12-03 15:29:53 -0500519 radeon_audio_enable(rdev, dig->afmt->pin, 0);
Alex Deucher4adb34e2014-09-18 18:07:08 -0400520 dig->afmt->pin = NULL;
521 }
522
Rafał Miłecki64fb4fb2012-04-30 15:44:53 +0200523 /* Older chipsets require setting HDMI and routing manually */
Alex Deuchera973bea2013-04-18 11:32:16 -0400524 if (!ASIC_IS_DCE3(rdev)) {
525 if (enable)
526 hdmi |= HDMI0_ENABLE;
Rafał Miłecki5715f672010-03-06 13:03:35 +0000527 switch (radeon_encoder->encoder_id) {
528 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
Alex Deuchera973bea2013-04-18 11:32:16 -0400529 if (enable) {
530 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
531 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
532 } else {
533 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
534 }
Rafał Miłecki5715f672010-03-06 13:03:35 +0000535 break;
536 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
Alex Deuchera973bea2013-04-18 11:32:16 -0400537 if (enable) {
538 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
539 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
540 } else {
541 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
542 }
Rafał Miłecki64fb4fb2012-04-30 15:44:53 +0200543 break;
544 case ENCODER_OBJECT_ID_INTERNAL_DDI:
Alex Deuchera973bea2013-04-18 11:32:16 -0400545 if (enable) {
546 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
547 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
548 } else {
549 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
550 }
Rafał Miłecki64fb4fb2012-04-30 15:44:53 +0200551 break;
552 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
Alex Deuchera973bea2013-04-18 11:32:16 -0400553 if (enable)
554 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
Rafał Miłecki5715f672010-03-06 13:03:35 +0000555 break;
556 default:
Rafał Miłecki64fb4fb2012-04-30 15:44:53 +0200557 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
558 radeon_encoder->encoder_id);
Rafał Miłecki5715f672010-03-06 13:03:35 +0000559 break;
560 }
Alex Deuchera973bea2013-04-18 11:32:16 -0400561 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
Rafał Miłecki5715f672010-03-06 13:03:35 +0000562 }
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200563
Alex Deucherf122c612012-03-30 08:59:57 -0400564 if (rdev->irq.installed) {
Christian Koenigf2594932010-04-10 03:13:16 +0200565 /* if irq is available use it */
Alex Deucher9054ae12013-04-18 09:42:13 -0400566 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
Alex Deuchera973bea2013-04-18 11:32:16 -0400567 if (enable)
Alex Deucher9054ae12013-04-18 09:42:13 -0400568 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
Alex Deuchera973bea2013-04-18 11:32:16 -0400569 else
570 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
Christian Koenigf2594932010-04-10 03:13:16 +0200571 }
Christian König58bd0862010-04-05 22:14:55 +0200572
Alex Deuchera973bea2013-04-18 11:32:16 -0400573 dig->afmt->enabled = enable;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200574
Alex Deuchera973bea2013-04-18 11:32:16 -0400575 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
576 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
Rafał Miłecki2cd62182010-03-08 22:14:01 +0000577}
578