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gerrit-public.fairphone.software / kernel / msm-5.4 / 933d87a56e3379479ff399a11899830b341809de / . / arch / arm / boot / dts / tegra114.dtsi
blob: 400a2752a7e1e433b0055ba6063a7315ace1b331 [file] [log] [blame]
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra114";
5 interrupt-parent = <&gic>;
6
7 gic: interrupt-controller {
8 compatible = "arm,cortex-a15-gic";
9 #interrupt-cells = <3>;
10 interrupt-controller;
11 reg = <0x50041000 0x1000>,
12 <0x50042000 0x1000>,
13 <0x50044000 0x2000>,
14 <0x50046000 0x2000>;
15 interrupts = <1 9 0xf04>;
16 };
17
18 timer@60005000 {
19 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
20 reg = <0x60005000 0x400>;
21 interrupts = <0 0 0x04
22 0 1 0x04
23 0 41 0x04
24 0 42 0x04
25 0 121 0x04
26 0 122 0x04>;
Peter De Schrijver672d8892013-04-03 17:40:48 +0300[diff] [blame]27 clocks = <&tegra_car 5>;
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]28 };
29
30 tegra_car: clock {
Peter De Schrijver672d8892013-04-03 17:40:48 +0300[diff] [blame]31 compatible = "nvidia,tegra114-car";
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]32 reg = <0x60006000 0x1000>;
33 #clock-cells = <1>;
34 };
35
Hiroshi Doyu0dfe42e2013-01-15 10:17:27 +0200[diff] [blame]36 ahb: ahb {
37 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
38 reg = <0x6000c004 0x14c>;
39 };
40
Laxman Dewanganb16f9182013-01-29 18:26:18 +0530[diff] [blame]41 gpio: gpio {
42 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
43 reg = <0x6000d000 0x1000>;
44 interrupts = <0 32 0x04
45 0 33 0x04
46 0 34 0x04
47 0 35 0x04
48 0 55 0x04
49 0 87 0x04
50 0 89 0x04
51 0 125 0x04>;
52 #gpio-cells = <2>;
53 gpio-controller;
54 #interrupt-cells = <2>;
55 interrupt-controller;
56 };
57
Laxman Dewangan031b77a2013-01-29 18:26:20 +0530[diff] [blame]58 pinmux: pinmux {
59 compatible = "nvidia,tegra114-pinmux";
60 reg = <0x70000868 0x148 /* Pad control registers */
61 0x70003000 0x40c>; /* Mux registers */
62 };
63
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]64 serial@70006000 {
65 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
66 reg = <0x70006000 0x40>;
67 reg-shift = <2>;
68 interrupts = <0 36 0x04>;
69 status = "disabled";
Peter De Schrijver672d8892013-04-03 17:40:48 +0300[diff] [blame]70 clocks = <&tegra_car 6>;
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]71 };
72
73 serial@70006040 {
74 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
75 reg = <0x70006040 0x40>;
76 reg-shift = <2>;
77 interrupts = <0 37 0x04>;
78 status = "disabled";
Peter De Schrijver672d8892013-04-03 17:40:48 +0300[diff] [blame]79 clocks = <&tegra_car 192>;
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]80 };
81
82 serial@70006200 {
83 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
84 reg = <0x70006200 0x100>;
85 reg-shift = <2>;
86 interrupts = <0 46 0x04>;
87 status = "disabled";
Peter De Schrijver672d8892013-04-03 17:40:48 +0300[diff] [blame]88 clocks = <&tegra_car 55>;
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]89 };
90
91 serial@70006300 {
92 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
93 reg = <0x70006300 0x100>;
94 reg-shift = <2>;
95 interrupts = <0 90 0x04>;
96 status = "disabled";
Peter De Schrijver672d8892013-04-03 17:40:48 +0300[diff] [blame]97 clocks = <&tegra_car 65>;
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]98 };
99
100 rtc {
101 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
102 reg = <0x7000e000 0x100>;
103 interrupts = <0 2 0x04>;
Peter De Schrijver672d8892013-04-03 17:40:48 +0300[diff] [blame]104 clocks = <&tegra_car 4>;
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]105 };
106
107 pmc {
Joseph Lo2b84e532013-02-26 16:27:43 +0000[diff] [blame]108 compatible = "nvidia,tegra114-pmc";
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]109 reg = <0x7000e400 0x400>;
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]110 clocks = <&tegra_car 261>, <&clk32k_in>;
111 clock-names = "pclk", "clk32k_in";
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]112 };
113
Hiroshi Doyu2da13962013-01-15 10:17:28 +0200[diff] [blame]114 iommu {
115 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
116 reg = <0x7000f010 0x02c
117 0x7000f1f0 0x010
118 0x7000f228 0x074>;
119 nvidia,#asids = <4>;
120 dma-window = <0 0x40000000>;
121 nvidia,swgroups = <0x18659fe>;
122 nvidia,ahb = <&ahb>;
123 };
124
Pritesh Raithatha933d87a2013-02-20 13:35:14 -0500[diff] [blame^]125 sdhci@78000000 {
126 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
127 reg = <0x78000000 0x200>;
128 interrupts = <0 14 0x04>;
129 clocks = <&tegra_car 14>;
130 status = "disable";
131 };
132
133 sdhci@78000200 {
134 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
135 reg = <0x78000200 0x200>;
136 interrupts = <0 15 0x04>;
137 clocks = <&tegra_car 9>;
138 status = "disable";
139 };
140
141 sdhci@78000400 {
142 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
143 reg = <0x78000400 0x200>;
144 interrupts = <0 19 0x04>;
145 clocks = <&tegra_car 69>;
146 status = "disable";
147 };
148
149 sdhci@78000600 {
150 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
151 reg = <0x78000600 0x200>;
152 interrupts = <0 31 0x04>;
153 clocks = <&tegra_car 15>;
154 status = "disable";
155 };
156
Hiroshi Doyu18a4df72013-01-24 01:10:23 +0000[diff] [blame]157 cpus {
158 #address-cells = <1>;
159 #size-cells = <0>;
160
161 cpu@0 {
162 device_type = "cpu";
163 compatible = "arm,cortex-a15";
164 reg = <0>;
165 };
166
167 cpu@1 {
168 device_type = "cpu";
169 compatible = "arm,cortex-a15";
170 reg = <1>;
171 };
172
173 cpu@2 {
174 device_type = "cpu";
175 compatible = "arm,cortex-a15";
176 reg = <2>;
177 };
178
179 cpu@3 {
180 device_type = "cpu";
181 compatible = "arm,cortex-a15";
182 reg = <3>;
183 };
184 };
185
186 timer {
187 compatible = "arm,armv7-timer";
188 interrupts = <1 13 0xf08>,
189 <1 14 0xf08>,
190 <1 11 0xf08>,
191 <1 10 0xf08>;
192 };
193};