Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/include/asm/thread_info.h |
| 3 | * |
| 4 | * Copyright (C) 2002 Russell King. |
| 5 | * Copyright (C) 2012 ARM Ltd. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | #ifndef __ASM_THREAD_INFO_H |
| 20 | #define __ASM_THREAD_INFO_H |
| 21 | |
| 22 | #ifdef __KERNEL__ |
| 23 | |
| 24 | #include <linux/compiler.h> |
| 25 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 26 | #ifndef __ASSEMBLY__ |
| 27 | |
| 28 | struct task_struct; |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 29 | |
Mark Rutland | dbc9344 | 2017-07-14 16:39:21 +0100 | [diff] [blame] | 30 | #include <asm/memory.h> |
Mark Rutland | a9ea001 | 2016-11-03 20:23:05 +0000 | [diff] [blame] | 31 | #include <asm/stack_pointer.h> |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 32 | #include <asm/types.h> |
| 33 | |
| 34 | typedef unsigned long mm_segment_t; |
| 35 | |
| 36 | /* |
| 37 | * low level task data that entry.S needs immediate access to. |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 38 | */ |
| 39 | struct thread_info { |
| 40 | unsigned long flags; /* low level flags */ |
| 41 | mm_segment_t addr_limit; /* address limit */ |
Catalin Marinas | 4b65a5d | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 42 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 43 | u64 ttbr0; /* saved TTBR0_EL1 */ |
| 44 | #endif |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 45 | int preempt_count; /* 0 => preemptable, <0 => bug */ |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | #define INIT_THREAD_INFO(tsk) \ |
| 49 | { \ |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 50 | .preempt_count = INIT_PREEMPT_COUNT, \ |
| 51 | .addr_limit = KERNEL_DS, \ |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 52 | } |
| 53 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 54 | #define thread_saved_pc(tsk) \ |
| 55 | ((unsigned long)(tsk->thread.cpu_context.pc)) |
| 56 | #define thread_saved_sp(tsk) \ |
| 57 | ((unsigned long)(tsk->thread.cpu_context.sp)) |
| 58 | #define thread_saved_fp(tsk) \ |
| 59 | ((unsigned long)(tsk->thread.cpu_context.fp)) |
| 60 | |
Yury Norov | d1be5c9 | 2017-08-20 13:20:48 +0300 | [diff] [blame] | 61 | void arch_setup_new_exec(void); |
| 62 | #define arch_setup_new_exec arch_setup_new_exec |
| 63 | |
Dave Martin | bc0ee47 | 2017-10-31 15:51:05 +0000 | [diff] [blame] | 64 | void arch_release_task_struct(struct task_struct *tsk); |
| 65 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 66 | #endif |
| 67 | |
| 68 | /* |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 69 | * thread information flags: |
| 70 | * TIF_SYSCALL_TRACE - syscall trace active |
AKASHI Takahiro | 449f81a | 2014-04-30 10:51:29 +0100 | [diff] [blame] | 71 | * TIF_SYSCALL_TRACEPOINT - syscall tracepoint for ftrace |
| 72 | * TIF_SYSCALL_AUDIT - syscall auditing |
| 73 | * TIF_SECOMP - syscall secure computing |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 74 | * TIF_SIGPENDING - signal pending |
| 75 | * TIF_NEED_RESCHED - rescheduling necessary |
| 76 | * TIF_NOTIFY_RESUME - callback before returning to user |
| 77 | * TIF_USEDFPU - FPU was used by this task this quantum (SMP) |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 78 | */ |
| 79 | #define TIF_SIGPENDING 0 |
| 80 | #define TIF_NEED_RESCHED 1 |
| 81 | #define TIF_NOTIFY_RESUME 2 /* callback before returning to user */ |
Ard Biesheuvel | 005f78c | 2014-05-08 11:20:23 +0200 | [diff] [blame] | 82 | #define TIF_FOREIGN_FPSTATE 3 /* CPU's FP state is not current's */ |
Pratyush Anand | 9842cea | 2016-11-02 14:40:46 +0530 | [diff] [blame] | 83 | #define TIF_UPROBE 4 /* uprobe breakpoint or singlestep */ |
Thomas Garnier | cf7de27 | 2017-06-14 18:12:03 -0700 | [diff] [blame] | 84 | #define TIF_FSCHECK 5 /* Check FS is USER_DS on return */ |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 85 | #define TIF_NOHZ 7 |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 86 | #define TIF_SYSCALL_TRACE 8 |
AKASHI Takahiro | 449f81a | 2014-04-30 10:51:29 +0100 | [diff] [blame] | 87 | #define TIF_SYSCALL_AUDIT 9 |
| 88 | #define TIF_SYSCALL_TRACEPOINT 10 |
| 89 | #define TIF_SECCOMP 11 |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 90 | #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ |
| 91 | #define TIF_FREEZE 19 |
| 92 | #define TIF_RESTORE_SIGMASK 20 |
| 93 | #define TIF_SINGLESTEP 21 |
| 94 | #define TIF_32BIT 22 /* 32bit process */ |
Dave Martin | bc0ee47 | 2017-10-31 15:51:05 +0000 | [diff] [blame] | 95 | #define TIF_SVE 23 /* Scalable Vector Extension in use */ |
Dave Martin | 79ab047 | 2017-10-31 15:51:06 +0000 | [diff] [blame] | 96 | #define TIF_SVE_VL_INHERIT 24 /* Inherit sve_vl_onexec across exec */ |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 97 | |
| 98 | #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) |
| 99 | #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) |
| 100 | #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) |
Ard Biesheuvel | 005f78c | 2014-05-08 11:20:23 +0200 | [diff] [blame] | 101 | #define _TIF_FOREIGN_FPSTATE (1 << TIF_FOREIGN_FPSTATE) |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 102 | #define _TIF_NOHZ (1 << TIF_NOHZ) |
AKASHI Takahiro | 449f81a | 2014-04-30 10:51:29 +0100 | [diff] [blame] | 103 | #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) |
| 104 | #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) |
| 105 | #define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) |
| 106 | #define _TIF_SECCOMP (1 << TIF_SECCOMP) |
Pratyush Anand | 9842cea | 2016-11-02 14:40:46 +0530 | [diff] [blame] | 107 | #define _TIF_UPROBE (1 << TIF_UPROBE) |
Thomas Garnier | cf7de27 | 2017-06-14 18:12:03 -0700 | [diff] [blame] | 108 | #define _TIF_FSCHECK (1 << TIF_FSCHECK) |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 109 | #define _TIF_32BIT (1 << TIF_32BIT) |
Dave Martin | bc0ee47 | 2017-10-31 15:51:05 +0000 | [diff] [blame] | 110 | #define _TIF_SVE (1 << TIF_SVE) |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 111 | |
| 112 | #define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \ |
Pratyush Anand | 9842cea | 2016-11-02 14:40:46 +0530 | [diff] [blame] | 113 | _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE | \ |
Thomas Garnier | cf7de27 | 2017-06-14 18:12:03 -0700 | [diff] [blame] | 114 | _TIF_UPROBE | _TIF_FSCHECK) |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 115 | |
AKASHI Takahiro | 449f81a | 2014-04-30 10:51:29 +0100 | [diff] [blame] | 116 | #define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \ |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 117 | _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP | \ |
| 118 | _TIF_NOHZ) |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 119 | |
| 120 | #endif /* __KERNEL__ */ |
| 121 | #endif /* __ASM_THREAD_INFO_H */ |