Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation; either version 2 |
| 7 | * of the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 17 | */ |
| 18 | #include <linux/config.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/linkage.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/spinlock.h> |
| 24 | #include <linux/smp.h> |
| 25 | #include <linux/mm.h> |
| 26 | #include <linux/slab.h> |
| 27 | #include <linux/kernel_stat.h> |
| 28 | |
| 29 | #include <asm/errno.h> |
| 30 | #include <asm/signal.h> |
| 31 | #include <asm/system.h> |
| 32 | #include <asm/ptrace.h> |
| 33 | #include <asm/io.h> |
| 34 | |
| 35 | #include <asm/sibyte/sb1250_regs.h> |
| 36 | #include <asm/sibyte/sb1250_int.h> |
| 37 | #include <asm/sibyte/sb1250_uart.h> |
| 38 | #include <asm/sibyte/sb1250_scd.h> |
| 39 | #include <asm/sibyte/sb1250.h> |
| 40 | |
| 41 | /* |
| 42 | * These are the routines that handle all the low level interrupt stuff. |
| 43 | * Actions handled here are: initialization of the interrupt map, requesting of |
| 44 | * interrupt lines by handlers, dispatching if interrupts to handlers, probing |
| 45 | * for interrupt lines |
| 46 | */ |
| 47 | |
| 48 | |
| 49 | #define shutdown_sb1250_irq disable_sb1250_irq |
| 50 | static void end_sb1250_irq(unsigned int irq); |
| 51 | static void enable_sb1250_irq(unsigned int irq); |
| 52 | static void disable_sb1250_irq(unsigned int irq); |
| 53 | static unsigned int startup_sb1250_irq(unsigned int irq); |
| 54 | static void ack_sb1250_irq(unsigned int irq); |
| 55 | #ifdef CONFIG_SMP |
Andrew Isaacson | 942d042 | 2005-06-22 16:01:09 -0700 | [diff] [blame^] | 56 | static void sb1250_set_affinity(unsigned int irq, cpumask_t mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | #endif |
| 58 | |
| 59 | #ifdef CONFIG_SIBYTE_HAS_LDT |
| 60 | extern unsigned long ldt_eoi_space; |
| 61 | #endif |
| 62 | |
| 63 | #ifdef CONFIG_KGDB |
| 64 | static int kgdb_irq; |
| 65 | |
| 66 | /* Default to UART1 */ |
| 67 | int kgdb_port = 1; |
| 68 | #ifdef CONFIG_SIBYTE_SB1250_DUART |
| 69 | extern char sb1250_duart_present[]; |
| 70 | #endif |
| 71 | #endif |
| 72 | |
| 73 | static struct hw_interrupt_type sb1250_irq_type = { |
Ralf Baechle | 8ab00b9 | 2005-02-28 13:39:57 +0000 | [diff] [blame] | 74 | .typename = "SB1250-IMR", |
| 75 | .startup = startup_sb1250_irq, |
| 76 | .shutdown = shutdown_sb1250_irq, |
| 77 | .enable = enable_sb1250_irq, |
| 78 | .disable = disable_sb1250_irq, |
| 79 | .ack = ack_sb1250_irq, |
| 80 | .end = end_sb1250_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | #ifdef CONFIG_SMP |
Ralf Baechle | 8ab00b9 | 2005-02-28 13:39:57 +0000 | [diff] [blame] | 82 | .set_affinity = sb1250_set_affinity |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | #endif |
| 84 | }; |
| 85 | |
| 86 | /* Store the CPU id (not the logical number) */ |
| 87 | int sb1250_irq_owner[SB1250_NR_IRQS]; |
| 88 | |
| 89 | DEFINE_SPINLOCK(sb1250_imr_lock); |
| 90 | |
| 91 | void sb1250_mask_irq(int cpu, int irq) |
| 92 | { |
| 93 | unsigned long flags; |
| 94 | u64 cur_ints; |
| 95 | |
| 96 | spin_lock_irqsave(&sb1250_imr_lock, flags); |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 97 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
| 98 | R_IMR_INTERRUPT_MASK)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 99 | cur_ints |= (((u64) 1) << irq); |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 100 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
| 101 | R_IMR_INTERRUPT_MASK)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | spin_unlock_irqrestore(&sb1250_imr_lock, flags); |
| 103 | } |
| 104 | |
| 105 | void sb1250_unmask_irq(int cpu, int irq) |
| 106 | { |
| 107 | unsigned long flags; |
| 108 | u64 cur_ints; |
| 109 | |
| 110 | spin_lock_irqsave(&sb1250_imr_lock, flags); |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 111 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
| 112 | R_IMR_INTERRUPT_MASK)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | cur_ints &= ~(((u64) 1) << irq); |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 114 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
| 115 | R_IMR_INTERRUPT_MASK)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | spin_unlock_irqrestore(&sb1250_imr_lock, flags); |
| 117 | } |
| 118 | |
| 119 | #ifdef CONFIG_SMP |
Andrew Isaacson | 942d042 | 2005-06-22 16:01:09 -0700 | [diff] [blame^] | 120 | static void sb1250_set_affinity(unsigned int irq, cpumask_t mask) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 121 | { |
| 122 | int i = 0, old_cpu, cpu, int_on; |
| 123 | u64 cur_ints; |
| 124 | irq_desc_t *desc = irq_desc + irq; |
| 125 | unsigned long flags; |
| 126 | |
Andrew Isaacson | 942d042 | 2005-06-22 16:01:09 -0700 | [diff] [blame^] | 127 | i = first_cpu(mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 128 | |
Andrew Isaacson | 942d042 | 2005-06-22 16:01:09 -0700 | [diff] [blame^] | 129 | if (cpus_weight(mask) > 1) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); |
| 131 | return; |
| 132 | } |
| 133 | |
| 134 | /* Convert logical CPU to physical CPU */ |
| 135 | cpu = cpu_logical_map(i); |
| 136 | |
| 137 | /* Protect against other affinity changers and IMR manipulation */ |
| 138 | spin_lock_irqsave(&desc->lock, flags); |
| 139 | spin_lock(&sb1250_imr_lock); |
| 140 | |
| 141 | /* Swizzle each CPU's IMR (but leave the IP selection alone) */ |
| 142 | old_cpu = sb1250_irq_owner[irq]; |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 143 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + |
| 144 | R_IMR_INTERRUPT_MASK)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 145 | int_on = !(cur_ints & (((u64) 1) << irq)); |
| 146 | if (int_on) { |
| 147 | /* If it was on, mask it */ |
| 148 | cur_ints |= (((u64) 1) << irq); |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 149 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + |
| 150 | R_IMR_INTERRUPT_MASK)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | } |
| 152 | sb1250_irq_owner[irq] = cpu; |
| 153 | if (int_on) { |
| 154 | /* unmask for the new CPU */ |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 155 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
| 156 | R_IMR_INTERRUPT_MASK)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | cur_ints &= ~(((u64) 1) << irq); |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 158 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
| 159 | R_IMR_INTERRUPT_MASK)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | } |
| 161 | spin_unlock(&sb1250_imr_lock); |
| 162 | spin_unlock_irqrestore(&desc->lock, flags); |
| 163 | } |
| 164 | #endif |
| 165 | |
| 166 | |
| 167 | /* Defined in arch/mips/sibyte/sb1250/irq_handler.S */ |
| 168 | extern void sb1250_irq_handler(void); |
| 169 | |
| 170 | /*****************************************************************************/ |
| 171 | |
| 172 | static unsigned int startup_sb1250_irq(unsigned int irq) |
| 173 | { |
| 174 | sb1250_unmask_irq(sb1250_irq_owner[irq], irq); |
| 175 | |
| 176 | return 0; /* never anything pending */ |
| 177 | } |
| 178 | |
| 179 | |
| 180 | static void disable_sb1250_irq(unsigned int irq) |
| 181 | { |
| 182 | sb1250_mask_irq(sb1250_irq_owner[irq], irq); |
| 183 | } |
| 184 | |
| 185 | static void enable_sb1250_irq(unsigned int irq) |
| 186 | { |
| 187 | sb1250_unmask_irq(sb1250_irq_owner[irq], irq); |
| 188 | } |
| 189 | |
| 190 | |
| 191 | static void ack_sb1250_irq(unsigned int irq) |
| 192 | { |
| 193 | #ifdef CONFIG_SIBYTE_HAS_LDT |
| 194 | u64 pending; |
| 195 | |
| 196 | /* |
| 197 | * If the interrupt was an HT interrupt, now is the time to |
| 198 | * clear it. NOTE: we assume the HT bridge was set up to |
| 199 | * deliver the interrupts to all CPUs (which makes affinity |
| 200 | * changing easier for us) |
| 201 | */ |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 202 | pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], |
| 203 | R_IMR_LDT_INTERRUPT))); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | pending &= ((u64)1 << (irq)); |
| 205 | if (pending) { |
| 206 | int i; |
| 207 | for (i=0; i<NR_CPUS; i++) { |
| 208 | int cpu; |
| 209 | #ifdef CONFIG_SMP |
| 210 | cpu = cpu_logical_map(i); |
| 211 | #else |
| 212 | cpu = i; |
| 213 | #endif |
| 214 | /* |
| 215 | * Clear for all CPUs so an affinity switch |
| 216 | * doesn't find an old status |
| 217 | */ |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 218 | __raw_writeq(pending, |
| 219 | IOADDR(A_IMR_REGISTER(cpu, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | R_IMR_LDT_INTERRUPT_CLR))); |
| 221 | } |
| 222 | |
| 223 | /* |
| 224 | * Generate EOI. For Pass 1 parts, EOI is a nop. For |
| 225 | * Pass 2, the LDT world may be edge-triggered, but |
| 226 | * this EOI shouldn't hurt. If they are |
| 227 | * level-sensitive, the EOI is required. |
| 228 | */ |
| 229 | *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0; |
| 230 | } |
| 231 | #endif |
| 232 | sb1250_mask_irq(sb1250_irq_owner[irq], irq); |
| 233 | } |
| 234 | |
| 235 | |
| 236 | static void end_sb1250_irq(unsigned int irq) |
| 237 | { |
| 238 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { |
| 239 | sb1250_unmask_irq(sb1250_irq_owner[irq], irq); |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | |
| 244 | void __init init_sb1250_irqs(void) |
| 245 | { |
| 246 | int i; |
| 247 | |
| 248 | for (i = 0; i < NR_IRQS; i++) { |
| 249 | irq_desc[i].status = IRQ_DISABLED; |
| 250 | irq_desc[i].action = 0; |
| 251 | irq_desc[i].depth = 1; |
| 252 | if (i < SB1250_NR_IRQS) { |
| 253 | irq_desc[i].handler = &sb1250_irq_type; |
| 254 | sb1250_irq_owner[i] = 0; |
| 255 | } else { |
| 256 | irq_desc[i].handler = &no_irq_type; |
| 257 | } |
| 258 | } |
| 259 | } |
| 260 | |
| 261 | |
| 262 | static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id, |
| 263 | struct pt_regs *regs) |
| 264 | { |
| 265 | return IRQ_NONE; |
| 266 | } |
| 267 | |
| 268 | static struct irqaction sb1250_dummy_action = { |
| 269 | .handler = sb1250_dummy_handler, |
| 270 | .flags = 0, |
| 271 | .mask = CPU_MASK_NONE, |
| 272 | .name = "sb1250-private", |
| 273 | .next = NULL, |
| 274 | .dev_id = 0 |
| 275 | }; |
| 276 | |
| 277 | int sb1250_steal_irq(int irq) |
| 278 | { |
| 279 | irq_desc_t *desc = irq_desc + irq; |
| 280 | unsigned long flags; |
| 281 | int retval = 0; |
| 282 | |
| 283 | if (irq >= SB1250_NR_IRQS) |
| 284 | return -EINVAL; |
| 285 | |
| 286 | spin_lock_irqsave(&desc->lock,flags); |
| 287 | /* Don't allow sharing at all for these */ |
| 288 | if (desc->action != NULL) |
| 289 | retval = -EBUSY; |
| 290 | else { |
| 291 | desc->action = &sb1250_dummy_action; |
| 292 | desc->depth = 0; |
| 293 | } |
| 294 | spin_unlock_irqrestore(&desc->lock,flags); |
| 295 | return 0; |
| 296 | } |
| 297 | |
| 298 | /* |
| 299 | * arch_init_irq is called early in the boot sequence from init/main.c via |
| 300 | * init_IRQ. It is responsible for setting up the interrupt mapper and |
| 301 | * installing the handler that will be responsible for dispatching interrupts |
| 302 | * to the "right" place. |
| 303 | */ |
| 304 | /* |
| 305 | * For now, map all interrupts to IP[2]. We could save |
| 306 | * some cycles by parceling out system interrupts to different |
| 307 | * IP lines, but keep it simple for bringup. We'll also direct |
| 308 | * all interrupts to a single CPU; we should probably route |
| 309 | * PCI and LDT to one cpu and everything else to the other |
| 310 | * to balance the load a bit. |
| 311 | * |
| 312 | * On the second cpu, everything is set to IP5, which is |
| 313 | * ignored, EXCEPT the mailbox interrupt. That one is |
| 314 | * set to IP[2] so it is handled. This is needed so we |
| 315 | * can do cross-cpu function calls, as requred by SMP |
| 316 | */ |
| 317 | |
| 318 | #define IMR_IP2_VAL K_INT_MAP_I0 |
| 319 | #define IMR_IP3_VAL K_INT_MAP_I1 |
| 320 | #define IMR_IP4_VAL K_INT_MAP_I2 |
| 321 | #define IMR_IP5_VAL K_INT_MAP_I3 |
| 322 | #define IMR_IP6_VAL K_INT_MAP_I4 |
| 323 | |
| 324 | void __init arch_init_irq(void) |
| 325 | { |
| 326 | |
| 327 | unsigned int i; |
| 328 | u64 tmp; |
| 329 | unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | |
| 330 | STATUSF_IP1 | STATUSF_IP0; |
| 331 | |
| 332 | /* Default everything to IP2 */ |
| 333 | for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 334 | __raw_writeq(IMR_IP2_VAL, |
| 335 | IOADDR(A_IMR_REGISTER(0, |
| 336 | R_IMR_INTERRUPT_MAP_BASE) + |
| 337 | (i << 3))); |
| 338 | __raw_writeq(IMR_IP2_VAL, |
| 339 | IOADDR(A_IMR_REGISTER(1, |
| 340 | R_IMR_INTERRUPT_MAP_BASE) + |
| 341 | (i << 3))); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | init_sb1250_irqs(); |
| 345 | |
| 346 | /* |
| 347 | * Map the high 16 bits of the mailbox registers to IP[3], for |
| 348 | * inter-cpu messages |
| 349 | */ |
| 350 | /* Was I1 */ |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 351 | __raw_writeq(IMR_IP3_VAL, |
| 352 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + |
| 353 | (K_INT_MBOX_0 << 3))); |
| 354 | __raw_writeq(IMR_IP3_VAL, |
| 355 | IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + |
| 356 | (K_INT_MBOX_0 << 3))); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | |
| 358 | /* Clear the mailboxes. The firmware may leave them dirty */ |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 359 | __raw_writeq(0xffffffffffffffffULL, |
| 360 | IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); |
| 361 | __raw_writeq(0xffffffffffffffffULL, |
| 362 | IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 363 | |
| 364 | /* Mask everything except the mailbox registers for both cpus */ |
| 365 | tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 366 | __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); |
| 367 | __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 368 | |
| 369 | sb1250_steal_irq(K_INT_MBOX_0); |
| 370 | |
| 371 | /* |
| 372 | * Note that the timer interrupts are also mapped, but this is |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 373 | * done in sb1250_time_init(). Also, the profiling driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | * does its own management of IP7. |
| 375 | */ |
| 376 | |
| 377 | #ifdef CONFIG_KGDB |
| 378 | imask |= STATUSF_IP6; |
| 379 | #endif |
| 380 | /* Enable necessary IPs, disable the rest */ |
| 381 | change_c0_status(ST0_IM, imask); |
| 382 | set_except_vector(0, sb1250_irq_handler); |
| 383 | |
| 384 | #ifdef CONFIG_KGDB |
| 385 | if (kgdb_flag) { |
| 386 | kgdb_irq = K_INT_UART_0 + kgdb_port; |
| 387 | |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 388 | #ifdef CONFIG_SIBYTE_SB1250_DUART |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 389 | sb1250_duart_present[kgdb_port] = 0; |
| 390 | #endif |
| 391 | /* Setup uart 1 settings, mapper */ |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 392 | __raw_writeq(M_DUART_IMR_BRK, |
| 393 | IOADDR(A_DUART_IMRREG(kgdb_port))); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | |
| 395 | sb1250_steal_irq(kgdb_irq); |
Maciej W. Rozycki | 65bda1a | 2005-02-22 21:51:30 +0000 | [diff] [blame] | 396 | __raw_writeq(IMR_IP6_VAL, |
| 397 | IOADDR(A_IMR_REGISTER(0, |
| 398 | R_IMR_INTERRUPT_MAP_BASE) + |
| 399 | (kgdb_irq << 3))); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 400 | sb1250_unmask_irq(0, kgdb_irq); |
| 401 | } |
| 402 | #endif |
| 403 | } |
| 404 | |
| 405 | #ifdef CONFIG_KGDB |
| 406 | |
| 407 | #include <linux/delay.h> |
| 408 | |
| 409 | #define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) |
| 410 | #define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) |
| 411 | |
| 412 | void sb1250_kgdb_interrupt(struct pt_regs *regs) |
| 413 | { |
| 414 | /* |
| 415 | * Clear break-change status (allow some time for the remote |
| 416 | * host to stop the break, since we would see another |
| 417 | * interrupt on the end-of-break too) |
| 418 | */ |
| 419 | kstat_this_cpu.irqs[kgdb_irq]++; |
| 420 | mdelay(500); |
| 421 | duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT | |
| 422 | M_DUART_RX_EN | M_DUART_TX_EN); |
| 423 | set_async_breakpoint(®s->cp0_epc); |
| 424 | } |
| 425 | |
| 426 | #endif /* CONFIG_KGDB */ |