| Michal Simek | 5abcdc2 | 2017-12-19 14:15:25 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | menu "Xilinx SoC drivers" |
| 3 | |
| Dhaval Shah | cee8113 | 2017-12-21 10:33:06 -0800 | [diff] [blame] | 4 | config XILINX_VCU |
| Michal Simek | 056b54e | 2018-01-16 08:36:09 +0100 | [diff] [blame] | 5 | tristate "Xilinx VCU logicoreIP Init" |
| Dhaval Shah | 0501506 | 2018-01-15 22:34:48 -0800 | [diff] [blame] | 6 | depends on HAS_IOMEM |
| Michal Simek | 056b54e | 2018-01-16 08:36:09 +0100 | [diff] [blame] | 7 | help |
| 8 | Provides the driver to enable and disable the isolation between the |
| 9 | processing system and programmable logic part by using the logicoreIP |
| 10 | register set. This driver also configures the frequency based on the |
| 11 | clock information from the logicoreIP register set. |
| Dhaval Shah | cee8113 | 2017-12-21 10:33:06 -0800 | [diff] [blame] | 12 | |
| Michal Simek | 056b54e | 2018-01-16 08:36:09 +0100 | [diff] [blame] | 13 | If you say yes here you get support for the logicoreIP. |
| Dhaval Shah | cee8113 | 2017-12-21 10:33:06 -0800 | [diff] [blame] | 14 | |
| Michal Simek | 056b54e | 2018-01-16 08:36:09 +0100 | [diff] [blame] | 15 | If unsure, say N. |
| Dhaval Shah | cee8113 | 2017-12-21 10:33:06 -0800 | [diff] [blame] | 16 | |
| Michal Simek | 056b54e | 2018-01-16 08:36:09 +0100 | [diff] [blame] | 17 | To compile this driver as a module, choose M here: the |
| 18 | module will be called xlnx_vcu. |
| Dhaval Shah | cee8113 | 2017-12-21 10:33:06 -0800 | [diff] [blame] | 19 | |
| Michal Simek | 5abcdc2 | 2017-12-19 14:15:25 +0100 | [diff] [blame] | 20 | endmenu |