| Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * ti_hdmi.h |
| 3 | * |
| 4 | * HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor. |
| 5 | * |
| 6 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License version 2 as published by |
| 10 | * the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #ifndef _TI_HDMI_H |
| 22 | #define _TI_HDMI_H |
| 23 | |
| 24 | enum hdmi_pll_pwr { |
| 25 | HDMI_PLLPWRCMD_ALLOFF = 0, |
| 26 | HDMI_PLLPWRCMD_PLLONLY = 1, |
| 27 | HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, |
| 28 | HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 |
| 29 | }; |
| 30 | |
| 31 | enum hdmi_core_hdmi_dvi { |
| 32 | HDMI_DVI = 0, |
| 33 | HDMI_HDMI = 1 |
| 34 | }; |
| 35 | |
| 36 | enum hdmi_clk_refsel { |
| 37 | HDMI_REFSEL_PCLK = 0, |
| 38 | HDMI_REFSEL_REF1 = 1, |
| 39 | HDMI_REFSEL_REF2 = 2, |
| 40 | HDMI_REFSEL_SYSCLK = 3 |
| 41 | }; |
| 42 | |
| 43 | struct hdmi_video_timings { |
| 44 | u16 x_res; |
| 45 | u16 y_res; |
| 46 | /* Unit: KHz */ |
| 47 | u32 pixel_clock; |
| 48 | u16 hsw; |
| 49 | u16 hfp; |
| 50 | u16 hbp; |
| 51 | u16 vsw; |
| 52 | u16 vfp; |
| 53 | u16 vbp; |
| 54 | }; |
| 55 | |
| 56 | /* HDMI timing structure */ |
| 57 | struct hdmi_timings { |
| 58 | struct hdmi_video_timings timings; |
| 59 | int vsync_pol; |
| 60 | int hsync_pol; |
| 61 | }; |
| 62 | |
| 63 | struct hdmi_cm { |
| 64 | int code; |
| 65 | int mode; |
| 66 | }; |
| 67 | |
| 68 | struct hdmi_config { |
| 69 | struct hdmi_timings timings; |
| 70 | u16 interlace; |
| 71 | struct hdmi_cm cm; |
| 72 | }; |
| 73 | |
| 74 | /* HDMI PLL structure */ |
| 75 | struct hdmi_pll_info { |
| 76 | u16 regn; |
| 77 | u16 regm; |
| 78 | u32 regmf; |
| 79 | u16 regm2; |
| 80 | u16 regsd; |
| 81 | u16 dcofreq; |
| 82 | enum hdmi_clk_refsel refsel; |
| 83 | }; |
| 84 | |
| 85 | struct hdmi_ip_data { |
| 86 | void __iomem *base_wp; /* HDMI wrapper */ |
| 87 | unsigned long core_sys_offset; |
| 88 | unsigned long core_av_offset; |
| 89 | unsigned long pll_offset; |
| 90 | unsigned long phy_offset; |
| 91 | struct hdmi_config cfg; |
| 92 | struct hdmi_pll_info pll_data; |
| 93 | }; |
| 94 | #endif |