blob: 6902ad6da710fe2d4f7fb7e9f56c3f84ba1c5b49 [file] [log] [blame]
Rob Clarka3376e32013-08-30 13:02:15 -04001/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "hdmi.h"
19
20struct hdmi_bridge {
21 struct drm_bridge base;
Rob Clarka3376e32013-08-30 13:02:15 -040022 struct hdmi *hdmi;
Rob Clarka3376e32013-08-30 13:02:15 -040023};
24#define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base)
25
26static void hdmi_bridge_destroy(struct drm_bridge *bridge)
27{
28 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
Rob Clarka3376e32013-08-30 13:02:15 -040029 drm_bridge_cleanup(bridge);
30 kfree(hdmi_bridge);
31}
32
Rob Clarkdada25b2013-12-01 12:12:54 -050033static void power_on(struct drm_bridge *bridge)
34{
35 struct drm_device *dev = bridge->dev;
36 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
37 struct hdmi *hdmi = hdmi_bridge->hdmi;
38 const struct hdmi_platform_config *config = hdmi->config;
39 int i, ret;
40
41 for (i = 0; i < config->pwr_reg_cnt; i++) {
42 ret = regulator_enable(hdmi->pwr_regs[i]);
43 if (ret) {
44 dev_err(dev->dev, "failed to enable pwr regulator: %s (%d)\n",
45 config->pwr_reg_names[i], ret);
46 }
47 }
48
49 if (config->pwr_clk_cnt > 0) {
Rob Clarkc0c0d9e2013-12-11 14:44:02 -050050 DBG("pixclock: %lu", hdmi->pixclock);
51 ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
Rob Clarkdada25b2013-12-01 12:12:54 -050052 if (ret) {
53 dev_err(dev->dev, "failed to set pixel clk: %s (%d)\n",
54 config->pwr_clk_names[0], ret);
55 }
56 }
57
58 for (i = 0; i < config->pwr_clk_cnt; i++) {
59 ret = clk_prepare_enable(hdmi->pwr_clks[i]);
60 if (ret) {
61 dev_err(dev->dev, "failed to enable pwr clk: %s (%d)\n",
62 config->pwr_clk_names[i], ret);
63 }
64 }
65}
66
67static void power_off(struct drm_bridge *bridge)
68{
69 struct drm_device *dev = bridge->dev;
70 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
71 struct hdmi *hdmi = hdmi_bridge->hdmi;
72 const struct hdmi_platform_config *config = hdmi->config;
73 int i, ret;
74
75 /* TODO do we need to wait for final vblank somewhere before
76 * cutting the clocks?
77 */
78 mdelay(16 + 4);
79
80 for (i = 0; i < config->pwr_clk_cnt; i++)
81 clk_disable_unprepare(hdmi->pwr_clks[i]);
82
83 for (i = 0; i < config->pwr_reg_cnt; i++) {
84 ret = regulator_disable(hdmi->pwr_regs[i]);
85 if (ret) {
86 dev_err(dev->dev, "failed to disable pwr regulator: %s (%d)\n",
87 config->pwr_reg_names[i], ret);
88 }
89 }
90}
91
Rob Clarka3376e32013-08-30 13:02:15 -040092static void hdmi_bridge_pre_enable(struct drm_bridge *bridge)
93{
94 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
95 struct hdmi *hdmi = hdmi_bridge->hdmi;
96 struct hdmi_phy *phy = hdmi->phy;
97
98 DBG("power up");
Rob Clarkdada25b2013-12-01 12:12:54 -050099
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500100 if (!hdmi->power_on) {
Rob Clarkdada25b2013-12-01 12:12:54 -0500101 power_on(bridge);
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500102 hdmi->power_on = true;
103 hdmi_audio_update(hdmi);
Rob Clarkdada25b2013-12-01 12:12:54 -0500104 }
105
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500106 phy->funcs->powerup(phy, hdmi->pixclock);
Rob Clarka3376e32013-08-30 13:02:15 -0400107 hdmi_set_mode(hdmi, true);
108}
109
110static void hdmi_bridge_enable(struct drm_bridge *bridge)
111{
112}
113
114static void hdmi_bridge_disable(struct drm_bridge *bridge)
115{
116}
117
118static void hdmi_bridge_post_disable(struct drm_bridge *bridge)
119{
120 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
121 struct hdmi *hdmi = hdmi_bridge->hdmi;
122 struct hdmi_phy *phy = hdmi->phy;
123
124 DBG("power down");
125 hdmi_set_mode(hdmi, false);
126 phy->funcs->powerdown(phy);
Rob Clarkdada25b2013-12-01 12:12:54 -0500127
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500128 if (hdmi->power_on) {
Rob Clarkdada25b2013-12-01 12:12:54 -0500129 power_off(bridge);
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500130 hdmi->power_on = false;
131 hdmi_audio_update(hdmi);
Rob Clarkdada25b2013-12-01 12:12:54 -0500132 }
Rob Clarka3376e32013-08-30 13:02:15 -0400133}
134
135static void hdmi_bridge_mode_set(struct drm_bridge *bridge,
136 struct drm_display_mode *mode,
137 struct drm_display_mode *adjusted_mode)
138{
139 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
140 struct hdmi *hdmi = hdmi_bridge->hdmi;
141 int hstart, hend, vstart, vend;
142 uint32_t frame_ctrl;
143
144 mode = adjusted_mode;
145
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500146 hdmi->pixclock = mode->clock * 1000;
Rob Clarka3376e32013-08-30 13:02:15 -0400147
148 hdmi->hdmi_mode = drm_match_cea_mode(mode) > 1;
149
150 hstart = mode->htotal - mode->hsync_start;
151 hend = mode->htotal - mode->hsync_start + mode->hdisplay;
152
153 vstart = mode->vtotal - mode->vsync_start - 1;
154 vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1;
155
156 DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d",
157 mode->htotal, mode->vtotal, hstart, hend, vstart, vend);
158
159 hdmi_write(hdmi, REG_HDMI_TOTAL,
160 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) |
161 HDMI_TOTAL_V_TOTAL(mode->vtotal - 1));
162
163 hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC,
164 HDMI_ACTIVE_HSYNC_START(hstart) |
165 HDMI_ACTIVE_HSYNC_END(hend));
166 hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC,
167 HDMI_ACTIVE_VSYNC_START(vstart) |
168 HDMI_ACTIVE_VSYNC_END(vend));
169
170 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
171 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
172 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal));
173 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
174 HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) |
175 HDMI_VSYNC_ACTIVE_F2_END(vend + 1));
176 } else {
177 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
178 HDMI_VSYNC_TOTAL_F2_V_TOTAL(0));
179 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
180 HDMI_VSYNC_ACTIVE_F2_START(0) |
181 HDMI_VSYNC_ACTIVE_F2_END(0));
182 }
183
184 frame_ctrl = 0;
185 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
186 frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW;
187 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
188 frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW;
189 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
190 frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN;
191 DBG("frame_ctrl=%08x", frame_ctrl);
192 hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
193
Rob Clarkc0c0d9e2013-12-11 14:44:02 -0500194 hdmi_audio_update(hdmi);
Rob Clarka3376e32013-08-30 13:02:15 -0400195}
196
197static const struct drm_bridge_funcs hdmi_bridge_funcs = {
198 .pre_enable = hdmi_bridge_pre_enable,
199 .enable = hdmi_bridge_enable,
200 .disable = hdmi_bridge_disable,
201 .post_disable = hdmi_bridge_post_disable,
202 .mode_set = hdmi_bridge_mode_set,
203 .destroy = hdmi_bridge_destroy,
204};
205
206
207/* initialize bridge */
208struct drm_bridge *hdmi_bridge_init(struct hdmi *hdmi)
209{
210 struct drm_bridge *bridge = NULL;
211 struct hdmi_bridge *hdmi_bridge;
212 int ret;
213
214 hdmi_bridge = kzalloc(sizeof(*hdmi_bridge), GFP_KERNEL);
215 if (!hdmi_bridge) {
216 ret = -ENOMEM;
217 goto fail;
218 }
219
Rob Clarkd1a717b2014-11-18 08:40:44 -0500220 hdmi_bridge->hdmi = hdmi;
Rob Clarka3376e32013-08-30 13:02:15 -0400221
222 bridge = &hdmi_bridge->base;
223
224 drm_bridge_init(hdmi->dev, bridge, &hdmi_bridge_funcs);
225
226 return bridge;
227
228fail:
229 if (bridge)
230 hdmi_bridge_destroy(bridge);
231
232 return ERR_PTR(ret);
233}