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gerrit-public.fairphone.software / kernel / msm-5.4 / 979f2b2f7936f4b71a3100baf2d16c8057f027eb / . / drivers / clk / sprd / sc9860-clk.c
blob: 9980ab55271ba2f71f7ad09ba04d2bbd23468eb7 [file] [log] [blame]
Chunyan Zhanga6ae1a22017-12-07 20:57:13 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2//
3// Spreatrum SC9860 clock driver
4//
5// Copyright (C) 2017 Spreadtrum, Inc.
6// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
7
8#include <linux/clk-provider.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <linux/slab.h>
15
16#include <dt-bindings/clock/sprd,sc9860-clk.h>
17
18#include "common.h"
19#include "composite.h"
20#include "div.h"
21#include "gate.h"
22#include "mux.h"
23#include "pll.h"
24
25static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
26 6, 1, 0);
27static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
28 13, 1, 0);
29static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
30 26, 1, 0);
31static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
32 104, 1, 0);
33static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
34 1, 1, 0);
35static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
36 1, 1, 0);
37static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
38 4, 1, 0);
39static CLK_FIXED_FACTOR(fac_rco_4m, "rco-4m", "ext-rc0-100m",
40 25, 1, 0);
41static CLK_FIXED_FACTOR(fac_rco_2m, "rco-2m", "ext-rc0-100m",
42 50, 1, 0);
43static CLK_FIXED_FACTOR(fac_3k2, "fac-3k2", "ext-32k",
44 10, 1, 0);
45static CLK_FIXED_FACTOR(fac_1k, "fac-1k", "ext-32k",
46 32, 1, 0);
47
48static SPRD_SC_GATE_CLK(mpll0_gate, "mpll0-gate", "ext-26m", 0xb0,
49 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
50static SPRD_SC_GATE_CLK(mpll1_gate, "mpll1-gate", "ext-26m", 0xb0,
51 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
52static SPRD_SC_GATE_CLK(dpll0_gate, "dpll0-gate", "ext-26m", 0xb4,
53 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
54static SPRD_SC_GATE_CLK(dpll1_gate, "dpll1-gate", "ext-26m", 0xb4,
55 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
56static SPRD_SC_GATE_CLK(ltepll0_gate, "ltepll0-gate", "ext-26m", 0xb8,
57 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
58static SPRD_SC_GATE_CLK(twpll_gate, "twpll-gate", "ext-26m", 0xbc,
59 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
60static SPRD_SC_GATE_CLK(ltepll1_gate, "ltepll1-gate", "ext-26m", 0x10c,
61 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
62static SPRD_SC_GATE_CLK(rpll0_gate, "rpll0-gate", "ext-26m", 0x16c,
63 0x1000, BIT(2), 0, 0);
64static SPRD_SC_GATE_CLK(rpll1_gate, "rpll1-gate", "ext-26m", 0x16c,
65 0x1000, BIT(18), 0, 0);
66static SPRD_SC_GATE_CLK(cppll_gate, "cppll-gate", "ext-26m", 0x2b4,
67 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
68static SPRD_SC_GATE_CLK(gpll_gate, "gpll-gate", "ext-26m", 0x32c,
69 0x1000, BIT(0), CLK_IGNORE_UNUSED, CLK_GATE_SET_TO_DISABLE);
70
71static struct sprd_clk_common *sc9860_pmu_gate_clks[] = {
72 /* address base is 0x402b0000 */
73 &mpll0_gate.common,
74 &mpll1_gate.common,
75 &dpll0_gate.common,
76 &dpll1_gate.common,
77 &ltepll0_gate.common,
78 &twpll_gate.common,
79 &ltepll1_gate.common,
80 &rpll0_gate.common,
81 &rpll1_gate.common,
82 &cppll_gate.common,
83 &gpll_gate.common,
84};
85
86static struct clk_hw_onecell_data sc9860_pmu_gate_hws = {
87 .hws = {
88 [CLK_FAC_4M] = &fac_4m.hw,
89 [CLK_FAC_2M] = &fac_2m.hw,
90 [CLK_FAC_1M] = &fac_1m.hw,
91 [CLK_FAC_250K] = &fac_250k.hw,
92 [CLK_FAC_RPLL0_26M] = &fac_rpll0_26m.hw,
93 [CLK_FAC_RPLL1_26M] = &fac_rpll1_26m.hw,
94 [CLK_FAC_RCO25M] = &fac_rco_25m.hw,
95 [CLK_FAC_RCO4M] = &fac_rco_4m.hw,
96 [CLK_FAC_RCO2M] = &fac_rco_2m.hw,
97 [CLK_FAC_3K2] = &fac_3k2.hw,
98 [CLK_FAC_1K] = &fac_1k.hw,
99 [CLK_MPLL0_GATE] = &mpll0_gate.common.hw,
100 [CLK_MPLL1_GATE] = &mpll1_gate.common.hw,
101 [CLK_DPLL0_GATE] = &dpll0_gate.common.hw,
102 [CLK_DPLL1_GATE] = &dpll1_gate.common.hw,
103 [CLK_LTEPLL0_GATE] = &ltepll0_gate.common.hw,
104 [CLK_TWPLL_GATE] = &twpll_gate.common.hw,
105 [CLK_LTEPLL1_GATE] = &ltepll1_gate.common.hw,
106 [CLK_RPLL0_GATE] = &rpll0_gate.common.hw,
107 [CLK_RPLL1_GATE] = &rpll1_gate.common.hw,
108 [CLK_CPPLL_GATE] = &cppll_gate.common.hw,
109 [CLK_GPLL_GATE] = &gpll_gate.common.hw,
110 },
111 .num = CLK_PMU_GATE_NUM,
112};
113
114static const struct sprd_clk_desc sc9860_pmu_gate_desc = {
115 .clk_clks = sc9860_pmu_gate_clks,
116 .num_clk_clks = ARRAY_SIZE(sc9860_pmu_gate_clks),
117 .hw_clks = &sc9860_pmu_gate_hws,
118};
119
120/* GPLL/LPLL/DPLL/RPLL/CPLL */
121static const u64 itable1[4] = {3, 780000000, 988000000, 1196000000};
122
123/* TWPLL/MPLL0/MPLL1 */
124static const u64 itable2[4] = {3, 1638000000, 2080000000, 2600000000UL};
125
126static const struct clk_bit_field f_mpll0[PLL_FACT_MAX] = {
127 { .shift = 20, .width = 1 }, /* lock_done */
128 { .shift = 19, .width = 1 }, /* div_s */
129 { .shift = 18, .width = 1 }, /* mod_en */
130 { .shift = 17, .width = 1 }, /* sdm_en */
131 { .shift = 0, .width = 0 }, /* refin */
132 { .shift = 11, .width = 2 }, /* ibias */
133 { .shift = 0, .width = 7 }, /* n */
134 { .shift = 57, .width = 7 }, /* nint */
135 { .shift = 32, .width = 23}, /* kint */
136 { .shift = 0, .width = 0 }, /* prediv */
137 { .shift = 56, .width = 1 }, /* postdiv */
138};
139static SPRD_PLL_WITH_ITABLE_K_FVCO(mpll0_clk, "mpll0", "mpll0-gate", 0x24,
140 2, itable2, f_mpll0, 200,
141 1000, 1000, 1, 1300000000);
142
143static const struct clk_bit_field f_mpll1[PLL_FACT_MAX] = {
144 { .shift = 20, .width = 1 }, /* lock_done */
145 { .shift = 19, .width = 1 }, /* div_s */
146 { .shift = 18, .width = 1 }, /* mod_en */
147 { .shift = 17, .width = 1 }, /* sdm_en */
148 { .shift = 0, .width = 0 }, /* refin */
149 { .shift = 11, .width = 2 }, /* ibias */
150 { .shift = 0, .width = 7 }, /* n */
151 { .shift = 57, .width = 7 }, /* nint */
152 { .shift = 32, .width = 23}, /* kint */
153 { .shift = 56, .width = 1 }, /* prediv */
154 { .shift = 0, .width = 0 }, /* postdiv */
155};
156static SPRD_PLL_WITH_ITABLE_1K(mpll1_clk, "mpll1", "mpll1-gate", 0x2c,
157 2, itable2, f_mpll1, 200);
158
159static const struct clk_bit_field f_dpll[PLL_FACT_MAX] = {
160 { .shift = 16, .width = 1 }, /* lock_done */
161 { .shift = 15, .width = 1 }, /* div_s */
162 { .shift = 14, .width = 1 }, /* mod_en */
163 { .shift = 13, .width = 1 }, /* sdm_en */
164 { .shift = 0, .width = 0 }, /* refin */
165 { .shift = 8, .width = 2 }, /* ibias */
166 { .shift = 0, .width = 7 }, /* n */
167 { .shift = 57, .width = 7 }, /* nint */
168 { .shift = 32, .width = 23}, /* kint */
169 { .shift = 0, .width = 0 }, /* prediv */
170 { .shift = 0, .width = 0 }, /* postdiv */
171};
172static SPRD_PLL_WITH_ITABLE_1K(dpll0_clk, "dpll0", "dpll0-gate", 0x34,
173 2, itable1, f_dpll, 200);
174
175static SPRD_PLL_WITH_ITABLE_1K(dpll1_clk, "dpll1", "dpll1-gate", 0x3c,
176 2, itable1, f_dpll, 200);
177
178static const struct clk_bit_field f_rpll[PLL_FACT_MAX] = {
179 { .shift = 0, .width = 1 }, /* lock_done */
180 { .shift = 3, .width = 1 }, /* div_s */
181 { .shift = 80, .width = 1 }, /* mod_en */
182 { .shift = 81, .width = 1 }, /* sdm_en */
183 { .shift = 0, .width = 0 }, /* refin */
184 { .shift = 14, .width = 2 }, /* ibias */
185 { .shift = 16, .width = 7 }, /* n */
186 { .shift = 4, .width = 7 }, /* nint */
187 { .shift = 32, .width = 23}, /* kint */
188 { .shift = 0, .width = 0 }, /* prediv */
189 { .shift = 0, .width = 0 }, /* postdiv */
190};
191static SPRD_PLL_WITH_ITABLE_1K(rpll0_clk, "rpll0", "rpll0-gate", 0x44,
192 3, itable1, f_rpll, 200);
193
194static SPRD_PLL_WITH_ITABLE_1K(rpll1_clk, "rpll1", "rpll1-gate", 0x50,
195 3, itable1, f_rpll, 200);
196
197static const struct clk_bit_field f_twpll[PLL_FACT_MAX] = {
198 { .shift = 21, .width = 1 }, /* lock_done */
199 { .shift = 20, .width = 1 }, /* div_s */
200 { .shift = 19, .width = 1 }, /* mod_en */
201 { .shift = 18, .width = 1 }, /* sdm_en */
202 { .shift = 0, .width = 0 }, /* refin */
203 { .shift = 13, .width = 2 }, /* ibias */
204 { .shift = 0, .width = 7 }, /* n */
205 { .shift = 57, .width = 7 }, /* nint */
206 { .shift = 32, .width = 23}, /* kint */
207 { .shift = 0, .width = 0 }, /* prediv */
208 { .shift = 0, .width = 0 }, /* postdiv */
209};
210static SPRD_PLL_WITH_ITABLE_1K(twpll_clk, "twpll", "twpll-gate", 0x5c,
211 2, itable2, f_twpll, 200);
212
213static const struct clk_bit_field f_ltepll[PLL_FACT_MAX] = {
214 { .shift = 31, .width = 1 }, /* lock_done */
215 { .shift = 27, .width = 1 }, /* div_s */
216 { .shift = 26, .width = 1 }, /* mod_en */
217 { .shift = 25, .width = 1 }, /* sdm_en */
218 { .shift = 0, .width = 0 }, /* refin */
219 { .shift = 20, .width = 2 }, /* ibias */
220 { .shift = 0, .width = 7 }, /* n */
221 { .shift = 57, .width = 7 }, /* nint */
222 { .shift = 32, .width = 23}, /* kint */
223 { .shift = 0, .width = 0 }, /* prediv */
224 { .shift = 0, .width = 0 }, /* postdiv */
225};
226static SPRD_PLL_WITH_ITABLE_1K(ltepll0_clk, "ltepll0", "ltepll0-gate",
227 0x64, 2, itable1,
228 f_ltepll, 200);
229static SPRD_PLL_WITH_ITABLE_1K(ltepll1_clk, "ltepll1", "ltepll1-gate",
230 0x6c, 2, itable1,
231 f_ltepll, 200);
232
233static const struct clk_bit_field f_gpll[PLL_FACT_MAX] = {
234 { .shift = 18, .width = 1 }, /* lock_done */
235 { .shift = 15, .width = 1 }, /* div_s */
236 { .shift = 14, .width = 1 }, /* mod_en */
237 { .shift = 13, .width = 1 }, /* sdm_en */
238 { .shift = 0, .width = 0 }, /* refin */
239 { .shift = 8, .width = 2 }, /* ibias */
240 { .shift = 0, .width = 7 }, /* n */
241 { .shift = 57, .width = 7 }, /* nint */
242 { .shift = 32, .width = 23}, /* kint */
243 { .shift = 0, .width = 0 }, /* prediv */
244 { .shift = 17, .width = 1 }, /* postdiv */
245};
246static SPRD_PLL_WITH_ITABLE_K_FVCO(gpll_clk, "gpll", "gpll-gate", 0x9c,
247 2, itable1, f_gpll, 200,
248 1000, 1000, 1, 600000000);
249
250static const struct clk_bit_field f_cppll[PLL_FACT_MAX] = {
251 { .shift = 17, .width = 1 }, /* lock_done */
252 { .shift = 15, .width = 1 }, /* div_s */
253 { .shift = 14, .width = 1 }, /* mod_en */
254 { .shift = 13, .width = 1 }, /* sdm_en */
255 { .shift = 0, .width = 0 }, /* refin */
256 { .shift = 8, .width = 2 }, /* ibias */
257 { .shift = 0, .width = 7 }, /* n */
258 { .shift = 57, .width = 7 }, /* nint */
259 { .shift = 32, .width = 23}, /* kint */
260 { .shift = 0, .width = 0 }, /* prediv */
261 { .shift = 0, .width = 0 }, /* postdiv */
262};
263static SPRD_PLL_WITH_ITABLE_1K(cppll_clk, "cppll", "cppll-gate", 0xc4,
264 2, itable1, f_cppll, 200);
265
266static CLK_FIXED_FACTOR(gpll_42m5, "gpll-42m5", "gpll", 20, 1, 0);
267static CLK_FIXED_FACTOR(twpll_768m, "twpll-768m", "twpll", 2, 1, 0);
268static CLK_FIXED_FACTOR(twpll_384m, "twpll-384m", "twpll", 4, 1, 0);
269static CLK_FIXED_FACTOR(twpll_192m, "twpll-192m", "twpll", 8, 1, 0);
270static CLK_FIXED_FACTOR(twpll_96m, "twpll-96m", "twpll", 16, 1, 0);
271static CLK_FIXED_FACTOR(twpll_48m, "twpll-48m", "twpll", 32, 1, 0);
272static CLK_FIXED_FACTOR(twpll_24m, "twpll-24m", "twpll", 64, 1, 0);
273static CLK_FIXED_FACTOR(twpll_12m, "twpll-12m", "twpll", 128, 1, 0);
274static CLK_FIXED_FACTOR(twpll_512m, "twpll-512m", "twpll", 3, 1, 0);
275static CLK_FIXED_FACTOR(twpll_256m, "twpll-256m", "twpll", 6, 1, 0);
276static CLK_FIXED_FACTOR(twpll_128m, "twpll-128m", "twpll", 12, 1, 0);
277static CLK_FIXED_FACTOR(twpll_64m, "twpll-64m", "twpll", 24, 1, 0);
278static CLK_FIXED_FACTOR(twpll_307m2, "twpll-307m2", "twpll", 5, 1, 0);
279static CLK_FIXED_FACTOR(twpll_153m6, "twpll-153m6", "twpll", 10, 1, 0);
280static CLK_FIXED_FACTOR(twpll_76m8, "twpll-76m8", "twpll", 20, 1, 0);
281static CLK_FIXED_FACTOR(twpll_51m2, "twpll-51m2", "twpll", 30, 1, 0);
282static CLK_FIXED_FACTOR(twpll_38m4, "twpll-38m4", "twpll", 40, 1, 0);
283static CLK_FIXED_FACTOR(twpll_19m2, "twpll-19m2", "twpll", 80, 1, 0);
284static CLK_FIXED_FACTOR(l0_614m4, "l0-614m4", "ltepll0", 2, 1, 0);
285static CLK_FIXED_FACTOR(l0_409m6, "l0-409m6", "ltepll0", 3, 1, 0);
286static CLK_FIXED_FACTOR(l0_38m, "l0-38m", "ltepll0", 32, 1, 0);
287static CLK_FIXED_FACTOR(l1_38m, "l1-38m", "ltepll1", 32, 1, 0);
288static CLK_FIXED_FACTOR(rpll0_192m, "rpll0-192m", "rpll0", 6, 1, 0);
289static CLK_FIXED_FACTOR(rpll0_96m, "rpll0-96m", "rpll0", 12, 1, 0);
290static CLK_FIXED_FACTOR(rpll0_48m, "rpll0-48m", "rpll0", 24, 1, 0);
291static CLK_FIXED_FACTOR(rpll1_468m, "rpll1-468m", "rpll1", 2, 1, 0);
292static CLK_FIXED_FACTOR(rpll1_192m, "rpll1-192m", "rpll1", 6, 1, 0);
293static CLK_FIXED_FACTOR(rpll1_96m, "rpll1-96m", "rpll1", 12, 1, 0);
294static CLK_FIXED_FACTOR(rpll1_64m, "rpll1-64m", "rpll1", 18, 1, 0);
295static CLK_FIXED_FACTOR(rpll1_48m, "rpll1-48m", "rpll1", 24, 1, 0);
296static CLK_FIXED_FACTOR(dpll0_50m, "dpll0-50m", "dpll0", 16, 1, 0);
297static CLK_FIXED_FACTOR(dpll1_50m, "dpll1-50m", "dpll1", 16, 1, 0);
298static CLK_FIXED_FACTOR(cppll_50m, "cppll-50m", "cppll", 18, 1, 0);
299static CLK_FIXED_FACTOR(m0_39m, "m0-39m", "mpll0", 32, 1, 0);
300static CLK_FIXED_FACTOR(m1_63m, "m1-63m", "mpll1", 32, 1, 0);
301
302static struct sprd_clk_common *sc9860_pll_clks[] = {
303 /* address base is 0x40400000 */
304 &mpll0_clk.common,
305 &mpll1_clk.common,
306 &dpll0_clk.common,
307 &dpll1_clk.common,
308 &rpll0_clk.common,
309 &rpll1_clk.common,
310 &twpll_clk.common,
311 &ltepll0_clk.common,
312 &ltepll1_clk.common,
313 &gpll_clk.common,
314 &cppll_clk.common,
315};
316
317static struct clk_hw_onecell_data sc9860_pll_hws = {
318 .hws = {
319 [CLK_MPLL0] = &mpll0_clk.common.hw,
320 [CLK_MPLL1] = &mpll1_clk.common.hw,
321 [CLK_DPLL0] = &dpll0_clk.common.hw,
322 [CLK_DPLL1] = &dpll1_clk.common.hw,
323 [CLK_RPLL0] = &rpll0_clk.common.hw,
324 [CLK_RPLL1] = &rpll1_clk.common.hw,
325 [CLK_TWPLL] = &twpll_clk.common.hw,
326 [CLK_LTEPLL0] = &ltepll0_clk.common.hw,
327 [CLK_LTEPLL1] = &ltepll1_clk.common.hw,
328 [CLK_GPLL] = &gpll_clk.common.hw,
329 [CLK_CPPLL] = &cppll_clk.common.hw,
330 [CLK_GPLL_42M5] = &gpll_42m5.hw,
331 [CLK_TWPLL_768M] = &twpll_768m.hw,
332 [CLK_TWPLL_384M] = &twpll_384m.hw,
333 [CLK_TWPLL_192M] = &twpll_192m.hw,
334 [CLK_TWPLL_96M] = &twpll_96m.hw,
335 [CLK_TWPLL_48M] = &twpll_48m.hw,
336 [CLK_TWPLL_24M] = &twpll_24m.hw,
337 [CLK_TWPLL_12M] = &twpll_12m.hw,
338 [CLK_TWPLL_512M] = &twpll_512m.hw,
339 [CLK_TWPLL_256M] = &twpll_256m.hw,
340 [CLK_TWPLL_128M] = &twpll_128m.hw,
341 [CLK_TWPLL_64M] = &twpll_64m.hw,
342 [CLK_TWPLL_307M2] = &twpll_307m2.hw,
343 [CLK_TWPLL_153M6] = &twpll_153m6.hw,
344 [CLK_TWPLL_76M8] = &twpll_76m8.hw,
345 [CLK_TWPLL_51M2] = &twpll_51m2.hw,
346 [CLK_TWPLL_38M4] = &twpll_38m4.hw,
347 [CLK_TWPLL_19M2] = &twpll_19m2.hw,
348 [CLK_L0_614M4] = &l0_614m4.hw,
349 [CLK_L0_409M6] = &l0_409m6.hw,
350 [CLK_L0_38M] = &l0_38m.hw,
351 [CLK_L1_38M] = &l1_38m.hw,
352 [CLK_RPLL0_192M] = &rpll0_192m.hw,
353 [CLK_RPLL0_96M] = &rpll0_96m.hw,
354 [CLK_RPLL0_48M] = &rpll0_48m.hw,
355 [CLK_RPLL1_468M] = &rpll1_468m.hw,
356 [CLK_RPLL1_192M] = &rpll1_192m.hw,
357 [CLK_RPLL1_96M] = &rpll1_96m.hw,
358 [CLK_RPLL1_64M] = &rpll1_64m.hw,
359 [CLK_RPLL1_48M] = &rpll1_48m.hw,
360 [CLK_DPLL0_50M] = &dpll0_50m.hw,
361 [CLK_DPLL1_50M] = &dpll1_50m.hw,
362 [CLK_CPPLL_50M] = &cppll_50m.hw,
363 [CLK_M0_39M] = &m0_39m.hw,
364 [CLK_M1_63M] = &m1_63m.hw,
365 },
366 .num = CLK_PLL_NUM,
367};
368
369static const struct sprd_clk_desc sc9860_pll_desc = {
370 .clk_clks = sc9860_pll_clks,
371 .num_clk_clks = ARRAY_SIZE(sc9860_pll_clks),
372 .hw_clks = &sc9860_pll_hws,
373};
374
375#define SC9860_MUX_FLAG \
376 (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)
377
378static const char * const ap_apb_parents[] = { "ext-26m", "twpll-64m",
379 "twpll-96m", "twpll-128m" };
380static SPRD_MUX_CLK(ap_apb, "ap-apb", ap_apb_parents,
381 0x20, 0, 1, SC9860_MUX_FLAG);
382
383static const char * const ap_apb_usb3[] = { "ext-32k", "twpll-24m" };
384static SPRD_MUX_CLK(ap_usb3, "ap-usb3", ap_apb_usb3,
385 0x2c, 0, 1, SC9860_MUX_FLAG);
386
387static const char * const uart_parents[] = { "ext-26m", "twpll-48m",
388 "twpll-51m2", "twpll-96m" };
389static SPRD_COMP_CLK(uart0_clk, "uart0", uart_parents, 0x30,
390 0, 2, 8, 3, 0);
391static SPRD_COMP_CLK(uart1_clk, "uart1", uart_parents, 0x34,
392 0, 2, 8, 3, 0);
393static SPRD_COMP_CLK(uart2_clk, "uart2", uart_parents, 0x38,
394 0, 2, 8, 3, 0);
395static SPRD_COMP_CLK(uart3_clk, "uart3", uart_parents, 0x3c,
396 0, 2, 8, 3, 0);
397static SPRD_COMP_CLK(uart4_clk, "uart4", uart_parents, 0x40,
398 0, 2, 8, 3, 0);
399
400static const char * const i2c_parents[] = { "ext-26m", "twpll-48m",
401 "twpll-51m2", "twpll-153m6" };
402static SPRD_COMP_CLK(i2c0_clk, "i2c0", i2c_parents, 0x44,
403 0, 2, 8, 3, 0);
404static SPRD_COMP_CLK(i2c1_clk, "i2c1", i2c_parents, 0x48,
405 0, 2, 8, 3, 0);
406static SPRD_COMP_CLK(i2c2_clk, "i2c2", i2c_parents, 0x4c,
407 0, 2, 8, 3, 0);
408static SPRD_COMP_CLK(i2c3_clk, "i2c3", i2c_parents, 0x50,
409 0, 2, 8, 3, 0);
410static SPRD_COMP_CLK(i2c4_clk, "i2c4", i2c_parents, 0x54,
411 0, 2, 8, 3, 0);
412static SPRD_COMP_CLK(i2c5_clk, "i2c5", i2c_parents, 0x58,
413 0, 2, 8, 3, 0);
414
415static const char * const spi_parents[] = { "ext-26m", "twpll-128m",
416 "twpll-153m6", "twpll-192m" };
417static SPRD_COMP_CLK(spi0_clk, "spi0", spi_parents, 0x5c,
418 0, 2, 8, 3, 0);
419static SPRD_COMP_CLK(spi1_clk, "spi1", spi_parents, 0x60,
420 0, 2, 8, 3, 0);
421static SPRD_COMP_CLK(spi2_clk, "spi2", spi_parents, 0x64,
422 0, 2, 8, 3, 0);
423static SPRD_COMP_CLK(spi3_clk, "spi3", spi_parents, 0x68,
424 0, 2, 8, 3, 0);
425
426static const char * const iis_parents[] = { "ext-26m",
427 "twpll-128m",
428 "twpll-153m6" };
429static SPRD_COMP_CLK(iis0_clk, "iis0", iis_parents, 0x6c,
430 0, 2, 8, 6, 0);
431static SPRD_COMP_CLK(iis1_clk, "iis1", iis_parents, 0x70,
432 0, 2, 8, 6, 0);
433static SPRD_COMP_CLK(iis2_clk, "iis2", iis_parents, 0x74,
434 0, 2, 8, 6, 0);
435static SPRD_COMP_CLK(iis3_clk, "iis3", iis_parents, 0x78,
436 0, 2, 8, 6, 0);
437
438static struct sprd_clk_common *sc9860_ap_clks[] = {
439 /* address base is 0x20000000 */
440 &ap_apb.common,
441 &ap_usb3.common,
442 &uart0_clk.common,
443 &uart1_clk.common,
444 &uart2_clk.common,
445 &uart3_clk.common,
446 &uart4_clk.common,
447 &i2c0_clk.common,
448 &i2c1_clk.common,
449 &i2c2_clk.common,
450 &i2c3_clk.common,
451 &i2c4_clk.common,
452 &i2c5_clk.common,
453 &spi0_clk.common,
454 &spi1_clk.common,
455 &spi2_clk.common,
456 &spi3_clk.common,
457 &iis0_clk.common,
458 &iis1_clk.common,
459 &iis2_clk.common,
460 &iis3_clk.common,
461};
462
463static struct clk_hw_onecell_data sc9860_ap_clk_hws = {
464 .hws = {
465 [CLK_AP_APB] = &ap_apb.common.hw,
466 [CLK_AP_USB3] = &ap_usb3.common.hw,
467 [CLK_UART0] = &uart0_clk.common.hw,
468 [CLK_UART1] = &uart1_clk.common.hw,
469 [CLK_UART2] = &uart2_clk.common.hw,
470 [CLK_UART3] = &uart3_clk.common.hw,
471 [CLK_UART4] = &uart4_clk.common.hw,
472 [CLK_I2C0] = &i2c0_clk.common.hw,
473 [CLK_I2C1] = &i2c1_clk.common.hw,
474 [CLK_I2C2] = &i2c2_clk.common.hw,
475 [CLK_I2C3] = &i2c3_clk.common.hw,
476 [CLK_I2C4] = &i2c4_clk.common.hw,
477 [CLK_I2C5] = &i2c5_clk.common.hw,
478 [CLK_SPI0] = &spi0_clk.common.hw,
479 [CLK_SPI1] = &spi1_clk.common.hw,
480 [CLK_SPI2] = &spi2_clk.common.hw,
481 [CLK_SPI3] = &spi3_clk.common.hw,
482 [CLK_IIS0] = &iis0_clk.common.hw,
483 [CLK_IIS1] = &iis1_clk.common.hw,
484 [CLK_IIS2] = &iis2_clk.common.hw,
485 [CLK_IIS3] = &iis3_clk.common.hw,
486 },
487 .num = CLK_AP_CLK_NUM,
488};
489
490static const struct sprd_clk_desc sc9860_ap_clk_desc = {
491 .clk_clks = sc9860_ap_clks,
492 .num_clk_clks = ARRAY_SIZE(sc9860_ap_clks),
493 .hw_clks = &sc9860_ap_clk_hws,
494};
495
496static const char * const aon_apb_parents[] = { "rco-25m", "ext-26m",
497 "ext-rco-100m", "twpll-96m",
498 "twpll-128m",
499 "twpll-153m6" };
500static SPRD_COMP_CLK(aon_apb, "aon-apb", aon_apb_parents, 0x230,
501 0, 3, 8, 2, 0);
502
503static const char * const aux_parents[] = { "ext-32k", "rpll0-26m",
504 "rpll1-26m", "ext-26m",
505 "cppll-50m", "rco-25m",
506 "dpll0-50m", "dpll1-50m",
507 "gpll-42m5", "twpll-48m",
508 "m0-39m", "m1-63m",
509 "l0-38m", "l1-38m" };
510
511static SPRD_COMP_CLK(aux0_clk, "aux0", aux_parents, 0x238,
512 0, 5, 8, 4, 0);
513static SPRD_COMP_CLK(aux1_clk, "aux1", aux_parents, 0x23c,
514 0, 5, 8, 4, 0);
515static SPRD_COMP_CLK(aux2_clk, "aux2", aux_parents, 0x240,
516 0, 5, 8, 4, 0);
517static SPRD_COMP_CLK(probe_clk, "probe", aux_parents, 0x244,
518 0, 5, 8, 4, 0);
519
520static const char * const sp_ahb_parents[] = { "rco-4m", "ext-26m",
521 "ext-rco-100m", "twpll-96m",
522 "twpll-128m",
523 "twpll-153m6" };
524static SPRD_COMP_CLK(sp_ahb, "sp-ahb", sp_ahb_parents, 0x2d0,
525 0, 3, 8, 2, 0);
526
527static const char * const cci_parents[] = { "ext-26m", "twpll-384m",
528 "l0-614m4", "twpll-768m" };
529static SPRD_COMP_CLK(cci_clk, "cci", cci_parents, 0x300,
530 0, 2, 8, 2, 0);
531static SPRD_COMP_CLK(gic_clk, "gic", cci_parents, 0x304,
532 0, 2, 8, 2, 0);
533static SPRD_COMP_CLK(cssys_clk, "cssys", cci_parents, 0x310,
534 0, 2, 8, 2, 0);
535
536static const char * const sdio_2x_parents[] = { "fac-1m", "ext-26m",
537 "twpll-307m2", "twpll-384m",
538 "l0-409m6" };
539static SPRD_COMP_CLK(sdio0_2x, "sdio0-2x", sdio_2x_parents, 0x328,
540 0, 3, 8, 4, 0);
541static SPRD_COMP_CLK(sdio1_2x, "sdio1-2x", sdio_2x_parents, 0x330,
542 0, 3, 8, 4, 0);
543static SPRD_COMP_CLK(sdio2_2x, "sdio2-2x", sdio_2x_parents, 0x338,
544 0, 3, 8, 4, 0);
545static SPRD_COMP_CLK(emmc_2x, "emmc-2x", sdio_2x_parents, 0x340,
546 0, 3, 8, 4, 0);
547
548static SPRD_DIV_CLK(sdio0_1x, "sdio0-1x", "sdio0-2x", 0x32c,
549 8, 1, 0);
550static SPRD_DIV_CLK(sdio1_1x, "sdio1-1x", "sdio1-2x", 0x334,
551 8, 1, 0);
552static SPRD_DIV_CLK(sdio2_1x, "sdio2-1x", "sdio2-2x", 0x33c,
553 8, 1, 0);
554static SPRD_DIV_CLK(emmc_1x, "emmc-1x", "emmc-2x", 0x344,
555 8, 1, 0);
556
557static const char * const adi_parents[] = { "rco-4m", "ext-26m",
558 "rco-25m", "twpll-38m4",
559 "twpll-51m2" };
560static SPRD_MUX_CLK(adi_clk, "adi", adi_parents, 0x234,
561 0, 3, SC9860_MUX_FLAG);
562
563static const char * const pwm_parents[] = { "ext-32k", "ext-26m",
564 "rco-4m", "rco-25m",
565 "twpll-48m" };
566static SPRD_MUX_CLK(pwm0_clk, "pwm0", pwm_parents, 0x248,
567 0, 3, SC9860_MUX_FLAG);
568static SPRD_MUX_CLK(pwm1_clk, "pwm1", pwm_parents, 0x24c,
569 0, 3, SC9860_MUX_FLAG);
570static SPRD_MUX_CLK(pwm2_clk, "pwm2", pwm_parents, 0x250,
571 0, 3, SC9860_MUX_FLAG);
572static SPRD_MUX_CLK(pwm3_clk, "pwm3", pwm_parents, 0x254,
573 0, 3, SC9860_MUX_FLAG);
574
575static const char * const efuse_parents[] = { "rco-25m", "ext-26m" };
576static SPRD_MUX_CLK(efuse_clk, "efuse", efuse_parents, 0x258,
577 0, 1, SC9860_MUX_FLAG);
578
579static const char * const cm3_uart_parents[] = { "rco-4m", "ext-26m",
580 "rco-100m", "twpll-48m",
581 "twpll-51m2", "twpll-96m",
582 "twpll-128m" };
583static SPRD_MUX_CLK(cm3_uart0, "cm3-uart0", cm3_uart_parents, 0x25c,
584 0, 3, SC9860_MUX_FLAG);
585static SPRD_MUX_CLK(cm3_uart1, "cm3-uart1", cm3_uart_parents, 0x260,
586 0, 3, SC9860_MUX_FLAG);
587
588static const char * const thm_parents[] = { "ext-32k", "fac-250k" };
589static SPRD_MUX_CLK(thm_clk, "thm", thm_parents, 0x270,
590 0, 1, SC9860_MUX_FLAG);
591
592static const char * const cm3_i2c_parents[] = { "rco-4m",
593 "ext-26m",
594 "rco-100m",
595 "twpll-48m",
596 "twpll-51m2",
597 "twpll-153m6" };
598static SPRD_MUX_CLK(cm3_i2c0, "cm3-i2c0", cm3_i2c_parents, 0x274,
599 0, 3, SC9860_MUX_FLAG);
600static SPRD_MUX_CLK(cm3_i2c1, "cm3-i2c1", cm3_i2c_parents, 0x278,
601 0, 3, SC9860_MUX_FLAG);
602static SPRD_MUX_CLK(aon_i2c, "aon-i2c", cm3_i2c_parents, 0x280,
603 0, 3, SC9860_MUX_FLAG);
604
605static const char * const cm4_spi_parents[] = { "ext-26m", "twpll-96m",
606 "rco-100m", "twpll-128m",
607 "twpll-153m6", "twpll-192m" };
608static SPRD_MUX_CLK(cm4_spi, "cm4-spi", cm4_spi_parents, 0x27c,
609 0, 3, SC9860_MUX_FLAG);
610
611static SPRD_MUX_CLK(avs_clk, "avs", uart_parents, 0x284,
612 0, 2, SC9860_MUX_FLAG);
613
614static const char * const ca53_dap_parents[] = { "ext-26m", "rco-4m",
615 "rco-100m", "twpll-76m8",
616 "twpll-128m", "twpll-153m6" };
617static SPRD_MUX_CLK(ca53_dap, "ca53-dap", ca53_dap_parents, 0x288,
618 0, 3, SC9860_MUX_FLAG);
619
620static const char * const ca53_ts_parents[] = { "ext-32k", "ext-26m",
621 "clk-twpll-128m",
622 "clk-twpll-153m6" };
623static SPRD_MUX_CLK(ca53_ts, "ca53-ts", ca53_ts_parents, 0x290,
624 0, 2, SC9860_MUX_FLAG);
625
626static const char * const djtag_tck_parents[] = { "rco-4m", "ext-26m" };
627static SPRD_MUX_CLK(djtag_tck, "djtag-tck", djtag_tck_parents, 0x2c8,
628 0, 1, SC9860_MUX_FLAG);
629
630static const char * const pmu_parents[] = { "ext-32k", "rco-4m", "clk-4m" };
631static SPRD_MUX_CLK(pmu_clk, "pmu", pmu_parents, 0x2e0,
632 0, 2, SC9860_MUX_FLAG);
633
634static const char * const pmu_26m_parents[] = { "rco-25m", "ext-26m" };
635static SPRD_MUX_CLK(pmu_26m, "pmu-26m", pmu_26m_parents, 0x2e4,
636 0, 1, SC9860_MUX_FLAG);
637
638static const char * const debounce_parents[] = { "ext-32k", "rco-4m",
639 "rco-25m", "ext-26m" };
640static SPRD_MUX_CLK(debounce_clk, "debounce", debounce_parents, 0x2e8,
641 0, 2, SC9860_MUX_FLAG);
642
643static const char * const otg2_ref_parents[] = { "twpll-12m", "twpll-24m" };
644static SPRD_MUX_CLK(otg2_ref, "otg2-ref", otg2_ref_parents, 0x2f4,
645 0, 1, SC9860_MUX_FLAG);
646
647static const char * const usb3_ref_parents[] = { "twpll-24m", "twpll-19m2",
648 "twpll-48m" };
649static SPRD_MUX_CLK(usb3_ref, "usb3-ref", usb3_ref_parents, 0x2f8,
650 0, 2, SC9860_MUX_FLAG);
651
652static const char * const ap_axi_parents[] = { "ext-26m", "twpll-76m8",
653 "twpll-128m", "twpll-256m" };
654static SPRD_MUX_CLK(ap_axi, "ap-axi", ap_axi_parents, 0x324,
655 0, 2, SC9860_MUX_FLAG);
656
657static struct sprd_clk_common *sc9860_aon_prediv[] = {
658 /* address base is 0x402d0000 */
659 &aon_apb.common,
660 &aux0_clk.common,
661 &aux1_clk.common,
662 &aux2_clk.common,
663 &probe_clk.common,
664 &sp_ahb.common,
665 &cci_clk.common,
666 &gic_clk.common,
667 &cssys_clk.common,
668 &sdio0_2x.common,
669 &sdio1_2x.common,
670 &sdio2_2x.common,
671 &emmc_2x.common,
672 &sdio0_1x.common,
673 &sdio1_1x.common,
674 &sdio2_1x.common,
675 &emmc_1x.common,
676 &adi_clk.common,
677 &pwm0_clk.common,
678 &pwm1_clk.common,
679 &pwm2_clk.common,
680 &pwm3_clk.common,
681 &efuse_clk.common,
682 &cm3_uart0.common,
683 &cm3_uart1.common,
684 &thm_clk.common,
685 &cm3_i2c0.common,
686 &cm3_i2c1.common,
687 &cm4_spi.common,
688 &aon_i2c.common,
689 &avs_clk.common,
690 &ca53_dap.common,
691 &ca53_ts.common,
692 &djtag_tck.common,
693 &pmu_clk.common,
694 &pmu_26m.common,
695 &debounce_clk.common,
696 &otg2_ref.common,
697 &usb3_ref.common,
698 &ap_axi.common,
699};
700
701static struct clk_hw_onecell_data sc9860_aon_prediv_hws = {
702 .hws = {
703 [CLK_AON_APB] = &aon_apb.common.hw,
704 [CLK_AUX0] = &aux0_clk.common.hw,
705 [CLK_AUX1] = &aux1_clk.common.hw,
706 [CLK_AUX2] = &aux2_clk.common.hw,
707 [CLK_PROBE] = &probe_clk.common.hw,
708 [CLK_SP_AHB] = &sp_ahb.common.hw,
709 [CLK_CCI] = &cci_clk.common.hw,
710 [CLK_GIC] = &gic_clk.common.hw,
711 [CLK_CSSYS] = &cssys_clk.common.hw,
712 [CLK_SDIO0_2X] = &sdio0_2x.common.hw,
713 [CLK_SDIO1_2X] = &sdio1_2x.common.hw,
714 [CLK_SDIO2_2X] = &sdio2_2x.common.hw,
715 [CLK_EMMC_2X] = &emmc_2x.common.hw,
716 [CLK_SDIO0_1X] = &sdio0_1x.common.hw,
717 [CLK_SDIO1_1X] = &sdio1_1x.common.hw,
718 [CLK_SDIO2_1X] = &sdio2_1x.common.hw,
719 [CLK_EMMC_1X] = &emmc_1x.common.hw,
720 [CLK_ADI] = &adi_clk.common.hw,
721 [CLK_PWM0] = &pwm0_clk.common.hw,
722 [CLK_PWM1] = &pwm1_clk.common.hw,
723 [CLK_PWM2] = &pwm2_clk.common.hw,
724 [CLK_PWM3] = &pwm3_clk.common.hw,
725 [CLK_EFUSE] = &efuse_clk.common.hw,
726 [CLK_CM3_UART0] = &cm3_uart0.common.hw,
727 [CLK_CM3_UART1] = &cm3_uart1.common.hw,
728 [CLK_THM] = &thm_clk.common.hw,
729 [CLK_CM3_I2C0] = &cm3_i2c0.common.hw,
730 [CLK_CM3_I2C1] = &cm3_i2c1.common.hw,
731 [CLK_CM4_SPI] = &cm4_spi.common.hw,
732 [CLK_AON_I2C] = &aon_i2c.common.hw,
733 [CLK_AVS] = &avs_clk.common.hw,
734 [CLK_CA53_DAP] = &ca53_dap.common.hw,
735 [CLK_CA53_TS] = &ca53_ts.common.hw,
736 [CLK_DJTAG_TCK] = &djtag_tck.common.hw,
737 [CLK_PMU] = &pmu_clk.common.hw,
738 [CLK_PMU_26M] = &pmu_26m.common.hw,
739 [CLK_DEBOUNCE] = &debounce_clk.common.hw,
740 [CLK_OTG2_REF] = &otg2_ref.common.hw,
741 [CLK_USB3_REF] = &usb3_ref.common.hw,
742 [CLK_AP_AXI] = &ap_axi.common.hw,
743 },
744 .num = CLK_AON_PREDIV_NUM,
745};
746
747static const struct sprd_clk_desc sc9860_aon_prediv_desc = {
748 .clk_clks = sc9860_aon_prediv,
749 .num_clk_clks = ARRAY_SIZE(sc9860_aon_prediv),
750 .hw_clks = &sc9860_aon_prediv_hws,
751};
752
753static SPRD_SC_GATE_CLK(usb3_eb, "usb3-eb", "ap-axi", 0x0,
754 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
755static SPRD_SC_GATE_CLK(usb3_suspend, "usb3-suspend", "ap-axi", 0x0,
756 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
757static SPRD_SC_GATE_CLK(usb3_ref_eb, "usb3-ref-eb", "ap-axi", 0x0,
758 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
759static SPRD_SC_GATE_CLK(dma_eb, "dma-eb", "ap-axi", 0x0,
760 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
761static SPRD_SC_GATE_CLK(sdio0_eb, "sdio0-eb", "ap-axi", 0x0,
762 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
763static SPRD_SC_GATE_CLK(sdio1_eb, "sdio1-eb", "ap-axi", 0x0,
764 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
765static SPRD_SC_GATE_CLK(sdio2_eb, "sdio2-eb", "ap-axi", 0x0,
766 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
767static SPRD_SC_GATE_CLK(emmc_eb, "emmc-eb", "ap-axi", 0x0,
768 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
769static SPRD_SC_GATE_CLK(rom_eb, "rom-eb", "ap-axi", 0x0,
770 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
771static SPRD_SC_GATE_CLK(busmon_eb, "busmon-eb", "ap-axi", 0x0,
772 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
773static SPRD_SC_GATE_CLK(cc63s_eb, "cc63s-eb", "ap-axi", 0x0,
774 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
775static SPRD_SC_GATE_CLK(cc63p_eb, "cc63p-eb", "ap-axi", 0x0,
776 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
777static SPRD_SC_GATE_CLK(ce0_eb, "ce0-eb", "ap-axi", 0x0,
778 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
779static SPRD_SC_GATE_CLK(ce1_eb, "ce1-eb", "ap-axi", 0x0,
780 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
781
782static struct sprd_clk_common *sc9860_apahb_gate[] = {
783 /* address base is 0x20210000 */
784 &usb3_eb.common,
785 &usb3_suspend.common,
786 &usb3_ref_eb.common,
787 &dma_eb.common,
788 &sdio0_eb.common,
789 &sdio1_eb.common,
790 &sdio2_eb.common,
791 &emmc_eb.common,
792 &rom_eb.common,
793 &busmon_eb.common,
794 &cc63s_eb.common,
795 &cc63p_eb.common,
796 &ce0_eb.common,
797 &ce1_eb.common,
798};
799
800static struct clk_hw_onecell_data sc9860_apahb_gate_hws = {
801 .hws = {
802 [CLK_USB3_EB] = &usb3_eb.common.hw,
803 [CLK_USB3_SUSPEND_EB] = &usb3_suspend.common.hw,
804 [CLK_USB3_REF_EB] = &usb3_ref_eb.common.hw,
805 [CLK_DMA_EB] = &dma_eb.common.hw,
806 [CLK_SDIO0_EB] = &sdio0_eb.common.hw,
807 [CLK_SDIO1_EB] = &sdio1_eb.common.hw,
808 [CLK_SDIO2_EB] = &sdio2_eb.common.hw,
809 [CLK_EMMC_EB] = &emmc_eb.common.hw,
810 [CLK_ROM_EB] = &rom_eb.common.hw,
811 [CLK_BUSMON_EB] = &busmon_eb.common.hw,
812 [CLK_CC63S_EB] = &cc63s_eb.common.hw,
813 [CLK_CC63P_EB] = &cc63p_eb.common.hw,
814 [CLK_CE0_EB] = &ce0_eb.common.hw,
815 [CLK_CE1_EB] = &ce1_eb.common.hw,
816 },
817 .num = CLK_APAHB_GATE_NUM,
818};
819
820static const struct sprd_clk_desc sc9860_apahb_gate_desc = {
821 .clk_clks = sc9860_apahb_gate,
822 .num_clk_clks = ARRAY_SIZE(sc9860_apahb_gate),
823 .hw_clks = &sc9860_apahb_gate_hws,
824};
825
826static SPRD_SC_GATE_CLK(avs_lit_eb, "avs-lit-eb", "aon-apb", 0x0,
827 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
828static SPRD_SC_GATE_CLK(avs_big_eb, "avs-big-eb", "aon-apb", 0x0,
829 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
830static SPRD_SC_GATE_CLK(ap_intc5_eb, "ap-intc5-eb", "aon-apb", 0x0,
831 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
832static SPRD_SC_GATE_CLK(gpio_eb, "gpio-eb", "aon-apb", 0x0,
833 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
834static SPRD_SC_GATE_CLK(pwm0_eb, "pwm0-eb", "aon-apb", 0x0,
835 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
836static SPRD_SC_GATE_CLK(pwm1_eb, "pwm1-eb", "aon-apb", 0x0,
837 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
838static SPRD_SC_GATE_CLK(pwm2_eb, "pwm2-eb", "aon-apb", 0x0,
839 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
840static SPRD_SC_GATE_CLK(pwm3_eb, "pwm3-eb", "aon-apb", 0x0,
841 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
842static SPRD_SC_GATE_CLK(kpd_eb, "kpd-eb", "aon-apb", 0x0,
843 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
844static SPRD_SC_GATE_CLK(aon_sys_eb, "aon-sys-eb", "aon-apb", 0x0,
845 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
846static SPRD_SC_GATE_CLK(ap_sys_eb, "ap-sys-eb", "aon-apb", 0x0,
847 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
848static SPRD_SC_GATE_CLK(aon_tmr_eb, "aon-tmr-eb", "aon-apb", 0x0,
849 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
850static SPRD_SC_GATE_CLK(ap_tmr0_eb, "ap-tmr0-eb", "aon-apb", 0x0,
851 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
852static SPRD_SC_GATE_CLK(efuse_eb, "efuse-eb", "aon-apb", 0x0,
853 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
854static SPRD_SC_GATE_CLK(eic_eb, "eic-eb", "aon-apb", 0x0,
855 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
856static SPRD_SC_GATE_CLK(pub1_reg_eb, "pub1-reg-eb", "aon-apb", 0x0,
857 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
858static SPRD_SC_GATE_CLK(adi_eb, "adi-eb", "aon-apb", 0x0,
859 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
860static SPRD_SC_GATE_CLK(ap_intc0_eb, "ap-intc0-eb", "aon-apb", 0x0,
861 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
862static SPRD_SC_GATE_CLK(ap_intc1_eb, "ap-intc1-eb", "aon-apb", 0x0,
863 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
864static SPRD_SC_GATE_CLK(ap_intc2_eb, "ap-intc2-eb", "aon-apb", 0x0,
865 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
866static SPRD_SC_GATE_CLK(ap_intc3_eb, "ap-intc3-eb", "aon-apb", 0x0,
867 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
868static SPRD_SC_GATE_CLK(ap_intc4_eb, "ap-intc4-eb", "aon-apb", 0x0,
869 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
870static SPRD_SC_GATE_CLK(splk_eb, "splk-eb", "aon-apb", 0x0,
871 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
872static SPRD_SC_GATE_CLK(mspi_eb, "mspi-eb", "aon-apb", 0x0,
873 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
874static SPRD_SC_GATE_CLK(pub0_reg_eb, "pub0-reg-eb", "aon-apb", 0x0,
875 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
876static SPRD_SC_GATE_CLK(pin_eb, "pin-eb", "aon-apb", 0x0,
877 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
878static SPRD_SC_GATE_CLK(aon_ckg_eb, "aon-ckg-eb", "aon-apb", 0x0,
879 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);
880static SPRD_SC_GATE_CLK(gpu_eb, "gpu-eb", "aon-apb", 0x0,
881 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
882static SPRD_SC_GATE_CLK(apcpu_ts0_eb, "apcpu-ts0-eb", "aon-apb", 0x0,
883 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);
884static SPRD_SC_GATE_CLK(apcpu_ts1_eb, "apcpu-ts1-eb", "aon-apb", 0x0,
885 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);
886static SPRD_SC_GATE_CLK(dap_eb, "dap-eb", "aon-apb", 0x0,
887 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);
888static SPRD_SC_GATE_CLK(i2c_eb, "i2c-eb", "aon-apb", 0x0,
889 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);
890static SPRD_SC_GATE_CLK(pmu_eb, "pmu-eb", "aon-apb", 0x4,
891 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
892static SPRD_SC_GATE_CLK(thm_eb, "thm-eb", "aon-apb", 0x4,
893 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
894static SPRD_SC_GATE_CLK(aux0_eb, "aux0-eb", "aon-apb", 0x4,
895 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
896static SPRD_SC_GATE_CLK(aux1_eb, "aux1-eb", "aon-apb", 0x4,
897 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
898static SPRD_SC_GATE_CLK(aux2_eb, "aux2-eb", "aon-apb", 0x4,
899 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
900static SPRD_SC_GATE_CLK(probe_eb, "probe-eb", "aon-apb", 0x4,
901 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
902static SPRD_SC_GATE_CLK(gpu0_avs_eb, "gpu0-avs-eb", "aon-apb", 0x4,
903 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
904static SPRD_SC_GATE_CLK(gpu1_avs_eb, "gpu1-avs-eb", "aon-apb", 0x4,
905 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
906static SPRD_SC_GATE_CLK(apcpu_wdg_eb, "apcpu-wdg-eb", "aon-apb", 0x4,
907 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
908static SPRD_SC_GATE_CLK(ap_tmr1_eb, "ap-tmr1-eb", "aon-apb", 0x4,
909 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
910static SPRD_SC_GATE_CLK(ap_tmr2_eb, "ap-tmr2-eb", "aon-apb", 0x4,
911 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
912static SPRD_SC_GATE_CLK(disp_emc_eb, "disp-emc-eb", "aon-apb", 0x4,
913 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
914static SPRD_SC_GATE_CLK(zip_emc_eb, "zip-emc-eb", "aon-apb", 0x4,
915 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
916static SPRD_SC_GATE_CLK(gsp_emc_eb, "gsp-emc-eb", "aon-apb", 0x4,
917 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
918static SPRD_SC_GATE_CLK(osc_aon_eb, "osc-aon-eb", "aon-apb", 0x4,
919 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
920static SPRD_SC_GATE_CLK(lvds_trx_eb, "lvds-trx-eb", "aon-apb", 0x4,
921 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
922static SPRD_SC_GATE_CLK(lvds_tcxo_eb, "lvds-tcxo-eb", "aon-apb", 0x4,
923 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
924static SPRD_SC_GATE_CLK(mdar_eb, "mdar-eb", "aon-apb", 0x4,
925 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
926static SPRD_SC_GATE_CLK(rtc4m0_cal_eb, "rtc4m0-cal-eb", "aon-apb", 0x4,
927 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
928static SPRD_SC_GATE_CLK(rct100m_cal_eb, "rct100m-cal-eb", "aon-apb", 0x4,
929 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
930static SPRD_SC_GATE_CLK(djtag_eb, "djtag-eb", "aon-apb", 0x4,
931 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
932static SPRD_SC_GATE_CLK(mbox_eb, "mbox-eb", "aon-apb", 0x4,
933 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
934static SPRD_SC_GATE_CLK(aon_dma_eb, "aon-dma-eb", "aon-apb", 0x4,
935 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
936static SPRD_SC_GATE_CLK(dbg_emc_eb, "dbg-emc-eb", "aon-apb", 0x4,
937 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
938static SPRD_SC_GATE_CLK(lvds_pll_div_en, "lvds-pll-div-en", "aon-apb", 0x4,
939 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
940static SPRD_SC_GATE_CLK(def_eb, "def-eb", "aon-apb", 0x4,
941 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);
942static SPRD_SC_GATE_CLK(aon_apb_rsv0, "aon-apb-rsv0", "aon-apb", 0x4,
943 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);
944static SPRD_SC_GATE_CLK(orp_jtag_eb, "orp-jtag-eb", "aon-apb", 0x4,
945 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
946static SPRD_SC_GATE_CLK(vsp_eb, "vsp-eb", "aon-apb", 0x4,
947 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);
948static SPRD_SC_GATE_CLK(cam_eb, "cam-eb", "aon-apb", 0x4,
949 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);
950static SPRD_SC_GATE_CLK(disp_eb, "disp-eb", "aon-apb", 0x4,
951 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);
952static SPRD_SC_GATE_CLK(dbg_axi_if_eb, "dbg-axi-if-eb", "aon-apb", 0x4,
953 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);
954static SPRD_SC_GATE_CLK(sdio0_2x_en, "sdio0-2x-en", "aon-apb", 0x13c,
955 0x1000, BIT(2), 0, 0);
956static SPRD_SC_GATE_CLK(sdio1_2x_en, "sdio1-2x-en", "aon-apb", 0x13c,
957 0x1000, BIT(4), 0, 0);
958static SPRD_SC_GATE_CLK(sdio2_2x_en, "sdio2-2x-en", "aon-apb", 0x13c,
959 0x1000, BIT(6), 0, 0);
960static SPRD_SC_GATE_CLK(emmc_2x_en, "emmc-2x-en", "aon-apb", 0x13c,
961 0x1000, BIT(9), 0, 0);
Chunyan Zhangb3316a62018-02-09 17:55:09 +0800[diff] [blame]962static SPRD_SC_GATE_CLK(arch_rtc_eb, "arch-rtc-eb", "aon-apb", 0x10,
963 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
964static SPRD_SC_GATE_CLK(kpb_rtc_eb, "kpb-rtc-eb", "aon-apb", 0x10,
965 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
966static SPRD_SC_GATE_CLK(aon_syst_rtc_eb, "aon-syst-rtc-eb", "aon-apb", 0x10,
967 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
968static SPRD_SC_GATE_CLK(ap_syst_rtc_eb, "ap-syst-rtc-eb", "aon-apb", 0x10,
969 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
970static SPRD_SC_GATE_CLK(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", "aon-apb", 0x10,
971 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
972static SPRD_SC_GATE_CLK(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", "aon-apb", 0x10,
973 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
974static SPRD_SC_GATE_CLK(eic_rtc_eb, "eic-rtc-eb", "aon-apb", 0x10,
975 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
976static SPRD_SC_GATE_CLK(eic_rtcdv5_eb, "eic-rtcdv5-eb", "aon-apb", 0x10,
977 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
978static SPRD_SC_GATE_CLK(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", "aon-apb", 0x10,
979 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
980static SPRD_SC_GATE_CLK(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", "aon-apb", 0x10,
981 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
982static SPRD_SC_GATE_CLK(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", "aon-apb", 0x10,
983 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
984static SPRD_SC_GATE_CLK(dcxo_tmr_rtc_eb, "dcxo-tmr-rtc-eb", "aon-apb", 0x10,
985 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
986static SPRD_SC_GATE_CLK(bb_cal_rtc_eb, "bb-cal-rtc-eb", "aon-apb", 0x10,
987 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
988static SPRD_SC_GATE_CLK(avs_big_rtc_eb, "avs-big-rtc-eb", "aon-apb", 0x10,
989 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
990static SPRD_SC_GATE_CLK(avs_lit_rtc_eb, "avs-lit-rtc-eb", "aon-apb", 0x10,
991 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
992static SPRD_SC_GATE_CLK(avs_gpu0_rtc_eb, "avs-gpu0-rtc-eb", "aon-apb", 0x10,
993 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
994static SPRD_SC_GATE_CLK(avs_gpu1_rtc_eb, "avs-gpu1-rtc-eb", "aon-apb", 0x10,
995 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
996static SPRD_SC_GATE_CLK(gpu_ts_eb, "gpu-ts-eb", "aon-apb", 0x10,
997 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
998static SPRD_SC_GATE_CLK(rtcdv10_eb, "rtcdv10-eb", "aon-apb", 0x10,
999 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
Chunyan Zhanga6ae1a22017-12-07 20:57:13 +0800[diff] [blame]1000
1001static struct sprd_clk_common *sc9860_aon_gate[] = {
1002 /* address base is 0x402e0000 */
1003 &avs_lit_eb.common,
1004 &avs_big_eb.common,
1005 &ap_intc5_eb.common,
1006 &gpio_eb.common,
1007 &pwm0_eb.common,
1008 &pwm1_eb.common,
1009 &pwm2_eb.common,
1010 &pwm3_eb.common,
1011 &kpd_eb.common,
1012 &aon_sys_eb.common,
1013 &ap_sys_eb.common,
1014 &aon_tmr_eb.common,
1015 &ap_tmr0_eb.common,
1016 &efuse_eb.common,
1017 &eic_eb.common,
1018 &pub1_reg_eb.common,
1019 &adi_eb.common,
1020 &ap_intc0_eb.common,
1021 &ap_intc1_eb.common,
1022 &ap_intc2_eb.common,
1023 &ap_intc3_eb.common,
1024 &ap_intc4_eb.common,
1025 &splk_eb.common,
1026 &mspi_eb.common,
1027 &pub0_reg_eb.common,
1028 &pin_eb.common,
1029 &aon_ckg_eb.common,
1030 &gpu_eb.common,
1031 &apcpu_ts0_eb.common,
1032 &apcpu_ts1_eb.common,
1033 &dap_eb.common,
1034 &i2c_eb.common,
1035 &pmu_eb.common,
1036 &thm_eb.common,
1037 &aux0_eb.common,
1038 &aux1_eb.common,
1039 &aux2_eb.common,
1040 &probe_eb.common,
1041 &gpu0_avs_eb.common,
1042 &gpu1_avs_eb.common,
1043 &apcpu_wdg_eb.common,
1044 &ap_tmr1_eb.common,
1045 &ap_tmr2_eb.common,
1046 &disp_emc_eb.common,
1047 &zip_emc_eb.common,
1048 &gsp_emc_eb.common,
1049 &osc_aon_eb.common,
1050 &lvds_trx_eb.common,
1051 &lvds_tcxo_eb.common,
1052 &mdar_eb.common,
1053 &rtc4m0_cal_eb.common,
1054 &rct100m_cal_eb.common,
1055 &djtag_eb.common,
1056 &mbox_eb.common,
1057 &aon_dma_eb.common,
1058 &dbg_emc_eb.common,
1059 &lvds_pll_div_en.common,
1060 &def_eb.common,
1061 &aon_apb_rsv0.common,
1062 &orp_jtag_eb.common,
1063 &vsp_eb.common,
1064 &cam_eb.common,
1065 &disp_eb.common,
1066 &dbg_axi_if_eb.common,
1067 &sdio0_2x_en.common,
1068 &sdio1_2x_en.common,
1069 &sdio2_2x_en.common,
1070 &emmc_2x_en.common,
Chunyan Zhangb3316a62018-02-09 17:55:09 +0800[diff] [blame]1071 &arch_rtc_eb.common,
1072 &kpb_rtc_eb.common,
1073 &aon_syst_rtc_eb.common,
1074 &ap_syst_rtc_eb.common,
1075 &aon_tmr_rtc_eb.common,
1076 &ap_tmr0_rtc_eb.common,
1077 &eic_rtc_eb.common,
1078 &eic_rtcdv5_eb.common,
1079 &ap_wdg_rtc_eb.common,
1080 &ap_tmr1_rtc_eb.common,
1081 &ap_tmr2_rtc_eb.common,
1082 &dcxo_tmr_rtc_eb.common,
1083 &bb_cal_rtc_eb.common,
1084 &avs_big_rtc_eb.common,
1085 &avs_lit_rtc_eb.common,
1086 &avs_gpu0_rtc_eb.common,
1087 &avs_gpu1_rtc_eb.common,
1088 &gpu_ts_eb.common,
1089 &rtcdv10_eb.common,
Chunyan Zhanga6ae1a22017-12-07 20:57:13 +0800[diff] [blame]1090};
1091
1092static struct clk_hw_onecell_data sc9860_aon_gate_hws = {
1093 .hws = {
1094 [CLK_AVS_LIT_EB] = &avs_lit_eb.common.hw,
1095 [CLK_AVS_BIG_EB] = &avs_big_eb.common.hw,
1096 [CLK_AP_INTC5_EB] = &ap_intc5_eb.common.hw,
1097 [CLK_GPIO_EB] = &gpio_eb.common.hw,
1098 [CLK_PWM0_EB] = &pwm0_eb.common.hw,
1099 [CLK_PWM1_EB] = &pwm1_eb.common.hw,
1100 [CLK_PWM2_EB] = &pwm2_eb.common.hw,
1101 [CLK_PWM3_EB] = &pwm3_eb.common.hw,
1102 [CLK_KPD_EB] = &kpd_eb.common.hw,
1103 [CLK_AON_SYS_EB] = &aon_sys_eb.common.hw,
1104 [CLK_AP_SYS_EB] = &ap_sys_eb.common.hw,
1105 [CLK_AON_TMR_EB] = &aon_tmr_eb.common.hw,
1106 [CLK_AP_TMR0_EB] = &ap_tmr0_eb.common.hw,
1107 [CLK_EFUSE_EB] = &efuse_eb.common.hw,
1108 [CLK_EIC_EB] = &eic_eb.common.hw,
1109 [CLK_PUB1_REG_EB] = &pub1_reg_eb.common.hw,
1110 [CLK_ADI_EB] = &adi_eb.common.hw,
1111 [CLK_AP_INTC0_EB] = &ap_intc0_eb.common.hw,
1112 [CLK_AP_INTC1_EB] = &ap_intc1_eb.common.hw,
1113 [CLK_AP_INTC2_EB] = &ap_intc2_eb.common.hw,
1114 [CLK_AP_INTC3_EB] = &ap_intc3_eb.common.hw,
1115 [CLK_AP_INTC4_EB] = &ap_intc4_eb.common.hw,
1116 [CLK_SPLK_EB] = &splk_eb.common.hw,
1117 [CLK_MSPI_EB] = &mspi_eb.common.hw,
1118 [CLK_PUB0_REG_EB] = &pub0_reg_eb.common.hw,
1119 [CLK_PIN_EB] = &pin_eb.common.hw,
1120 [CLK_AON_CKG_EB] = &aon_ckg_eb.common.hw,
1121 [CLK_GPU_EB] = &gpu_eb.common.hw,
1122 [CLK_APCPU_TS0_EB] = &apcpu_ts0_eb.common.hw,
1123 [CLK_APCPU_TS1_EB] = &apcpu_ts1_eb.common.hw,
1124 [CLK_DAP_EB] = &dap_eb.common.hw,
1125 [CLK_I2C_EB] = &i2c_eb.common.hw,
1126 [CLK_PMU_EB] = &pmu_eb.common.hw,
1127 [CLK_THM_EB] = &thm_eb.common.hw,
1128 [CLK_AUX0_EB] = &aux0_eb.common.hw,
1129 [CLK_AUX1_EB] = &aux1_eb.common.hw,
1130 [CLK_AUX2_EB] = &aux2_eb.common.hw,
1131 [CLK_PROBE_EB] = &probe_eb.common.hw,
1132 [CLK_GPU0_AVS_EB] = &gpu0_avs_eb.common.hw,
1133 [CLK_GPU1_AVS_EB] = &gpu1_avs_eb.common.hw,
1134 [CLK_APCPU_WDG_EB] = &apcpu_wdg_eb.common.hw,
1135 [CLK_AP_TMR1_EB] = &ap_tmr1_eb.common.hw,
1136 [CLK_AP_TMR2_EB] = &ap_tmr2_eb.common.hw,
1137 [CLK_DISP_EMC_EB] = &disp_emc_eb.common.hw,
1138 [CLK_ZIP_EMC_EB] = &zip_emc_eb.common.hw,
1139 [CLK_GSP_EMC_EB] = &gsp_emc_eb.common.hw,
1140 [CLK_OSC_AON_EB] = &osc_aon_eb.common.hw,
1141 [CLK_LVDS_TRX_EB] = &lvds_trx_eb.common.hw,
1142 [CLK_LVDS_TCXO_EB] = &lvds_tcxo_eb.common.hw,
1143 [CLK_MDAR_EB] = &mdar_eb.common.hw,
1144 [CLK_RTC4M0_CAL_EB] = &rtc4m0_cal_eb.common.hw,
1145 [CLK_RCT100M_CAL_EB] = &rct100m_cal_eb.common.hw,
1146 [CLK_DJTAG_EB] = &djtag_eb.common.hw,
1147 [CLK_MBOX_EB] = &mbox_eb.common.hw,
1148 [CLK_AON_DMA_EB] = &aon_dma_eb.common.hw,
1149 [CLK_DBG_EMC_EB] = &dbg_emc_eb.common.hw,
1150 [CLK_LVDS_PLL_DIV_EN] = &lvds_pll_div_en.common.hw,
1151 [CLK_DEF_EB] = &def_eb.common.hw,
1152 [CLK_AON_APB_RSV0] = &aon_apb_rsv0.common.hw,
1153 [CLK_ORP_JTAG_EB] = &orp_jtag_eb.common.hw,
1154 [CLK_VSP_EB] = &vsp_eb.common.hw,
1155 [CLK_CAM_EB] = &cam_eb.common.hw,
1156 [CLK_DISP_EB] = &disp_eb.common.hw,
1157 [CLK_DBG_AXI_IF_EB] = &dbg_axi_if_eb.common.hw,
1158 [CLK_SDIO0_2X_EN] = &sdio0_2x_en.common.hw,
1159 [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw,
1160 [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw,
1161 [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw,
Chunyan Zhangb3316a62018-02-09 17:55:09 +0800[diff] [blame]1162 [CLK_ARCH_RTC_EB] = &arch_rtc_eb.common.hw,
1163 [CLK_KPB_RTC_EB] = &kpb_rtc_eb.common.hw,
1164 [CLK_AON_SYST_RTC_EB] = &aon_syst_rtc_eb.common.hw,
1165 [CLK_AP_SYST_RTC_EB] = &ap_syst_rtc_eb.common.hw,
1166 [CLK_AON_TMR_RTC_EB] = &aon_tmr_rtc_eb.common.hw,
1167 [CLK_AP_TMR0_RTC_EB] = &ap_tmr0_rtc_eb.common.hw,
1168 [CLK_EIC_RTC_EB] = &eic_rtc_eb.common.hw,
1169 [CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw,
1170 [CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw,
1171 [CLK_AP_TMR1_RTC_EB] = &ap_tmr1_rtc_eb.common.hw,
1172 [CLK_AP_TMR2_RTC_EB] = &ap_tmr2_rtc_eb.common.hw,
1173 [CLK_DCXO_TMR_RTC_EB] = &dcxo_tmr_rtc_eb.common.hw,
1174 [CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw,
1175 [CLK_AVS_BIG_RTC_EB] = &avs_big_rtc_eb.common.hw,
1176 [CLK_AVS_LIT_RTC_EB] = &avs_lit_rtc_eb.common.hw,
1177 [CLK_AVS_GPU0_RTC_EB] = &avs_gpu0_rtc_eb.common.hw,
1178 [CLK_AVS_GPU1_RTC_EB] = &avs_gpu1_rtc_eb.common.hw,
1179 [CLK_GPU_TS_EB] = &gpu_ts_eb.common.hw,
1180 [CLK_RTCDV10_EB] = &rtcdv10_eb.common.hw,
Chunyan Zhanga6ae1a22017-12-07 20:57:13 +0800[diff] [blame]1181 },
1182 .num = CLK_AON_GATE_NUM,
1183};
1184
1185static const struct sprd_clk_desc sc9860_aon_gate_desc = {
1186 .clk_clks = sc9860_aon_gate,
1187 .num_clk_clks = ARRAY_SIZE(sc9860_aon_gate),
1188 .hw_clks = &sc9860_aon_gate_hws,
1189};
1190
1191static const u8 mcu_table[] = { 0, 1, 2, 3, 4, 8 };
1192static const char * const lit_mcu_parents[] = { "ext-26m", "twpll-512m",
1193 "twpll-768m", "ltepll0",
1194 "twpll", "mpll0" };
1195static SPRD_COMP_CLK_TABLE(lit_mcu, "lit-mcu", lit_mcu_parents, 0x20,
1196 mcu_table, 0, 4, 4, 3, 0);
1197
1198static const char * const big_mcu_parents[] = { "ext-26m", "twpll-512m",
1199 "twpll-768m", "ltepll0",
1200 "twpll", "mpll1" };
1201static SPRD_COMP_CLK_TABLE(big_mcu, "big-mcu", big_mcu_parents, 0x24,
1202 mcu_table, 0, 4, 4, 3, 0);
1203
1204static struct sprd_clk_common *sc9860_aonsecure_clk[] = {
1205 /* address base is 0x40880000 */
1206 &lit_mcu.common,
1207 &big_mcu.common,
1208};
1209
1210static struct clk_hw_onecell_data sc9860_aonsecure_clk_hws = {
1211 .hws = {
1212 [CLK_LIT_MCU] = &lit_mcu.common.hw,
1213 [CLK_BIG_MCU] = &big_mcu.common.hw,
1214 },
1215 .num = CLK_AONSECURE_NUM,
1216};
1217
1218static const struct sprd_clk_desc sc9860_aonsecure_clk_desc = {
1219 .clk_clks = sc9860_aonsecure_clk,
1220 .num_clk_clks = ARRAY_SIZE(sc9860_aonsecure_clk),
1221 .hw_clks = &sc9860_aonsecure_clk_hws,
1222};
1223
1224static SPRD_SC_GATE_CLK(agcp_iis0_eb, "agcp-iis0-eb", "aon-apb",
1225 0x0, 0x100, BIT(0), 0, 0);
1226static SPRD_SC_GATE_CLK(agcp_iis1_eb, "agcp-iis1-eb", "aon-apb",
1227 0x0, 0x100, BIT(1), 0, 0);
1228static SPRD_SC_GATE_CLK(agcp_iis2_eb, "agcp-iis2-eb", "aon-apb",
1229 0x0, 0x100, BIT(2), 0, 0);
1230static SPRD_SC_GATE_CLK(agcp_iis3_eb, "agcp-iis3-eb", "aon-apb",
1231 0x0, 0x100, BIT(3), 0, 0);
1232static SPRD_SC_GATE_CLK(agcp_uart_eb, "agcp-uart-eb", "aon-apb",
1233 0x0, 0x100, BIT(4), 0, 0);
1234static SPRD_SC_GATE_CLK(agcp_dmacp_eb, "agcp-dmacp-eb", "aon-apb",
1235 0x0, 0x100, BIT(5), 0, 0);
1236static SPRD_SC_GATE_CLK(agcp_dmaap_eb, "agcp-dmaap-eb", "aon-apb",
1237 0x0, 0x100, BIT(6), 0, 0);
1238static SPRD_SC_GATE_CLK(agcp_arc48k_eb, "agcp-arc48k-eb", "aon-apb",
1239 0x0, 0x100, BIT(10), 0, 0);
1240static SPRD_SC_GATE_CLK(agcp_src44p1k_eb, "agcp-src44p1k-eb", "aon-apb",
1241 0x0, 0x100, BIT(11), 0, 0);
1242static SPRD_SC_GATE_CLK(agcp_mcdt_eb, "agcp-mcdt-eb", "aon-apb",
1243 0x0, 0x100, BIT(12), 0, 0);
1244static SPRD_SC_GATE_CLK(agcp_vbcifd_eb, "agcp-vbcifd-eb", "aon-apb",
1245 0x0, 0x100, BIT(13), 0, 0);
1246static SPRD_SC_GATE_CLK(agcp_vbc_eb, "agcp-vbc-eb", "aon-apb",
1247 0x0, 0x100, BIT(14), 0, 0);
1248static SPRD_SC_GATE_CLK(agcp_spinlock_eb, "agcp-spinlock-eb", "aon-apb",
1249 0x0, 0x100, BIT(15), 0, 0);
1250static SPRD_SC_GATE_CLK(agcp_icu_eb, "agcp-icu-eb", "aon-apb",
1251 0x0, 0x100, BIT(16), CLK_IGNORE_UNUSED, 0);
1252static SPRD_SC_GATE_CLK(agcp_ap_ashb_eb, "agcp-ap-ashb-eb", "aon-apb",
1253 0x0, 0x100, BIT(17), 0, 0);
1254static SPRD_SC_GATE_CLK(agcp_cp_ashb_eb, "agcp-cp-ashb-eb", "aon-apb",
1255 0x0, 0x100, BIT(18), 0, 0);
1256static SPRD_SC_GATE_CLK(agcp_aud_eb, "agcp-aud-eb", "aon-apb",
1257 0x0, 0x100, BIT(19), 0, 0);
1258static SPRD_SC_GATE_CLK(agcp_audif_eb, "agcp-audif-eb", "aon-apb",
1259 0x0, 0x100, BIT(20), 0, 0);
1260
1261static struct sprd_clk_common *sc9860_agcp_gate[] = {
1262 /* address base is 0x415e0000 */
1263 &agcp_iis0_eb.common,
1264 &agcp_iis1_eb.common,
1265 &agcp_iis2_eb.common,
1266 &agcp_iis3_eb.common,
1267 &agcp_uart_eb.common,
1268 &agcp_dmacp_eb.common,
1269 &agcp_dmaap_eb.common,
1270 &agcp_arc48k_eb.common,
1271 &agcp_src44p1k_eb.common,
1272 &agcp_mcdt_eb.common,
1273 &agcp_vbcifd_eb.common,
1274 &agcp_vbc_eb.common,
1275 &agcp_spinlock_eb.common,
1276 &agcp_icu_eb.common,
1277 &agcp_ap_ashb_eb.common,
1278 &agcp_cp_ashb_eb.common,
1279 &agcp_aud_eb.common,
1280 &agcp_audif_eb.common,
1281};
1282
1283static struct clk_hw_onecell_data sc9860_agcp_gate_hws = {
1284 .hws = {
1285 [CLK_AGCP_IIS0_EB] = &agcp_iis0_eb.common.hw,
1286 [CLK_AGCP_IIS1_EB] = &agcp_iis1_eb.common.hw,
1287 [CLK_AGCP_IIS2_EB] = &agcp_iis2_eb.common.hw,
1288 [CLK_AGCP_IIS3_EB] = &agcp_iis3_eb.common.hw,
1289 [CLK_AGCP_UART_EB] = &agcp_uart_eb.common.hw,
1290 [CLK_AGCP_DMACP_EB] = &agcp_dmacp_eb.common.hw,
1291 [CLK_AGCP_DMAAP_EB] = &agcp_dmaap_eb.common.hw,
1292 [CLK_AGCP_ARC48K_EB] = &agcp_arc48k_eb.common.hw,
1293 [CLK_AGCP_SRC44P1K_EB] = &agcp_src44p1k_eb.common.hw,
1294 [CLK_AGCP_MCDT_EB] = &agcp_mcdt_eb.common.hw,
1295 [CLK_AGCP_VBCIFD_EB] = &agcp_vbcifd_eb.common.hw,
1296 [CLK_AGCP_VBC_EB] = &agcp_vbc_eb.common.hw,
1297 [CLK_AGCP_SPINLOCK_EB] = &agcp_spinlock_eb.common.hw,
1298 [CLK_AGCP_ICU_EB] = &agcp_icu_eb.common.hw,
1299 [CLK_AGCP_AP_ASHB_EB] = &agcp_ap_ashb_eb.common.hw,
1300 [CLK_AGCP_CP_ASHB_EB] = &agcp_cp_ashb_eb.common.hw,
1301 [CLK_AGCP_AUD_EB] = &agcp_aud_eb.common.hw,
1302 [CLK_AGCP_AUDIF_EB] = &agcp_audif_eb.common.hw,
1303 },
1304 .num = CLK_AGCP_GATE_NUM,
1305};
1306
1307static const struct sprd_clk_desc sc9860_agcp_gate_desc = {
1308 .clk_clks = sc9860_agcp_gate,
1309 .num_clk_clks = ARRAY_SIZE(sc9860_agcp_gate),
1310 .hw_clks = &sc9860_agcp_gate_hws,
1311};
1312
1313static const char * const gpu_parents[] = { "twpll-512m",
1314 "twpll-768m",
1315 "gpll" };
1316static SPRD_COMP_CLK(gpu_clk, "gpu", gpu_parents, 0x20,
1317 0, 2, 8, 4, 0);
1318
1319static struct sprd_clk_common *sc9860_gpu_clk[] = {
1320 /* address base is 0x60200000 */
1321 &gpu_clk.common,
1322};
1323
1324static struct clk_hw_onecell_data sc9860_gpu_clk_hws = {
1325 .hws = {
1326 [CLK_GPU] = &gpu_clk.common.hw,
1327 },
1328 .num = CLK_GPU_NUM,
1329};
1330
1331static const struct sprd_clk_desc sc9860_gpu_clk_desc = {
1332 .clk_clks = sc9860_gpu_clk,
1333 .num_clk_clks = ARRAY_SIZE(sc9860_gpu_clk),
1334 .hw_clks = &sc9860_gpu_clk_hws,
1335};
1336
1337static const char * const ahb_parents[] = { "ext-26m", "twpll-96m",
1338 "twpll-128m", "twpll-153m6" };
1339static SPRD_MUX_CLK(ahb_vsp, "ahb-vsp", ahb_parents, 0x20,
1340 0, 2, SC9860_MUX_FLAG);
1341
1342static const char * const vsp_parents[] = { "twpll-76m8", "twpll-128m",
1343 "twpll-256m", "twpll-307m2",
1344 "twpll-384m" };
1345static SPRD_COMP_CLK(vsp_clk, "vsp", vsp_parents, 0x24, 0, 3, 8, 2, 0);
1346
1347static const char * const dispc_parents[] = { "twpll-76m8", "twpll-128m",
1348 "twpll-256m", "twpll-307m2" };
1349static SPRD_COMP_CLK(vsp_enc, "vsp-enc", dispc_parents, 0x28, 0, 2, 8, 2, 0);
1350
1351static const char * const vpp_parents[] = { "twpll-96m", "twpll-153m6",
1352 "twpll-192m", "twpll-256m" };
1353static SPRD_MUX_CLK(vpp_clk, "vpp", vpp_parents, 0x2c,
1354 0, 2, SC9860_MUX_FLAG);
1355static const char * const vsp_26m_parents[] = { "ext-26m" };
1356static SPRD_MUX_CLK(vsp_26m, "vsp-26m", vsp_26m_parents, 0x30,
1357 0, 1, SC9860_MUX_FLAG);
1358
1359static struct sprd_clk_common *sc9860_vsp_clk[] = {
1360 /* address base is 0x61000000 */
1361 &ahb_vsp.common,
1362 &vsp_clk.common,
1363 &vsp_enc.common,
1364 &vpp_clk.common,
1365 &vsp_26m.common,
1366};
1367
1368static struct clk_hw_onecell_data sc9860_vsp_clk_hws = {
1369 .hws = {
1370 [CLK_AHB_VSP] = &ahb_vsp.common.hw,
1371 [CLK_VSP] = &vsp_clk.common.hw,
1372 [CLK_VSP_ENC] = &vsp_enc.common.hw,
1373 [CLK_VPP] = &vpp_clk.common.hw,
1374 [CLK_VSP_26M] = &vsp_26m.common.hw,
1375 },
1376 .num = CLK_VSP_NUM,
1377};
1378
1379static const struct sprd_clk_desc sc9860_vsp_clk_desc = {
1380 .clk_clks = sc9860_vsp_clk,
1381 .num_clk_clks = ARRAY_SIZE(sc9860_vsp_clk),
1382 .hw_clks = &sc9860_vsp_clk_hws,
1383};
1384
1385static SPRD_SC_GATE_CLK(vsp_dec_eb, "vsp-dec-eb", "ahb-vsp", 0x0,
1386 0x1000, BIT(0), 0, 0);
1387static SPRD_SC_GATE_CLK(vsp_ckg_eb, "vsp-ckg-eb", "ahb-vsp", 0x0,
1388 0x1000, BIT(1), 0, 0);
1389static SPRD_SC_GATE_CLK(vsp_mmu_eb, "vsp-mmu-eb", "ahb-vsp", 0x0,
1390 0x1000, BIT(2), 0, 0);
1391static SPRD_SC_GATE_CLK(vsp_enc_eb, "vsp-enc-eb", "ahb-vsp", 0x0,
1392 0x1000, BIT(3), 0, 0);
1393static SPRD_SC_GATE_CLK(vpp_eb, "vpp-eb", "ahb-vsp", 0x0,
1394 0x1000, BIT(4), 0, 0);
1395static SPRD_SC_GATE_CLK(vsp_26m_eb, "vsp-26m-eb", "ahb-vsp", 0x0,
1396 0x1000, BIT(5), 0, 0);
1397static SPRD_GATE_CLK(vsp_axi_gate, "vsp-axi-gate", "ahb-vsp", 0x8,
1398 BIT(0), 0, 0);
1399static SPRD_GATE_CLK(vsp_enc_gate, "vsp-enc-gate", "ahb-vsp", 0x8,
1400 BIT(1), 0, 0);
1401static SPRD_GATE_CLK(vpp_axi_gate, "vpp-axi-gate", "ahb-vsp", 0x8,
1402 BIT(2), 0, 0);
1403static SPRD_GATE_CLK(vsp_bm_gate, "vsp-bm-gate", "ahb-vsp", 0x8,
1404 BIT(8), 0, 0);
1405static SPRD_GATE_CLK(vsp_enc_bm_gate, "vsp-enc-bm-gate", "ahb-vsp", 0x8,
1406 BIT(9), 0, 0);
1407static SPRD_GATE_CLK(vpp_bm_gate, "vpp-bm-gate", "ahb-vsp", 0x8,
1408 BIT(10), 0, 0);
1409
1410static struct sprd_clk_common *sc9860_vsp_gate[] = {
1411 /* address base is 0x61100000 */
1412 &vsp_dec_eb.common,
1413 &vsp_ckg_eb.common,
1414 &vsp_mmu_eb.common,
1415 &vsp_enc_eb.common,
1416 &vpp_eb.common,
1417 &vsp_26m_eb.common,
1418 &vsp_axi_gate.common,
1419 &vsp_enc_gate.common,
1420 &vpp_axi_gate.common,
1421 &vsp_bm_gate.common,
1422 &vsp_enc_bm_gate.common,
1423 &vpp_bm_gate.common,
1424};
1425
1426static struct clk_hw_onecell_data sc9860_vsp_gate_hws = {
1427 .hws = {
1428 [CLK_VSP_DEC_EB] = &vsp_dec_eb.common.hw,
1429 [CLK_VSP_CKG_EB] = &vsp_ckg_eb.common.hw,
1430 [CLK_VSP_MMU_EB] = &vsp_mmu_eb.common.hw,
1431 [CLK_VSP_ENC_EB] = &vsp_enc_eb.common.hw,
1432 [CLK_VPP_EB] = &vpp_eb.common.hw,
1433 [CLK_VSP_26M_EB] = &vsp_26m_eb.common.hw,
1434 [CLK_VSP_AXI_GATE] = &vsp_axi_gate.common.hw,
1435 [CLK_VSP_ENC_GATE] = &vsp_enc_gate.common.hw,
1436 [CLK_VPP_AXI_GATE] = &vpp_axi_gate.common.hw,
1437 [CLK_VSP_BM_GATE] = &vsp_bm_gate.common.hw,
1438 [CLK_VSP_ENC_BM_GATE] = &vsp_enc_bm_gate.common.hw,
1439 [CLK_VPP_BM_GATE] = &vpp_bm_gate.common.hw,
1440 },
1441 .num = CLK_VSP_GATE_NUM,
1442};
1443
1444static const struct sprd_clk_desc sc9860_vsp_gate_desc = {
1445 .clk_clks = sc9860_vsp_gate,
1446 .num_clk_clks = ARRAY_SIZE(sc9860_vsp_gate),
1447 .hw_clks = &sc9860_vsp_gate_hws,
1448};
1449
1450static SPRD_MUX_CLK(ahb_cam, "ahb-cam", ahb_parents, 0x20,
1451 0, 2, SC9860_MUX_FLAG);
1452static const char * const sensor_parents[] = { "ext-26m", "twpll-48m",
1453 "twpll-76m8", "twpll-96m" };
1454static SPRD_COMP_CLK(sensor0_clk, "sensor0", sensor_parents, 0x24,
1455 0, 2, 8, 3, 0);
1456static SPRD_COMP_CLK(sensor1_clk, "sensor1", sensor_parents, 0x28,
1457 0, 2, 8, 3, 0);
1458static SPRD_COMP_CLK(sensor2_clk, "sensor2", sensor_parents, 0x2c,
1459 0, 2, 8, 3, 0);
1460static SPRD_GATE_CLK(mipi_csi0_eb, "mipi-csi0-eb", "ahb-cam", 0x4c,
1461 BIT(16), 0, 0);
1462static SPRD_GATE_CLK(mipi_csi1_eb, "mipi-csi1-eb", "ahb-cam", 0x50,
1463 BIT(16), 0, 0);
1464
1465static struct sprd_clk_common *sc9860_cam_clk[] = {
1466 /* address base is 0x62000000 */
1467 &ahb_cam.common,
1468 &sensor0_clk.common,
1469 &sensor1_clk.common,
1470 &sensor2_clk.common,
1471 &mipi_csi0_eb.common,
1472 &mipi_csi1_eb.common,
1473};
1474
1475static struct clk_hw_onecell_data sc9860_cam_clk_hws = {
1476 .hws = {
1477 [CLK_AHB_CAM] = &ahb_cam.common.hw,
1478 [CLK_SENSOR0] = &sensor0_clk.common.hw,
1479 [CLK_SENSOR1] = &sensor1_clk.common.hw,
1480 [CLK_SENSOR2] = &sensor2_clk.common.hw,
1481 [CLK_MIPI_CSI0_EB] = &mipi_csi0_eb.common.hw,
1482 [CLK_MIPI_CSI1_EB] = &mipi_csi1_eb.common.hw,
1483 },
1484 .num = CLK_CAM_NUM,
1485};
1486
1487static const struct sprd_clk_desc sc9860_cam_clk_desc = {
1488 .clk_clks = sc9860_cam_clk,
1489 .num_clk_clks = ARRAY_SIZE(sc9860_cam_clk),
1490 .hw_clks = &sc9860_cam_clk_hws,
1491};
1492
1493static SPRD_SC_GATE_CLK(dcam0_eb, "dcam0-eb", "ahb-cam", 0x0,
1494 0x1000, BIT(0), 0, 0);
1495static SPRD_SC_GATE_CLK(dcam1_eb, "dcam1-eb", "ahb-cam", 0x0,
1496 0x1000, BIT(1), 0, 0);
1497static SPRD_SC_GATE_CLK(isp0_eb, "isp0-eb", "ahb-cam", 0x0,
1498 0x1000, BIT(2), 0, 0);
1499static SPRD_SC_GATE_CLK(csi0_eb, "csi0-eb", "ahb-cam", 0x0,
1500 0x1000, BIT(3), 0, 0);
1501static SPRD_SC_GATE_CLK(csi1_eb, "csi1-eb", "ahb-cam", 0x0,
1502 0x1000, BIT(4), 0, 0);
1503static SPRD_SC_GATE_CLK(jpg0_eb, "jpg0-eb", "ahb-cam", 0x0,
1504 0x1000, BIT(5), 0, 0);
1505static SPRD_SC_GATE_CLK(jpg1_eb, "jpg1-eb", "ahb-cam", 0x0,
1506 0x1000, BIT(6), 0, 0);
1507static SPRD_SC_GATE_CLK(cam_ckg_eb, "cam-ckg-eb", "ahb-cam", 0x0,
1508 0x1000, BIT(7), 0, 0);
1509static SPRD_SC_GATE_CLK(cam_mmu_eb, "cam-mmu-eb", "ahb-cam", 0x0,
1510 0x1000, BIT(8), 0, 0);
1511static SPRD_SC_GATE_CLK(isp1_eb, "isp1-eb", "ahb-cam", 0x0,
1512 0x1000, BIT(9), 0, 0);
1513static SPRD_SC_GATE_CLK(cpp_eb, "cpp-eb", "ahb-cam", 0x0,
1514 0x1000, BIT(10), 0, 0);
1515static SPRD_SC_GATE_CLK(mmu_pf_eb, "mmu-pf-eb", "ahb-cam", 0x0,
1516 0x1000, BIT(11), 0, 0);
1517static SPRD_SC_GATE_CLK(isp2_eb, "isp2-eb", "ahb-cam", 0x0,
1518 0x1000, BIT(12), 0, 0);
1519static SPRD_SC_GATE_CLK(dcam2isp_if_eb, "dcam2isp-if-eb", "ahb-cam", 0x0,
1520 0x1000, BIT(13), 0, 0);
1521static SPRD_SC_GATE_CLK(isp2dcam_if_eb, "isp2dcam-if-eb", "ahb-cam", 0x0,
1522 0x1000, BIT(14), 0, 0);
1523static SPRD_SC_GATE_CLK(isp_lclk_eb, "isp-lclk-eb", "ahb-cam", 0x0,
1524 0x1000, BIT(15), 0, 0);
1525static SPRD_SC_GATE_CLK(isp_iclk_eb, "isp-iclk-eb", "ahb-cam", 0x0,
1526 0x1000, BIT(16), 0, 0);
1527static SPRD_SC_GATE_CLK(isp_mclk_eb, "isp-mclk-eb", "ahb-cam", 0x0,
1528 0x1000, BIT(17), 0, 0);
1529static SPRD_SC_GATE_CLK(isp_pclk_eb, "isp-pclk-eb", "ahb-cam", 0x0,
1530 0x1000, BIT(18), 0, 0);
1531static SPRD_SC_GATE_CLK(isp_isp2dcam_eb, "isp-isp2dcam-eb", "ahb-cam", 0x0,
1532 0x1000, BIT(19), 0, 0);
1533static SPRD_SC_GATE_CLK(dcam0_if_eb, "dcam0-if-eb", "ahb-cam", 0x0,
1534 0x1000, BIT(20), 0, 0);
1535static SPRD_SC_GATE_CLK(clk26m_if_eb, "clk26m-if-eb", "ahb-cam", 0x0,
1536 0x1000, BIT(21), 0, 0);
1537static SPRD_GATE_CLK(cphy0_gate, "cphy0-gate", "ahb-cam", 0x8,
1538 BIT(0), 0, 0);
1539static SPRD_GATE_CLK(mipi_csi0_gate, "mipi-csi0-gate", "ahb-cam", 0x8,
1540 BIT(1), 0, 0);
1541static SPRD_GATE_CLK(cphy1_gate, "cphy1-gate", "ahb-cam", 0x8,
1542 BIT(2), 0, 0);
1543static SPRD_GATE_CLK(mipi_csi1, "mipi-csi1", "ahb-cam", 0x8,
1544 BIT(3), 0, 0);
1545static SPRD_GATE_CLK(dcam0_axi_gate, "dcam0-axi-gate", "ahb-cam", 0x8,
1546 BIT(4), 0, 0);
1547static SPRD_GATE_CLK(dcam1_axi_gate, "dcam1-axi-gate", "ahb-cam", 0x8,
1548 BIT(5), 0, 0);
1549static SPRD_GATE_CLK(sensor0_gate, "sensor0-gate", "ahb-cam", 0x8,
1550 BIT(6), 0, 0);
1551static SPRD_GATE_CLK(sensor1_gate, "sensor1-gate", "ahb-cam", 0x8,
1552 BIT(7), 0, 0);
1553static SPRD_GATE_CLK(jpg0_axi_gate, "jpg0-axi-gate", "ahb-cam", 0x8,
1554 BIT(8), 0, 0);
1555static SPRD_GATE_CLK(gpg1_axi_gate, "gpg1-axi-gate", "ahb-cam", 0x8,
1556 BIT(9), 0, 0);
1557static SPRD_GATE_CLK(isp0_axi_gate, "isp0-axi-gate", "ahb-cam", 0x8,
1558 BIT(10), 0, 0);
1559static SPRD_GATE_CLK(isp1_axi_gate, "isp1-axi-gate", "ahb-cam", 0x8,
1560 BIT(11), 0, 0);
1561static SPRD_GATE_CLK(isp2_axi_gate, "isp2-axi-gate", "ahb-cam", 0x8,
1562 BIT(12), 0, 0);
1563static SPRD_GATE_CLK(cpp_axi_gate, "cpp-axi-gate", "ahb-cam", 0x8,
1564 BIT(13), 0, 0);
1565static SPRD_GATE_CLK(d0_if_axi_gate, "d0-if-axi-gate", "ahb-cam", 0x8,
1566 BIT(14), 0, 0);
1567static SPRD_GATE_CLK(d2i_if_axi_gate, "d2i-if-axi-gate", "ahb-cam", 0x8,
1568 BIT(15), 0, 0);
1569static SPRD_GATE_CLK(i2d_if_axi_gate, "i2d-if-axi-gate", "ahb-cam", 0x8,
1570 BIT(16), 0, 0);
1571static SPRD_GATE_CLK(spare_axi_gate, "spare-axi-gate", "ahb-cam", 0x8,
1572 BIT(17), 0, 0);
1573static SPRD_GATE_CLK(sensor2_gate, "sensor2-gate", "ahb-cam", 0x8,
1574 BIT(18), 0, 0);
1575static SPRD_SC_GATE_CLK(d0if_in_d_en, "d0if-in-d-en", "ahb-cam", 0x28,
1576 0x1000, BIT(0), 0, 0);
1577static SPRD_SC_GATE_CLK(d1if_in_d_en, "d1if-in-d-en", "ahb-cam", 0x28,
1578 0x1000, BIT(1), 0, 0);
1579static SPRD_SC_GATE_CLK(d0if_in_d2i_en, "d0if-in-d2i-en", "ahb-cam", 0x28,
1580 0x1000, BIT(2), 0, 0);
1581static SPRD_SC_GATE_CLK(d1if_in_d2i_en, "d1if-in-d2i-en", "ahb-cam", 0x28,
1582 0x1000, BIT(3), 0, 0);
1583static SPRD_SC_GATE_CLK(ia_in_d2i_en, "ia-in-d2i-en", "ahb-cam", 0x28,
1584 0x1000, BIT(4), 0, 0);
1585static SPRD_SC_GATE_CLK(ib_in_d2i_en, "ib-in-d2i-en", "ahb-cam", 0x28,
1586 0x1000, BIT(5), 0, 0);
1587static SPRD_SC_GATE_CLK(ic_in_d2i_en, "ic-in-d2i-en", "ahb-cam", 0x28,
1588 0x1000, BIT(6), 0, 0);
1589static SPRD_SC_GATE_CLK(ia_in_i_en, "ia-in-i-en", "ahb-cam", 0x28,
1590 0x1000, BIT(7), 0, 0);
1591static SPRD_SC_GATE_CLK(ib_in_i_en, "ib-in-i-en", "ahb-cam", 0x28,
1592 0x1000, BIT(8), 0, 0);
1593static SPRD_SC_GATE_CLK(ic_in_i_en, "ic-in-i-en", "ahb-cam", 0x28,
1594 0x1000, BIT(9), 0, 0);
1595
1596static struct sprd_clk_common *sc9860_cam_gate[] = {
1597 /* address base is 0x62100000 */
1598 &dcam0_eb.common,
1599 &dcam1_eb.common,
1600 &isp0_eb.common,
1601 &csi0_eb.common,
1602 &csi1_eb.common,
1603 &jpg0_eb.common,
1604 &jpg1_eb.common,
1605 &cam_ckg_eb.common,
1606 &cam_mmu_eb.common,
1607 &isp1_eb.common,
1608 &cpp_eb.common,
1609 &mmu_pf_eb.common,
1610 &isp2_eb.common,
1611 &dcam2isp_if_eb.common,
1612 &isp2dcam_if_eb.common,
1613 &isp_lclk_eb.common,
1614 &isp_iclk_eb.common,
1615 &isp_mclk_eb.common,
1616 &isp_pclk_eb.common,
1617 &isp_isp2dcam_eb.common,
1618 &dcam0_if_eb.common,
1619 &clk26m_if_eb.common,
1620 &cphy0_gate.common,
1621 &mipi_csi0_gate.common,
1622 &cphy1_gate.common,
1623 &mipi_csi1.common,
1624 &dcam0_axi_gate.common,
1625 &dcam1_axi_gate.common,
1626 &sensor0_gate.common,
1627 &sensor1_gate.common,
1628 &jpg0_axi_gate.common,
1629 &gpg1_axi_gate.common,
1630 &isp0_axi_gate.common,
1631 &isp1_axi_gate.common,
1632 &isp2_axi_gate.common,
1633 &cpp_axi_gate.common,
1634 &d0_if_axi_gate.common,
1635 &d2i_if_axi_gate.common,
1636 &i2d_if_axi_gate.common,
1637 &spare_axi_gate.common,
1638 &sensor2_gate.common,
1639 &d0if_in_d_en.common,
1640 &d1if_in_d_en.common,
1641 &d0if_in_d2i_en.common,
1642 &d1if_in_d2i_en.common,
1643 &ia_in_d2i_en.common,
1644 &ib_in_d2i_en.common,
1645 &ic_in_d2i_en.common,
1646 &ia_in_i_en.common,
1647 &ib_in_i_en.common,
1648 &ic_in_i_en.common,
1649};
1650
1651static struct clk_hw_onecell_data sc9860_cam_gate_hws = {
1652 .hws = {
1653 [CLK_DCAM0_EB] = &dcam0_eb.common.hw,
1654 [CLK_DCAM1_EB] = &dcam1_eb.common.hw,
1655 [CLK_ISP0_EB] = &isp0_eb.common.hw,
1656 [CLK_CSI0_EB] = &csi0_eb.common.hw,
1657 [CLK_CSI1_EB] = &csi1_eb.common.hw,
1658 [CLK_JPG0_EB] = &jpg0_eb.common.hw,
1659 [CLK_JPG1_EB] = &jpg1_eb.common.hw,
1660 [CLK_CAM_CKG_EB] = &cam_ckg_eb.common.hw,
1661 [CLK_CAM_MMU_EB] = &cam_mmu_eb.common.hw,
1662 [CLK_ISP1_EB] = &isp1_eb.common.hw,
1663 [CLK_CPP_EB] = &cpp_eb.common.hw,
1664 [CLK_MMU_PF_EB] = &mmu_pf_eb.common.hw,
1665 [CLK_ISP2_EB] = &isp2_eb.common.hw,
1666 [CLK_DCAM2ISP_IF_EB] = &dcam2isp_if_eb.common.hw,
1667 [CLK_ISP2DCAM_IF_EB] = &isp2dcam_if_eb.common.hw,
1668 [CLK_ISP_LCLK_EB] = &isp_lclk_eb.common.hw,
1669 [CLK_ISP_ICLK_EB] = &isp_iclk_eb.common.hw,
1670 [CLK_ISP_MCLK_EB] = &isp_mclk_eb.common.hw,
1671 [CLK_ISP_PCLK_EB] = &isp_pclk_eb.common.hw,
1672 [CLK_ISP_ISP2DCAM_EB] = &isp_isp2dcam_eb.common.hw,
1673 [CLK_DCAM0_IF_EB] = &dcam0_if_eb.common.hw,
1674 [CLK_CLK26M_IF_EB] = &clk26m_if_eb.common.hw,
1675 [CLK_CPHY0_GATE] = &cphy0_gate.common.hw,
1676 [CLK_MIPI_CSI0_GATE] = &mipi_csi0_gate.common.hw,
1677 [CLK_CPHY1_GATE] = &cphy1_gate.common.hw,
1678 [CLK_MIPI_CSI1] = &mipi_csi1.common.hw,
1679 [CLK_DCAM0_AXI_GATE] = &dcam0_axi_gate.common.hw,
1680 [CLK_DCAM1_AXI_GATE] = &dcam1_axi_gate.common.hw,
1681 [CLK_SENSOR0_GATE] = &sensor0_gate.common.hw,
1682 [CLK_SENSOR1_GATE] = &sensor1_gate.common.hw,
1683 [CLK_JPG0_AXI_GATE] = &jpg0_axi_gate.common.hw,
1684 [CLK_GPG1_AXI_GATE] = &gpg1_axi_gate.common.hw,
1685 [CLK_ISP0_AXI_GATE] = &isp0_axi_gate.common.hw,
1686 [CLK_ISP1_AXI_GATE] = &isp1_axi_gate.common.hw,
1687 [CLK_ISP2_AXI_GATE] = &isp2_axi_gate.common.hw,
1688 [CLK_CPP_AXI_GATE] = &cpp_axi_gate.common.hw,
1689 [CLK_D0_IF_AXI_GATE] = &d0_if_axi_gate.common.hw,
1690 [CLK_D2I_IF_AXI_GATE] = &d2i_if_axi_gate.common.hw,
1691 [CLK_I2D_IF_AXI_GATE] = &i2d_if_axi_gate.common.hw,
1692 [CLK_SPARE_AXI_GATE] = &spare_axi_gate.common.hw,
1693 [CLK_SENSOR2_GATE] = &sensor2_gate.common.hw,
1694 [CLK_D0IF_IN_D_EN] = &d0if_in_d_en.common.hw,
1695 [CLK_D1IF_IN_D_EN] = &d1if_in_d_en.common.hw,
1696 [CLK_D0IF_IN_D2I_EN] = &d0if_in_d2i_en.common.hw,
1697 [CLK_D1IF_IN_D2I_EN] = &d1if_in_d2i_en.common.hw,
1698 [CLK_IA_IN_D2I_EN] = &ia_in_d2i_en.common.hw,
1699 [CLK_IB_IN_D2I_EN] = &ib_in_d2i_en.common.hw,
1700 [CLK_IC_IN_D2I_EN] = &ic_in_d2i_en.common.hw,
1701 [CLK_IA_IN_I_EN] = &ia_in_i_en.common.hw,
1702 [CLK_IB_IN_I_EN] = &ib_in_i_en.common.hw,
1703 [CLK_IC_IN_I_EN] = &ic_in_i_en.common.hw,
1704 },
1705 .num = CLK_CAM_GATE_NUM,
1706};
1707
1708static const struct sprd_clk_desc sc9860_cam_gate_desc = {
1709 .clk_clks = sc9860_cam_gate,
1710 .num_clk_clks = ARRAY_SIZE(sc9860_cam_gate),
1711 .hw_clks = &sc9860_cam_gate_hws,
1712};
1713
1714static SPRD_MUX_CLK(ahb_disp, "ahb-disp", ahb_parents, 0x20,
1715 0, 2, SC9860_MUX_FLAG);
1716static SPRD_COMP_CLK(dispc0_dpi, "dispc0-dpi", dispc_parents, 0x34,
1717 0, 2, 8, 2, 0);
1718static SPRD_COMP_CLK(dispc1_dpi, "dispc1-dpi", dispc_parents, 0x40,
1719 0, 2, 8, 2, 0);
1720
1721static struct sprd_clk_common *sc9860_disp_clk[] = {
1722 /* address base is 0x63000000 */
1723 &ahb_disp.common,
1724 &dispc0_dpi.common,
1725 &dispc1_dpi.common,
1726};
1727
1728static struct clk_hw_onecell_data sc9860_disp_clk_hws = {
1729 .hws = {
1730 [CLK_AHB_DISP] = &ahb_disp.common.hw,
1731 [CLK_DISPC0_DPI] = &dispc0_dpi.common.hw,
1732 [CLK_DISPC1_DPI] = &dispc1_dpi.common.hw,
1733 },
1734 .num = CLK_DISP_NUM,
1735};
1736
1737static const struct sprd_clk_desc sc9860_disp_clk_desc = {
1738 .clk_clks = sc9860_disp_clk,
1739 .num_clk_clks = ARRAY_SIZE(sc9860_disp_clk),
1740 .hw_clks = &sc9860_disp_clk_hws,
1741};
1742
1743static SPRD_SC_GATE_CLK(dispc0_eb, "dispc0-eb", "ahb-disp", 0x0,
1744 0x1000, BIT(0), 0, 0);
1745static SPRD_SC_GATE_CLK(dispc1_eb, "dispc1-eb", "ahb-disp", 0x0,
1746 0x1000, BIT(1), 0, 0);
1747static SPRD_SC_GATE_CLK(dispc_mmu_eb, "dispc-mmu-eb", "ahb-disp", 0x0,
1748 0x1000, BIT(2), 0, 0);
1749static SPRD_SC_GATE_CLK(gsp0_eb, "gsp0-eb", "ahb-disp", 0x0,
1750 0x1000, BIT(3), 0, 0);
1751static SPRD_SC_GATE_CLK(gsp1_eb, "gsp1-eb", "ahb-disp", 0x0,
1752 0x1000, BIT(4), 0, 0);
1753static SPRD_SC_GATE_CLK(gsp0_mmu_eb, "gsp0-mmu-eb", "ahb-disp", 0x0,
1754 0x1000, BIT(5), 0, 0);
1755static SPRD_SC_GATE_CLK(gsp1_mmu_eb, "gsp1-mmu-eb", "ahb-disp", 0x0,
1756 0x1000, BIT(6), 0, 0);
1757static SPRD_SC_GATE_CLK(dsi0_eb, "dsi0-eb", "ahb-disp", 0x0,
1758 0x1000, BIT(7), 0, 0);
1759static SPRD_SC_GATE_CLK(dsi1_eb, "dsi1-eb", "ahb-disp", 0x0,
1760 0x1000, BIT(8), 0, 0);
1761static SPRD_SC_GATE_CLK(disp_ckg_eb, "disp-ckg-eb", "ahb-disp", 0x0,
1762 0x1000, BIT(9), 0, 0);
1763static SPRD_SC_GATE_CLK(disp_gpu_eb, "disp-gpu-eb", "ahb-disp", 0x0,
1764 0x1000, BIT(10), 0, 0);
1765static SPRD_SC_GATE_CLK(gpu_mtx_eb, "gpu-mtx-eb", "ahb-disp", 0x0,
1766 0x1000, BIT(13), 0, 0);
1767static SPRD_SC_GATE_CLK(gsp_mtx_eb, "gsp-mtx-eb", "ahb-disp", 0x0,
1768 0x1000, BIT(14), 0, 0);
1769static SPRD_SC_GATE_CLK(tmc_mtx_eb, "tmc-mtx-eb", "ahb-disp", 0x0,
1770 0x1000, BIT(15), 0, 0);
1771static SPRD_SC_GATE_CLK(dispc_mtx_eb, "dispc-mtx-eb", "ahb-disp", 0x0,
1772 0x1000, BIT(16), 0, 0);
1773static SPRD_GATE_CLK(dphy0_gate, "dphy0-gate", "ahb-disp", 0x8,
1774 BIT(0), 0, 0);
1775static SPRD_GATE_CLK(dphy1_gate, "dphy1-gate", "ahb-disp", 0x8,
1776 BIT(1), 0, 0);
1777static SPRD_GATE_CLK(gsp0_a_gate, "gsp0-a-gate", "ahb-disp", 0x8,
1778 BIT(2), 0, 0);
1779static SPRD_GATE_CLK(gsp1_a_gate, "gsp1-a-gate", "ahb-disp", 0x8,
1780 BIT(3), 0, 0);
1781static SPRD_GATE_CLK(gsp0_f_gate, "gsp0-f-gate", "ahb-disp", 0x8,
1782 BIT(4), 0, 0);
1783static SPRD_GATE_CLK(gsp1_f_gate, "gsp1-f-gate", "ahb-disp", 0x8,
1784 BIT(5), 0, 0);
1785static SPRD_GATE_CLK(d_mtx_f_gate, "d-mtx-f-gate", "ahb-disp", 0x8,
1786 BIT(6), 0, 0);
1787static SPRD_GATE_CLK(d_mtx_a_gate, "d-mtx-a-gate", "ahb-disp", 0x8,
1788 BIT(7), 0, 0);
1789static SPRD_GATE_CLK(d_noc_f_gate, "d-noc-f-gate", "ahb-disp", 0x8,
1790 BIT(8), 0, 0);
1791static SPRD_GATE_CLK(d_noc_a_gate, "d-noc-a-gate", "ahb-disp", 0x8,
1792 BIT(9), 0, 0);
1793static SPRD_GATE_CLK(gsp_mtx_f_gate, "gsp-mtx-f-gate", "ahb-disp", 0x8,
1794 BIT(10), 0, 0);
1795static SPRD_GATE_CLK(gsp_mtx_a_gate, "gsp-mtx-a-gate", "ahb-disp", 0x8,
1796 BIT(11), 0, 0);
1797static SPRD_GATE_CLK(gsp_noc_f_gate, "gsp-noc-f-gate", "ahb-disp", 0x8,
1798 BIT(12), 0, 0);
1799static SPRD_GATE_CLK(gsp_noc_a_gate, "gsp-noc-a-gate", "ahb-disp", 0x8,
1800 BIT(13), 0, 0);
1801static SPRD_GATE_CLK(dispm0idle_gate, "dispm0idle-gate", "ahb-disp", 0x8,
1802 BIT(14), 0, 0);
1803static SPRD_GATE_CLK(gspm0idle_gate, "gspm0idle-gate", "ahb-disp", 0x8,
1804 BIT(15), 0, 0);
1805
1806static struct sprd_clk_common *sc9860_disp_gate[] = {
1807 /* address base is 0x63100000 */
1808 &dispc0_eb.common,
1809 &dispc1_eb.common,
1810 &dispc_mmu_eb.common,
1811 &gsp0_eb.common,
1812 &gsp1_eb.common,
1813 &gsp0_mmu_eb.common,
1814 &gsp1_mmu_eb.common,
1815 &dsi0_eb.common,
1816 &dsi1_eb.common,
1817 &disp_ckg_eb.common,
1818 &disp_gpu_eb.common,
1819 &gpu_mtx_eb.common,
1820 &gsp_mtx_eb.common,
1821 &tmc_mtx_eb.common,
1822 &dispc_mtx_eb.common,
1823 &dphy0_gate.common,
1824 &dphy1_gate.common,
1825 &gsp0_a_gate.common,
1826 &gsp1_a_gate.common,
1827 &gsp0_f_gate.common,
1828 &gsp1_f_gate.common,
1829 &d_mtx_f_gate.common,
1830 &d_mtx_a_gate.common,
1831 &d_noc_f_gate.common,
1832 &d_noc_a_gate.common,
1833 &gsp_mtx_f_gate.common,
1834 &gsp_mtx_a_gate.common,
1835 &gsp_noc_f_gate.common,
1836 &gsp_noc_a_gate.common,
1837 &dispm0idle_gate.common,
1838 &gspm0idle_gate.common,
1839};
1840
1841static struct clk_hw_onecell_data sc9860_disp_gate_hws = {
1842 .hws = {
1843 [CLK_DISPC0_EB] = &dispc0_eb.common.hw,
1844 [CLK_DISPC1_EB] = &dispc1_eb.common.hw,
1845 [CLK_DISPC_MMU_EB] = &dispc_mmu_eb.common.hw,
1846 [CLK_GSP0_EB] = &gsp0_eb.common.hw,
1847 [CLK_GSP1_EB] = &gsp1_eb.common.hw,
1848 [CLK_GSP0_MMU_EB] = &gsp0_mmu_eb.common.hw,
1849 [CLK_GSP1_MMU_EB] = &gsp1_mmu_eb.common.hw,
1850 [CLK_DSI0_EB] = &dsi0_eb.common.hw,
1851 [CLK_DSI1_EB] = &dsi1_eb.common.hw,
1852 [CLK_DISP_CKG_EB] = &disp_ckg_eb.common.hw,
1853 [CLK_DISP_GPU_EB] = &disp_gpu_eb.common.hw,
1854 [CLK_GPU_MTX_EB] = &gpu_mtx_eb.common.hw,
1855 [CLK_GSP_MTX_EB] = &gsp_mtx_eb.common.hw,
1856 [CLK_TMC_MTX_EB] = &tmc_mtx_eb.common.hw,
1857 [CLK_DISPC_MTX_EB] = &dispc_mtx_eb.common.hw,
1858 [CLK_DPHY0_GATE] = &dphy0_gate.common.hw,
1859 [CLK_DPHY1_GATE] = &dphy1_gate.common.hw,
1860 [CLK_GSP0_A_GATE] = &gsp0_a_gate.common.hw,
1861 [CLK_GSP1_A_GATE] = &gsp1_a_gate.common.hw,
1862 [CLK_GSP0_F_GATE] = &gsp0_f_gate.common.hw,
1863 [CLK_GSP1_F_GATE] = &gsp1_f_gate.common.hw,
1864 [CLK_D_MTX_F_GATE] = &d_mtx_f_gate.common.hw,
1865 [CLK_D_MTX_A_GATE] = &d_mtx_a_gate.common.hw,
1866 [CLK_D_NOC_F_GATE] = &d_noc_f_gate.common.hw,
1867 [CLK_D_NOC_A_GATE] = &d_noc_a_gate.common.hw,
1868 [CLK_GSP_MTX_F_GATE] = &gsp_mtx_f_gate.common.hw,
1869 [CLK_GSP_MTX_A_GATE] = &gsp_mtx_a_gate.common.hw,
1870 [CLK_GSP_NOC_F_GATE] = &gsp_noc_f_gate.common.hw,
1871 [CLK_GSP_NOC_A_GATE] = &gsp_noc_a_gate.common.hw,
1872 [CLK_DISPM0IDLE_GATE] = &dispm0idle_gate.common.hw,
1873 [CLK_GSPM0IDLE_GATE] = &gspm0idle_gate.common.hw,
1874 },
1875 .num = CLK_DISP_GATE_NUM,
1876};
1877
1878static const struct sprd_clk_desc sc9860_disp_gate_desc = {
1879 .clk_clks = sc9860_disp_gate,
1880 .num_clk_clks = ARRAY_SIZE(sc9860_disp_gate),
1881 .hw_clks = &sc9860_disp_gate_hws,
1882};
1883
1884static SPRD_SC_GATE_CLK(sim0_eb, "sim0-eb", "ap-apb", 0x0,
1885 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
1886static SPRD_SC_GATE_CLK(iis0_eb, "iis0-eb", "ap-apb", 0x0,
1887 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
1888static SPRD_SC_GATE_CLK(iis1_eb, "iis1-eb", "ap-apb", 0x0,
1889 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
1890static SPRD_SC_GATE_CLK(iis2_eb, "iis2-eb", "ap-apb", 0x0,
1891 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
1892static SPRD_SC_GATE_CLK(iis3_eb, "iis3-eb", "ap-apb", 0x0,
1893 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
1894static SPRD_SC_GATE_CLK(spi0_eb, "spi0-eb", "ap-apb", 0x0,
1895 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
1896static SPRD_SC_GATE_CLK(spi1_eb, "spi1-eb", "ap-apb", 0x0,
1897 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
1898static SPRD_SC_GATE_CLK(spi2_eb, "spi2-eb", "ap-apb", 0x0,
1899 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
1900static SPRD_SC_GATE_CLK(i2c0_eb, "i2c0-eb", "ap-apb", 0x0,
1901 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
1902static SPRD_SC_GATE_CLK(i2c1_eb, "i2c1-eb", "ap-apb", 0x0,
1903 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
1904static SPRD_SC_GATE_CLK(i2c2_eb, "i2c2-eb", "ap-apb", 0x0,
1905 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
1906static SPRD_SC_GATE_CLK(i2c3_eb, "i2c3-eb", "ap-apb", 0x0,
1907 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
1908static SPRD_SC_GATE_CLK(i2c4_eb, "i2c4-eb", "ap-apb", 0x0,
1909 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
1910static SPRD_SC_GATE_CLK(i2c5_eb, "i2c5-eb", "ap-apb", 0x0,
1911 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
1912static SPRD_SC_GATE_CLK(uart0_eb, "uart0-eb", "ap-apb", 0x0,
1913 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
1914static SPRD_SC_GATE_CLK(uart1_eb, "uart1-eb", "ap-apb", 0x0,
1915 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
1916static SPRD_SC_GATE_CLK(uart2_eb, "uart2-eb", "ap-apb", 0x0,
1917 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
1918static SPRD_SC_GATE_CLK(uart3_eb, "uart3-eb", "ap-apb", 0x0,
1919 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
1920static SPRD_SC_GATE_CLK(uart4_eb, "uart4-eb", "ap-apb", 0x0,
1921 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
1922static SPRD_SC_GATE_CLK(ap_ckg_eb, "ap-ckg-eb", "ap-apb", 0x0,
1923 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
1924static SPRD_SC_GATE_CLK(spi3_eb, "spi3-eb", "ap-apb", 0x0,
1925 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
1926
1927static struct sprd_clk_common *sc9860_apapb_gate[] = {
1928 /* address base is 0x70b00000 */
1929 &sim0_eb.common,
1930 &iis0_eb.common,
1931 &iis1_eb.common,
1932 &iis2_eb.common,
1933 &iis3_eb.common,
1934 &spi0_eb.common,
1935 &spi1_eb.common,
1936 &spi2_eb.common,
1937 &i2c0_eb.common,
1938 &i2c1_eb.common,
1939 &i2c2_eb.common,
1940 &i2c3_eb.common,
1941 &i2c4_eb.common,
1942 &i2c5_eb.common,
1943 &uart0_eb.common,
1944 &uart1_eb.common,
1945 &uart2_eb.common,
1946 &uart3_eb.common,
1947 &uart4_eb.common,
1948 &ap_ckg_eb.common,
1949 &spi3_eb.common,
1950};
1951
1952static struct clk_hw_onecell_data sc9860_apapb_gate_hws = {
1953 .hws = {
1954 [CLK_SIM0_EB] = &sim0_eb.common.hw,
1955 [CLK_IIS0_EB] = &iis0_eb.common.hw,
1956 [CLK_IIS1_EB] = &iis1_eb.common.hw,
1957 [CLK_IIS2_EB] = &iis2_eb.common.hw,
1958 [CLK_IIS3_EB] = &iis3_eb.common.hw,
1959 [CLK_SPI0_EB] = &spi0_eb.common.hw,
1960 [CLK_SPI1_EB] = &spi1_eb.common.hw,
1961 [CLK_SPI2_EB] = &spi2_eb.common.hw,
1962 [CLK_I2C0_EB] = &i2c0_eb.common.hw,
1963 [CLK_I2C1_EB] = &i2c1_eb.common.hw,
1964 [CLK_I2C2_EB] = &i2c2_eb.common.hw,
1965 [CLK_I2C3_EB] = &i2c3_eb.common.hw,
1966 [CLK_I2C4_EB] = &i2c4_eb.common.hw,
1967 [CLK_I2C5_EB] = &i2c5_eb.common.hw,
1968 [CLK_UART0_EB] = &uart0_eb.common.hw,
1969 [CLK_UART1_EB] = &uart1_eb.common.hw,
1970 [CLK_UART2_EB] = &uart2_eb.common.hw,
1971 [CLK_UART3_EB] = &uart3_eb.common.hw,
1972 [CLK_UART4_EB] = &uart4_eb.common.hw,
1973 [CLK_AP_CKG_EB] = &ap_ckg_eb.common.hw,
1974 [CLK_SPI3_EB] = &spi3_eb.common.hw,
1975 },
1976 .num = CLK_APAPB_GATE_NUM,
1977};
1978
1979static const struct sprd_clk_desc sc9860_apapb_gate_desc = {
1980 .clk_clks = sc9860_apapb_gate,
1981 .num_clk_clks = ARRAY_SIZE(sc9860_apapb_gate),
1982 .hw_clks = &sc9860_apapb_gate_hws,
1983};
1984
1985static const struct of_device_id sprd_sc9860_clk_ids[] = {
1986 { .compatible = "sprd,sc9860-pmu-gate", /* 0x402b */
1987 .data = &sc9860_pmu_gate_desc },
1988 { .compatible = "sprd,sc9860-pll", /* 0x4040 */
1989 .data = &sc9860_pll_desc },
1990 { .compatible = "sprd,sc9860-ap-clk", /* 0x2000 */
1991 .data = &sc9860_ap_clk_desc },
1992 { .compatible = "sprd,sc9860-aon-prediv", /* 0x402d */
1993 .data = &sc9860_aon_prediv_desc },
1994 { .compatible = "sprd,sc9860-apahb-gate", /* 0x2021 */
1995 .data = &sc9860_apahb_gate_desc },
1996 { .compatible = "sprd,sc9860-aon-gate", /* 0x402e */
1997 .data = &sc9860_aon_gate_desc },
1998 { .compatible = "sprd,sc9860-aonsecure-clk", /* 0x4088 */
1999 .data = &sc9860_aonsecure_clk_desc },
2000 { .compatible = "sprd,sc9860-agcp-gate", /* 0x415e */
2001 .data = &sc9860_agcp_gate_desc },
2002 { .compatible = "sprd,sc9860-gpu-clk", /* 0x6020 */
2003 .data = &sc9860_gpu_clk_desc },
2004 { .compatible = "sprd,sc9860-vsp-clk", /* 0x6100 */
2005 .data = &sc9860_vsp_clk_desc },
2006 { .compatible = "sprd,sc9860-vsp-gate", /* 0x6110 */
2007 .data = &sc9860_vsp_gate_desc },
2008 { .compatible = "sprd,sc9860-cam-clk", /* 0x6200 */
2009 .data = &sc9860_cam_clk_desc },
2010 { .compatible = "sprd,sc9860-cam-gate", /* 0x6210 */
2011 .data = &sc9860_cam_gate_desc },
2012 { .compatible = "sprd,sc9860-disp-clk", /* 0x6300 */
2013 .data = &sc9860_disp_clk_desc },
2014 { .compatible = "sprd,sc9860-disp-gate", /* 0x6310 */
2015 .data = &sc9860_disp_gate_desc },
2016 { .compatible = "sprd,sc9860-apapb-gate", /* 0x70b0 */
2017 .data = &sc9860_apapb_gate_desc },
2018 { }
2019};
2020MODULE_DEVICE_TABLE(of, sprd_sc9860_clk_ids);
2021
2022static int sc9860_clk_probe(struct platform_device *pdev)
2023{
2024 const struct of_device_id *match;
2025 const struct sprd_clk_desc *desc;
2026
2027 match = of_match_node(sprd_sc9860_clk_ids, pdev->dev.of_node);
2028 if (!match) {
2029 pr_err("%s: of_match_node() failed", __func__);
2030 return -ENODEV;
2031 }
2032
2033 desc = match->data;
2034 sprd_clk_regmap_init(pdev, desc);
2035
2036 return sprd_clk_probe(&pdev->dev, desc->hw_clks);
2037}
2038
2039static struct platform_driver sc9860_clk_driver = {
2040 .probe = sc9860_clk_probe,
2041 .driver = {
2042 .name = "sc9860-clk",
2043 .of_match_table = sprd_sc9860_clk_ids,
2044 },
2045};
2046module_platform_driver(sc9860_clk_driver);
2047
2048MODULE_DESCRIPTION("Spreadtrum SC9860 Clock Driver");
2049MODULE_LICENSE("GPL v2");
2050MODULE_ALIAS("platform:sc9860-clk");