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gerrit-public.fairphone.software / kernel / msm-5.4 / 980ce7d94e0738aaee3c1ea3e2d5670bddeffc04 / . / arch / arm / boot / dts / sama5d3.dtsi
blob: 95c00a3ae9257dc85d05418485ad03c2d46c2928 [file] [log] [blame]
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 model = "Atmel SAMA5D3 family SoC";
15 compatible = "atmel,sama5d3", "atmel,sama5";
16 interrupt-parent = <&aic>;
17
18 aliases {
19 serial0 = &dbgu;
20 serial1 = &usart0;
21 serial2 = &usart1;
22 serial3 = &usart2;
23 serial4 = &usart3;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 gpio4 = &pioE;
29 tcb0 = &tcb0;
30 tcb1 = &tcb1;
31 i2c0 = &i2c0;
32 i2c1 = &i2c1;
33 i2c2 = &i2c2;
34 ssc0 = &ssc0;
35 ssc1 = &ssc1;
36 };
37 cpus {
38 cpu@0 {
39 compatible = "arm,cortex-a5";
40 };
41 };
42
43 memory {
44 reg = <0x20000000 0x8000000>;
45 };
46
47 ahb {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
52
53 apb {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
59 mmc0: mmc@f0000000 {
60 compatible = "atmel,hsmci";
61 reg = <0xf0000000 0x600>;
62 interrupts = <21 4 0>;
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
65 status = "disabled";
66 #address-cells = <1>;
67 #size-cells = <0>;
68 };
69
70 spi0: spi@f0004000 {
71 #address-cells = <1>;
72 #size-cells = <0>;
73 compatible = "atmel,at91sam9x5-spi";
74 reg = <0xf0004000 0x100>;
75 interrupts = <24 4 3>;
76 cs-gpios = <&pioD 13 0
77 &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
78 &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
79 &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */
80 >;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_spi0>;
83 status = "disabled";
84 };
85
86 ssc0: ssc@f0008000 {
87 compatible = "atmel,at91sam9g45-ssc";
88 reg = <0xf0008000 0x4000>;
89 interrupts = <38 4 4>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
92 status = "disabled";
93 };
94
95 can0: can@f000c000 {
96 compatible = "atmel,at91sam9x5-can";
97 reg = <0xf000c000 0x300>;
98 interrupts = <40 4 3>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_can0_rx_tx>;
101 status = "disabled";
102 };
103
104 tcb0: timer@f0010000 {
105 compatible = "atmel,at91sam9x5-tcb";
106 reg = <0xf0010000 0x100>;
107 interrupts = <26 4 0>;
108 };
109
110 i2c0: i2c@f0014000 {
111 compatible = "atmel,at91sam9x5-i2c";
112 reg = <0xf0014000 0x4000>;
113 interrupts = <18 4 6>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_i2c0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 status = "disabled";
119 };
120
121 i2c1: i2c@f0018000 {
122 compatible = "atmel,at91sam9x5-i2c";
123 reg = <0xf0018000 0x4000>;
124 interrupts = <19 4 6>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_i2c1>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 status = "disabled";
130 };
131
132 usart0: serial@f001c000 {
133 compatible = "atmel,at91sam9260-usart";
134 reg = <0xf001c000 0x100>;
135 interrupts = <12 4 5>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_usart0>;
138 status = "disabled";
139 };
140
141 usart1: serial@f0020000 {
142 compatible = "atmel,at91sam9260-usart";
143 reg = <0xf0020000 0x100>;
144 interrupts = <13 4 5>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_usart1>;
147 status = "disabled";
148 };
149
150 macb0: ethernet@f0028000 {
151 compatible = "cnds,pc302-gem", "cdns,gem";
152 reg = <0xf0028000 0x100>;
153 interrupts = <34 4 3>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
156 status = "disabled";
157 };
158
159 isi: isi@f0034000 {
160 compatible = "atmel,at91sam9g45-isi";
161 reg = <0xf0034000 0x4000>;
162 interrupts = <37 4 5>;
163 status = "disabled";
164 };
165
166 mmc1: mmc@f8000000 {
167 compatible = "atmel,hsmci";
168 reg = <0xf8000000 0x600>;
169 interrupts = <22 4 0>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
172 status = "disabled";
173 #address-cells = <1>;
174 #size-cells = <0>;
175 };
176
177 mmc2: mmc@f8004000 {
178 compatible = "atmel,hsmci";
179 reg = <0xf8004000 0x600>;
180 interrupts = <23 4 0>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
183 status = "disabled";
184 #address-cells = <1>;
185 #size-cells = <0>;
186 };
187
188 spi1: spi@f8008000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "atmel,at91sam9x5-spi";
192 reg = <0xf8008000 0x100>;
193 interrupts = <25 4 3>;
194 cs-gpios = <&pioC 25 0
195 &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
196 &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
197 &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */
198 >;
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_spi1>;
201 status = "disabled";
202 };
203
204 ssc1: ssc@f800c000 {
205 compatible = "atmel,at91sam9g45-ssc";
206 reg = <0xf800c000 0x4000>;
207 interrupts = <39 4 4>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
210 status = "disabled";
211 };
212
213 can1: can@f8010000 {
214 compatible = "atmel,at91sam9x5-can";
215 reg = <0xf8010000 0x300>;
216 interrupts = <41 4 3>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_can1_rx_tx>;
219 };
220
221 tcb1: timer@f8014000 {
222 compatible = "atmel,at91sam9x5-tcb";
223 reg = <0xf8014000 0x100>;
224 interrupts = <27 4 0>;
225 };
226
227 adc0: adc@f8018000 {
228 compatible = "atmel,at91sam9260-adc";
229 reg = <0xf8018000 0x100>;
230 interrupts = <29 4 5>;
231 pinctrl-names = "default";
232 pinctrl-0 = <
233 &pinctrl_adc0_adtrg
234 &pinctrl_adc0_ad0
235 &pinctrl_adc0_ad1
236 &pinctrl_adc0_ad2
237 &pinctrl_adc0_ad3
238 &pinctrl_adc0_ad4
239 &pinctrl_adc0_ad5
240 &pinctrl_adc0_ad6
241 &pinctrl_adc0_ad7
242 &pinctrl_adc0_ad8
243 &pinctrl_adc0_ad9
244 &pinctrl_adc0_ad10
245 &pinctrl_adc0_ad11
246 >;
247 atmel,adc-channel-base = <0x50>;
248 atmel,adc-channels-used = <0xfff>;
249 atmel,adc-drdy-mask = <0x1000000>;
250 atmel,adc-num-channels = <12>;
251 atmel,adc-startup-time = <40>;
252 atmel,adc-status-register = <0x30>;
253 atmel,adc-trigger-register = <0xc0>;
254 atmel,adc-use-external;
255 atmel,adc-vref = <3000>;
256 atmel,adc-res = <10 12>;
257 atmel,adc-res-names = "lowres", "highres";
258 status = "disabled";
259
260 trigger@0 {
261 trigger-name = "external-rising";
262 trigger-value = <0x1>;
263 trigger-external;
264 };
265 trigger@1 {
266 trigger-name = "external-falling";
267 trigger-value = <0x2>;
268 trigger-external;
269 };
270 trigger@2 {
271 trigger-name = "external-any";
272 trigger-value = <0x3>;
273 trigger-external;
274 };
275 trigger@3 {
276 trigger-name = "continuous";
277 trigger-value = <0x6>;
278 };
279 };
280
281 tsadcc: tsadcc@f8018000 {
282 compatible = "atmel,at91sam9x5-tsadcc";
283 reg = <0xf8018000 0x4000>;
284 interrupts = <29 4 5>;
285 atmel,tsadcc_clock = <300000>;
286 atmel,filtering_average = <0x03>;
287 atmel,pendet_debounce = <0x08>;
288 atmel,pendet_sensitivity = <0x02>;
289 atmel,ts_sample_hold_time = <0x0a>;
290 status = "disabled";
291 };
292
293 i2c2: i2c@f801c000 {
294 compatible = "atmel,at91sam9x5-i2c";
295 reg = <0xf801c000 0x4000>;
296 interrupts = <20 4 6>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 status = "disabled";
300 };
301
302 usart2: serial@f8020000 {
303 compatible = "atmel,at91sam9260-usart";
304 reg = <0xf8020000 0x100>;
305 interrupts = <14 4 5>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_usart2>;
308 status = "disabled";
309 };
310
311 usart3: serial@f8024000 {
312 compatible = "atmel,at91sam9260-usart";
313 reg = <0xf8024000 0x100>;
314 interrupts = <15 4 5>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_usart3>;
317 status = "disabled";
318 };
319
320 macb1: ethernet@f802c000 {
321 compatible = "cdns,at32ap7000-macb", "cdns,macb";
322 reg = <0xf802c000 0x100>;
323 interrupts = <35 4 3>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_macb1_rmii>;
326 status = "disabled";
327 };
328
329 sha@f8034000 {
330 compatible = "atmel,sam9g46-sha";
331 reg = <0xf8034000 0x100>;
332 interrupts = <42 4 0>;
333 };
334
335 aes@f8038000 {
336 compatible = "atmel,sam9g46-aes";
337 reg = <0xf8038000 0x100>;
338 interrupts = <43 4 0>;
339 };
340
341 tdes@f803c000 {
342 compatible = "atmel,sam9g46-tdes";
343 reg = <0xf803c000 0x100>;
344 interrupts = <44 4 0>;
345 };
346
347 dma0: dma-controller@ffffe600 {
348 compatible = "atmel,at91sam9g45-dma";
349 reg = <0xffffe600 0x200>;
350 interrupts = <30 4 0>;
Ludovic Desroches980ce7d2013-04-16 15:03:06 +0200[diff] [blame^]351 #dma-cells = <2>;
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]352 };
353
354 dma1: dma-controller@ffffe800 {
355 compatible = "atmel,at91sam9g45-dma";
356 reg = <0xffffe800 0x200>;
357 interrupts = <31 4 0>;
Ludovic Desroches980ce7d2013-04-16 15:03:06 +0200[diff] [blame^]358 #dma-cells = <2>;
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]359 };
360
361 ramc0: ramc@ffffea00 {
362 compatible = "atmel,at91sam9g45-ddramc";
363 reg = <0xffffea00 0x200>;
364 };
365
366 dbgu: serial@ffffee00 {
367 compatible = "atmel,at91sam9260-usart";
368 reg = <0xffffee00 0x200>;
369 interrupts = <2 4 7>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_dbgu>;
372 status = "disabled";
373 };
374
375 aic: interrupt-controller@fffff000 {
376 #interrupt-cells = <3>;
377 compatible = "atmel,sama5d3-aic";
378 interrupt-controller;
379 reg = <0xfffff000 0x200>;
380 atmel,external-irqs = <47>;
381 };
382
383 pinctrl@fffff200 {
384 #address-cells = <1>;
385 #size-cells = <1>;
386 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
387 ranges = <0xfffff200 0xfffff200 0xa00>;
388 atmel,mux-mask = <
389 /* A B C */
390 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
391 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
392 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
393 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
394 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
395 >;
396
397 /* shared pinctrl settings */
398 adc0 {
399 pinctrl_adc0_adtrg: adc0_adtrg {
400 atmel,pins =
401 <3 19 0x1 0x0>; /* PD19 periph A ADTRG */
402 };
403 pinctrl_adc0_ad0: adc0_ad0 {
404 atmel,pins =
405 <3 20 0x1 0x0>; /* PD20 periph A AD0 */
406 };
407 pinctrl_adc0_ad1: adc0_ad1 {
408 atmel,pins =
409 <3 21 0x1 0x0>; /* PD21 periph A AD1 */
410 };
411 pinctrl_adc0_ad2: adc0_ad2 {
412 atmel,pins =
413 <3 22 0x1 0x0>; /* PD22 periph A AD2 */
414 };
415 pinctrl_adc0_ad3: adc0_ad3 {
416 atmel,pins =
417 <3 23 0x1 0x0>; /* PD23 periph A AD3 */
418 };
419 pinctrl_adc0_ad4: adc0_ad4 {
420 atmel,pins =
421 <3 24 0x1 0x0>; /* PD24 periph A AD4 */
422 };
423 pinctrl_adc0_ad5: adc0_ad5 {
424 atmel,pins =
425 <3 25 0x1 0x0>; /* PD25 periph A AD5 */
426 };
427 pinctrl_adc0_ad6: adc0_ad6 {
428 atmel,pins =
429 <3 26 0x1 0x0>; /* PD26 periph A AD6 */
430 };
431 pinctrl_adc0_ad7: adc0_ad7 {
432 atmel,pins =
433 <3 27 0x1 0x0>; /* PD27 periph A AD7 */
434 };
435 pinctrl_adc0_ad8: adc0_ad8 {
436 atmel,pins =
437 <3 28 0x1 0x0>; /* PD28 periph A AD8 */
438 };
439 pinctrl_adc0_ad9: adc0_ad9 {
440 atmel,pins =
441 <3 29 0x1 0x0>; /* PD29 periph A AD9 */
442 };
443 pinctrl_adc0_ad10: adc0_ad10 {
444 atmel,pins =
445 <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */
446 };
447 pinctrl_adc0_ad11: adc0_ad11 {
448 atmel,pins =
449 <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */
450 };
451 };
452
453 can0 {
454 pinctrl_can0_rx_tx: can0_rx_tx {
455 atmel,pins =
456 <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
457 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
458 };
459 };
460
461 can1 {
462 pinctrl_can1_rx_tx: can1_rx_tx {
463 atmel,pins =
464 <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */
465 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */
466 };
467 };
468
469 dbgu {
470 pinctrl_dbgu: dbgu-0 {
471 atmel,pins =
472 <1 30 0x1 0x0 /* PB30 periph A */
473 1 31 0x1 0x1>; /* PB31 periph A with pullup */
474 };
475 };
476
477 i2c0 {
478 pinctrl_i2c0: i2c0-0 {
479 atmel,pins =
480 <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
481 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
482 };
483 };
484
485 i2c1 {
486 pinctrl_i2c1: i2c1-0 {
487 atmel,pins =
488 <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
489 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
490 };
491 };
492
493 isi {
494 pinctrl_isi: isi-0 {
495 atmel,pins =
496 <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
497 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
498 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
499 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
500 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
501 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
502 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
503 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
504 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
505 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
506 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
507 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
508 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
509 };
510 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
511 atmel,pins =
512 <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */
513 };
514 };
515
516 lcd {
517 pinctrl_lcd: lcd-0 {
518 atmel,pins =
519 <0 24 0x1 0x0 /* PA24 periph A LCDPWM */
520 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */
521 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */
522 0 25 0x1 0x0 /* PA25 periph A LCDDISP */
523 0 29 0x1 0x0 /* PA29 periph A LCDDEN */
524 0 28 0x1 0x0 /* PA28 periph A LCDPCK */
525 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */
526 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */
527 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */
528 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */
529 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */
530 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */
531 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */
532 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */
533 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */
534 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */
535 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */
536 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */
537 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */
538 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */
539 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */
540 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */
541 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */
542 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */
543 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */
544 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */
545 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */
546 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */
547 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */
548 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */
549 };
550 };
551
552 macb0 {
553 pinctrl_macb0_data_rgmii: macb0_data_rgmii {
554 atmel,pins =
555 <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */
556 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */
557 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */
558 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */
559 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */
560 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */
561 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */
562 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */
563 };
564 pinctrl_macb0_data_gmii: macb0_data_gmii {
565 atmel,pins =
566 <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */
567 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
568 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
569 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
570 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
571 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */
572 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */
573 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */
574 };
575 pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
576 atmel,pins =
577 <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */
578 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */
579 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */
580 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */
581 1 16 0x1 0x0 /* PB16 periph A GMDC */
582 1 17 0x1 0x0 /* PB17 periph A GMDIO */
583 1 18 0x1 0x0>; /* PB18 periph A G125CK */
584 };
585 pinctrl_macb0_signal_gmii: macb0_signal_gmii {
586 atmel,pins =
587 <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */
588 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */
589 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */
590 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */
591 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */
592 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */
593 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */
594 1 16 0x1 0x0 /* PB16 periph A GMDC */
595 1 17 0x1 0x0 /* PB17 periph A GMDIO */
596 1 27 0x2 0x0>; /* PB27 periph B G125CKO */
597 };
598
599 };
600
601 macb1 {
602 pinctrl_macb1_rmii: macb1_rmii-0 {
603 atmel,pins =
604 <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */
605 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */
606 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */
607 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */
608 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */
609 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */
610 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */
611 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */
612 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */
613 2 9 0x1 0x0>; /* PC9 periph A EMDIO */
614 };
615 };
616
617 mmc0 {
618 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
619 atmel,pins =
620 <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */
621 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */
622 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */
623 };
624 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
625 atmel,pins =
626 <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */
627 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */
628 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */
629 };
630 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
631 atmel,pins =
632 <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
633 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
634 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
635 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
636 };
637 };
638
639 mmc1 {
640 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
641 atmel,pins =
642 <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */
643 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
644 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
645 };
646 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
647 atmel,pins =
648 <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
649 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
650 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
651 };
652 };
653
654 mmc2 {
655 pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
656 atmel,pins =
657 <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */
658 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */
659 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */
660 };
661 pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
662 atmel,pins =
663 <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
664 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
665 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
666 };
667 };
668
669 nand0 {
670 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
671 atmel,pins =
672 <4 21 0x1 0x1 /* PE21 periph A with pullup */
673 4 22 0x1 0x1>; /* PE22 periph A with pullup */
674 };
675 };
676
677 pioA: gpio@fffff200 {
678 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
679 reg = <0xfffff200 0x100>;
680 interrupts = <6 4 1>;
681 #gpio-cells = <2>;
682 gpio-controller;
683 interrupt-controller;
684 #interrupt-cells = <2>;
685 };
686
687 pioB: gpio@fffff400 {
688 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
689 reg = <0xfffff400 0x100>;
690 interrupts = <7 4 1>;
691 #gpio-cells = <2>;
692 gpio-controller;
693 interrupt-controller;
694 #interrupt-cells = <2>;
695 };
696
697 pioC: gpio@fffff600 {
698 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
699 reg = <0xfffff600 0x100>;
700 interrupts = <8 4 1>;
701 #gpio-cells = <2>;
702 gpio-controller;
703 interrupt-controller;
704 #interrupt-cells = <2>;
705 };
706
707 pioD: gpio@fffff800 {
708 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
709 reg = <0xfffff800 0x100>;
710 interrupts = <9 4 1>;
711 #gpio-cells = <2>;
712 gpio-controller;
713 interrupt-controller;
714 #interrupt-cells = <2>;
715 };
716
717 pioE: gpio@fffffa00 {
718 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
719 reg = <0xfffffa00 0x100>;
720 interrupts = <10 4 1>;
721 #gpio-cells = <2>;
722 gpio-controller;
723 interrupt-controller;
724 #interrupt-cells = <2>;
725 };
726
727 spi0 {
728 pinctrl_spi0: spi0-0 {
729 atmel,pins =
730 <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */
731 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */
732 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */
733 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */
734 };
735 };
736
737 spi1 {
738 pinctrl_spi1: spi1-0 {
739 atmel,pins =
740 <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */
741 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */
742 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */
743 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */
744 };
745 };
746
747 ssc0 {
748 pinctrl_ssc0_tx: ssc0_tx {
749 atmel,pins =
750 <2 16 0x1 0x0 /* PC16 periph A TK0 */
751 2 17 0x1 0x0 /* PC17 periph A TF0 */
752 2 18 0x1 0x0>; /* PC18 periph A TD0 */
753 };
754
755 pinctrl_ssc0_rx: ssc0_rx {
756 atmel,pins =
757 <2 19 0x1 0x0 /* PC19 periph A RK0 */
758 2 20 0x1 0x0 /* PC20 periph A RF0 */
759 2 21 0x1 0x0>; /* PC21 periph A RD0 */
760 };
761 };
762
763 ssc1 {
764 pinctrl_ssc1_tx: ssc1_tx {
765 atmel,pins =
766 <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */
767 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */
768 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */
769 };
770
771 pinctrl_ssc1_rx: ssc1_rx {
772 atmel,pins =
773 <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */
774 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */
775 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */
776 };
777 };
778
779 uart0 {
780 pinctrl_uart0: uart0-0 {
781 atmel,pins =
782 <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
783 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
784 };
785 };
786
787 uart1 {
788 pinctrl_uart1: uart1-0 {
789 atmel,pins =
790 <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
791 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
792 };
793 };
794
795 usart0 {
796 pinctrl_usart0: usart0-0 {
797 atmel,pins =
798 <3 17 0x1 0x0 /* PD17 periph A */
799 3 18 0x1 0x1>; /* PD18 periph A with pullup */
800 };
801
802 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
803 atmel,pins =
804 <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
805 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
806 };
807 };
808
809 usart1 {
810 pinctrl_usart1: usart1-0 {
811 atmel,pins =
812 <1 28 0x1 0x0 /* PB28 periph A */
813 1 29 0x1 0x1>; /* PB29 periph A with pullup */
814 };
815
816 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
817 atmel,pins =
818 <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */
819 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */
820 };
821 };
822
823 usart2 {
824 pinctrl_usart2: usart2-0 {
825 atmel,pins =
826 <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */
827 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */
828 };
829
830 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
831 atmel,pins =
832 <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */
833 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */
834 };
835 };
836
837 usart3 {
838 pinctrl_usart3: usart3-0 {
839 atmel,pins =
840 <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */
841 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */
842 };
843
844 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
845 atmel,pins =
846 <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */
847 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */
848 };
849 };
850 };
851
852 pmc: pmc@fffffc00 {
853 compatible = "atmel,at91rm9200-pmc";
854 reg = <0xfffffc00 0x120>;
855 };
856
857 rstc@fffffe00 {
858 compatible = "atmel,at91sam9g45-rstc";
859 reg = <0xfffffe00 0x10>;
860 };
861
862 pit: timer@fffffe30 {
863 compatible = "atmel,at91sam9260-pit";
864 reg = <0xfffffe30 0xf>;
865 interrupts = <3 4 5>;
866 };
867
868 watchdog@fffffe40 {
869 compatible = "atmel,at91sam9260-wdt";
870 reg = <0xfffffe40 0x10>;
871 status = "disabled";
872 };
873
874 rtc@fffffeb0 {
875 compatible = "atmel,at91rm9200-rtc";
876 reg = <0xfffffeb0 0x30>;
877 interrupts = <1 4 7>;
878 };
879 };
880
881 usb0: gadget@00500000 {
882 #address-cells = <1>;
883 #size-cells = <0>;
884 compatible = "atmel,at91sam9rl-udc";
885 reg = <0x00500000 0x100000
886 0xf8030000 0x4000>;
887 interrupts = <33 4 2>;
888 status = "disabled";
889
890 ep0 {
891 reg = <0>;
892 atmel,fifo-size = <64>;
893 atmel,nb-banks = <1>;
894 };
895
896 ep1 {
897 reg = <1>;
898 atmel,fifo-size = <1024>;
899 atmel,nb-banks = <3>;
900 atmel,can-dma;
901 atmel,can-isoc;
902 };
903
904 ep2 {
905 reg = <2>;
906 atmel,fifo-size = <1024>;
907 atmel,nb-banks = <3>;
908 atmel,can-dma;
909 atmel,can-isoc;
910 };
911
912 ep3 {
913 reg = <3>;
914 atmel,fifo-size = <1024>;
915 atmel,nb-banks = <2>;
916 atmel,can-dma;
917 };
918
919 ep4 {
920 reg = <4>;
921 atmel,fifo-size = <1024>;
922 atmel,nb-banks = <2>;
923 atmel,can-dma;
924 };
925
926 ep5 {
927 reg = <5>;
928 atmel,fifo-size = <1024>;
929 atmel,nb-banks = <2>;
930 atmel,can-dma;
931 };
932
933 ep6 {
934 reg = <6>;
935 atmel,fifo-size = <1024>;
936 atmel,nb-banks = <2>;
937 atmel,can-dma;
938 };
939
940 ep7 {
941 reg = <7>;
942 atmel,fifo-size = <1024>;
943 atmel,nb-banks = <2>;
944 atmel,can-dma;
945 };
946
947 ep8 {
948 reg = <8>;
949 atmel,fifo-size = <1024>;
950 atmel,nb-banks = <2>;
951 };
952
953 ep9 {
954 reg = <9>;
955 atmel,fifo-size = <1024>;
956 atmel,nb-banks = <2>;
957 };
958
959 ep10 {
960 reg = <10>;
961 atmel,fifo-size = <1024>;
962 atmel,nb-banks = <2>;
963 };
964
965 ep11 {
966 reg = <11>;
967 atmel,fifo-size = <1024>;
968 atmel,nb-banks = <2>;
969 };
970
971 ep12 {
972 reg = <12>;
973 atmel,fifo-size = <1024>;
974 atmel,nb-banks = <2>;
975 };
976
977 ep13 {
978 reg = <13>;
979 atmel,fifo-size = <1024>;
980 atmel,nb-banks = <2>;
981 };
982
983 ep14 {
984 reg = <14>;
985 atmel,fifo-size = <1024>;
986 atmel,nb-banks = <2>;
987 };
988
989 ep15 {
990 reg = <15>;
991 atmel,fifo-size = <1024>;
992 atmel,nb-banks = <2>;
993 };
994 };
995
996 usb1: ohci@00600000 {
997 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
998 reg = <0x00600000 0x100000>;
999 interrupts = <32 4 2>;
1000 status = "disabled";
1001 };
1002
1003 usb2: ehci@00700000 {
1004 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1005 reg = <0x00700000 0x100000>;
1006 interrupts = <32 4 2>;
1007 status = "disabled";
1008 };
1009
1010 nand0: nand@60000000 {
1011 compatible = "atmel,at91rm9200-nand";
1012 #address-cells = <1>;
1013 #size-cells = <1>;
1014 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1015 0xffffc070 0x00000490 /* SMC PMECC regs */
1016 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1017 0x00100000 0x00100000 /* ROM code */
1018 0x70000000 0x10000000 /* NFC Command Registers */
1019 0xffffc000 0x00000070 /* NFC HSMC regs */
1020 0x00200000 0x00100000 /* NFC SRAM banks */
1021 >;
1022 interrupts = <5 4 6>;
1023 atmel,nand-addr-offset = <21>;
1024 atmel,nand-cmd-offset = <22>;
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1027 atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
1028 status = "disabled";
1029 };
1030 };
1031};