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gerrit-public.fairphone.software / kernel / msm-5.4 / 4216be14be19ef3ca0c0afdb2f5c1a352e688a61 / . / drivers / media / dvb-frontends / cxd2841er.c
blob: 94de6ba3d0e274c0041fe276ab728f22a157c589 [file] [log] [blame]
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1/*
2 * cxd2841er.c
3 *
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]4 * Sony digital demodulator driver for
Abylay Ospan9ca17362016-05-16 11:57:04 -0300[diff] [blame]5 * CXD2841ER - DVB-S/S2/T/T2/C/C2
6 * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]7 *
8 * Copyright 2012 Sony Corporation
9 * Copyright (C) 2014 NetUP Inc.
10 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
11 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/bitops.h>
29#include <linux/math64.h>
30#include <linux/log2.h>
31#include <linux/dynamic_debug.h>
32
33#include "dvb_math.h"
34#include "dvb_frontend.h"
35#include "cxd2841er.h"
36#include "cxd2841er_priv.h"
37
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]38#define MAX_WRITE_REGSIZE 16
39
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]40enum cxd2841er_state {
41 STATE_SHUTDOWN = 0,
42 STATE_SLEEP_S,
43 STATE_ACTIVE_S,
44 STATE_SLEEP_TC,
45 STATE_ACTIVE_TC
46};
47
48struct cxd2841er_priv {
49 struct dvb_frontend frontend;
50 struct i2c_adapter *i2c;
51 u8 i2c_addr_slvx;
52 u8 i2c_addr_slvt;
53 const struct cxd2841er_config *config;
54 enum cxd2841er_state state;
55 u8 system;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]56 enum cxd2841er_xtal xtal;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]57 enum fe_caps caps;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]58};
59
60static const struct cxd2841er_cnr_data s_cn_data[] = {
61 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
62 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
63 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
64 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
65 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
66 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
67 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
68 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
69 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
70 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
71 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
72 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
73 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
74 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
75 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
76 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
77 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
78 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
79 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
80 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
81 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
82 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
83 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
84 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
85 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
86 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
87 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
88 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
89 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
90 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
91 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
92 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
93 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
94 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
95 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
96 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
97 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
98 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
99 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
100 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
101 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
102 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
103 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
104 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
105 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
106 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
107 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
108 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
109 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
110 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
111 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
112 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
113 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
114 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
115 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
116 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
117 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
118 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
119 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
120 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
121 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
122 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
123 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
124 { 0x0015, 19900 }, { 0x0014, 20000 },
125};
126
127static const struct cxd2841er_cnr_data s2_cn_data[] = {
128 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
129 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
130 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
131 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
132 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
133 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
134 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
135 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
136 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
137 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
138 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
139 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
140 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
141 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
142 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
143 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
144 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
145 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
146 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
147 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
148 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
149 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
150 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
151 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
152 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
153 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
154 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
155 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
156 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
157 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
158 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
159 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
160 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
161 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
162 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
163 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
164 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
165 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
166 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
167 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
168 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
169 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
170 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
171 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
172 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
173 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
174 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
175 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
176 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
177 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
178 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
179 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
180 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
181 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
182 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
183 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
184 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
185 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
186 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
187 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
188 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
189 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
190 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
191 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
192};
193
194#define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]195#define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
196 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
197 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]198
199static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
200 u8 addr, u8 reg, u8 write,
201 const u8 *data, u32 len)
202{
203 dev_dbg(&priv->i2c->dev,
204 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
205 (write == 0 ? "read" : "write"), addr, reg, len);
206 print_hex_dump_bytes("cxd2841er: I2C data: ",
207 DUMP_PREFIX_OFFSET, data, len);
208}
209
210static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
211 u8 addr, u8 reg, const u8 *data, u32 len)
212{
213 int ret;
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]214 u8 buf[MAX_WRITE_REGSIZE + 1];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]215 u8 i2c_addr = (addr == I2C_SLVX ?
216 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
217 struct i2c_msg msg[1] = {
218 {
219 .addr = i2c_addr,
220 .flags = 0,
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]221 .len = len + 1,
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]222 .buf = buf,
223 }
224 };
225
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]226 if (len + 1 >= sizeof(buf)) {
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]227 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]228 reg, len + 1);
229 return -E2BIG;
230 }
231
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]232 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
233 buf[0] = reg;
234 memcpy(&buf[1], data, len);
235
236 ret = i2c_transfer(priv->i2c, msg, 1);
237 if (ret >= 0 && ret != 1)
238 ret = -EIO;
239 if (ret < 0) {
240 dev_warn(&priv->i2c->dev,
241 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
242 KBUILD_MODNAME, ret, i2c_addr, reg, len);
243 return ret;
244 }
245 return 0;
246}
247
248static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
249 u8 addr, u8 reg, u8 val)
250{
251 return cxd2841er_write_regs(priv, addr, reg, &val, 1);
252}
253
254static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
255 u8 addr, u8 reg, u8 *val, u32 len)
256{
257 int ret;
258 u8 i2c_addr = (addr == I2C_SLVX ?
259 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
260 struct i2c_msg msg[2] = {
261 {
262 .addr = i2c_addr,
263 .flags = 0,
264 .len = 1,
265 .buf = &reg,
266 }, {
267 .addr = i2c_addr,
268 .flags = I2C_M_RD,
269 .len = len,
270 .buf = val,
271 }
272 };
273
274 ret = i2c_transfer(priv->i2c, &msg[0], 1);
275 if (ret >= 0 && ret != 1)
276 ret = -EIO;
277 if (ret < 0) {
278 dev_warn(&priv->i2c->dev,
279 "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
280 KBUILD_MODNAME, ret, i2c_addr, reg);
281 return ret;
282 }
283 ret = i2c_transfer(priv->i2c, &msg[1], 1);
284 if (ret >= 0 && ret != 1)
285 ret = -EIO;
286 if (ret < 0) {
287 dev_warn(&priv->i2c->dev,
288 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
289 KBUILD_MODNAME, ret, i2c_addr, reg);
290 return ret;
291 }
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]292 cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]293 return 0;
294}
295
296static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
297 u8 addr, u8 reg, u8 *val)
298{
299 return cxd2841er_read_regs(priv, addr, reg, val, 1);
300}
301
302static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
303 u8 addr, u8 reg, u8 data, u8 mask)
304{
305 int res;
306 u8 rdata;
307
308 if (mask != 0xff) {
309 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
310 if (res)
311 return res;
312 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
313 }
314 return cxd2841er_write_reg(priv, addr, reg, data);
315}
316
317static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
318 u32 symbol_rate)
319{
320 u32 reg_value = 0;
321 u8 data[3] = {0, 0, 0};
322
323 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
324 /*
325 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
326 * = ((symbolRateKSps * 2^14) + 500) / 1000
327 * = ((symbolRateKSps * 16384) + 500) / 1000
328 */
329 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
330 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
331 dev_err(&priv->i2c->dev,
332 "%s(): reg_value is out of range\n", __func__);
333 return -EINVAL;
334 }
335 data[0] = (u8)((reg_value >> 16) & 0x0F);
336 data[1] = (u8)((reg_value >> 8) & 0xFF);
337 data[2] = (u8)(reg_value & 0xFF);
338 /* Set SLV-T Bank : 0xAE */
339 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
340 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
341 return 0;
342}
343
344static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
345 u8 system);
346
347static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
348 u8 system, u32 symbol_rate)
349{
350 int ret;
351 u8 data[4] = { 0, 0, 0, 0 };
352
353 if (priv->state != STATE_SLEEP_S) {
354 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
355 __func__, (int)priv->state);
356 return -EINVAL;
357 }
358 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
359 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
360 /* Set demod mode */
361 if (system == SYS_DVBS) {
362 data[0] = 0x0A;
363 } else if (system == SYS_DVBS2) {
364 data[0] = 0x0B;
365 } else {
366 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
367 __func__, system);
368 return -EINVAL;
369 }
370 /* Set SLV-X Bank : 0x00 */
371 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
372 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
373 /* DVB-S/S2 */
374 data[0] = 0x00;
375 /* Set SLV-T Bank : 0x00 */
376 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
377 /* Enable S/S2 auto detection 1 */
378 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
379 /* Set SLV-T Bank : 0xAE */
380 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
381 /* Enable S/S2 auto detection 2 */
382 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
383 /* Set SLV-T Bank : 0x00 */
384 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
385 /* Enable demod clock */
386 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
387 /* Enable ADC clock */
388 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
389 /* Enable ADC 1 */
390 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
391 /* Enable ADC 2 */
392 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
393 /* Set SLV-X Bank : 0x00 */
394 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
395 /* Enable ADC 3 */
396 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
397 /* Set SLV-T Bank : 0xA3 */
398 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
399 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
400 data[0] = 0x07;
401 data[1] = 0x3B;
402 data[2] = 0x08;
403 data[3] = 0xC5;
404 /* Set SLV-T Bank : 0xAB */
405 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
406 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
407 data[0] = 0x05;
408 data[1] = 0x80;
409 data[2] = 0x0A;
410 data[3] = 0x80;
411 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
412 data[0] = 0x0C;
413 data[1] = 0xCC;
414 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
415 /* Set demod parameter */
416 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
417 if (ret != 0)
418 return ret;
419 /* Set SLV-T Bank : 0x00 */
420 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
421 /* disable Hi-Z setting 1 */
422 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
423 /* disable Hi-Z setting 2 */
424 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
425 priv->state = STATE_ACTIVE_S;
426 return 0;
427}
428
429static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
430 u32 bandwidth);
431
432static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
433 u32 bandwidth);
434
435static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
436 u32 bandwidth);
437
Mauro Carvalho Chehab76344a3f2016-05-04 18:25:38 -0300[diff] [blame]438static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
439 u32 bandwidth);
440
441static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
442
443static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
444
445static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
446
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]447static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
448 struct dtv_frontend_properties *p)
449{
450 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
451 if (priv->state != STATE_ACTIVE_S &&
452 priv->state != STATE_ACTIVE_TC) {
453 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
454 __func__, priv->state);
455 return -EINVAL;
456 }
457 /* Set SLV-T Bank : 0x00 */
458 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
459 /* disable TS output */
460 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
461 if (priv->state == STATE_ACTIVE_S)
462 return cxd2841er_dvbs2_set_symbol_rate(
463 priv, p->symbol_rate / 1000);
464 else if (priv->state == STATE_ACTIVE_TC) {
465 switch (priv->system) {
466 case SYS_DVBT:
467 return cxd2841er_sleep_tc_to_active_t_band(
468 priv, p->bandwidth_hz);
469 case SYS_DVBT2:
470 return cxd2841er_sleep_tc_to_active_t2_band(
471 priv, p->bandwidth_hz);
472 case SYS_DVBC_ANNEX_A:
473 return cxd2841er_sleep_tc_to_active_c_band(
Mauro Carvalho Chehab76344a3f2016-05-04 18:25:38 -0300[diff] [blame]474 priv, p->bandwidth_hz);
475 case SYS_ISDBT:
476 cxd2841er_active_i_to_sleep_tc(priv);
477 cxd2841er_sleep_tc_to_shutdown(priv);
478 cxd2841er_shutdown_to_sleep_tc(priv);
479 return cxd2841er_sleep_tc_to_active_i(
480 priv, p->bandwidth_hz);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]481 }
482 }
483 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
484 __func__, priv->system);
485 return -EINVAL;
486}
487
488static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
489{
490 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
491 if (priv->state != STATE_ACTIVE_S) {
492 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
493 __func__, priv->state);
494 return -EINVAL;
495 }
496 /* Set SLV-T Bank : 0x00 */
497 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
498 /* disable TS output */
499 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
500 /* enable Hi-Z setting 1 */
501 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
502 /* enable Hi-Z setting 2 */
503 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
504 /* Set SLV-X Bank : 0x00 */
505 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
506 /* disable ADC 1 */
507 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
508 /* Set SLV-T Bank : 0x00 */
509 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
510 /* disable ADC clock */
511 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
512 /* disable ADC 2 */
513 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
514 /* disable ADC 3 */
515 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
516 /* SADC Bias ON */
517 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
518 /* disable demod clock */
519 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
520 /* Set SLV-T Bank : 0xAE */
521 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
522 /* disable S/S2 auto detection1 */
523 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
524 /* Set SLV-T Bank : 0x00 */
525 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
526 /* disable S/S2 auto detection2 */
527 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
528 priv->state = STATE_SLEEP_S;
529 return 0;
530}
531
532static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
533{
534 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
535 if (priv->state != STATE_SLEEP_S) {
536 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
537 __func__, priv->state);
538 return -EINVAL;
539 }
540 /* Set SLV-T Bank : 0x00 */
541 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
542 /* Disable DSQOUT */
543 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
544 /* Disable DSQIN */
545 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
546 /* Set SLV-X Bank : 0x00 */
547 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
548 /* Disable oscillator */
549 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
550 /* Set demod mode */
551 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
552 priv->state = STATE_SHUTDOWN;
553 return 0;
554}
555
556static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
557{
558 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
559 if (priv->state != STATE_SLEEP_TC) {
560 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
561 __func__, priv->state);
562 return -EINVAL;
563 }
564 /* Set SLV-X Bank : 0x00 */
565 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
566 /* Disable oscillator */
567 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
568 /* Set demod mode */
569 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
570 priv->state = STATE_SHUTDOWN;
571 return 0;
572}
573
574static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
575{
576 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
577 if (priv->state != STATE_ACTIVE_TC) {
578 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
579 __func__, priv->state);
580 return -EINVAL;
581 }
582 /* Set SLV-T Bank : 0x00 */
583 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
584 /* disable TS output */
585 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
586 /* enable Hi-Z setting 1 */
587 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
588 /* enable Hi-Z setting 2 */
589 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
590 /* Set SLV-X Bank : 0x00 */
591 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
592 /* disable ADC 1 */
593 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
594 /* Set SLV-T Bank : 0x00 */
595 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
596 /* Disable ADC 2 */
597 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
598 /* Disable ADC 3 */
599 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
600 /* Disable ADC clock */
601 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
602 /* Disable RF level monitor */
603 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
604 /* Disable demod clock */
605 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
606 priv->state = STATE_SLEEP_TC;
607 return 0;
608}
609
610static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
611{
612 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
613 if (priv->state != STATE_ACTIVE_TC) {
614 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
615 __func__, priv->state);
616 return -EINVAL;
617 }
618 /* Set SLV-T Bank : 0x00 */
619 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
620 /* disable TS output */
621 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
622 /* enable Hi-Z setting 1 */
623 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
624 /* enable Hi-Z setting 2 */
625 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
626 /* Cancel DVB-T2 setting */
627 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
628 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
629 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
630 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
631 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
632 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
633 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
634 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
635 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
636 /* Set SLV-X Bank : 0x00 */
637 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
638 /* disable ADC 1 */
639 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
640 /* Set SLV-T Bank : 0x00 */
641 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
642 /* Disable ADC 2 */
643 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
644 /* Disable ADC 3 */
645 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
646 /* Disable ADC clock */
647 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
648 /* Disable RF level monitor */
649 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
650 /* Disable demod clock */
651 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
652 priv->state = STATE_SLEEP_TC;
653 return 0;
654}
655
656static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
657{
658 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
659 if (priv->state != STATE_ACTIVE_TC) {
660 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
661 __func__, priv->state);
662 return -EINVAL;
663 }
664 /* Set SLV-T Bank : 0x00 */
665 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
666 /* disable TS output */
667 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
668 /* enable Hi-Z setting 1 */
669 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
670 /* enable Hi-Z setting 2 */
671 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
672 /* Cancel DVB-C setting */
673 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
674 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
675 /* Set SLV-X Bank : 0x00 */
676 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
677 /* disable ADC 1 */
678 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
679 /* Set SLV-T Bank : 0x00 */
680 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
681 /* Disable ADC 2 */
682 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
683 /* Disable ADC 3 */
684 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
685 /* Disable ADC clock */
686 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
687 /* Disable RF level monitor */
688 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
689 /* Disable demod clock */
690 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
691 priv->state = STATE_SLEEP_TC;
692 return 0;
693}
694
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]695static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
696{
697 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
698 if (priv->state != STATE_ACTIVE_TC) {
699 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
700 __func__, priv->state);
701 return -EINVAL;
702 }
703 /* Set SLV-T Bank : 0x00 */
704 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
705 /* disable TS output */
706 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
707 /* enable Hi-Z setting 1 */
708 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
709 /* enable Hi-Z setting 2 */
710 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
711
712 /* TODO: Cancel demod parameter */
713
714 /* Set SLV-X Bank : 0x00 */
715 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
716 /* disable ADC 1 */
717 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
718 /* Set SLV-T Bank : 0x00 */
719 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
720 /* Disable ADC 2 */
721 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
722 /* Disable ADC 3 */
723 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
724 /* Disable ADC clock */
725 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
726 /* Disable RF level monitor */
727 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
728 /* Disable demod clock */
729 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
730 priv->state = STATE_SLEEP_TC;
731 return 0;
732}
733
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]734static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
735{
736 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
737 if (priv->state != STATE_SHUTDOWN) {
738 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
739 __func__, priv->state);
740 return -EINVAL;
741 }
742 /* Set SLV-X Bank : 0x00 */
743 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
744 /* Clear all demodulator registers */
745 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
746 usleep_range(3000, 5000);
747 /* Set SLV-X Bank : 0x00 */
748 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
749 /* Set demod SW reset */
750 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]751
752 switch (priv->xtal) {
753 case SONY_XTAL_20500:
754 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
755 break;
756 case SONY_XTAL_24000:
757 /* Select demod frequency */
758 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
759 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
760 break;
761 case SONY_XTAL_41000:
762 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
763 break;
764 default:
765 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
766 __func__, priv->xtal);
767 return -EINVAL;
768 }
769
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]770 /* Set demod mode */
771 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
772 /* Clear demod SW reset */
773 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
774 usleep_range(1000, 2000);
775 /* Set SLV-T Bank : 0x00 */
776 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
777 /* enable DSQOUT */
778 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
779 /* enable DSQIN */
780 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
781 /* TADC Bias On */
782 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
783 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
784 /* SADC Bias On */
785 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
786 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
787 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
788 priv->state = STATE_SLEEP_S;
789 return 0;
790}
791
792static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
793{
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]794 u8 data = 0;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]795
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]796 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
797 if (priv->state != STATE_SHUTDOWN) {
798 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
799 __func__, priv->state);
800 return -EINVAL;
801 }
802 /* Set SLV-X Bank : 0x00 */
803 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
804 /* Clear all demodulator registers */
805 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
806 usleep_range(3000, 5000);
807 /* Set SLV-X Bank : 0x00 */
808 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
809 /* Set demod SW reset */
810 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]811 /* Select ADC clock mode */
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]812 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]813
814 switch (priv->xtal) {
815 case SONY_XTAL_20500:
816 data = 0x0;
817 break;
818 case SONY_XTAL_24000:
819 /* Select demod frequency */
820 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
821 data = 0x3;
822 break;
823 case SONY_XTAL_41000:
824 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
825 data = 0x1;
826 break;
827 }
828 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]829 /* Clear demod SW reset */
830 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
831 usleep_range(1000, 2000);
832 /* Set SLV-T Bank : 0x00 */
833 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
834 /* TADC Bias On */
835 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
836 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
837 /* SADC Bias On */
838 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
839 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
840 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
841 priv->state = STATE_SLEEP_TC;
842 return 0;
843}
844
845static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
846{
847 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
848 /* Set SLV-T Bank : 0x00 */
849 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
850 /* SW Reset */
851 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
852 /* Enable TS output */
853 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
854 return 0;
855}
856
857/* Set TS parallel mode */
858static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
859 u8 system)
860{
861 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
862
863 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
864 /* Set SLV-T Bank : 0x00 */
865 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
866 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
867 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
868 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
869 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
870 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
871
872 /*
873 * slave Bank Addr Bit default Name
874 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
875 */
876 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
877 /*
878 * Disable TS IF Clock
879 * slave Bank Addr Bit default Name
880 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
881 */
882 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
883 /*
884 * slave Bank Addr Bit default Name
885 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
886 */
887 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
888 /*
889 * Enable TS IF Clock
890 * slave Bank Addr Bit default Name
891 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
892 */
893 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
894
895 if (system == SYS_DVBT) {
896 /* Enable parity period for DVB-T */
897 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
898 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
899 } else if (system == SYS_DVBC_ANNEX_A) {
900 /* Enable parity period for DVB-C */
901 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
902 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
903 }
904}
905
906static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
907{
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]908 u8 chip_id = 0;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]909
910 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]911 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
912 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
913 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
914 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
915
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]916 return chip_id;
917}
918
919static int cxd2841er_read_status_s(struct dvb_frontend *fe,
920 enum fe_status *status)
921{
922 u8 reg = 0;
923 struct cxd2841er_priv *priv = fe->demodulator_priv;
924
925 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
926 *status = 0;
927 if (priv->state != STATE_ACTIVE_S) {
928 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
929 __func__, priv->state);
930 return -EINVAL;
931 }
932 /* Set SLV-T Bank : 0xA0 */
933 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
934 /*
935 * slave Bank Addr Bit Signal name
936 * <SLV-T> A0h 11h [2] ITSLOCK
937 */
938 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
939 if (reg & 0x04) {
940 *status = FE_HAS_SIGNAL
941 | FE_HAS_CARRIER
942 | FE_HAS_VITERBI
943 | FE_HAS_SYNC
944 | FE_HAS_LOCK;
945 }
946 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
947 return 0;
948}
949
950static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
951 u8 *sync, u8 *tslock, u8 *unlock)
952{
953 u8 data = 0;
954
955 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
956 if (priv->state != STATE_ACTIVE_TC)
957 return -EINVAL;
958 if (priv->system == SYS_DVBT) {
959 /* Set SLV-T Bank : 0x10 */
960 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
961 } else {
962 /* Set SLV-T Bank : 0x20 */
963 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
964 }
965 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
966 if ((data & 0x07) == 0x07) {
967 dev_dbg(&priv->i2c->dev,
968 "%s(): invalid hardware state detected\n", __func__);
969 *sync = 0;
970 *tslock = 0;
971 *unlock = 0;
972 } else {
973 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
974 *tslock = ((data & 0x20) ? 1 : 0);
975 *unlock = ((data & 0x10) ? 1 : 0);
976 }
977 return 0;
978}
979
980static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
981{
982 u8 data;
983
984 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
985 if (priv->state != STATE_ACTIVE_TC)
986 return -EINVAL;
987 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
988 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
989 if ((data & 0x01) == 0) {
990 *tslock = 0;
991 } else {
992 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
993 *tslock = ((data & 0x20) ? 1 : 0);
994 }
995 return 0;
996}
997
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]998static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
999 u8 *sync, u8 *tslock, u8 *unlock)
1000{
1001 u8 data = 0;
1002
1003 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1004 if (priv->state != STATE_ACTIVE_TC)
1005 return -EINVAL;
1006 /* Set SLV-T Bank : 0x60 */
1007 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1008 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1009 dev_dbg(&priv->i2c->dev,
1010 "%s(): lock=0x%x\n", __func__, data);
1011 *sync = ((data & 0x02) ? 1 : 0);
1012 *tslock = ((data & 0x01) ? 1 : 0);
1013 *unlock = ((data & 0x10) ? 1 : 0);
1014 return 0;
1015}
1016
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1017static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1018 enum fe_status *status)
1019{
1020 int ret = 0;
1021 u8 sync = 0;
1022 u8 tslock = 0;
1023 u8 unlock = 0;
1024 struct cxd2841er_priv *priv = fe->demodulator_priv;
1025
1026 *status = 0;
1027 if (priv->state == STATE_ACTIVE_TC) {
1028 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1029 ret = cxd2841er_read_status_t_t2(
1030 priv, &sync, &tslock, &unlock);
1031 if (ret)
1032 goto done;
1033 if (unlock)
1034 goto done;
1035 if (sync)
1036 *status = FE_HAS_SIGNAL |
1037 FE_HAS_CARRIER |
1038 FE_HAS_VITERBI |
1039 FE_HAS_SYNC;
1040 if (tslock)
1041 *status |= FE_HAS_LOCK;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1042 } else if (priv->system == SYS_ISDBT) {
1043 ret = cxd2841er_read_status_i(
1044 priv, &sync, &tslock, &unlock);
1045 if (ret)
1046 goto done;
1047 if (unlock)
1048 goto done;
1049 if (sync)
1050 *status = FE_HAS_SIGNAL |
1051 FE_HAS_CARRIER |
1052 FE_HAS_VITERBI |
1053 FE_HAS_SYNC;
1054 if (tslock)
1055 *status |= FE_HAS_LOCK;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1056 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1057 ret = cxd2841er_read_status_c(priv, &tslock);
1058 if (ret)
1059 goto done;
1060 if (tslock)
1061 *status = FE_HAS_SIGNAL |
1062 FE_HAS_CARRIER |
1063 FE_HAS_VITERBI |
1064 FE_HAS_SYNC |
1065 FE_HAS_LOCK;
1066 }
1067 }
1068done:
1069 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1070 return ret;
1071}
1072
1073static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1074 int *offset)
1075{
1076 u8 data[3];
1077 u8 is_hs_mode;
1078 s32 cfrl_ctrlval;
1079 s32 temp_div, temp_q, temp_r;
1080
1081 if (priv->state != STATE_ACTIVE_S) {
1082 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1083 __func__, priv->state);
1084 return -EINVAL;
1085 }
1086 /*
1087 * Get High Sampling Rate mode
1088 * slave Bank Addr Bit Signal name
1089 * <SLV-T> A0h 10h [0] ITRL_LOCK
1090 */
1091 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1092 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1093 if (data[0] & 0x01) {
1094 /*
1095 * slave Bank Addr Bit Signal name
1096 * <SLV-T> A0h 50h [4] IHSMODE
1097 */
1098 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1099 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1100 } else {
1101 dev_dbg(&priv->i2c->dev,
1102 "%s(): unable to detect sampling rate mode\n",
1103 __func__);
1104 return -EINVAL;
1105 }
1106 /*
1107 * slave Bank Addr Bit Signal name
1108 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1109 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1110 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1111 */
1112 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1113 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1114 (((u32)data[1] & 0xFF) << 8) |
1115 ((u32)data[2] & 0xFF), 20);
1116 temp_div = (is_hs_mode ? 1048576 : 1572864);
1117 if (cfrl_ctrlval > 0) {
1118 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1119 temp_div, &temp_r);
1120 } else {
1121 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1122 temp_div, &temp_r);
1123 }
1124 if (temp_r >= temp_div / 2)
1125 temp_q++;
1126 if (cfrl_ctrlval > 0)
1127 temp_q *= -1;
1128 *offset = temp_q;
1129 return 0;
1130}
1131
Mauro Carvalho Chehab76344a3f2016-05-04 18:25:38 -0300[diff] [blame]1132static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1133 u32 bandwidth, int *offset)
1134{
1135 u8 data[4];
1136
1137 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1138 if (priv->state != STATE_ACTIVE_TC) {
1139 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1140 __func__, priv->state);
1141 return -EINVAL;
1142 }
1143 if (priv->system != SYS_ISDBT) {
1144 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1145 __func__, priv->system);
1146 return -EINVAL;
1147 }
1148 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1149 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1150 *offset = -1 * sign_extend32(
1151 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1152 ((u32)data[2] << 8) | (u32)data[3], 29);
1153
1154 switch (bandwidth) {
1155 case 6000000:
1156 *offset = -1 * ((*offset) * 8/264);
1157 break;
1158 case 7000000:
1159 *offset = -1 * ((*offset) * 8/231);
1160 break;
1161 case 8000000:
1162 *offset = -1 * ((*offset) * 8/198);
1163 break;
1164 default:
1165 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1166 __func__, bandwidth);
1167 return -EINVAL;
1168 }
1169
1170 dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1171 __func__, bandwidth, *offset);
1172
1173 return 0;
1174}
1175
Abylay Ospanc5ea46d2016-04-02 23:31:50 -0300[diff] [blame]1176static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1177 u32 bandwidth, int *offset)
1178{
1179 u8 data[4];
1180
1181 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1182 if (priv->state != STATE_ACTIVE_TC) {
1183 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1184 __func__, priv->state);
1185 return -EINVAL;
1186 }
1187 if (priv->system != SYS_DVBT) {
1188 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1189 __func__, priv->system);
1190 return -EINVAL;
1191 }
1192 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1193 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1194 *offset = -1 * sign_extend32(
1195 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1196 ((u32)data[2] << 8) | (u32)data[3], 29);
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1197 *offset *= (bandwidth / 1000000);
1198 *offset /= 235;
Abylay Ospanc5ea46d2016-04-02 23:31:50 -0300[diff] [blame]1199 return 0;
1200}
1201
Mauro Carvalho Chehabc8946c82015-08-11 15:08:47 -0300[diff] [blame]1202static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1203 u32 bandwidth, int *offset)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1204{
1205 u8 data[4];
1206
1207 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1208 if (priv->state != STATE_ACTIVE_TC) {
1209 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1210 __func__, priv->state);
1211 return -EINVAL;
1212 }
1213 if (priv->system != SYS_DVBT2) {
1214 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1215 __func__, priv->system);
1216 return -EINVAL;
1217 }
1218 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1219 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1220 *offset = -1 * sign_extend32(
1221 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1222 ((u32)data[2] << 8) | (u32)data[3], 27);
1223 switch (bandwidth) {
1224 case 1712000:
1225 *offset /= 582;
1226 break;
1227 case 5000000:
1228 case 6000000:
1229 case 7000000:
1230 case 8000000:
1231 *offset *= (bandwidth / 1000000);
1232 *offset /= 940;
1233 break;
1234 default:
1235 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1236 __func__, bandwidth);
1237 return -EINVAL;
1238 }
1239 return 0;
1240}
1241
Mauro Carvalho Chehabc8946c82015-08-11 15:08:47 -0300[diff] [blame]1242static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1243 int *offset)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1244{
1245 u8 data[2];
1246
1247 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1248 if (priv->state != STATE_ACTIVE_TC) {
1249 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1250 __func__, priv->state);
1251 return -EINVAL;
1252 }
1253 if (priv->system != SYS_DVBC_ANNEX_A) {
1254 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1255 __func__, priv->system);
1256 return -EINVAL;
1257 }
1258 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1259 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1260 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1261 | (u32)data[1], 13), 16384);
1262 return 0;
1263}
1264
1265static int cxd2841er_read_packet_errors_t(
1266 struct cxd2841er_priv *priv, u32 *penum)
1267{
1268 u8 data[3];
1269
1270 *penum = 0;
1271 if (priv->state != STATE_ACTIVE_TC) {
1272 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1273 __func__, priv->state);
1274 return -EINVAL;
1275 }
1276 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1277 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1278 if (data[2] & 0x01)
1279 *penum = ((u32)data[0] << 8) | (u32)data[1];
1280 return 0;
1281}
1282
1283static int cxd2841er_read_packet_errors_t2(
1284 struct cxd2841er_priv *priv, u32 *penum)
1285{
1286 u8 data[3];
1287
1288 *penum = 0;
1289 if (priv->state != STATE_ACTIVE_TC) {
1290 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1291 __func__, priv->state);
1292 return -EINVAL;
1293 }
1294 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1295 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1296 if (data[0] & 0x01)
1297 *penum = ((u32)data[1] << 8) | (u32)data[2];
1298 return 0;
1299}
1300
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1301static int cxd2841er_read_packet_errors_i(
1302 struct cxd2841er_priv *priv, u32 *penum)
1303{
1304 u8 data[2];
1305
1306 *penum = 0;
1307 if (priv->state != STATE_ACTIVE_TC) {
1308 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1309 __func__, priv->state);
1310 return -EINVAL;
1311 }
1312 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1313 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1314
1315 if (!(data[0] & 0x01))
1316 return 0;
1317
1318 /* Layer A */
1319 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1320 *penum = ((u32)data[0] << 8) | (u32)data[1];
1321
1322 /* Layer B */
1323 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1324 *penum += ((u32)data[0] << 8) | (u32)data[1];
1325
1326 /* Layer C */
1327 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1328 *penum += ((u32)data[0] << 8) | (u32)data[1];
1329
1330 return 0;
1331}
1332
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1333static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1334 u32 *bit_error, u32 *bit_count)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1335{
1336 u8 data[11];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1337
1338 /* Set SLV-T Bank : 0xA0 */
1339 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1340 /*
1341 * slave Bank Addr Bit Signal name
1342 * <SLV-T> A0h 35h [0] IFVBER_VALID
1343 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1344 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1345 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1346 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1347 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1348 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1349 */
1350 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1351 if (data[0] & 0x01) {
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1352 *bit_error = ((u32)(data[1] & 0x3F) << 16) |
1353 ((u32)(data[2] & 0xFF) << 8) |
1354 (u32)(data[3] & 0xFF);
1355 *bit_count = ((u32)(data[8] & 0x3F) << 16) |
1356 ((u32)(data[9] & 0xFF) << 8) |
1357 (u32)(data[10] & 0xFF);
1358 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1359 dev_dbg(&priv->i2c->dev,
1360 "%s(): invalid bit_error %d, bit_count %d\n",
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1361 __func__, *bit_error, *bit_count);
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1362 return -EINVAL;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1363 }
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1364 return 0;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1365 }
1366 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1367 return -EINVAL;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1368}
1369
1370
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1371static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1372 u32 *bit_error, u32 *bit_count)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1373{
1374 u8 data[5];
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1375 u32 period;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1376
1377 /* Set SLV-T Bank : 0xB2 */
1378 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1379 /*
1380 * slave Bank Addr Bit Signal name
1381 * <SLV-T> B2h 30h [0] IFLBER_VALID
1382 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1383 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1384 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1385 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1386 */
1387 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1388 if (data[0] & 0x01) {
1389 /* Bit error count */
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1390 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1391 ((u32)(data[2] & 0xFF) << 16) |
1392 ((u32)(data[3] & 0xFF) << 8) |
1393 (u32)(data[4] & 0xFF);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1394
1395 /* Set SLV-T Bank : 0xA0 */
1396 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1397 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1398 /* Measurement period */
1399 period = (u32)(1 << (data[0] & 0x0F));
1400 if (period == 0) {
1401 dev_dbg(&priv->i2c->dev,
1402 "%s(): period is 0\n", __func__);
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1403 return -EINVAL;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1404 }
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1405 if (*bit_error > (period * 64800)) {
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1406 dev_dbg(&priv->i2c->dev,
1407 "%s(): invalid bit_err 0x%x period 0x%x\n",
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1408 __func__, *bit_error, period);
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1409 return -EINVAL;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1410 }
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1411 *bit_count = period * 64800;
1412
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1413 return 0;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1414 } else {
1415 dev_dbg(&priv->i2c->dev,
1416 "%s(): no data available\n", __func__);
1417 }
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1418 return -EINVAL;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1419}
1420
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1421static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1422 u32 *bit_error, u32 *bit_count)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1423{
1424 u8 data[4];
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1425 u32 period_exp, n_ldpc;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1426
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1427 if (priv->state != STATE_ACTIVE_TC) {
1428 dev_dbg(&priv->i2c->dev,
1429 "%s(): invalid state %d\n", __func__, priv->state);
1430 return -EINVAL;
1431 }
1432 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1433 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1434 if (!(data[0] & 0x10)) {
1435 dev_dbg(&priv->i2c->dev,
1436 "%s(): no valid BER data\n", __func__);
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1437 return -EINVAL;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1438 }
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1439 *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1440 ((u32)data[1] << 16) |
1441 ((u32)data[2] << 8) |
1442 (u32)data[3];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1443 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1444 period_exp = data[0] & 0x0f;
1445 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1446 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1447 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1448 if (*bit_error > ((1U << period_exp) * n_ldpc)) {
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1449 dev_dbg(&priv->i2c->dev,
1450 "%s(): invalid BER value\n", __func__);
1451 return -EINVAL;
1452 }
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1453
1454 /*
1455 * FIXME: the right thing would be to return bit_error untouched,
1456 * but, as we don't know the scale returned by the counters, let's
1457 * at least preserver BER = bit_error/bit_count.
1458 */
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1459 if (period_exp >= 4) {
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1460 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1461 *bit_error *= 3125ULL;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1462 } else {
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1463 *bit_count = (1U << period_exp) * (n_ldpc / 200);
1464 *bit_error *= 50000ULL;;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1465 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1466 return 0;
1467}
1468
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1469static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1470 u32 *bit_error, u32 *bit_count)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1471{
1472 u8 data[2];
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1473 u32 period;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1474
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1475 if (priv->state != STATE_ACTIVE_TC) {
1476 dev_dbg(&priv->i2c->dev,
1477 "%s(): invalid state %d\n", __func__, priv->state);
1478 return -EINVAL;
1479 }
1480 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1481 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1482 if (!(data[0] & 0x01)) {
1483 dev_dbg(&priv->i2c->dev,
1484 "%s(): no valid BER data\n", __func__);
1485 return 0;
1486 }
1487 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1488 *bit_error = ((u32)data[0] << 8) | (u32)data[1];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1489 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1490 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1491
1492 /*
1493 * FIXME: the right thing would be to return bit_error untouched,
1494 * but, as we don't know the scale returned by the counters, let's
1495 * at least preserver BER = bit_error/bit_count.
1496 */
1497 *bit_count = period / 128;
1498 *bit_error *= 78125ULL;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1499 return 0;
1500}
1501
1502static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1503{
1504 u8 data[3];
1505 u32 res = 0, value;
1506 int min_index, max_index, index;
1507 static const struct cxd2841er_cnr_data *cn_data;
1508
1509 /* Set SLV-T Bank : 0xA1 */
1510 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1511 /*
1512 * slave Bank Addr Bit Signal name
1513 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1514 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1515 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1516 */
1517 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1518 if (data[0] & 0x01) {
1519 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1520 min_index = 0;
1521 if (delsys == SYS_DVBS) {
1522 cn_data = s_cn_data;
1523 max_index = sizeof(s_cn_data) /
1524 sizeof(s_cn_data[0]) - 1;
1525 } else {
1526 cn_data = s2_cn_data;
1527 max_index = sizeof(s2_cn_data) /
1528 sizeof(s2_cn_data[0]) - 1;
1529 }
1530 if (value >= cn_data[min_index].value) {
1531 res = cn_data[min_index].cnr_x1000;
1532 goto done;
1533 }
1534 if (value <= cn_data[max_index].value) {
1535 res = cn_data[max_index].cnr_x1000;
1536 goto done;
1537 }
1538 while ((max_index - min_index) > 1) {
1539 index = (max_index + min_index) / 2;
1540 if (value == cn_data[index].value) {
1541 res = cn_data[index].cnr_x1000;
1542 goto done;
1543 } else if (value > cn_data[index].value)
1544 max_index = index;
1545 else
1546 min_index = index;
1547 if ((max_index - min_index) <= 1) {
1548 if (value == cn_data[max_index].value) {
1549 res = cn_data[max_index].cnr_x1000;
1550 goto done;
1551 } else {
1552 res = cn_data[min_index].cnr_x1000;
1553 goto done;
1554 }
1555 }
1556 }
1557 } else {
1558 dev_dbg(&priv->i2c->dev,
1559 "%s(): no data available\n", __func__);
1560 }
1561done:
1562 return res;
1563}
1564
1565static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1566{
1567 u32 reg;
1568 u8 data[2];
1569
1570 *snr = 0;
1571 if (priv->state != STATE_ACTIVE_TC) {
1572 dev_dbg(&priv->i2c->dev,
1573 "%s(): invalid state %d\n", __func__, priv->state);
1574 return -EINVAL;
1575 }
1576 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1577 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1578 reg = ((u32)data[0] << 8) | (u32)data[1];
1579 if (reg == 0) {
1580 dev_dbg(&priv->i2c->dev,
1581 "%s(): reg value out of range\n", __func__);
1582 return 0;
1583 }
1584 if (reg > 4996)
1585 reg = 4996;
1586 *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1587 return 0;
1588}
1589
Mauro Carvalho Chehabc8946c82015-08-11 15:08:47 -0300[diff] [blame]1590static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1591{
1592 u32 reg;
1593 u8 data[2];
1594
1595 *snr = 0;
1596 if (priv->state != STATE_ACTIVE_TC) {
1597 dev_dbg(&priv->i2c->dev,
1598 "%s(): invalid state %d\n", __func__, priv->state);
1599 return -EINVAL;
1600 }
1601 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1602 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1603 reg = ((u32)data[0] << 8) | (u32)data[1];
1604 if (reg == 0) {
1605 dev_dbg(&priv->i2c->dev,
1606 "%s(): reg value out of range\n", __func__);
1607 return 0;
1608 }
1609 if (reg > 10876)
1610 reg = 10876;
1611 *snr = 10000 * ((intlog10(reg) -
1612 intlog10(12600 - reg)) >> 24) + 32000;
1613 return 0;
1614}
1615
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1616static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1617{
1618 u32 reg;
1619 u8 data[2];
1620
1621 *snr = 0;
1622 if (priv->state != STATE_ACTIVE_TC) {
1623 dev_dbg(&priv->i2c->dev,
1624 "%s(): invalid state %d\n", __func__,
1625 priv->state);
1626 return -EINVAL;
1627 }
1628
1629 /* Freeze all registers */
1630 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1631
1632
1633 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1634 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1635 reg = ((u32)data[0] << 8) | (u32)data[1];
1636 if (reg == 0) {
1637 dev_dbg(&priv->i2c->dev,
1638 "%s(): reg value out of range\n", __func__);
1639 return 0;
1640 }
1641 if (reg > 4996)
1642 reg = 4996;
1643 *snr = 100 * intlog10(reg) - 9031;
1644 return 0;
1645}
1646
Abylay Ospand0998ce2016-06-30 23:09:48 -0300[diff] [blame]1647static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1648 u8 delsys)
1649{
1650 u8 data[2];
1651
1652 cxd2841er_write_reg(
1653 priv, I2C_SLVT, 0x00, 0x40);
1654 cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1655 dev_dbg(&priv->i2c->dev,
1656 "%s(): AGC value=%u\n",
1657 __func__, (((u16)data[0] & 0x0F) << 8) |
1658 (u16)(data[1] & 0xFF));
1659 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1660}
1661
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1662static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1663 u8 delsys)
1664{
1665 u8 data[2];
1666
1667 cxd2841er_write_reg(
1668 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1669 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
Abylay Ospanc5ea46d2016-04-02 23:31:50 -0300[diff] [blame]1670 dev_dbg(&priv->i2c->dev,
1671 "%s(): AGC value=%u\n",
1672 __func__, (((u16)data[0] & 0x0F) << 8) |
1673 (u16)(data[1] & 0xFF));
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1674 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1675}
1676
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1677static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1678 u8 delsys)
1679{
1680 u8 data[2];
1681
1682 cxd2841er_write_reg(
1683 priv, I2C_SLVT, 0x00, 0x60);
1684 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1685
1686 dev_dbg(&priv->i2c->dev,
1687 "%s(): AGC value=%u\n",
1688 __func__, (((u16)data[0] & 0x0F) << 8) |
1689 (u16)(data[1] & 0xFF));
1690 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1691}
1692
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1693static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1694{
1695 u8 data[2];
1696
1697 /* Set SLV-T Bank : 0xA0 */
1698 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1699 /*
1700 * slave Bank Addr Bit Signal name
1701 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1702 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1703 */
1704 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1705 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1706}
1707
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1708static void cxd2841er_read_ber(struct dvb_frontend *fe)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1709{
1710 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1711 struct cxd2841er_priv *priv = fe->demodulator_priv;
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1712 u32 ret, bit_error = 0, bit_count = 0;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1713
1714 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1715 switch (p->delivery_system) {
1716 case SYS_DVBS:
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1717 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1718 break;
1719 case SYS_DVBS2:
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1720 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1721 break;
1722 case SYS_DVBT:
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1723 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1724 break;
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1725 case SYS_DVBT2:
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1726 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1727 break;
1728 default:
1729 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1730 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1731 return;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1732 }
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1733
1734 if (!ret) {
1735 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1736 p->post_bit_error.stat[0].uvalue = bit_error;
1737 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1738 p->post_bit_count.stat[0].uvalue = bit_count;
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1739 } else {
1740 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]1741 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1742 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1743}
1744
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame]1745static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1746{
1747 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1748 struct cxd2841er_priv *priv = fe->demodulator_priv;
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame]1749 u32 strength;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1750
1751 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1752 switch (p->delivery_system) {
Abylay Ospand0998ce2016-06-30 23:09:48 -0300[diff] [blame]1753 case SYS_DVBC_ANNEX_A:
1754 case SYS_DVBC_ANNEX_B:
1755 case SYS_DVBC_ANNEX_C:
1756 strength = 65535 - cxd2841er_read_agc_gain_c(
1757 priv, p->delivery_system);
1758 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1759 p->strength.stat[0].uvalue = strength;
1760 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1761 case SYS_DVBT:
1762 case SYS_DVBT2:
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame]1763 strength = cxd2841er_read_agc_gain_t_t2(priv,
1764 p->delivery_system);
1765 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1766 /* Formula was empirically determinated @ 410 MHz */
1767 p->strength.stat[0].uvalue = ((s32)strength) * 366 / 100 - 89520;
1768 break; /* Code moved out of the function */
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1769 case SYS_ISDBT:
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame]1770 strength = 65535 - cxd2841er_read_agc_gain_i(
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1771 priv, p->delivery_system);
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame]1772 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1773 p->strength.stat[0].uvalue = strength;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1774 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1775 case SYS_DVBS:
1776 case SYS_DVBS2:
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame]1777 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1778 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1779 p->strength.stat[0].uvalue = strength;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1780 break;
1781 default:
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1782 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1783 break;
1784 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1785}
1786
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1787static void cxd2841er_read_snr(struct dvb_frontend *fe)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1788{
1789 u32 tmp = 0;
1790 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1791 struct cxd2841er_priv *priv = fe->demodulator_priv;
1792
1793 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1794 switch (p->delivery_system) {
1795 case SYS_DVBT:
1796 cxd2841er_read_snr_t(priv, &tmp);
1797 break;
1798 case SYS_DVBT2:
1799 cxd2841er_read_snr_t2(priv, &tmp);
1800 break;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1801 case SYS_ISDBT:
1802 cxd2841er_read_snr_i(priv, &tmp);
1803 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1804 case SYS_DVBS:
1805 case SYS_DVBS2:
1806 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1807 break;
1808 default:
1809 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1810 __func__, p->delivery_system);
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1811 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1812 return;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1813 }
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1814
1815 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1816 p->cnr.stat[0].svalue = tmp;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1817}
1818
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1819static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1820{
1821 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1822 struct cxd2841er_priv *priv = fe->demodulator_priv;
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1823 u32 ucblocks;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1824
1825 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1826 switch (p->delivery_system) {
1827 case SYS_DVBT:
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1828 cxd2841er_read_packet_errors_t(priv, &ucblocks);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1829 break;
1830 case SYS_DVBT2:
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1831 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1832 break;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1833 case SYS_ISDBT:
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1834 cxd2841er_read_packet_errors_i(priv, &ucblocks);
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]1835 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1836 default:
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1837 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1838 return;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1839 }
1840 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]1841
1842 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
1843 p->block_error.stat[0].uvalue = ucblocks;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1844}
1845
1846static int cxd2841er_dvbt2_set_profile(
1847 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1848{
1849 u8 tune_mode;
1850 u8 seq_not2d_time;
1851
1852 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1853 switch (profile) {
1854 case DVBT2_PROFILE_BASE:
1855 tune_mode = 0x01;
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1856 /* Set early unlock time */
1857 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1858 break;
1859 case DVBT2_PROFILE_LITE:
1860 tune_mode = 0x05;
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1861 /* Set early unlock time */
1862 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1863 break;
1864 case DVBT2_PROFILE_ANY:
1865 tune_mode = 0x00;
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1866 /* Set early unlock time */
1867 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1868 break;
1869 default:
1870 return -EINVAL;
1871 }
1872 /* Set SLV-T Bank : 0x2E */
1873 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1874 /* Set profile and tune mode */
1875 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1876 /* Set SLV-T Bank : 0x2B */
1877 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1878 /* Set early unlock detection time */
1879 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1880 return 0;
1881}
1882
1883static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1884 u8 is_auto, u8 plp_id)
1885{
1886 if (is_auto) {
1887 dev_dbg(&priv->i2c->dev,
1888 "%s() using auto PLP selection\n", __func__);
1889 } else {
1890 dev_dbg(&priv->i2c->dev,
1891 "%s() using manual PLP selection, ID %d\n",
1892 __func__, plp_id);
1893 }
1894 /* Set SLV-T Bank : 0x23 */
1895 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1896 if (!is_auto) {
1897 /* Manual PLP selection mode. Set the data PLP Id. */
1898 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1899 }
1900 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1901 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1902 return 0;
1903}
1904
1905static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1906 u32 bandwidth)
1907{
1908 u32 iffreq;
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1909 u8 data[MAX_WRITE_REGSIZE];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1910
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1911 const uint8_t nominalRate8bw[3][5] = {
1912 /* TRCG Nominal Rate [37:0] */
1913 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1914 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1915 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
1916 };
1917
1918 const uint8_t nominalRate7bw[3][5] = {
1919 /* TRCG Nominal Rate [37:0] */
1920 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1921 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1922 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
1923 };
1924
1925 const uint8_t nominalRate6bw[3][5] = {
1926 /* TRCG Nominal Rate [37:0] */
1927 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
1928 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1929 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
1930 };
1931
1932 const uint8_t nominalRate5bw[3][5] = {
1933 /* TRCG Nominal Rate [37:0] */
1934 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
1935 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
1936 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
1937 };
1938
1939 const uint8_t nominalRate17bw[3][5] = {
1940 /* TRCG Nominal Rate [37:0] */
1941 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
1942 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
1943 {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */
1944 };
1945
1946 const uint8_t itbCoef8bw[3][14] = {
1947 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1948 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
1949 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
1950 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
1951 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1952 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
1953 };
1954
1955 const uint8_t itbCoef7bw[3][14] = {
1956 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1957 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
1958 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
1959 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
1960 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1961 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
1962 };
1963
1964 const uint8_t itbCoef6bw[3][14] = {
1965 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1966 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1967 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1968 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
1969 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1970 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
1971 };
1972
1973 const uint8_t itbCoef5bw[3][14] = {
1974 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1975 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1976 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1977 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
1978 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1979 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
1980 };
1981
1982 const uint8_t itbCoef17bw[3][14] = {
1983 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
1984 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
1985 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
1986 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */
1987 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
1988 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */
1989 };
1990
1991 /* Set SLV-T Bank : 0x20 */
1992 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1993
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1994 switch (bandwidth) {
1995 case 8000000:
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]1996 /* <Timing Recovery setting> */
1997 cxd2841er_write_regs(priv, I2C_SLVT,
1998 0x9F, nominalRate8bw[priv->xtal], 5);
1999
2000 /* Set SLV-T Bank : 0x27 */
2001 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2002 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2003 0x7a, 0x00, 0x0f);
2004
2005 /* Set SLV-T Bank : 0x10 */
2006 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2007
2008 /* Group delay equaliser settings for
2009 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2010 */
2011 cxd2841er_write_regs(priv, I2C_SLVT,
2012 0xA6, itbCoef8bw[priv->xtal], 14);
2013 /* <IF freq setting> */
2014 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2015 data[0] = (u8) ((iffreq >> 16) & 0xff);
2016 data[1] = (u8)((iffreq >> 8) & 0xff);
2017 data[2] = (u8)(iffreq & 0xff);
2018 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2019 /* System bandwidth setting */
2020 cxd2841er_set_reg_bits(
2021 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2022 break;
2023 case 7000000:
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2024 /* <Timing Recovery setting> */
2025 cxd2841er_write_regs(priv, I2C_SLVT,
2026 0x9F, nominalRate7bw[priv->xtal], 5);
2027
2028 /* Set SLV-T Bank : 0x27 */
2029 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2030 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2031 0x7a, 0x00, 0x0f);
2032
2033 /* Set SLV-T Bank : 0x10 */
2034 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2035
2036 /* Group delay equaliser settings for
2037 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2038 */
2039 cxd2841er_write_regs(priv, I2C_SLVT,
2040 0xA6, itbCoef7bw[priv->xtal], 14);
2041 /* <IF freq setting> */
2042 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2043 data[0] = (u8) ((iffreq >> 16) & 0xff);
2044 data[1] = (u8)((iffreq >> 8) & 0xff);
2045 data[2] = (u8)(iffreq & 0xff);
2046 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2047 /* System bandwidth setting */
2048 cxd2841er_set_reg_bits(
2049 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2050 break;
2051 case 6000000:
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2052 /* <Timing Recovery setting> */
2053 cxd2841er_write_regs(priv, I2C_SLVT,
2054 0x9F, nominalRate6bw[priv->xtal], 5);
2055
2056 /* Set SLV-T Bank : 0x27 */
2057 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2058 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2059 0x7a, 0x00, 0x0f);
2060
2061 /* Set SLV-T Bank : 0x10 */
2062 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2063
2064 /* Group delay equaliser settings for
2065 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2066 */
2067 cxd2841er_write_regs(priv, I2C_SLVT,
2068 0xA6, itbCoef6bw[priv->xtal], 14);
2069 /* <IF freq setting> */
2070 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2071 data[0] = (u8) ((iffreq >> 16) & 0xff);
2072 data[1] = (u8)((iffreq >> 8) & 0xff);
2073 data[2] = (u8)(iffreq & 0xff);
2074 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2075 /* System bandwidth setting */
2076 cxd2841er_set_reg_bits(
2077 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2078 break;
2079 case 5000000:
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2080 /* <Timing Recovery setting> */
2081 cxd2841er_write_regs(priv, I2C_SLVT,
2082 0x9F, nominalRate5bw[priv->xtal], 5);
2083
2084 /* Set SLV-T Bank : 0x27 */
2085 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2086 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2087 0x7a, 0x00, 0x0f);
2088
2089 /* Set SLV-T Bank : 0x10 */
2090 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2091
2092 /* Group delay equaliser settings for
2093 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2094 */
2095 cxd2841er_write_regs(priv, I2C_SLVT,
2096 0xA6, itbCoef5bw[priv->xtal], 14);
2097 /* <IF freq setting> */
2098 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2099 data[0] = (u8) ((iffreq >> 16) & 0xff);
2100 data[1] = (u8)((iffreq >> 8) & 0xff);
2101 data[2] = (u8)(iffreq & 0xff);
2102 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2103 /* System bandwidth setting */
2104 cxd2841er_set_reg_bits(
2105 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2106 break;
2107 case 1712000:
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2108 /* <Timing Recovery setting> */
2109 cxd2841er_write_regs(priv, I2C_SLVT,
2110 0x9F, nominalRate17bw[priv->xtal], 5);
2111
2112 /* Set SLV-T Bank : 0x27 */
2113 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2114 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2115 0x7a, 0x03, 0x0f);
2116
2117 /* Set SLV-T Bank : 0x10 */
2118 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2119
2120 /* Group delay equaliser settings for
2121 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2122 */
2123 cxd2841er_write_regs(priv, I2C_SLVT,
2124 0xA6, itbCoef17bw[priv->xtal], 14);
2125 /* <IF freq setting> */
2126 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.50);
2127 data[0] = (u8) ((iffreq >> 16) & 0xff);
2128 data[1] = (u8)((iffreq >> 8) & 0xff);
2129 data[2] = (u8)(iffreq & 0xff);
2130 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2131 /* System bandwidth setting */
2132 cxd2841er_set_reg_bits(
2133 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2134 break;
2135 default:
2136 return -EINVAL;
2137 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2138 return 0;
2139}
2140
2141static int cxd2841er_sleep_tc_to_active_t_band(
2142 struct cxd2841er_priv *priv, u32 bandwidth)
2143{
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2144 u8 data[MAX_WRITE_REGSIZE];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2145 u32 iffreq;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2146 u8 nominalRate8bw[3][5] = {
2147 /* TRCG Nominal Rate [37:0] */
2148 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2149 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2150 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2151 };
2152 u8 nominalRate7bw[3][5] = {
2153 /* TRCG Nominal Rate [37:0] */
2154 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2155 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2156 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2157 };
2158 u8 nominalRate6bw[3][5] = {
2159 /* TRCG Nominal Rate [37:0] */
2160 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2161 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2162 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2163 };
2164 u8 nominalRate5bw[3][5] = {
2165 /* TRCG Nominal Rate [37:0] */
2166 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2167 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2168 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2169 };
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2170
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2171 u8 itbCoef8bw[3][14] = {
2172 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2173 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2174 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2175 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2176 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2177 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2178 };
2179 u8 itbCoef7bw[3][14] = {
2180 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2181 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2182 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2183 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2184 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2185 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2186 };
2187 u8 itbCoef6bw[3][14] = {
2188 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2189 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2190 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2191 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2192 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2193 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2194 };
2195 u8 itbCoef5bw[3][14] = {
2196 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2197 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2198 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2199 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2200 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2201 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2202 };
2203
2204 /* Set SLV-T Bank : 0x13 */
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2205 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2206 /* Echo performance optimization setting */
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2207 data[0] = 0x01;
2208 data[1] = 0x14;
2209 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2210
2211 /* Set SLV-T Bank : 0x10 */
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2212 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2213
2214 switch (bandwidth) {
2215 case 8000000:
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2216 /* <Timing Recovery setting> */
2217 cxd2841er_write_regs(priv, I2C_SLVT,
2218 0x9F, nominalRate8bw[priv->xtal], 5);
2219 /* Group delay equaliser settings for
2220 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2221 */
2222 cxd2841er_write_regs(priv, I2C_SLVT,
2223 0xA6, itbCoef8bw[priv->xtal], 14);
2224 /* <IF freq setting> */
2225 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2226 data[0] = (u8) ((iffreq >> 16) & 0xff);
2227 data[1] = (u8)((iffreq >> 8) & 0xff);
2228 data[2] = (u8)(iffreq & 0xff);
2229 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2230 /* System bandwidth setting */
2231 cxd2841er_set_reg_bits(
2232 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2233
2234 /* Demod core latency setting */
2235 if (priv->xtal == SONY_XTAL_24000) {
2236 data[0] = 0x15;
2237 data[1] = 0x28;
2238 } else {
2239 data[0] = 0x01;
2240 data[1] = 0xE0;
2241 }
2242 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2243
2244 /* Notch filter setting */
2245 data[0] = 0x01;
2246 data[1] = 0x02;
2247 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2248 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2249 break;
2250 case 7000000:
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2251 /* <Timing Recovery setting> */
2252 cxd2841er_write_regs(priv, I2C_SLVT,
2253 0x9F, nominalRate7bw[priv->xtal], 5);
2254 /* Group delay equaliser settings for
2255 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2256 */
2257 cxd2841er_write_regs(priv, I2C_SLVT,
2258 0xA6, itbCoef7bw[priv->xtal], 14);
2259 /* <IF freq setting> */
2260 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2261 data[0] = (u8) ((iffreq >> 16) & 0xff);
2262 data[1] = (u8)((iffreq >> 8) & 0xff);
2263 data[2] = (u8)(iffreq & 0xff);
2264 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2265 /* System bandwidth setting */
2266 cxd2841er_set_reg_bits(
2267 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2268
2269 /* Demod core latency setting */
2270 if (priv->xtal == SONY_XTAL_24000) {
2271 data[0] = 0x1F;
2272 data[1] = 0xF8;
2273 } else {
2274 data[0] = 0x12;
2275 data[1] = 0xF8;
2276 }
2277 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2278
2279 /* Notch filter setting */
2280 data[0] = 0x00;
2281 data[1] = 0x03;
2282 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2283 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2284 break;
2285 case 6000000:
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2286 /* <Timing Recovery setting> */
2287 cxd2841er_write_regs(priv, I2C_SLVT,
2288 0x9F, nominalRate6bw[priv->xtal], 5);
2289 /* Group delay equaliser settings for
2290 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2291 */
2292 cxd2841er_write_regs(priv, I2C_SLVT,
2293 0xA6, itbCoef6bw[priv->xtal], 14);
2294 /* <IF freq setting> */
2295 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2296 data[0] = (u8) ((iffreq >> 16) & 0xff);
2297 data[1] = (u8)((iffreq >> 8) & 0xff);
2298 data[2] = (u8)(iffreq & 0xff);
2299 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2300 /* System bandwidth setting */
2301 cxd2841er_set_reg_bits(
2302 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2303
2304 /* Demod core latency setting */
2305 if (priv->xtal == SONY_XTAL_24000) {
2306 data[0] = 0x25;
2307 data[1] = 0x4C;
2308 } else {
2309 data[0] = 0x1F;
2310 data[1] = 0xDC;
2311 }
2312 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2313
2314 /* Notch filter setting */
2315 data[0] = 0x00;
2316 data[1] = 0x03;
2317 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2318 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2319 break;
2320 case 5000000:
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2321 /* <Timing Recovery setting> */
2322 cxd2841er_write_regs(priv, I2C_SLVT,
2323 0x9F, nominalRate5bw[priv->xtal], 5);
2324 /* Group delay equaliser settings for
2325 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2326 */
2327 cxd2841er_write_regs(priv, I2C_SLVT,
2328 0xA6, itbCoef5bw[priv->xtal], 14);
2329 /* <IF freq setting> */
2330 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2331 data[0] = (u8) ((iffreq >> 16) & 0xff);
2332 data[1] = (u8)((iffreq >> 8) & 0xff);
2333 data[2] = (u8)(iffreq & 0xff);
2334 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2335 /* System bandwidth setting */
2336 cxd2841er_set_reg_bits(
2337 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2338
2339 /* Demod core latency setting */
2340 if (priv->xtal == SONY_XTAL_24000) {
2341 data[0] = 0x2C;
2342 data[1] = 0xC2;
2343 } else {
2344 data[0] = 0x26;
2345 data[1] = 0x3C;
2346 }
2347 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2348
2349 /* Notch filter setting */
2350 data[0] = 0x00;
2351 data[1] = 0x03;
2352 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2353 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2354 break;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2355 }
2356
2357 return 0;
2358}
2359
2360static int cxd2841er_sleep_tc_to_active_i_band(
2361 struct cxd2841er_priv *priv, u32 bandwidth)
2362{
2363 u32 iffreq;
2364 u8 data[3];
2365
2366 /* TRCG Nominal Rate */
2367 u8 nominalRate8bw[3][5] = {
2368 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2369 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2370 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2371 };
2372
2373 u8 nominalRate7bw[3][5] = {
2374 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2375 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2376 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2377 };
2378
2379 u8 nominalRate6bw[3][5] = {
2380 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2381 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2382 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2383 };
2384
2385 u8 itbCoef8bw[3][14] = {
2386 {0x00}, /* 20.5MHz XTal */
2387 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2388 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2389 {0x0}, /* 41MHz XTal */
2390 };
2391
2392 u8 itbCoef7bw[3][14] = {
2393 {0x00}, /* 20.5MHz XTal */
2394 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2395 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2396 {0x00}, /* 41MHz XTal */
2397 };
2398
2399 u8 itbCoef6bw[3][14] = {
2400 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2401 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2402 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2403 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2404 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2405 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2406 };
2407
2408 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2409 /* Set SLV-T Bank : 0x10 */
2410 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2411
2412 /* 20.5/41MHz Xtal support is not available
2413 * on ISDB-T 7MHzBW and 8MHzBW
2414 */
2415 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2416 dev_err(&priv->i2c->dev,
2417 "%s(): bandwidth %d supported only for 24MHz xtal\n",
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2418 __func__, bandwidth);
2419 return -EINVAL;
2420 }
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2421
2422 switch (bandwidth) {
2423 case 8000000:
2424 /* TRCG Nominal Rate */
2425 cxd2841er_write_regs(priv, I2C_SLVT,
2426 0x9F, nominalRate8bw[priv->xtal], 5);
2427 /* Group delay equaliser settings for ASCOT tuners optimized */
2428 cxd2841er_write_regs(priv, I2C_SLVT,
2429 0xA6, itbCoef8bw[priv->xtal], 14);
2430
2431 /* IF freq setting */
2432 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2433 data[0] = (u8) ((iffreq >> 16) & 0xff);
2434 data[1] = (u8)((iffreq >> 8) & 0xff);
2435 data[2] = (u8)(iffreq & 0xff);
2436 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2437
2438 /* System bandwidth setting */
2439 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2440
2441 /* Demod core latency setting */
2442 data[0] = 0x13;
2443 data[1] = 0xFC;
2444 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2445
2446 /* Acquisition optimization setting */
2447 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2448 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2449 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2450 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2451 break;
2452 case 7000000:
2453 /* TRCG Nominal Rate */
2454 cxd2841er_write_regs(priv, I2C_SLVT,
2455 0x9F, nominalRate7bw[priv->xtal], 5);
2456 /* Group delay equaliser settings for ASCOT tuners optimized */
2457 cxd2841er_write_regs(priv, I2C_SLVT,
2458 0xA6, itbCoef7bw[priv->xtal], 14);
2459
2460 /* IF freq setting */
2461 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2462 data[0] = (u8) ((iffreq >> 16) & 0xff);
2463 data[1] = (u8)((iffreq >> 8) & 0xff);
2464 data[2] = (u8)(iffreq & 0xff);
2465 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2466
2467 /* System bandwidth setting */
2468 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2469
2470 /* Demod core latency setting */
2471 data[0] = 0x1A;
2472 data[1] = 0xFA;
2473 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2474
2475 /* Acquisition optimization setting */
2476 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2477 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2478 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2479 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2480 break;
2481 case 6000000:
2482 /* TRCG Nominal Rate */
2483 cxd2841er_write_regs(priv, I2C_SLVT,
2484 0x9F, nominalRate6bw[priv->xtal], 5);
2485 /* Group delay equaliser settings for ASCOT tuners optimized */
2486 cxd2841er_write_regs(priv, I2C_SLVT,
2487 0xA6, itbCoef6bw[priv->xtal], 14);
2488
2489 /* IF freq setting */
2490 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2491 data[0] = (u8) ((iffreq >> 16) & 0xff);
2492 data[1] = (u8)((iffreq >> 8) & 0xff);
2493 data[2] = (u8)(iffreq & 0xff);
2494 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2495
2496 /* System bandwidth setting */
2497 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2498
2499 /* Demod core latency setting */
2500 if (priv->xtal == SONY_XTAL_24000) {
2501 data[0] = 0x1F;
2502 data[1] = 0x79;
2503 } else {
2504 data[0] = 0x1A;
2505 data[1] = 0xE2;
2506 }
2507 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2508
2509 /* Acquisition optimization setting */
2510 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2511 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2512 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2513 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2514 break;
2515 default:
2516 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2517 __func__, bandwidth);
2518 return -EINVAL;
2519 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2520 return 0;
2521}
2522
2523static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2524 u32 bandwidth)
2525{
2526 u8 bw7_8mhz_b10_a6[] = {
2527 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2528 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2529 u8 bw6mhz_b10_a6[] = {
2530 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2531 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2532 u8 b10_b6[3];
2533 u32 iffreq;
2534
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]2535 dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2536 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2537 switch (bandwidth) {
2538 case 8000000:
2539 case 7000000:
2540 cxd2841er_write_regs(
2541 priv, I2C_SLVT, 0xa6,
2542 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2543 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2544 break;
2545 case 6000000:
2546 cxd2841er_write_regs(
2547 priv, I2C_SLVT, 0xa6,
2548 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2549 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2550 break;
2551 default:
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]2552 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2553 __func__, bandwidth);
2554 return -EINVAL;
2555 }
2556 /* <IF freq setting> */
2557 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2558 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2559 b10_b6[2] = (u8)(iffreq & 0xff);
2560 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2561 /* Set SLV-T Bank : 0x11 */
2562 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2563 switch (bandwidth) {
2564 case 8000000:
2565 case 7000000:
2566 cxd2841er_set_reg_bits(
2567 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2568 break;
2569 case 6000000:
2570 cxd2841er_set_reg_bits(
2571 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2572 break;
2573 }
2574 /* Set SLV-T Bank : 0x40 */
2575 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2576 switch (bandwidth) {
2577 case 8000000:
2578 cxd2841er_set_reg_bits(
2579 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2580 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2581 break;
2582 case 7000000:
2583 cxd2841er_set_reg_bits(
2584 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2585 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2586 break;
2587 case 6000000:
2588 cxd2841er_set_reg_bits(
2589 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2590 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2591 break;
2592 }
2593 return 0;
2594}
2595
2596static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2597 u32 bandwidth)
2598{
2599 u8 data[2] = { 0x09, 0x54 };
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2600 u8 data24m[3] = {0xDC, 0x6C, 0x00};
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2601
2602 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2603 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2604 /* Set SLV-X Bank : 0x00 */
2605 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2606 /* Set demod mode */
2607 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2608 /* Set SLV-T Bank : 0x00 */
2609 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2610 /* Enable demod clock */
2611 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2612 /* Disable RF level monitor */
2613 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2614 /* Enable ADC clock */
2615 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2616 /* Enable ADC 1 */
2617 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2618 /* Enable ADC 2 & 3 */
2619 if (priv->xtal == SONY_XTAL_41000) {
2620 data[0] = 0x0A;
2621 data[1] = 0xD4;
2622 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2623 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2624 /* Enable ADC 4 */
2625 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2626 /* Set SLV-T Bank : 0x10 */
2627 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2628 /* IFAGC gain settings */
2629 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2630 /* Set SLV-T Bank : 0x11 */
2631 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2632 /* BBAGC TARGET level setting */
2633 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2634 /* Set SLV-T Bank : 0x10 */
2635 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2636 /* ASCOT setting ON */
2637 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2638 /* Set SLV-T Bank : 0x18 */
2639 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2640 /* Pre-RS BER moniter setting */
2641 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2642 /* FEC Auto Recovery setting */
2643 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2644 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2645 /* Set SLV-T Bank : 0x00 */
2646 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2647 /* TSIF setting */
2648 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2649 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2650
2651 if (priv->xtal == SONY_XTAL_24000) {
2652 /* Set SLV-T Bank : 0x10 */
2653 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2654 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2655 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2656 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2657 }
2658
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2659 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2660 /* Set SLV-T Bank : 0x00 */
2661 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2662 /* Disable HiZ Setting 1 */
2663 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2664 /* Disable HiZ Setting 2 */
2665 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2666 priv->state = STATE_ACTIVE_TC;
2667 return 0;
2668}
2669
2670static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2671 u32 bandwidth)
2672{
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2673 u8 data[MAX_WRITE_REGSIZE];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2674
2675 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2676 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2677 /* Set SLV-X Bank : 0x00 */
2678 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2679 /* Set demod mode */
2680 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2681 /* Set SLV-T Bank : 0x00 */
2682 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2683 /* Enable demod clock */
2684 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2685 /* Disable RF level monitor */
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2686 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2687 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2688 /* Enable ADC clock */
2689 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2690 /* Enable ADC 1 */
2691 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2692
2693 if (priv->xtal == SONY_XTAL_41000) {
2694 data[0] = 0x0A;
2695 data[1] = 0xD4;
2696 } else {
2697 data[0] = 0x09;
2698 data[1] = 0x54;
2699 }
2700
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2701 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2702 /* Enable ADC 4 */
2703 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2704 /* Set SLV-T Bank : 0x10 */
2705 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2706 /* IFAGC gain settings */
2707 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2708 /* Set SLV-T Bank : 0x11 */
2709 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2710 /* BBAGC TARGET level setting */
2711 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2712 /* Set SLV-T Bank : 0x10 */
2713 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2714 /* ASCOT setting ON */
2715 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2716 /* Set SLV-T Bank : 0x20 */
2717 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2718 /* Acquisition optimization setting */
2719 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2720 /* Set SLV-T Bank : 0x2b */
2721 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2722 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2723 /* Set SLV-T Bank : 0x23 */
2724 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2725 /* L1 Control setting */
2726 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2727 /* Set SLV-T Bank : 0x00 */
2728 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2729 /* TSIF setting */
2730 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2731 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2732 /* DVB-T2 initial setting */
2733 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2734 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2735 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2736 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2737 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2738 /* Set SLV-T Bank : 0x2a */
2739 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2740 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2741 /* Set SLV-T Bank : 0x2b */
2742 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2743 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2744
Abylay Ospan6c771612016-05-16 11:43:25 -0300[diff] [blame]2745 /* 24MHz Xtal setting */
2746 if (priv->xtal == SONY_XTAL_24000) {
2747 /* Set SLV-T Bank : 0x11 */
2748 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2749 data[0] = 0xEB;
2750 data[1] = 0x03;
2751 data[2] = 0x3B;
2752 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
2753
2754 /* Set SLV-T Bank : 0x20 */
2755 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2756 data[0] = 0x5E;
2757 data[1] = 0x5E;
2758 data[2] = 0x47;
2759 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
2760
2761 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
2762
2763 data[0] = 0x3F;
2764 data[1] = 0xFF;
2765 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2766
2767 /* Set SLV-T Bank : 0x24 */
2768 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
2769 data[0] = 0x0B;
2770 data[1] = 0x72;
2771 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
2772
2773 data[0] = 0x93;
2774 data[1] = 0xF3;
2775 data[2] = 0x00;
2776 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
2777
2778 data[0] = 0x05;
2779 data[1] = 0xB8;
2780 data[2] = 0xD8;
2781 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
2782
2783 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
2784
2785 /* Set SLV-T Bank : 0x25 */
2786 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
2787 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
2788
2789 /* Set SLV-T Bank : 0x27 */
2790 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2791 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
2792
2793 /* Set SLV-T Bank : 0x2B */
2794 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
2795 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
2796 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
2797
2798 /* Set SLV-T Bank : 0x2D */
2799 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
2800 data[0] = 0x89;
2801 data[1] = 0x89;
2802 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
2803
2804 /* Set SLV-T Bank : 0x5E */
2805 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
2806 data[0] = 0x24;
2807 data[1] = 0x95;
2808 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
2809 }
2810
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2811 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2812
2813 /* Set SLV-T Bank : 0x00 */
2814 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2815 /* Disable HiZ Setting 1 */
2816 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2817 /* Disable HiZ Setting 2 */
2818 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2819 priv->state = STATE_ACTIVE_TC;
2820 return 0;
2821}
2822
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2823/* ISDB-Tb part */
2824static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
2825 u32 bandwidth)
2826{
2827 u8 data[2] = { 0x09, 0x54 };
2828 u8 data24m[2] = {0x60, 0x00};
2829 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
2830
2831 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2832 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2833 /* Set SLV-X Bank : 0x00 */
2834 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2835 /* Set demod mode */
2836 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
2837 /* Set SLV-T Bank : 0x00 */
2838 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2839 /* Enable demod clock */
2840 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2841 /* Enable RF level monitor */
2842 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
2843 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
2844 /* Enable ADC clock */
2845 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2846 /* Enable ADC 1 */
2847 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2848 /* xtal freq 20.5MHz or 24M */
2849 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2850 /* Enable ADC 4 */
2851 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2852 /* ASCOT setting ON */
2853 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2854 /* FEC Auto Recovery setting */
2855 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2856 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
2857 /* ISDB-T initial setting */
2858 /* Set SLV-T Bank : 0x00 */
2859 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2860 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
2861 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
2862 /* Set SLV-T Bank : 0x10 */
2863 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2864 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
2865 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
2866 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
2867 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
2868 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
2869 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
2870 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
2871 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
2872 /* Set SLV-T Bank : 0x15 */
2873 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2874 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
2875 /* Set SLV-T Bank : 0x1E */
2876 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
2877 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
2878 /* Set SLV-T Bank : 0x63 */
2879 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
2880 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
2881
2882 /* for xtal 24MHz */
2883 /* Set SLV-T Bank : 0x10 */
2884 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2885 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
2886 /* Set SLV-T Bank : 0x60 */
2887 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
2888 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
2889
2890 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
2891 /* Set SLV-T Bank : 0x00 */
2892 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2893 /* Disable HiZ Setting 1 */
2894 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2895 /* Disable HiZ Setting 2 */
2896 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2897 priv->state = STATE_ACTIVE_TC;
2898 return 0;
2899}
2900
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2901static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2902 u32 bandwidth)
2903{
2904 u8 data[2] = { 0x09, 0x54 };
2905
2906 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2907 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2908 /* Set SLV-X Bank : 0x00 */
2909 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2910 /* Set demod mode */
2911 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2912 /* Set SLV-T Bank : 0x00 */
2913 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2914 /* Enable demod clock */
2915 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2916 /* Disable RF level monitor */
2917 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2918 /* Enable ADC clock */
2919 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2920 /* Enable ADC 1 */
2921 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2922 /* xtal freq 20.5MHz */
2923 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2924 /* Enable ADC 4 */
2925 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2926 /* Set SLV-T Bank : 0x10 */
2927 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2928 /* IFAGC gain settings */
2929 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2930 /* Set SLV-T Bank : 0x11 */
2931 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2932 /* BBAGC TARGET level setting */
2933 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2934 /* Set SLV-T Bank : 0x10 */
2935 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2936 /* ASCOT setting ON */
2937 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2938 /* Set SLV-T Bank : 0x40 */
2939 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2940 /* Demod setting */
2941 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2942 /* Set SLV-T Bank : 0x00 */
2943 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2944 /* TSIF setting */
2945 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2946 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2947
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]2948 cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2949 /* Set SLV-T Bank : 0x00 */
2950 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2951 /* Disable HiZ Setting 1 */
2952 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2953 /* Disable HiZ Setting 2 */
2954 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2955 priv->state = STATE_ACTIVE_TC;
2956 return 0;
2957}
2958
Mauro Carvalho Chehab7e3e68b2016-02-04 12:58:30 -0200[diff] [blame]2959static int cxd2841er_get_frontend(struct dvb_frontend *fe,
2960 struct dtv_frontend_properties *p)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2961{
2962 enum fe_status status = 0;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2963 struct cxd2841er_priv *priv = fe->demodulator_priv;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2964
2965 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2966 if (priv->state == STATE_ACTIVE_S)
2967 cxd2841er_read_status_s(fe, &status);
2968 else if (priv->state == STATE_ACTIVE_TC)
2969 cxd2841er_read_status_tc(fe, &status);
2970
Mauro Carvalho Chehab5fda1b62016-06-30 19:41:45 -0300[diff] [blame]2971 cxd2841er_read_signal_strength(fe);
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]2972
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2973 if (status & FE_HAS_LOCK) {
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]2974 cxd2841er_read_snr(fe);
2975 cxd2841er_read_ucblocks(fe);
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]2976
Mauro Carvalho Chehabf1b26622016-07-01 11:03:13 -0300[diff] [blame]2977 cxd2841er_read_ber(fe);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2978 } else {
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2979 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2980 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2981 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]2982 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2983 }
2984 return 0;
2985}
2986
2987static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2988{
2989 int ret = 0, i, timeout, carr_offset;
2990 enum fe_status status;
2991 struct cxd2841er_priv *priv = fe->demodulator_priv;
2992 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2993 u32 symbol_rate = p->symbol_rate/1000;
2994
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2995 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2996 __func__,
2997 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]2998 p->frequency, symbol_rate, priv->xtal);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2999 switch (priv->state) {
3000 case STATE_SLEEP_S:
3001 ret = cxd2841er_sleep_s_to_active_s(
3002 priv, p->delivery_system, symbol_rate);
3003 break;
3004 case STATE_ACTIVE_S:
3005 ret = cxd2841er_retune_active(priv, p);
3006 break;
3007 default:
3008 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3009 __func__, priv->state);
3010 ret = -EINVAL;
3011 goto done;
3012 }
3013 if (ret) {
3014 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3015 goto done;
3016 }
3017 if (fe->ops.i2c_gate_ctrl)
3018 fe->ops.i2c_gate_ctrl(fe, 1);
3019 if (fe->ops.tuner_ops.set_params)
3020 fe->ops.tuner_ops.set_params(fe);
3021 if (fe->ops.i2c_gate_ctrl)
3022 fe->ops.i2c_gate_ctrl(fe, 0);
3023 cxd2841er_tune_done(priv);
3024 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3025 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3026 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3027 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3028 cxd2841er_read_status_s(fe, &status);
3029 if (status & FE_HAS_LOCK)
3030 break;
3031 }
3032 if (status & FE_HAS_LOCK) {
3033 if (cxd2841er_get_carrier_offset_s_s2(
3034 priv, &carr_offset)) {
3035 ret = -EINVAL;
3036 goto done;
3037 }
3038 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3039 __func__, carr_offset);
3040 }
3041done:
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]3042 /* Reset stats */
3043 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3044 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3045 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3046 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]3047 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]3048
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3049 return ret;
3050}
3051
3052static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3053{
3054 int ret = 0, timeout;
3055 enum fe_status status;
3056 struct cxd2841er_priv *priv = fe->demodulator_priv;
3057 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3058
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3059 dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3060 __func__, p->delivery_system, p->bandwidth_hz);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3061 if (p->delivery_system == SYS_DVBT) {
3062 priv->system = SYS_DVBT;
3063 switch (priv->state) {
3064 case STATE_SLEEP_TC:
3065 ret = cxd2841er_sleep_tc_to_active_t(
3066 priv, p->bandwidth_hz);
3067 break;
3068 case STATE_ACTIVE_TC:
3069 ret = cxd2841er_retune_active(priv, p);
3070 break;
3071 default:
3072 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3073 __func__, priv->state);
3074 ret = -EINVAL;
3075 }
3076 } else if (p->delivery_system == SYS_DVBT2) {
3077 priv->system = SYS_DVBT2;
3078 cxd2841er_dvbt2_set_plp_config(priv,
3079 (int)(p->stream_id > 255), p->stream_id);
3080 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3081 switch (priv->state) {
3082 case STATE_SLEEP_TC:
3083 ret = cxd2841er_sleep_tc_to_active_t2(priv,
3084 p->bandwidth_hz);
3085 break;
3086 case STATE_ACTIVE_TC:
3087 ret = cxd2841er_retune_active(priv, p);
3088 break;
3089 default:
3090 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3091 __func__, priv->state);
3092 ret = -EINVAL;
3093 }
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]3094 } else if (p->delivery_system == SYS_ISDBT) {
3095 priv->system = SYS_ISDBT;
3096 switch (priv->state) {
3097 case STATE_SLEEP_TC:
3098 ret = cxd2841er_sleep_tc_to_active_i(
3099 priv, p->bandwidth_hz);
3100 break;
3101 case STATE_ACTIVE_TC:
3102 ret = cxd2841er_retune_active(priv, p);
3103 break;
3104 default:
3105 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3106 __func__, priv->state);
3107 ret = -EINVAL;
3108 }
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3109 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3110 p->delivery_system == SYS_DVBC_ANNEX_C) {
3111 priv->system = SYS_DVBC_ANNEX_A;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3112 /* correct bandwidth */
3113 if (p->bandwidth_hz != 6000000 &&
3114 p->bandwidth_hz != 7000000 &&
3115 p->bandwidth_hz != 8000000) {
3116 p->bandwidth_hz = 8000000;
3117 dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3118 __func__, p->bandwidth_hz);
3119 }
3120
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3121 switch (priv->state) {
3122 case STATE_SLEEP_TC:
3123 ret = cxd2841er_sleep_tc_to_active_c(
3124 priv, p->bandwidth_hz);
3125 break;
3126 case STATE_ACTIVE_TC:
3127 ret = cxd2841er_retune_active(priv, p);
3128 break;
3129 default:
3130 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3131 __func__, priv->state);
3132 ret = -EINVAL;
3133 }
3134 } else {
3135 dev_dbg(&priv->i2c->dev,
3136 "%s(): invalid delivery system %d\n",
3137 __func__, p->delivery_system);
3138 ret = -EINVAL;
3139 }
3140 if (ret)
3141 goto done;
3142 if (fe->ops.i2c_gate_ctrl)
3143 fe->ops.i2c_gate_ctrl(fe, 1);
3144 if (fe->ops.tuner_ops.set_params)
3145 fe->ops.tuner_ops.set_params(fe);
3146 if (fe->ops.i2c_gate_ctrl)
3147 fe->ops.i2c_gate_ctrl(fe, 0);
3148 cxd2841er_tune_done(priv);
3149 timeout = 2500;
3150 while (timeout > 0) {
3151 ret = cxd2841er_read_status_tc(fe, &status);
3152 if (ret)
3153 goto done;
3154 if (status & FE_HAS_LOCK)
3155 break;
3156 msleep(20);
3157 timeout -= 20;
3158 }
3159 if (timeout < 0)
3160 dev_dbg(&priv->i2c->dev,
3161 "%s(): LOCK wait timeout\n", __func__);
3162done:
3163 return ret;
3164}
3165
3166static int cxd2841er_tune_s(struct dvb_frontend *fe,
3167 bool re_tune,
3168 unsigned int mode_flags,
3169 unsigned int *delay,
3170 enum fe_status *status)
3171{
3172 int ret, carrier_offset;
3173 struct cxd2841er_priv *priv = fe->demodulator_priv;
3174 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3175
3176 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3177 if (re_tune) {
3178 ret = cxd2841er_set_frontend_s(fe);
3179 if (ret)
3180 return ret;
3181 cxd2841er_read_status_s(fe, status);
3182 if (*status & FE_HAS_LOCK) {
3183 if (cxd2841er_get_carrier_offset_s_s2(
3184 priv, &carrier_offset))
3185 return -EINVAL;
3186 p->frequency += carrier_offset;
3187 ret = cxd2841er_set_frontend_s(fe);
3188 if (ret)
3189 return ret;
3190 }
3191 }
3192 *delay = HZ / 5;
3193 return cxd2841er_read_status_s(fe, status);
3194}
3195
3196static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3197 bool re_tune,
3198 unsigned int mode_flags,
3199 unsigned int *delay,
3200 enum fe_status *status)
3201{
3202 int ret, carrier_offset;
3203 struct cxd2841er_priv *priv = fe->demodulator_priv;
3204 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3205
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3206 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3207 re_tune, p->bandwidth_hz);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3208 if (re_tune) {
3209 ret = cxd2841er_set_frontend_tc(fe);
3210 if (ret)
3211 return ret;
3212 cxd2841er_read_status_tc(fe, status);
3213 if (*status & FE_HAS_LOCK) {
3214 switch (priv->system) {
Mauro Carvalho Chehab76344a3f2016-05-04 18:25:38 -0300[diff] [blame]3215 case SYS_ISDBT:
3216 ret = cxd2841er_get_carrier_offset_i(
3217 priv, p->bandwidth_hz,
3218 &carrier_offset);
3219 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3220 case SYS_DVBT:
Abylay Ospanc5ea46d2016-04-02 23:31:50 -0300[diff] [blame]3221 ret = cxd2841er_get_carrier_offset_t(
3222 priv, p->bandwidth_hz,
3223 &carrier_offset);
3224 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3225 case SYS_DVBT2:
3226 ret = cxd2841er_get_carrier_offset_t2(
3227 priv, p->bandwidth_hz,
3228 &carrier_offset);
3229 break;
3230 case SYS_DVBC_ANNEX_A:
3231 ret = cxd2841er_get_carrier_offset_c(
3232 priv, &carrier_offset);
3233 break;
3234 default:
3235 dev_dbg(&priv->i2c->dev,
3236 "%s(): invalid delivery system %d\n",
3237 __func__, priv->system);
3238 return -EINVAL;
3239 }
3240 if (ret)
3241 return ret;
3242 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3243 __func__, carrier_offset);
3244 p->frequency += carrier_offset;
3245 ret = cxd2841er_set_frontend_tc(fe);
3246 if (ret)
3247 return ret;
3248 }
3249 }
3250 *delay = HZ / 5;
3251 return cxd2841er_read_status_tc(fe, status);
3252}
3253
3254static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3255{
3256 struct cxd2841er_priv *priv = fe->demodulator_priv;
3257
3258 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3259 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3260 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3261 return 0;
3262}
3263
3264static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3265{
3266 struct cxd2841er_priv *priv = fe->demodulator_priv;
3267
3268 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3269 if (priv->state == STATE_ACTIVE_TC) {
3270 switch (priv->system) {
3271 case SYS_DVBT:
3272 cxd2841er_active_t_to_sleep_tc(priv);
3273 break;
3274 case SYS_DVBT2:
3275 cxd2841er_active_t2_to_sleep_tc(priv);
3276 break;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]3277 case SYS_ISDBT:
3278 cxd2841er_active_i_to_sleep_tc(priv);
3279 break;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3280 case SYS_DVBC_ANNEX_A:
3281 cxd2841er_active_c_to_sleep_tc(priv);
3282 break;
3283 default:
3284 dev_warn(&priv->i2c->dev,
3285 "%s(): unknown delivery system %d\n",
3286 __func__, priv->system);
3287 }
3288 }
3289 if (priv->state != STATE_SLEEP_TC) {
3290 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3291 __func__, priv->state);
3292 return -EINVAL;
3293 }
3294 cxd2841er_sleep_tc_to_shutdown(priv);
3295 return 0;
3296}
3297
3298static int cxd2841er_send_burst(struct dvb_frontend *fe,
3299 enum fe_sec_mini_cmd burst)
3300{
3301 u8 data;
3302 struct cxd2841er_priv *priv = fe->demodulator_priv;
3303
3304 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3305 (burst == SEC_MINI_A ? "A" : "B"));
3306 if (priv->state != STATE_SLEEP_S &&
3307 priv->state != STATE_ACTIVE_S) {
3308 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3309 __func__, priv->state);
3310 return -EINVAL;
3311 }
3312 data = (burst == SEC_MINI_A ? 0 : 1);
3313 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3314 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3315 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3316 return 0;
3317}
3318
3319static int cxd2841er_set_tone(struct dvb_frontend *fe,
3320 enum fe_sec_tone_mode tone)
3321{
3322 u8 data;
3323 struct cxd2841er_priv *priv = fe->demodulator_priv;
3324
3325 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3326 (tone == SEC_TONE_ON ? "On" : "Off"));
3327 if (priv->state != STATE_SLEEP_S &&
3328 priv->state != STATE_ACTIVE_S) {
3329 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3330 __func__, priv->state);
3331 return -EINVAL;
3332 }
3333 data = (tone == SEC_TONE_ON ? 1 : 0);
3334 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3335 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3336 return 0;
3337}
3338
3339static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3340 struct dvb_diseqc_master_cmd *cmd)
3341{
3342 int i;
3343 u8 data[12];
3344 struct cxd2841er_priv *priv = fe->demodulator_priv;
3345
3346 if (priv->state != STATE_SLEEP_S &&
3347 priv->state != STATE_ACTIVE_S) {
3348 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3349 __func__, priv->state);
3350 return -EINVAL;
3351 }
3352 dev_dbg(&priv->i2c->dev,
3353 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3354 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3355 /* DiDEqC enable */
3356 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3357 /* cmd1 length & data */
3358 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3359 memset(data, 0, sizeof(data));
3360 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3361 data[i] = cmd->msg[i];
3362 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3363 /* repeat count for cmd1 */
3364 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3365 /* repeat count for cmd2: always 0 */
3366 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3367 /* start transmit */
3368 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3369 /* wait for 1 sec timeout */
3370 for (i = 0; i < 50; i++) {
3371 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3372 if (!data[0]) {
3373 dev_dbg(&priv->i2c->dev,
3374 "%s(): DiSEqC cmd has been sent\n", __func__);
3375 return 0;
3376 }
3377 msleep(20);
3378 }
3379 dev_dbg(&priv->i2c->dev,
3380 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3381 return -ETIMEDOUT;
3382}
3383
3384static void cxd2841er_release(struct dvb_frontend *fe)
3385{
3386 struct cxd2841er_priv *priv = fe->demodulator_priv;
3387
3388 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3389 kfree(priv);
3390}
3391
3392static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3393{
3394 struct cxd2841er_priv *priv = fe->demodulator_priv;
3395
3396 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3397 cxd2841er_set_reg_bits(
3398 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3399 return 0;
3400}
3401
3402static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3403{
3404 struct cxd2841er_priv *priv = fe->demodulator_priv;
3405
3406 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3407 return DVBFE_ALGO_HW;
3408}
3409
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]3410static void cxd2841er_init_stats(struct dvb_frontend *fe)
3411{
3412 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3413
3414 p->strength.len = 1;
3415 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3416 p->cnr.len = 1;
3417 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3418 p->block_error.len = 1;
3419 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3420 p->post_bit_error.len = 1;
3421 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Mauro Carvalho Chehab4216be12016-07-01 11:03:15 -0300[diff] [blame^]3422 p->post_bit_count.len = 1;
3423 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]3424}
3425
3426
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3427static int cxd2841er_init_s(struct dvb_frontend *fe)
3428{
3429 struct cxd2841er_priv *priv = fe->demodulator_priv;
3430
Abylay Ospan30ae3302016-04-05 15:02:37 -0300[diff] [blame]3431 /* sanity. force demod to SHUTDOWN state */
3432 if (priv->state == STATE_SLEEP_S) {
3433 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3434 __func__);
3435 cxd2841er_sleep_s_to_shutdown(priv);
3436 } else if (priv->state == STATE_ACTIVE_S) {
3437 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3438 __func__);
3439 cxd2841er_active_s_to_sleep_s(priv);
3440 cxd2841er_sleep_s_to_shutdown(priv);
3441 }
3442
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3443 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3444 cxd2841er_shutdown_to_sleep_s(priv);
3445 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3446 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3447 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]3448
3449 cxd2841er_init_stats(fe);
3450
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3451 return 0;
3452}
3453
3454static int cxd2841er_init_tc(struct dvb_frontend *fe)
3455{
3456 struct cxd2841er_priv *priv = fe->demodulator_priv;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3457 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3458
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3459 dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3460 __func__, p->bandwidth_hz);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3461 cxd2841er_shutdown_to_sleep_tc(priv);
3462 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3463 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3464 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3465 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3466 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3467 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3468 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3469 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
Mauro Carvalho Chehabd0e20e12016-06-30 00:34:59 -0300[diff] [blame]3470
3471 cxd2841er_init_stats(fe);
3472
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3473 return 0;
3474}
3475
3476static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3477static struct dvb_frontend_ops cxd2841er_t_c_ops;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3478
3479static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3480 struct i2c_adapter *i2c,
3481 u8 system)
3482{
3483 u8 chip_id = 0;
3484 const char *type;
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3485 const char *name;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3486 struct cxd2841er_priv *priv = NULL;
3487
3488 /* allocate memory for the internal state */
3489 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3490 if (!priv)
3491 return NULL;
3492 priv->i2c = i2c;
3493 priv->config = cfg;
3494 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3495 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]3496 priv->xtal = cfg->xtal;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3497 priv->frontend.demodulator_priv = priv;
3498 dev_info(&priv->i2c->dev,
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3499 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3500 __func__, priv->i2c,
3501 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3502 chip_id = cxd2841er_chip_id(priv);
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3503 switch (chip_id) {
3504 case CXD2841ER_CHIP_ID:
3505 snprintf(cxd2841er_t_c_ops.info.name, 128,
3506 "Sony CXD2841ER DVB-T/T2/C demodulator");
3507 name = "CXD2841ER";
3508 break;
3509 case CXD2854ER_CHIP_ID:
3510 snprintf(cxd2841er_t_c_ops.info.name, 128,
3511 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3512 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3513 name = "CXD2854ER";
3514 break;
3515 default:
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3516 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3517 __func__, chip_id);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3518 priv->frontend.demodulator_priv = NULL;
3519 kfree(priv);
3520 return NULL;
3521 }
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3522
3523 /* create dvb_frontend */
3524 if (system == SYS_DVBS) {
3525 memcpy(&priv->frontend.ops,
3526 &cxd2841er_dvbs_s2_ops,
3527 sizeof(struct dvb_frontend_ops));
3528 type = "S/S2";
3529 } else {
3530 memcpy(&priv->frontend.ops,
3531 &cxd2841er_t_c_ops,
3532 sizeof(struct dvb_frontend_ops));
3533 type = "T/T2/C/ISDB-T";
3534 }
3535
3536 dev_info(&priv->i2c->dev,
3537 "%s(): attaching %s DVB-%s frontend\n",
3538 __func__, name, type);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3539 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3540 __func__, chip_id);
3541 return &priv->frontend;
3542}
3543
3544struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3545 struct i2c_adapter *i2c)
3546{
3547 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3548}
3549EXPORT_SYMBOL(cxd2841er_attach_s);
3550
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3551struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3552 struct i2c_adapter *i2c)
3553{
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3554 return cxd2841er_attach(cfg, i2c, 0);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3555}
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3556EXPORT_SYMBOL(cxd2841er_attach_t_c);
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3557
3558static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3559 .delsys = { SYS_DVBS, SYS_DVBS2 },
3560 .info = {
3561 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3562 .frequency_min = 500000,
3563 .frequency_max = 2500000,
3564 .frequency_stepsize = 0,
3565 .symbol_rate_min = 1000000,
3566 .symbol_rate_max = 45000000,
3567 .symbol_rate_tolerance = 500,
3568 .caps = FE_CAN_INVERSION_AUTO |
3569 FE_CAN_FEC_AUTO |
3570 FE_CAN_QPSK,
3571 },
3572 .init = cxd2841er_init_s,
3573 .sleep = cxd2841er_sleep_s,
3574 .release = cxd2841er_release,
3575 .set_frontend = cxd2841er_set_frontend_s,
3576 .get_frontend = cxd2841er_get_frontend,
3577 .read_status = cxd2841er_read_status_s,
3578 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3579 .get_frontend_algo = cxd2841er_get_algo,
3580 .set_tone = cxd2841er_set_tone,
3581 .diseqc_send_burst = cxd2841er_send_burst,
3582 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3583 .tune = cxd2841er_tune_s
3584};
3585
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3586static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3587 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3588 .info = {
Abylay Ospan3f3b48a2016-05-14 00:08:40 -0300[diff] [blame]3589 .name = "", /* will set in attach function */
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3590 .caps = FE_CAN_FEC_1_2 |
3591 FE_CAN_FEC_2_3 |
3592 FE_CAN_FEC_3_4 |
3593 FE_CAN_FEC_5_6 |
3594 FE_CAN_FEC_7_8 |
3595 FE_CAN_FEC_AUTO |
3596 FE_CAN_QPSK |
3597 FE_CAN_QAM_16 |
3598 FE_CAN_QAM_32 |
3599 FE_CAN_QAM_64 |
3600 FE_CAN_QAM_128 |
3601 FE_CAN_QAM_256 |
3602 FE_CAN_QAM_AUTO |
3603 FE_CAN_TRANSMISSION_MODE_AUTO |
3604 FE_CAN_GUARD_INTERVAL_AUTO |
3605 FE_CAN_HIERARCHY_AUTO |
3606 FE_CAN_MUTE_TS |
3607 FE_CAN_2G_MODULATION,
3608 .frequency_min = 42000000,
3609 .frequency_max = 1002000000
3610 },
3611 .init = cxd2841er_init_tc,
3612 .sleep = cxd2841er_sleep_tc,
3613 .release = cxd2841er_release,
3614 .set_frontend = cxd2841er_set_frontend_tc,
3615 .get_frontend = cxd2841er_get_frontend,
3616 .read_status = cxd2841er_read_status_tc,
3617 .tune = cxd2841er_tune_tc,
3618 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3619 .get_frontend_algo = cxd2841er_get_algo
3620};
3621
Abylay Ospan83808c22016-03-22 19:20:34 -0300[diff] [blame]3622MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3623MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]3624MODULE_LICENSE("GPL");