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Roland Stiggee04920d2012-04-22 12:01:19 +02001/*
2 * PHYTEC phyCORE-LPC3250 board
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
Vladimir Zapolskiy1a24edd2015-10-18 00:35:50 +030015#include "lpc32xx.dtsi"
Roland Stiggee04920d2012-04-22 12:01:19 +020016
17/ {
18 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
19 compatible = "phytec,phy3250", "nxp,lpc3250";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 device_type = "memory";
Vladimir Zapolskiycae59492015-10-18 00:35:54 +030025 reg = <0x80000000 0x4000000>;
Roland Stiggee04920d2012-04-22 12:01:19 +020026 };
27
Vladimir Zapolskiyf6d44342015-12-21 21:54:25 +020028 regulators {
29 backlight_reg: regulator@0 {
30 compatible = "regulator-fixed";
31 regulator-name = "backlight_reg";
32 regulator-min-microvolt = <1800000>;
33 regulator-max-microvolt = <1800000>;
34 gpio = <&gpio 5 4 0>;
35 enable-active-high;
36 regulator-boot-on;
37 };
38
39 lcd_reg: regulator@1 {
40 compatible = "regulator-fixed";
41 regulator-name = "lcd_reg";
42 regulator-min-microvolt = <1800000>;
43 regulator-max-microvolt = <1800000>;
44 gpio = <&gpio 5 0 0>;
45 enable-active-high;
46 regulator-boot-on;
47 };
Vladimir Zapolskiyd06670e2015-12-21 21:54:26 +020048
49 sd_reg: regulator@2 {
50 compatible = "regulator-fixed";
51 regulator-name = "sd_reg";
52 regulator-min-microvolt = <1800000>;
53 regulator-max-microvolt = <1800000>;
54 gpio = <&gpio 5 5 0>;
55 enable-active-high;
56 };
Vladimir Zapolskiyf6d44342015-12-21 21:54:25 +020057 };
58
Roland Stiggee04920d2012-04-22 12:01:19 +020059 leds {
60 compatible = "gpio-leds";
61
Roland Stigge07c7e122012-09-25 10:11:41 +020062 led0 { /* red */
63 gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
Roland Stiggee04920d2012-04-22 12:01:19 +020064 default-state = "off";
65 };
66
Roland Stigge07c7e122012-09-25 10:11:41 +020067 led1 { /* green */
68 gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
69 linux,default-trigger = "heartbeat";
Roland Stiggee04920d2012-04-22 12:01:19 +020070 };
71 };
72};
Vladimir Zapolskiyaa29efb2015-10-18 00:35:57 +030073
Vladimir Zapolskiy6101f4b2016-04-27 00:10:32 +030074&clcd {
Vladimir Zapolskiyaa29efb2015-10-18 00:35:57 +030075 status = "okay";
76};
77
Vladimir Zapolskiy6101f4b2016-04-27 00:10:32 +030078&i2c1 {
79 clock-frequency = <100000>;
80
81 uda1380: uda1380@18 {
82 compatible = "nxp,uda1380";
83 reg = <0x18>;
84 power-gpio = <&gpio 0x59 0>;
85 reset-gpio = <&gpio 0x51 0>;
86 dac-clk = "wspll";
87 };
88
89 pcf8563: rtc@51 {
90 compatible = "nxp,pcf8563";
91 reg = <0x51>;
92 };
93};
94
95&i2c2 {
96 clock-frequency = <100000>;
97};
98
Vladimir Zapolskiyaa29efb2015-10-18 00:35:57 +030099&i2cusb {
100 clock-frequency = <100000>;
101
102 isp1301: usb-transceiver@2c {
103 compatible = "nxp,isp1301";
104 reg = <0x2c>;
105 };
106};
Vladimir Zapolskiy6101f4b2016-04-27 00:10:32 +0300107
108&key {
109 keypad,num-rows = <1>;
110 keypad,num-columns = <1>;
111 nxp,debounce-delay-ms = <3>;
112 nxp,scan-delay-ms = <34>;
113 linux,keymap = <0x00000002>;
114 status = "okay";
115};
116
117&mac {
118 phy-mode = "rmii";
119 use-iram;
120};
121
122/* Here, choose exactly one from: ohci, usbd */
123&ohci /* &usbd */ {
124 transceiver = <&isp1301>;
125 status = "okay";
126};
127
128&sd {
129 wp-gpios = <&gpio 3 0 0>;
130 cd-gpios = <&gpio 3 1 0>;
131 cd-inverted;
132 bus-width = <4>;
133 vmmc-supply = <&sd_reg>;
134 status = "okay";
135};
136
137/* 64MB Flash via SLC NAND controller */
138&slc {
139 #address-cells = <1>;
140 #size-cells = <1>;
141 status = "okay";
142
143 nxp,wdr-clks = <14>;
144 nxp,wwidth = <40000000>;
145 nxp,whold = <100000000>;
146 nxp,wsetup = <100000000>;
147 nxp,rdr-clks = <14>;
148 nxp,rwidth = <40000000>;
149 nxp,rhold = <66666666>;
150 nxp,rsetup = <100000000>;
151 nand-on-flash-bbt;
152 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
153
154 mtd0@00000000 {
155 label = "phy3250-boot";
156 reg = <0x00000000 0x00064000>;
157 read-only;
158 };
159
160 mtd1@00064000 {
161 label = "phy3250-uboot";
162 reg = <0x00064000 0x00190000>;
163 read-only;
164 };
165
166 mtd2@001f4000 {
167 label = "phy3250-ubt-prms";
168 reg = <0x001f4000 0x00010000>;
169 };
170
171 mtd3@00204000 {
172 label = "phy3250-kernel";
173 reg = <0x00204000 0x00400000>;
174 };
175
176 mtd4@00604000 {
177 label = "phy3250-rootfs";
178 reg = <0x00604000 0x039fc000>;
179 };
180};
181
182&ssp0 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 num-cs = <1>;
186 cs-gpios = <&gpio 3 5 0>;
187 status = "okay";
188
189 eeprom: at25@0 {
190 compatible = "atmel,at25";
191 reg = <0>;
192 spi-max-frequency = <5000000>;
193
194 pl022,interface = <0>;
195 pl022,com-mode = <0>;
196 pl022,rx-level-trig = <1>;
197 pl022,tx-level-trig = <1>;
198 pl022,ctrl-len = <11>;
199 pl022,wait-state = <0>;
200 pl022,duplex = <0>;
201
202 at25,byte-len = <0x8000>;
203 at25,addr-mode = <2>;
204 at25,page-size = <64>;
205 };
206};
207
208&tsc {
209 status = "okay";
210};
211
212&uart2 {
213 status = "okay";
214};
215
216&uart3 {
217 status = "okay";
218};
219
220&uart5 {
221 status = "okay";
222};