blob: 8ac368f48edab73f5fa84c9d3f5ac2abcf05d0aa [file] [log] [blame]
Roland Stiggee04920d2012-04-22 12:01:19 +02001/*
2 * PHYTEC phyCORE-LPC3250 board
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
Vladimir Zapolskiy1a24edd2015-10-18 00:35:50 +030015#include "lpc32xx.dtsi"
Roland Stiggee04920d2012-04-22 12:01:19 +020016
17/ {
18 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
19 compatible = "phytec,phy3250", "nxp,lpc3250";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 device_type = "memory";
Vladimir Zapolskiycae59492015-10-18 00:35:54 +030025 reg = <0x80000000 0x4000000>;
Roland Stiggee04920d2012-04-22 12:01:19 +020026 };
27
Vladimir Zapolskiyf6d44342015-12-21 21:54:25 +020028 regulators {
29 backlight_reg: regulator@0 {
30 compatible = "regulator-fixed";
31 regulator-name = "backlight_reg";
32 regulator-min-microvolt = <1800000>;
33 regulator-max-microvolt = <1800000>;
34 gpio = <&gpio 5 4 0>;
35 enable-active-high;
36 regulator-boot-on;
37 };
38
39 lcd_reg: regulator@1 {
40 compatible = "regulator-fixed";
41 regulator-name = "lcd_reg";
42 regulator-min-microvolt = <1800000>;
43 regulator-max-microvolt = <1800000>;
44 gpio = <&gpio 5 0 0>;
45 enable-active-high;
46 regulator-boot-on;
47 };
48 };
49
Roland Stiggee04920d2012-04-22 12:01:19 +020050 ahb {
51 mac: ethernet@31060000 {
52 phy-mode = "rmii";
53 use-iram;
54 };
55
Roland Stiggee04920d2012-04-22 12:01:19 +020056 clcd@31040000 {
57 status = "okay";
58 };
59
60 /* 64MB Flash via SLC NAND controller */
61 slc: flash@20020000 {
62 status = "okay";
63 #address-cells = <1>;
64 #size-cells = <1>;
65
Roland Stigge15ab2182012-06-14 16:16:16 +020066 nxp,wdr-clks = <14>;
67 nxp,wwidth = <40000000>;
68 nxp,whold = <100000000>;
69 nxp,wsetup = <100000000>;
70 nxp,rdr-clks = <14>;
71 nxp,rwidth = <40000000>;
72 nxp,rhold = <66666666>;
73 nxp,rsetup = <100000000>;
74 nand-on-flash-bbt;
75 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
76
Roland Stiggee04920d2012-04-22 12:01:19 +020077 mtd0@00000000 {
78 label = "phy3250-boot";
79 reg = <0x00000000 0x00064000>;
80 read-only;
81 };
82
83 mtd1@00064000 {
84 label = "phy3250-uboot";
85 reg = <0x00064000 0x00190000>;
86 read-only;
87 };
88
89 mtd2@001f4000 {
90 label = "phy3250-ubt-prms";
91 reg = <0x001f4000 0x00010000>;
92 };
93
94 mtd3@00204000 {
95 label = "phy3250-kernel";
96 reg = <0x00204000 0x00400000>;
97 };
98
99 mtd4@00604000 {
100 label = "phy3250-rootfs";
101 reg = <0x00604000 0x039fc000>;
102 };
103 };
104
105 apb {
Roland Stiggec70426f2012-06-14 16:16:18 +0200106 uart5: serial@40090000 {
107 status = "okay";
108 };
109
110 uart3: serial@40080000 {
111 status = "okay";
112 };
113
Roland Stiggee04920d2012-04-22 12:01:19 +0200114 i2c1: i2c@400A0000 {
115 clock-frequency = <100000>;
116
117 pcf8563: rtc@51 {
118 compatible = "nxp,pcf8563";
119 reg = <0x51>;
120 };
121
122 uda1380: uda1380@18 {
123 compatible = "nxp,uda1380";
124 reg = <0x18>;
125 power-gpio = <&gpio 0x59 0>;
126 reset-gpio = <&gpio 0x51 0>;
127 dac-clk = "wspll";
128 };
129 };
130
131 i2c2: i2c@400A8000 {
132 clock-frequency = <100000>;
133 };
134
Roland Stiggee04920d2012-04-22 12:01:19 +0200135 ssp0: ssp@20084000 {
Alexandre Pereira da Silva2e0b5a32012-06-12 10:34:12 -0300136 #address-cells = <1>;
137 #size-cells = <0>;
Roland Stigge067c1822012-09-06 11:40:42 +0200138 num-cs = <1>;
Alexandre Pereira da Silva2e0b5a32012-06-12 10:34:12 -0300139 cs-gpios = <&gpio 3 5 0>;
140
Roland Stiggee04920d2012-04-22 12:01:19 +0200141 eeprom: at25@0 {
Alexandre Pereira da Silva2e0b5a32012-06-12 10:34:12 -0300142 pl022,interface = <0>;
Alexandre Pereira da Silva2e0b5a32012-06-12 10:34:12 -0300143 pl022,com-mode = <0>;
144 pl022,rx-level-trig = <1>;
145 pl022,tx-level-trig = <1>;
146 pl022,ctrl-len = <11>;
147 pl022,wait-state = <0>;
148 pl022,duplex = <0>;
149
150 at25,byte-len = <0x8000>;
151 at25,addr-mode = <2>;
152 at25,page-size = <64>;
153
Roland Stiggee04920d2012-04-22 12:01:19 +0200154 compatible = "atmel,at25";
Alexandre Pereira da Silva2e0b5a32012-06-12 10:34:12 -0300155 reg = <0>;
156 spi-max-frequency = <5000000>;
Roland Stiggee04920d2012-04-22 12:01:19 +0200157 };
158 };
Roland Stigge2c7fa282012-06-14 16:16:18 +0200159
160 sd@20098000 {
161 wp-gpios = <&gpio 3 0 0>;
162 cd-gpios = <&gpio 3 1 0>;
163 cd-inverted;
164 bus-width = <4>;
165 status = "okay";
166 };
Roland Stiggee04920d2012-04-22 12:01:19 +0200167 };
168
169 fab {
Roland Stiggeac5ced92012-06-14 16:16:18 +0200170 uart2: serial@40018000 {
171 status = "okay";
172 };
173
Roland Stiggee04920d2012-04-22 12:01:19 +0200174 tsc@40048000 {
175 status = "okay";
176 };
Roland Stiggea6d1be02012-06-14 16:16:17 +0200177
178 key@40050000 {
179 status = "okay";
180 keypad,num-rows = <1>;
181 keypad,num-columns = <1>;
182 nxp,debounce-delay-ms = <3>;
183 nxp,scan-delay-ms = <34>;
184 linux,keymap = <0x00000002>;
185 };
Roland Stiggee04920d2012-04-22 12:01:19 +0200186 };
187 };
188
189 leds {
190 compatible = "gpio-leds";
191
Roland Stigge07c7e122012-09-25 10:11:41 +0200192 led0 { /* red */
193 gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
Roland Stiggee04920d2012-04-22 12:01:19 +0200194 default-state = "off";
195 };
196
Roland Stigge07c7e122012-09-25 10:11:41 +0200197 led1 { /* green */
198 gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
199 linux,default-trigger = "heartbeat";
Roland Stiggee04920d2012-04-22 12:01:19 +0200200 };
201 };
202};
Vladimir Zapolskiyaa29efb2015-10-18 00:35:57 +0300203
204/* Here, choose exactly one from: ohci, usbd */
205&ohci /* &usbd */ {
206 transceiver = <&isp1301>;
207 status = "okay";
208};
209
210&i2cusb {
211 clock-frequency = <100000>;
212
213 isp1301: usb-transceiver@2c {
214 compatible = "nxp,isp1301";
215 reg = <0x2c>;
216 };
217};