blob: 4fdd148747b255d6665dc47c7dcc779e4846fb32 [file] [log] [blame]
Ben Hutchingsafd4aea2009-11-29 15:15:25 +00001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
Ben Hutchings0a6f40c2011-02-25 00:01:34 +00004 * Copyright 2006-2010 Solarflare Communications Inc.
Ben Hutchingsafd4aea2009-11-29 15:15:25 +00005 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/slab.h>
Ben Hutchingsd614cfb2010-04-28 09:29:02 +000016#include <linux/random.h>
Ben Hutchingsafd4aea2009-11-29 15:15:25 +000017#include "net_driver.h"
18#include "bitfield.h"
19#include "efx.h"
20#include "nic.h"
21#include "mac.h"
22#include "spi.h"
23#include "regs.h"
24#include "io.h"
25#include "phy.h"
26#include "workarounds.h"
27#include "mcdi.h"
28#include "mcdi_pcol.h"
29
30/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31
32static void siena_init_wol(struct efx_nic *efx);
33
34
35static void siena_push_irq_moderation(struct efx_channel *channel)
36{
37 efx_dword_t timer_cmd;
38
Ben Hutchings9e393b32011-09-05 07:43:04 +000039 BUILD_BUG_ON(EFX_IRQ_MOD_MAX > (1 << FRF_CZ_TC_TIMER_VAL_WIDTH));
40
Ben Hutchingsafd4aea2009-11-29 15:15:25 +000041 if (channel->irq_moderation)
42 EFX_POPULATE_DWORD_2(timer_cmd,
43 FRF_CZ_TC_TIMER_MODE,
44 FFE_CZ_TIMER_MODE_INT_HLDOFF,
45 FRF_CZ_TC_TIMER_VAL,
46 channel->irq_moderation - 1);
47 else
48 EFX_POPULATE_DWORD_2(timer_cmd,
49 FRF_CZ_TC_TIMER_MODE,
50 FFE_CZ_TIMER_MODE_DIS,
51 FRF_CZ_TC_TIMER_VAL, 0);
52 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
53 channel->channel);
54}
55
56static void siena_push_multicast_hash(struct efx_nic *efx)
57{
58 WARN_ON(!mutex_is_locked(&efx->mac_lock));
59
60 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
61 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
62 NULL, 0, NULL);
63}
64
65static int siena_mdio_write(struct net_device *net_dev,
66 int prtad, int devad, u16 addr, u16 value)
67{
68 struct efx_nic *efx = netdev_priv(net_dev);
69 uint32_t status;
70 int rc;
71
72 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
73 addr, value, &status);
74 if (rc)
75 return rc;
76 if (status != MC_CMD_MDIO_STATUS_GOOD)
77 return -EIO;
78
79 return 0;
80}
81
82static int siena_mdio_read(struct net_device *net_dev,
83 int prtad, int devad, u16 addr)
84{
85 struct efx_nic *efx = netdev_priv(net_dev);
86 uint16_t value;
87 uint32_t status;
88 int rc;
89
90 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
91 addr, &value, &status);
92 if (rc)
93 return rc;
94 if (status != MC_CMD_MDIO_STATUS_GOOD)
95 return -EIO;
96
97 return (int)value;
98}
99
100/* This call is responsible for hooking in the MAC and PHY operations */
101static int siena_probe_port(struct efx_nic *efx)
102{
103 int rc;
104
105 /* Hook in PHY operations table */
106 efx->phy_op = &efx_mcdi_phy_ops;
107
108 /* Set up MDIO structure for PHY */
109 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
110 efx->mdio.mdio_read = siena_mdio_read;
111 efx->mdio.mdio_write = siena_mdio_write;
112
Steve Hodgson7a6b8f62010-02-03 09:30:38 +0000113 /* Fill out MDIO structure, loopback modes, and initial link state */
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000114 rc = efx->phy_op->probe(efx);
115 if (rc != 0)
116 return rc;
117
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000118 /* Allocate buffer for stats */
119 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
120 MC_CMD_MAC_NSTATS * sizeof(u64));
121 if (rc)
122 return rc;
Ben Hutchings62776d02010-06-23 11:30:07 +0000123 netif_dbg(efx, probe, efx->net_dev,
124 "stats buffer at %llx (virt %p phys %llx)\n",
125 (u64)efx->stats_buffer.dma_addr,
126 efx->stats_buffer.addr,
127 (u64)virt_to_phys(efx->stats_buffer.addr));
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000128
129 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
130
131 return 0;
132}
133
stephen hemmingerd2156972010-10-18 05:27:31 +0000134static void siena_remove_port(struct efx_nic *efx)
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000135{
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000136 efx->phy_op->remove(efx);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000137 efx_nic_free_buffer(efx, &efx->stats_buffer);
138}
139
140static const struct efx_nic_register_test siena_register_tests[] = {
141 { FR_AZ_ADR_REGION,
Steve Hodgson4cddca52010-02-03 09:31:40 +0000142 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000143 { FR_CZ_USR_EV_CFG,
144 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
145 { FR_AZ_RX_CFG,
146 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
147 { FR_AZ_TX_CFG,
148 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
149 { FR_AZ_TX_RESERVED,
150 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
151 { FR_AZ_SRM_TX_DC_CFG,
152 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
153 { FR_AZ_RX_DC_CFG,
154 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
155 { FR_AZ_RX_DC_PF_WM,
156 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
157 { FR_BZ_DP_CTRL,
158 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
159 { FR_BZ_RX_RSS_TKEY,
160 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
161 { FR_CZ_RX_RSS_IPV6_REG1,
162 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
163 { FR_CZ_RX_RSS_IPV6_REG2,
164 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
165 { FR_CZ_RX_RSS_IPV6_REG3,
166 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
167};
168
169static int siena_test_registers(struct efx_nic *efx)
170{
171 return efx_nic_test_registers(efx, siena_register_tests,
172 ARRAY_SIZE(siena_register_tests));
173}
174
175/**************************************************************************
176 *
177 * Device reset
178 *
179 **************************************************************************
180 */
181
Ben Hutchings0e2a9c72011-06-24 20:50:07 +0100182static enum reset_type siena_map_reset_reason(enum reset_type reason)
183{
184 return RESET_TYPE_ALL;
185}
186
187static int siena_map_reset_flags(u32 *flags)
188{
189 enum {
190 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
191 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
192 ETH_RESET_PHY),
193 SIENA_RESET_MC = (SIENA_RESET_PORT |
194 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
195 };
196
197 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
198 *flags &= ~SIENA_RESET_MC;
199 return RESET_TYPE_WORLD;
200 }
201
202 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
203 *flags &= ~SIENA_RESET_PORT;
204 return RESET_TYPE_ALL;
205 }
206
207 /* no invisible reset implemented */
208
209 return -EINVAL;
210}
211
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000212static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
213{
Steve Hodgson8b2103a2010-02-03 09:30:17 +0000214 int rc;
215
216 /* Recover from a failed assertion pre-reset */
217 rc = efx_mcdi_handle_assertion(efx);
218 if (rc)
219 return rc;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000220
221 if (method == RESET_TYPE_WORLD)
222 return efx_mcdi_reset_mc(efx);
223 else
224 return efx_mcdi_reset_port(efx);
225}
226
227static int siena_probe_nvconfig(struct efx_nic *efx)
228{
Ben Hutchings7e300bc2010-12-02 13:48:28 +0000229 return efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000230}
231
232static int siena_probe_nic(struct efx_nic *efx)
233{
234 struct siena_nic_data *nic_data;
235 bool already_attached = 0;
Ben Hutchingsd42a8f42010-06-01 11:32:43 +0000236 efx_oword_t reg;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000237 int rc;
238
239 /* Allocate storage for hardware specific data */
240 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
241 if (!nic_data)
242 return -ENOMEM;
243 efx->nic_data = nic_data;
244
245 if (efx_nic_fpga_ver(efx) != 0) {
Ben Hutchings62776d02010-06-23 11:30:07 +0000246 netif_err(efx, probe, efx->net_dev,
247 "Siena FPGA not supported\n");
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000248 rc = -ENODEV;
249 goto fail1;
250 }
251
Ben Hutchingsd42a8f42010-06-01 11:32:43 +0000252 efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
Ben Hutchings3df95ce2010-06-02 10:39:56 +0000253 efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
Ben Hutchingsd42a8f42010-06-01 11:32:43 +0000254
Ben Hutchings747df222011-05-11 17:41:18 +0100255 /* Initialise MCDI */
256 nic_data->mcdi_smem = ioremap_nocache(efx->membase_phys +
257 FR_CZ_MC_TREG_SMEM,
258 FR_CZ_MC_TREG_SMEM_STEP *
259 FR_CZ_MC_TREG_SMEM_ROWS);
260 if (!nic_data->mcdi_smem) {
261 netif_err(efx, probe, efx->net_dev,
262 "could not map MCDI at %llx+%x\n",
263 (unsigned long long)efx->membase_phys +
264 FR_CZ_MC_TREG_SMEM,
265 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS);
266 rc = -ENOMEM;
267 goto fail1;
268 }
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000269 efx_mcdi_init(efx);
270
271 /* Recover from a failed assertion before probing */
272 rc = efx_mcdi_handle_assertion(efx);
273 if (rc)
Ben Hutchings747df222011-05-11 17:41:18 +0100274 goto fail2;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000275
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000276 /* Let the BMC know that the driver is now in charge of link and
277 * filter settings. We must do this before we reset the NIC */
278 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
279 if (rc) {
Ben Hutchings62776d02010-06-23 11:30:07 +0000280 netif_err(efx, probe, efx->net_dev,
281 "Unable to register driver with MCPU\n");
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000282 goto fail2;
283 }
284 if (already_attached)
285 /* Not a fatal error */
Ben Hutchings62776d02010-06-23 11:30:07 +0000286 netif_err(efx, probe, efx->net_dev,
287 "Host already registered with MCPU\n");
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000288
289 /* Now we can reset the NIC */
290 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
291 if (rc) {
Ben Hutchings62776d02010-06-23 11:30:07 +0000292 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000293 goto fail3;
294 }
295
296 siena_init_wol(efx);
297
298 /* Allocate memory for INT_KER */
299 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
300 if (rc)
301 goto fail4;
302 BUG_ON(efx->irq_status.dma_addr & 0x0f);
303
Ben Hutchings62776d02010-06-23 11:30:07 +0000304 netif_dbg(efx, probe, efx->net_dev,
305 "INT_KER at %llx (virt %p phys %llx)\n",
306 (unsigned long long)efx->irq_status.dma_addr,
307 efx->irq_status.addr,
308 (unsigned long long)virt_to_phys(efx->irq_status.addr));
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000309
310 /* Read in the non-volatile configuration */
311 rc = siena_probe_nvconfig(efx);
312 if (rc == -EINVAL) {
Ben Hutchings62776d02010-06-23 11:30:07 +0000313 netif_err(efx, probe, efx->net_dev,
314 "NVRAM is invalid therefore using defaults\n");
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000315 efx->phy_type = PHY_TYPE_NONE;
316 efx->mdio.prtad = MDIO_PRTAD_NONE;
317 } else if (rc) {
318 goto fail5;
319 }
320
321 return 0;
322
323fail5:
324 efx_nic_free_buffer(efx, &efx->irq_status);
325fail4:
326fail3:
327 efx_mcdi_drv_attach(efx, false, NULL);
328fail2:
Ben Hutchings747df222011-05-11 17:41:18 +0100329 iounmap(nic_data->mcdi_smem);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000330fail1:
331 kfree(efx->nic_data);
332 return rc;
333}
334
335/* This call performs hardware-specific global initialisation, such as
336 * defining the descriptor cache sizes and number of RSS channels.
337 * It does not set up any buffers, descriptor rings or event queues.
338 */
339static int siena_init_nic(struct efx_nic *efx)
340{
341 efx_oword_t temp;
342 int rc;
343
344 /* Recover from a failed assertion post-reset */
345 rc = efx_mcdi_handle_assertion(efx);
346 if (rc)
347 return rc;
348
349 /* Squash TX of packets of 16 bytes or less */
350 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
351 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
352 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
353
354 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
355 * descriptors (which is bad).
356 */
357 efx_reado(efx, &temp, FR_AZ_TX_CFG);
358 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
359 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
360 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
361
362 efx_reado(efx, &temp, FR_AZ_RX_CFG);
363 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
364 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
Ben Hutchings477e54e2010-06-25 07:05:56 +0000365 /* Enable hash insertion. This is broken for the 'Falcon' hash
366 * if IPv6 hashing is also enabled, so also select Toeplitz
367 * TCP/IPv4 and IPv4 hashes. */
368 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
369 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
370 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000371 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
372
Ben Hutchings477e54e2010-06-25 07:05:56 +0000373 /* Set hash key for IPv4 */
374 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
375 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
376
Ben Hutchingsd614cfb2010-04-28 09:29:02 +0000377 /* Enable IPv6 RSS */
Ben Hutchings5d3a6fc2010-06-25 07:05:43 +0000378 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
Ben Hutchingsd614cfb2010-04-28 09:29:02 +0000379 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
380 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
Ben Hutchings5d3a6fc2010-06-25 07:05:43 +0000381 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
Ben Hutchingsd614cfb2010-04-28 09:29:02 +0000382 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
Ben Hutchings5d3a6fc2010-06-25 07:05:43 +0000383 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
Ben Hutchingsd614cfb2010-04-28 09:29:02 +0000384 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
385 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
386 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
Ben Hutchings5d3a6fc2010-06-25 07:05:43 +0000387 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
Ben Hutchingsd614cfb2010-04-28 09:29:02 +0000388 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
389 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
390
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000391 /* Enable event logging */
392 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
393 if (rc)
394 return rc;
395
396 /* Set destination of both TX and RX Flush events */
397 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
398 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
399
400 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
401 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
402
403 efx_nic_init_common(efx);
404 return 0;
405}
406
407static void siena_remove_nic(struct efx_nic *efx)
408{
Ben Hutchings747df222011-05-11 17:41:18 +0100409 struct siena_nic_data *nic_data = efx->nic_data;
410
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000411 efx_nic_free_buffer(efx, &efx->irq_status);
412
413 siena_reset_hw(efx, RESET_TYPE_ALL);
414
415 /* Relinquish the device back to the BMC */
416 if (efx_nic_has_mc(efx))
417 efx_mcdi_drv_attach(efx, false, NULL);
418
419 /* Tear down the private nic state */
Ben Hutchings747df222011-05-11 17:41:18 +0100420 iounmap(nic_data->mcdi_smem);
421 kfree(nic_data);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000422 efx->nic_data = NULL;
423}
424
Steve Hodgsona659b2a2011-06-22 12:11:33 +0100425#define STATS_GENERATION_INVALID ((__force __le64)(-1))
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000426
427static int siena_try_update_nic_stats(struct efx_nic *efx)
428{
Steve Hodgsona659b2a2011-06-22 12:11:33 +0100429 __le64 *dma_stats;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000430 struct efx_mac_stats *mac_stats;
Steve Hodgsona659b2a2011-06-22 12:11:33 +0100431 __le64 generation_start, generation_end;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000432
433 mac_stats = &efx->mac_stats;
Joe Perches43d620c2011-06-16 19:08:06 +0000434 dma_stats = efx->stats_buffer.addr;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000435
436 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
437 if (generation_end == STATS_GENERATION_INVALID)
438 return 0;
439 rmb();
440
441#define MAC_STAT(M, D) \
Steve Hodgsona659b2a2011-06-22 12:11:33 +0100442 mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D])
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000443
444 MAC_STAT(tx_bytes, TX_BYTES);
445 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
446 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
447 mac_stats->tx_bad_bytes);
448 MAC_STAT(tx_packets, TX_PKTS);
449 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
450 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
451 MAC_STAT(tx_control, TX_CONTROL_PKTS);
452 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
453 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
454 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
455 MAC_STAT(tx_lt64, TX_LT64_PKTS);
456 MAC_STAT(tx_64, TX_64_PKTS);
457 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
458 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
459 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
460 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
461 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
462 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
463 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
464 mac_stats->tx_collision = 0;
465 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
466 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
467 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
468 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
469 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
470 mac_stats->tx_collision = (mac_stats->tx_single_collision +
471 mac_stats->tx_multiple_collision +
472 mac_stats->tx_excessive_collision +
473 mac_stats->tx_late_collision);
474 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
475 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
476 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
477 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
478 MAC_STAT(rx_bytes, RX_BYTES);
479 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
480 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
481 mac_stats->rx_bad_bytes);
482 MAC_STAT(rx_packets, RX_PKTS);
483 MAC_STAT(rx_good, RX_GOOD_PKTS);
Ben Hutchings1cdc2cf2010-09-10 06:41:00 +0000484 MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000485 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
486 MAC_STAT(rx_control, RX_CONTROL_PKTS);
487 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
488 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
489 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
490 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
491 MAC_STAT(rx_64, RX_64_PKTS);
492 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
493 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
494 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
495 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
496 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
497 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
498 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
499 mac_stats->rx_bad_lt64 = 0;
500 mac_stats->rx_bad_64_to_15xx = 0;
501 mac_stats->rx_bad_15xx_to_jumbo = 0;
502 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
503 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
504 mac_stats->rx_missed = 0;
505 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
506 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
507 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
508 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
509 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
510 mac_stats->rx_good_lt64 = 0;
511
Steve Hodgsona659b2a2011-06-22 12:11:33 +0100512 efx->n_rx_nodesc_drop_cnt =
513 le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000514
515#undef MAC_STAT
516
517 rmb();
518 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
519 if (generation_end != generation_start)
520 return -EAGAIN;
521
522 return 0;
523}
524
525static void siena_update_nic_stats(struct efx_nic *efx)
526{
Ben Hutchingsaabc5642010-04-28 09:00:35 +0000527 int retry;
528
529 /* If we're unlucky enough to read statistics wduring the DMA, wait
530 * up to 10ms for it to finish (typically takes <500us) */
531 for (retry = 0; retry < 100; ++retry) {
532 if (siena_try_update_nic_stats(efx) == 0)
533 return;
534 udelay(100);
535 }
536
537 /* Use the old values instead */
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000538}
539
540static void siena_start_nic_stats(struct efx_nic *efx)
541{
Steve Hodgsona659b2a2011-06-22 12:11:33 +0100542 __le64 *dma_stats = efx->stats_buffer.addr;
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000543
544 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
545
546 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
547 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
548}
549
550static void siena_stop_nic_stats(struct efx_nic *efx)
551{
552 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
553}
554
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000555/**************************************************************************
556 *
557 * Wake on LAN
558 *
559 **************************************************************************
560 */
561
562static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
563{
564 struct siena_nic_data *nic_data = efx->nic_data;
565
566 wol->supported = WAKE_MAGIC;
567 if (nic_data->wol_filter_id != -1)
568 wol->wolopts = WAKE_MAGIC;
569 else
570 wol->wolopts = 0;
571 memset(&wol->sopass, 0, sizeof(wol->sopass));
572}
573
574
575static int siena_set_wol(struct efx_nic *efx, u32 type)
576{
577 struct siena_nic_data *nic_data = efx->nic_data;
578 int rc;
579
580 if (type & ~WAKE_MAGIC)
581 return -EINVAL;
582
583 if (type & WAKE_MAGIC) {
584 if (nic_data->wol_filter_id != -1)
585 efx_mcdi_wol_filter_remove(efx,
586 nic_data->wol_filter_id);
Ben Hutchings02ebc262010-12-02 13:48:20 +0000587 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000588 &nic_data->wol_filter_id);
589 if (rc)
590 goto fail;
591
592 pci_wake_from_d3(efx->pci_dev, true);
593 } else {
594 rc = efx_mcdi_wol_filter_reset(efx);
595 nic_data->wol_filter_id = -1;
596 pci_wake_from_d3(efx->pci_dev, false);
597 if (rc)
598 goto fail;
599 }
600
601 return 0;
602 fail:
Ben Hutchings62776d02010-06-23 11:30:07 +0000603 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
604 __func__, type, rc);
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000605 return rc;
606}
607
608
609static void siena_init_wol(struct efx_nic *efx)
610{
611 struct siena_nic_data *nic_data = efx->nic_data;
612 int rc;
613
614 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
615
616 if (rc != 0) {
617 /* If it failed, attempt to get into a synchronised
618 * state with MC by resetting any set WoL filters */
619 efx_mcdi_wol_filter_reset(efx);
620 nic_data->wol_filter_id = -1;
621 } else if (nic_data->wol_filter_id != -1) {
622 pci_wake_from_d3(efx->pci_dev, true);
623 }
624}
625
626
627/**************************************************************************
628 *
629 * Revision-dependent attributes used by efx.c and nic.c
630 *
631 **************************************************************************
632 */
633
stephen hemminger6c8c2512011-04-14 05:50:12 +0000634const struct efx_nic_type siena_a0_nic_type = {
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000635 .probe = siena_probe_nic,
636 .remove = siena_remove_nic,
637 .init = siena_init_nic,
638 .fini = efx_port_dummy_op_void,
639 .monitor = NULL,
Ben Hutchings0e2a9c72011-06-24 20:50:07 +0100640 .map_reset_reason = siena_map_reset_reason,
641 .map_reset_flags = siena_map_reset_flags,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000642 .reset = siena_reset_hw,
643 .probe_port = siena_probe_port,
644 .remove_port = siena_remove_port,
645 .prepare_flush = efx_port_dummy_op_void,
646 .update_stats = siena_update_nic_stats,
647 .start_stats = siena_start_nic_stats,
648 .stop_stats = siena_stop_nic_stats,
649 .set_id_led = efx_mcdi_set_id_led,
650 .push_irq_moderation = siena_push_irq_moderation,
651 .push_multicast_hash = siena_push_multicast_hash,
652 .reconfigure_port = efx_mcdi_phy_reconfigure,
653 .get_wol = siena_get_wol,
654 .set_wol = siena_set_wol,
655 .resume_wol = siena_init_wol,
656 .test_registers = siena_test_registers,
Ben Hutchings2e803402010-02-03 09:31:01 +0000657 .test_nvram = efx_mcdi_nvram_test_all,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000658 .default_mac_ops = &efx_mcdi_mac_operations,
659
660 .revision = EFX_REV_SIENA_A0,
Ben Hutchings747df222011-05-11 17:41:18 +0100661 .mem_map_size = FR_CZ_MC_TREG_SMEM, /* MC_TREG_SMEM mapped separately */
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000662 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
663 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
664 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
665 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
666 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
667 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
Ben Hutchings39c9cf02010-06-23 11:31:28 +0000668 .rx_buffer_hash_size = 0x10,
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000669 .rx_buffer_padding = 0,
670 .max_interrupt_mode = EFX_INT_MODE_MSIX,
671 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
672 * interrupt handler only supports 32
673 * channels */
674 .tx_dc_base = 0x88000,
675 .rx_dc_base = 0x68000,
Ben Hutchings39c9cf02010-06-23 11:31:28 +0000676 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
Ben Hutchingsb4187e42010-09-20 08:43:42 +0000677 NETIF_F_RXHASH | NETIF_F_NTUPLE),
Ben Hutchingsafd4aea2009-11-29 15:15:25 +0000678};