blob: 5d57a4249412dd68ded25f6ddb9fd88f1ab16251 [file] [log] [blame]
Greg Ungererb5aaf3f2005-09-02 10:42:52 +10001/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/523x/config.c
5 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -03006 * Sub-architcture dependent initialization code for the Freescale
Greg Ungererb5aaf3f2005-09-02 10:42:52 +10007 * 523x CPUs.
8 *
9 * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
11 */
12
13/***************************************************************************/
14
Greg Ungererb5aaf3f2005-09-02 10:42:52 +100015#include <linux/kernel.h>
Greg Ungererb5aaf3f2005-09-02 10:42:52 +100016#include <linux/param.h>
17#include <linux/init.h>
Greg Ungerer4b61a352008-02-01 17:34:15 +100018#include <linux/io.h>
Greg Ungererb5aaf3f2005-09-02 10:42:52 +100019#include <asm/machdep.h>
20#include <asm/coldfire.h>
21#include <asm/mcfsim.h>
Greg Ungerer045f8c42012-04-17 14:16:16 +100022#include <asm/mcfgpio.h>
23
24/***************************************************************************/
25
26struct mcf_gpio_chip mcf_gpio_chips[] = {
27 MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
28 MCFGPF(ADDR, 13, 3),
29 MCFGPF(DATAH, 16, 8),
30 MCFGPF(DATAL, 24, 8),
31 MCFGPF(BUSCTL, 32, 8),
32 MCFGPF(BS, 40, 4),
33 MCFGPF(CS, 49, 7),
34 MCFGPF(SDRAM, 56, 6),
35 MCFGPF(FECI2C, 64, 4),
36 MCFGPF(UARTH, 72, 2),
37 MCFGPF(UARTL, 80, 8),
38 MCFGPF(QSPI, 88, 5),
39 MCFGPF(TIMER, 96, 8),
40 MCFGPF(ETPU, 104, 3),
41};
42
43unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
Greg Ungererb5aaf3f2005-09-02 10:42:52 +100044
45/***************************************************************************/
46
Steven King83ca6002012-05-06 12:22:53 -070047#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
Steven King91d60412010-01-22 12:43:03 -080048
49static void __init m523x_qspi_init(void)
50{
51 u16 par;
52
53 /* setup QSPS pins for QSPI with gpio CS control */
54 writeb(0x1f, MCFGPIO_PAR_QSPI);
55 /* and CS2 & CS3 as gpio */
56 par = readw(MCFGPIO_PAR_TIMER);
57 par &= 0x3f3f;
58 writew(par, MCFGPIO_PAR_TIMER);
59}
Steven King91d60412010-01-22 12:43:03 -080060
Steven King83ca6002012-05-06 12:22:53 -070061#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
Greg Ungerer4b61a352008-02-01 17:34:15 +100062
63/***************************************************************************/
64
Greg Ungerer14c16db2009-08-12 16:14:43 +100065static void __init m523x_fec_init(void)
66{
67 u16 par;
68 u8 v;
69
70 /* Set multi-function pins to ethernet use */
71 par = readw(MCF_IPSBAR + 0x100082);
72 writew(par | 0xf00, MCF_IPSBAR + 0x100082);
73 v = readb(MCF_IPSBAR + 0x100078);
74 writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
75}
76
77/***************************************************************************/
78
Greg Ungerer4b61a352008-02-01 17:34:15 +100079void __init config_BSP(char *commandp, int size)
Greg Ungererb5aaf3f2005-09-02 10:42:52 +100080{
Greg Ungerer35aefb22012-01-23 15:34:58 +100081 mach_sched_init = hw_timer_init;
Greg Ungerer2ba168a2011-12-24 13:00:02 +100082 m523x_fec_init();
Steven King83ca6002012-05-06 12:22:53 -070083#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
Steven King91d60412010-01-22 12:43:03 -080084 m523x_qspi_init();
85#endif
Greg Ungerer4b61a352008-02-01 17:34:15 +100086}
87
Greg Ungerer4b61a352008-02-01 17:34:15 +100088/***************************************************************************/