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gerrit-public.fairphone.software / kernel / msm-5.4 / 9f790afbdd54d49b04116c7bdae655ede21846d7 / . / arch / arm / boot / dts / stm32mp157c.dtsi
blob: c81f7edf4954ad8d727bb555df6a760ec8ed0b3d [file] [log] [blame]
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]7#include <dt-bindings/clock/stm32mp1-clks.h>
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu0: cpu@0 {
18 compatible = "arm,cortex-a7";
19 device_type = "cpu";
20 reg = <0>;
21 };
22
23 cpu1: cpu@1 {
24 compatible = "arm,cortex-a7";
25 device_type = "cpu";
26 reg = <1>;
27 };
28 };
29
30 psci {
31 compatible = "arm,psci";
32 method = "smc";
33 cpu_off = <0x84000002>;
34 cpu_on = <0x84000003>;
35 };
36
37 aliases {
38 gpio0 = &gpioa;
39 gpio1 = &gpiob;
40 gpio2 = &gpioc;
41 gpio3 = &gpiod;
42 gpio4 = &gpioe;
43 gpio5 = &gpiof;
44 gpio6 = &gpiog;
45 gpio7 = &gpioh;
46 gpio8 = &gpioi;
47 gpio9 = &gpioj;
48 gpio10 = &gpiok;
49 };
50
51 intc: interrupt-controller@a0021000 {
52 compatible = "arm,cortex-a7-gic";
53 #interrupt-cells = <3>;
54 interrupt-controller;
55 reg = <0xa0021000 0x1000>,
56 <0xa0022000 0x2000>;
57 };
58
59 timer {
60 compatible = "arm,armv7-timer";
61 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
65 interrupt-parent = <&intc>;
66 };
67
68 clocks {
69 clk_hse: clk-hse {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <24000000>;
73 };
74
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]75 clk_hsi: clk-hsi {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <64000000>;
79 };
80
81 clk_lse: clk-lse {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <32768>;
85 };
86
87 clk_lsi: clk-lsi {
88 #clock-cells = <0>;
89 compatible = "fixed-clock";
90 clock-frequency = <32000>;
91 };
92
93 clk_csi: clk-csi {
94 #clock-cells = <0>;
95 compatible = "fixed-clock";
96 clock-frequency = <4000000>;
97 };
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]98 };
99
100 soc {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 interrupt-parent = <&intc>;
105 ranges;
106
Fabrice Gasnier61fc2112018-04-17 15:45:00 +0200[diff] [blame]107 timers2: timer@40000000 {
108 #address-cells = <1>;
109 #size-cells = <0>;
110 compatible = "st,stm32-timers";
111 reg = <0x40000000 0x400>;
112 clocks = <&rcc TIM2_K>;
113 clock-names = "int";
114 status = "disabled";
115
116 pwm {
117 compatible = "st,stm32-pwm";
118 status = "disabled";
119 };
120
121 timer@1 {
122 compatible = "st,stm32h7-timer-trigger";
123 reg = <1>;
124 status = "disabled";
125 };
126 };
127
128 timers3: timer@40001000 {
129 #address-cells = <1>;
130 #size-cells = <0>;
131 compatible = "st,stm32-timers";
132 reg = <0x40001000 0x400>;
133 clocks = <&rcc TIM3_K>;
134 clock-names = "int";
135 status = "disabled";
136
137 pwm {
138 compatible = "st,stm32-pwm";
139 status = "disabled";
140 };
141
142 timer@2 {
143 compatible = "st,stm32h7-timer-trigger";
144 reg = <2>;
145 status = "disabled";
146 };
147 };
148
149 timers4: timer@40002000 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 compatible = "st,stm32-timers";
153 reg = <0x40002000 0x400>;
154 clocks = <&rcc TIM4_K>;
155 clock-names = "int";
156 status = "disabled";
157
158 pwm {
159 compatible = "st,stm32-pwm";
160 status = "disabled";
161 };
162
163 timer@3 {
164 compatible = "st,stm32h7-timer-trigger";
165 reg = <3>;
166 status = "disabled";
167 };
168 };
169
170 timers5: timer@40003000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "st,stm32-timers";
174 reg = <0x40003000 0x400>;
175 clocks = <&rcc TIM5_K>;
176 clock-names = "int";
177 status = "disabled";
178
179 pwm {
180 compatible = "st,stm32-pwm";
181 status = "disabled";
182 };
183
184 timer@4 {
185 compatible = "st,stm32h7-timer-trigger";
186 reg = <4>;
187 status = "disabled";
188 };
189 };
190
191 timers6: timer@40004000 {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 compatible = "st,stm32-timers";
195 reg = <0x40004000 0x400>;
196 clocks = <&rcc TIM6_K>;
197 clock-names = "int";
198 status = "disabled";
199
200 timer@5 {
201 compatible = "st,stm32h7-timer-trigger";
202 reg = <5>;
203 status = "disabled";
204 };
205 };
206
207 timers7: timer@40005000 {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 compatible = "st,stm32-timers";
211 reg = <0x40005000 0x400>;
212 clocks = <&rcc TIM7_K>;
213 clock-names = "int";
214 status = "disabled";
215
216 timer@6 {
217 compatible = "st,stm32h7-timer-trigger";
218 reg = <6>;
219 status = "disabled";
220 };
221 };
222
223 timers12: timer@40006000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "st,stm32-timers";
227 reg = <0x40006000 0x400>;
228 clocks = <&rcc TIM12_K>;
229 clock-names = "int";
230 status = "disabled";
231
232 pwm {
233 compatible = "st,stm32-pwm";
234 status = "disabled";
235 };
236
237 timer@11 {
238 compatible = "st,stm32h7-timer-trigger";
239 reg = <11>;
240 status = "disabled";
241 };
242 };
243
244 timers13: timer@40007000 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "st,stm32-timers";
248 reg = <0x40007000 0x400>;
249 clocks = <&rcc TIM13_K>;
250 clock-names = "int";
251 status = "disabled";
252
253 pwm {
254 compatible = "st,stm32-pwm";
255 status = "disabled";
256 };
257
258 timer@12 {
259 compatible = "st,stm32h7-timer-trigger";
260 reg = <12>;
261 status = "disabled";
262 };
263 };
264
265 timers14: timer@40008000 {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 compatible = "st,stm32-timers";
269 reg = <0x40008000 0x400>;
270 clocks = <&rcc TIM14_K>;
271 clock-names = "int";
272 status = "disabled";
273
274 pwm {
275 compatible = "st,stm32-pwm";
276 status = "disabled";
277 };
278
279 timer@13 {
280 compatible = "st,stm32h7-timer-trigger";
281 reg = <13>;
282 status = "disabled";
283 };
284 };
285
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]286 usart2: serial@4000e000 {
287 compatible = "st,stm32h7-uart";
288 reg = <0x4000e000 0x400>;
289 interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]290 clocks = <&rcc USART2_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]291 status = "disabled";
292 };
293
294 usart3: serial@4000f000 {
295 compatible = "st,stm32h7-uart";
296 reg = <0x4000f000 0x400>;
297 interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]298 clocks = <&rcc USART3_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]299 status = "disabled";
300 };
301
302 uart4: serial@40010000 {
303 compatible = "st,stm32h7-uart";
304 reg = <0x40010000 0x400>;
305 interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]306 clocks = <&rcc UART4_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]307 status = "disabled";
308 };
309
310 uart5: serial@40011000 {
311 compatible = "st,stm32h7-uart";
312 reg = <0x40011000 0x400>;
313 interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]314 clocks = <&rcc UART5_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]315 status = "disabled";
316 };
317
318 uart7: serial@40018000 {
319 compatible = "st,stm32h7-uart";
320 reg = <0x40018000 0x400>;
321 interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]322 clocks = <&rcc UART7_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]323 status = "disabled";
324 };
325
326 uart8: serial@40019000 {
327 compatible = "st,stm32h7-uart";
328 reg = <0x40019000 0x400>;
329 interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]330 clocks = <&rcc UART8_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]331 status = "disabled";
332 };
333
Fabrice Gasnier61fc2112018-04-17 15:45:00 +0200[diff] [blame]334 timers1: timer@44000000 {
335 #address-cells = <1>;
336 #size-cells = <0>;
337 compatible = "st,stm32-timers";
338 reg = <0x44000000 0x400>;
339 clocks = <&rcc TIM1_K>;
340 clock-names = "int";
341 status = "disabled";
342
343 pwm {
344 compatible = "st,stm32-pwm";
345 status = "disabled";
346 };
347
348 timer@0 {
349 compatible = "st,stm32h7-timer-trigger";
350 reg = <0>;
351 status = "disabled";
352 };
353 };
354
355 timers8: timer@44001000 {
356 #address-cells = <1>;
357 #size-cells = <0>;
358 compatible = "st,stm32-timers";
359 reg = <0x44001000 0x400>;
360 clocks = <&rcc TIM8_K>;
361 clock-names = "int";
362 status = "disabled";
363
364 pwm {
365 compatible = "st,stm32-pwm";
366 status = "disabled";
367 };
368
369 timer@7 {
370 compatible = "st,stm32h7-timer-trigger";
371 reg = <7>;
372 status = "disabled";
373 };
374 };
375
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]376 usart6: serial@44003000 {
377 compatible = "st,stm32h7-uart";
378 reg = <0x44003000 0x400>;
379 interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]380 clocks = <&rcc USART6_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]381 status = "disabled";
382 };
383
Fabrice Gasnier61fc2112018-04-17 15:45:00 +0200[diff] [blame]384 timers15: timer@44006000 {
385 #address-cells = <1>;
386 #size-cells = <0>;
387 compatible = "st,stm32-timers";
388 reg = <0x44006000 0x400>;
389 clocks = <&rcc TIM15_K>;
390 clock-names = "int";
391 status = "disabled";
392
393 pwm {
394 compatible = "st,stm32-pwm";
395 status = "disabled";
396 };
397
398 timer@14 {
399 compatible = "st,stm32h7-timer-trigger";
400 reg = <14>;
401 status = "disabled";
402 };
403 };
404
405 timers16: timer@44007000 {
406 #address-cells = <1>;
407 #size-cells = <0>;
408 compatible = "st,stm32-timers";
409 reg = <0x44007000 0x400>;
410 clocks = <&rcc TIM16_K>;
411 clock-names = "int";
412 status = "disabled";
413
414 pwm {
415 compatible = "st,stm32-pwm";
416 status = "disabled";
417 };
418 timer@15 {
419 compatible = "st,stm32h7-timer-trigger";
420 reg = <15>;
421 status = "disabled";
422 };
423 };
424
425 timers17: timer@44008000 {
426 #address-cells = <1>;
427 #size-cells = <0>;
428 compatible = "st,stm32-timers";
429 reg = <0x44008000 0x400>;
430 clocks = <&rcc TIM17_K>;
431 clock-names = "int";
432 status = "disabled";
433
434 pwm {
435 compatible = "st,stm32-pwm";
436 status = "disabled";
437 };
438
439 timer@16 {
440 compatible = "st,stm32h7-timer-trigger";
441 reg = <16>;
442 status = "disabled";
443 };
444 };
445
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]446 rcc: rcc@50000000 {
447 compatible = "st,stm32mp1-rcc", "syscon";
448 reg = <0x50000000 0x1000>;
449 #clock-cells = <1>;
450 #reset-cells = <1>;
451 };
452
Fabrice Gasnier9f790af2018-04-18 09:47:00 +0200[diff] [blame^]453 vrefbuf: vrefbuf@50025000 {
454 compatible = "st,stm32-vrefbuf";
455 reg = <0x50025000 0x8>;
456 regulator-min-microvolt = <1500000>;
457 regulator-max-microvolt = <2500000>;
458 clocks = <&rcc VREF>;
459 status = "disabled";
460 };
461
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]462 usart1: serial@5c000000 {
463 compatible = "st,stm32h7-uart";
464 reg = <0x5c000000 0x400>;
465 interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]466 clocks = <&rcc USART1_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]467 status = "disabled";
468 };
469 };
470};