Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-5.4 / db27136a89d061bf9dceb28953a61a8ef862ca7f / . / drivers / scsi / mpt2sas / mpi / mpi2_cnfg.h
blob: 5af66dbe3239894789ee6bc6d6ac072c3c7c64f2 [file] [log] [blame]
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1/*
2 * Copyright (c) 2000-2009 LSI Corporation.
3 *
4 *
5 * Name: mpi2_cnfg.h
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
8 *
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]9 * mpi2_cnfg.h Version: 02.00.11
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
20 * define.
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
25 * forms.
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
31 * Page 0).
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
37 * NVDATA.
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
46 * Page 0.
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
58 * to 0x000000FF.
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
83 * to this page.
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
86 * Page 6.
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
97 * SAS Device Page 0.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
99 * Unit Page 6.
100 * Added expander reduced functionality data to SAS
101 * Expander Page 0.
102 * Added SAS PHY Page 2 and SAS PHY Page 3.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]103 * --------------------------------------------------------------------------
104 */
105
106#ifndef MPI2_CNFG_H
107#define MPI2_CNFG_H
108
109/*****************************************************************************
110* Configuration Page Header and defines
111*****************************************************************************/
112
113/* Config Page Header */
114typedef struct _MPI2_CONFIG_PAGE_HEADER
115{
116 U8 PageVersion; /* 0x00 */
117 U8 PageLength; /* 0x01 */
118 U8 PageNumber; /* 0x02 */
119 U8 PageType; /* 0x03 */
120} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
121 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
122
123typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
124{
125 MPI2_CONFIG_PAGE_HEADER Struct;
126 U8 Bytes[4];
127 U16 Word16[2];
128 U32 Word32;
129} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
130 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
131
132/* Extended Config Page Header */
133typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
134{
135 U8 PageVersion; /* 0x00 */
136 U8 Reserved1; /* 0x01 */
137 U8 PageNumber; /* 0x02 */
138 U8 PageType; /* 0x03 */
139 U16 ExtPageLength; /* 0x04 */
140 U8 ExtPageType; /* 0x06 */
141 U8 Reserved2; /* 0x07 */
142} MPI2_CONFIG_EXTENDED_PAGE_HEADER,
143 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
144 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
145
146typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
147{
148 MPI2_CONFIG_PAGE_HEADER Struct;
149 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
150 U8 Bytes[8];
151 U16 Word16[4];
152 U32 Word32[2];
153} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
154 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
155
156
157/* PageType field values */
158#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
159#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
160#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
161#define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
162
163#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
164#define MPI2_CONFIG_PAGETYPE_IOC (0x01)
165#define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
166#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
167#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
168#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
169#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
170#define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
171
172#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
173
174
175/* ExtPageType field values */
176#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
177#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
178#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
179#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
180#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
181#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
182#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
183#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
184#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
185
186
187/*****************************************************************************
188* PageAddress defines
189*****************************************************************************/
190
191/* RAID Volume PageAddress format */
192#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
193#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
194#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
195
196#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
197
198
199/* RAID Physical Disk PageAddress format */
200#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
201#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
202#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
203#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
204
205#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
206#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
207
208
209/* SAS Expander PageAddress format */
210#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
211#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
212#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
213#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
214
215#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
216#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
217#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
218
219
220/* SAS Device PageAddress format */
221#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
222#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
223#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
224
225#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
226
227
228/* SAS PHY PageAddress format */
229#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
230#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
231#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
232
233#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
234#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
235
236
237/* SAS Port PageAddress format */
238#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
239#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
240#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
241
242#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
243
244
245/* SAS Enclosure PageAddress format */
246#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
247#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
248#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
249
250#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
251
252
253/* RAID Configuration PageAddress format */
254#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
255#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
256#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
257#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
258
259#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
260
261
262/* Driver Persistent Mapping PageAddress format */
263#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
264#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
265
266#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
267#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
268#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
269
270
271/****************************************************************************
272* Configuration messages
273****************************************************************************/
274
275/* Configuration Request Message */
276typedef struct _MPI2_CONFIG_REQUEST
277{
278 U8 Action; /* 0x00 */
279 U8 SGLFlags; /* 0x01 */
280 U8 ChainOffset; /* 0x02 */
281 U8 Function; /* 0x03 */
282 U16 ExtPageLength; /* 0x04 */
283 U8 ExtPageType; /* 0x06 */
284 U8 MsgFlags; /* 0x07 */
285 U8 VP_ID; /* 0x08 */
286 U8 VF_ID; /* 0x09 */
287 U16 Reserved1; /* 0x0A */
288 U32 Reserved2; /* 0x0C */
289 U32 Reserved3; /* 0x10 */
290 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
291 U32 PageAddress; /* 0x18 */
292 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
293} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
294 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
295
296/* values for the Action field */
297#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
298#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
299#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
300#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
301#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
302#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
303#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
304#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
305
306/* values for SGLFlags field are in the SGL section of mpi2.h */
307
308
309/* Config Reply Message */
310typedef struct _MPI2_CONFIG_REPLY
311{
312 U8 Action; /* 0x00 */
313 U8 SGLFlags; /* 0x01 */
314 U8 MsgLength; /* 0x02 */
315 U8 Function; /* 0x03 */
316 U16 ExtPageLength; /* 0x04 */
317 U8 ExtPageType; /* 0x06 */
318 U8 MsgFlags; /* 0x07 */
319 U8 VP_ID; /* 0x08 */
320 U8 VF_ID; /* 0x09 */
321 U16 Reserved1; /* 0x0A */
322 U16 Reserved2; /* 0x0C */
323 U16 IOCStatus; /* 0x0E */
324 U32 IOCLogInfo; /* 0x10 */
325 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
326} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
327 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
328
329
330
331/*****************************************************************************
332*
333* C o n f i g u r a t i o n P a g e s
334*
335*****************************************************************************/
336
337/****************************************************************************
338* Manufacturing Config pages
339****************************************************************************/
340
341#define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
342
343/* SAS */
344#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
345#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
346#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
347#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
348#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
349#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
350#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
Kashyap, Desaidb271362009-09-23 17:24:27 +0530[diff] [blame^]351#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
352#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
353#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
354#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
355#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
356#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
357#define MPI2_MFGPAGE_DEVID_SAS2208_7 (0x0086)
358#define MPI2_MFGPAGE_DEVID_SAS2208_8 (0x0087)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]359
360
361/* Manufacturing Page 0 */
362
363typedef struct _MPI2_CONFIG_PAGE_MAN_0
364{
365 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
366 U8 ChipName[16]; /* 0x04 */
367 U8 ChipRevision[8]; /* 0x14 */
368 U8 BoardName[16]; /* 0x1C */
369 U8 BoardAssembly[16]; /* 0x2C */
370 U8 BoardTracerNumber[16]; /* 0x3C */
371} MPI2_CONFIG_PAGE_MAN_0,
372 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
373 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
374
375#define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
376
377
378/* Manufacturing Page 1 */
379
380typedef struct _MPI2_CONFIG_PAGE_MAN_1
381{
382 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
383 U8 VPD[256]; /* 0x04 */
384} MPI2_CONFIG_PAGE_MAN_1,
385 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
386 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
387
388#define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
389
390
391typedef struct _MPI2_CHIP_REVISION_ID
392{
393 U16 DeviceID; /* 0x00 */
394 U8 PCIRevisionID; /* 0x02 */
395 U8 Reserved; /* 0x03 */
396} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
397 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
398
399
400/* Manufacturing Page 2 */
401
402/*
403 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
404 * one and check Header.PageLength at runtime.
405 */
406#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
407#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
408#endif
409
410typedef struct _MPI2_CONFIG_PAGE_MAN_2
411{
412 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
413 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
414 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
415} MPI2_CONFIG_PAGE_MAN_2,
416 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
417 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
418
419#define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
420
421
422/* Manufacturing Page 3 */
423
424/*
425 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
426 * one and check Header.PageLength at runtime.
427 */
428#ifndef MPI2_MAN_PAGE_3_INFO_WORDS
429#define MPI2_MAN_PAGE_3_INFO_WORDS (1)
430#endif
431
432typedef struct _MPI2_CONFIG_PAGE_MAN_3
433{
434 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
435 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
436 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
437} MPI2_CONFIG_PAGE_MAN_3,
438 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
439 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
440
441#define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
442
443
444/* Manufacturing Page 4 */
445
446typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
447{
448 U8 PowerSaveFlags; /* 0x00 */
449 U8 InternalOperationsSleepTime; /* 0x01 */
450 U8 InternalOperationsRunTime; /* 0x02 */
451 U8 HostIdleTime; /* 0x03 */
452} MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
453 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
454 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
455
456/* defines for the PowerSaveFlags field */
457#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
458#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
459#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
460#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
461
462typedef struct _MPI2_CONFIG_PAGE_MAN_4
463{
464 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
465 U32 Reserved1; /* 0x04 */
466 U32 Flags; /* 0x08 */
467 U8 InquirySize; /* 0x0C */
468 U8 Reserved2; /* 0x0D */
469 U16 Reserved3; /* 0x0E */
470 U8 InquiryData[56]; /* 0x10 */
471 U32 RAID0VolumeSettings; /* 0x48 */
472 U32 RAID1EVolumeSettings; /* 0x4C */
473 U32 RAID1VolumeSettings; /* 0x50 */
474 U32 RAID10VolumeSettings; /* 0x54 */
475 U32 Reserved4; /* 0x58 */
476 U32 Reserved5; /* 0x5C */
477 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
478 U8 MaxOCEDisks; /* 0x64 */
479 U8 ResyncRate; /* 0x65 */
480 U16 DataScrubDuration; /* 0x66 */
481 U8 MaxHotSpares; /* 0x68 */
482 U8 MaxPhysDisksPerVol; /* 0x69 */
483 U8 MaxPhysDisks; /* 0x6A */
484 U8 MaxVolumes; /* 0x6B */
485} MPI2_CONFIG_PAGE_MAN_4,
486 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
487 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
488
489#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
490
491/* Manufacturing Page 4 Flags field */
492#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
493#define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
494
495#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
496#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
497#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
498
499#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
500#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
501#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
502#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
503#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
504
505#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
506#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
507#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
508#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
509
510#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
511#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
512#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
513#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
514#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
515#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
516#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
517#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
518
519
520/* Manufacturing Page 5 */
521
522/*
523 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
524 * one and check Header.PageLength or NumPhys at runtime.
525 */
526#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
527#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
528#endif
529
530typedef struct _MPI2_MANUFACTURING5_ENTRY
531{
532 U64 WWID; /* 0x00 */
533 U64 DeviceName; /* 0x08 */
534} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
535 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
536
537typedef struct _MPI2_CONFIG_PAGE_MAN_5
538{
539 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
540 U8 NumPhys; /* 0x04 */
541 U8 Reserved1; /* 0x05 */
542 U16 Reserved2; /* 0x06 */
543 U32 Reserved3; /* 0x08 */
544 U32 Reserved4; /* 0x0C */
545 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
546} MPI2_CONFIG_PAGE_MAN_5,
547 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
548 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
549
550#define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
551
552
553/* Manufacturing Page 6 */
554
555typedef struct _MPI2_CONFIG_PAGE_MAN_6
556{
557 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
558 U32 ProductSpecificInfo;/* 0x04 */
559} MPI2_CONFIG_PAGE_MAN_6,
560 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
561 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
562
563#define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
564
565
566/* Manufacturing Page 7 */
567
568typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
569{
570 U32 Pinout; /* 0x00 */
571 U8 Connector[16]; /* 0x04 */
572 U8 Location; /* 0x14 */
573 U8 Reserved1; /* 0x15 */
574 U16 Slot; /* 0x16 */
575 U32 Reserved2; /* 0x18 */
576} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
577 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
578
579/* defines for the Pinout field */
580#define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
581#define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
582#define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
583#define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
584#define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
585#define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
586#define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
587#define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
588#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
589#define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
590
591/* defines for the Location field */
592#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
593#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
594#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
595#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
596#define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
597#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
598#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
599
600/*
601 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
602 * one and check NumPhys at runtime.
603 */
604#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
605#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
606#endif
607
608typedef struct _MPI2_CONFIG_PAGE_MAN_7
609{
610 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
611 U32 Reserved1; /* 0x04 */
612 U32 Reserved2; /* 0x08 */
613 U32 Flags; /* 0x0C */
614 U8 EnclosureName[16]; /* 0x10 */
615 U8 NumPhys; /* 0x20 */
616 U8 Reserved3; /* 0x21 */
617 U16 Reserved4; /* 0x22 */
618 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
619} MPI2_CONFIG_PAGE_MAN_7,
620 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
621 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
622
623#define MPI2_MANUFACTURING7_PAGEVERSION (0x00)
624
625/* defines for the Flags field */
626#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
627
628
629/*
630 * Generic structure to use for product-specific manufacturing pages
631 * (currently Manufacturing Page 8 through Manufacturing Page 31).
632 */
633
634typedef struct _MPI2_CONFIG_PAGE_MAN_PS
635{
636 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
637 U32 ProductSpecificInfo;/* 0x04 */
638} MPI2_CONFIG_PAGE_MAN_PS,
639 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
640 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
641
642#define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
643#define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
644#define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
645#define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
646#define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
647#define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
648#define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
649#define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
650#define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
651#define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
652#define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
653#define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
654#define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
655#define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
656#define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
657#define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
658#define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
659#define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
660#define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
661#define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
662#define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
663#define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
664#define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
665#define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
666
667
668/****************************************************************************
669* IO Unit Config Pages
670****************************************************************************/
671
672/* IO Unit Page 0 */
673
674typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
675{
676 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
677 U64 UniqueValue; /* 0x04 */
678 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
679 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
680} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
681 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
682
683#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
684
685
686/* IO Unit Page 1 */
687
688typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
689{
690 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
691 U32 Flags; /* 0x04 */
692} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
693 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
694
695#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
696
697/* IO Unit Page 1 Flags defines */
698#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
699#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
700#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
701#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
702#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
703#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
704#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
705#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
706#define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002)
707#define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
708
709
710/* IO Unit Page 3 */
711
712/*
713 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
714 * one and check Header.PageLength at runtime.
715 */
716#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
717#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
718#endif
719
720typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
721{
722 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
723 U8 GPIOCount; /* 0x04 */
724 U8 Reserved1; /* 0x05 */
725 U16 Reserved2; /* 0x06 */
726 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
727} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
728 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
729
730#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
731
732/* defines for IO Unit Page 3 GPIOVal field */
733#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
734#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
735#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
736#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
737
738
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]739/* IO Unit Page 5 */
740
741/*
742 * Upper layer code (drivers, utilities, etc.) should leave this define set to
743 * one and check Header.PageLength or NumDmaEngines at runtime.
744 */
745#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
746#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
747#endif
748
749typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
750 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
751 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
752 U64 RaidAcceleratorBufferSize; /* 0x0C */
753 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
754 U8 RAControlSize; /* 0x1C */
755 U8 NumDmaEngines; /* 0x1D */
756 U8 RAMinControlSize; /* 0x1E */
757 U8 RAMaxControlSize; /* 0x1F */
758 U32 Reserved1; /* 0x20 */
759 U32 Reserved2; /* 0x24 */
760 U32 Reserved3; /* 0x28 */
761 U32 DmaEngineCapabilities
762 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
763} MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
764 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
765
766#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
767
768/* defines for IO Unit Page 5 DmaEngineCapabilities field */
769#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
770#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
771
772#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
773#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
774#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
775#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
776
777
778/* IO Unit Page 6 */
779
780typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
781 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
782 U16 Flags; /* 0x04 */
783 U8 RAHostControlSize; /* 0x06 */
784 U8 Reserved0; /* 0x07 */
785 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
786 U32 Reserved1; /* 0x10 */
787 U32 Reserved2; /* 0x14 */
788 U32 Reserved3; /* 0x18 */
789} MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
790 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
791
792#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
793
794/* defines for IO Unit Page 6 Flags field */
795#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
796
797
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]798/****************************************************************************
799* IOC Config Pages
800****************************************************************************/
801
802/* IOC Page 0 */
803
804typedef struct _MPI2_CONFIG_PAGE_IOC_0
805{
806 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
807 U32 Reserved1; /* 0x04 */
808 U32 Reserved2; /* 0x08 */
809 U16 VendorID; /* 0x0C */
810 U16 DeviceID; /* 0x0E */
811 U8 RevisionID; /* 0x10 */
812 U8 Reserved3; /* 0x11 */
813 U16 Reserved4; /* 0x12 */
814 U32 ClassCode; /* 0x14 */
815 U16 SubsystemVendorID; /* 0x18 */
816 U16 SubsystemID; /* 0x1A */
817} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
818 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
819
820#define MPI2_IOCPAGE0_PAGEVERSION (0x02)
821
822
823/* IOC Page 1 */
824
825typedef struct _MPI2_CONFIG_PAGE_IOC_1
826{
827 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
828 U32 Flags; /* 0x04 */
829 U32 CoalescingTimeout; /* 0x08 */
830 U8 CoalescingDepth; /* 0x0C */
831 U8 PCISlotNum; /* 0x0D */
832 U8 PCIBusNum; /* 0x0E */
833 U8 PCIDomainSegment; /* 0x0F */
834 U32 Reserved1; /* 0x10 */
835 U32 Reserved2; /* 0x14 */
836} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
837 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
838
839#define MPI2_IOCPAGE1_PAGEVERSION (0x05)
840
841/* defines for IOC Page 1 Flags field */
842#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
843
844#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
845#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
846#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
847
848/* IOC Page 6 */
849
850typedef struct _MPI2_CONFIG_PAGE_IOC_6
851{
852 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
853 U32 CapabilitiesFlags; /* 0x04 */
854 U8 MaxDrivesRAID0; /* 0x08 */
855 U8 MaxDrivesRAID1; /* 0x09 */
856 U8 MaxDrivesRAID1E; /* 0x0A */
857 U8 MaxDrivesRAID10; /* 0x0B */
858 U8 MinDrivesRAID0; /* 0x0C */
859 U8 MinDrivesRAID1; /* 0x0D */
860 U8 MinDrivesRAID1E; /* 0x0E */
861 U8 MinDrivesRAID10; /* 0x0F */
862 U32 Reserved1; /* 0x10 */
863 U8 MaxGlobalHotSpares; /* 0x14 */
864 U8 MaxPhysDisks; /* 0x15 */
865 U8 MaxVolumes; /* 0x16 */
866 U8 MaxConfigs; /* 0x17 */
867 U8 MaxOCEDisks; /* 0x18 */
868 U8 Reserved2; /* 0x19 */
869 U16 Reserved3; /* 0x1A */
870 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
871 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
872 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
873 U32 Reserved4; /* 0x28 */
874 U32 Reserved5; /* 0x2C */
875 U16 DefaultMetadataSize; /* 0x30 */
876 U16 Reserved6; /* 0x32 */
877 U16 MaxBadBlockTableEntries; /* 0x34 */
878 U16 Reserved7; /* 0x36 */
879 U32 IRNvsramVersion; /* 0x38 */
880} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
881 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
882
883#define MPI2_IOCPAGE6_PAGEVERSION (0x04)
884
885/* defines for IOC Page 6 CapabilitiesFlags */
886#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
887#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
888#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
889#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
890#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
891
892
893/* IOC Page 7 */
894
895#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
896
897typedef struct _MPI2_CONFIG_PAGE_IOC_7
898{
899 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
900 U32 Reserved1; /* 0x04 */
901 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
902 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
903 U16 Reserved2; /* 0x1A */
904 U32 Reserved3; /* 0x1C */
905} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
906 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
907
908#define MPI2_IOCPAGE7_PAGEVERSION (0x01)
909
910
911/* IOC Page 8 */
912
913typedef struct _MPI2_CONFIG_PAGE_IOC_8
914{
915 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
916 U8 NumDevsPerEnclosure; /* 0x04 */
917 U8 Reserved1; /* 0x05 */
918 U16 Reserved2; /* 0x06 */
919 U16 MaxPersistentEntries; /* 0x08 */
920 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
921 U16 Flags; /* 0x0C */
922 U16 Reserved3; /* 0x0E */
923 U16 IRVolumeMappingFlags; /* 0x10 */
924 U16 Reserved4; /* 0x12 */
925 U32 Reserved5; /* 0x14 */
926} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
927 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
928
929#define MPI2_IOCPAGE8_PAGEVERSION (0x00)
930
931/* defines for IOC Page 8 Flags field */
932#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
933#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
934
935#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
936#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
937#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
938
939#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
940#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
941
942/* defines for IOC Page 8 IRVolumeMappingFlags */
943#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
944#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
945#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
946
947
948/****************************************************************************
949* BIOS Config Pages
950****************************************************************************/
951
952/* BIOS Page 1 */
953
954typedef struct _MPI2_CONFIG_PAGE_BIOS_1
955{
956 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
957 U32 BiosOptions; /* 0x04 */
958 U32 IOCSettings; /* 0x08 */
959 U32 Reserved1; /* 0x0C */
960 U32 DeviceSettings; /* 0x10 */
961 U16 NumberOfDevices; /* 0x14 */
962 U16 Reserved2; /* 0x16 */
963 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
964 U16 IOTimeoutSequential; /* 0x1A */
965 U16 IOTimeoutOther; /* 0x1C */
966 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
967} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
968 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
969
970#define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
971
972/* values for BIOS Page 1 BiosOptions field */
973#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
974
975/* values for BIOS Page 1 IOCSettings field */
976#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
977#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
978#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
979
980#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
981#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
982#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
983#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
984
985#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
986#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
987#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
988#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
989#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
990
991#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
992
993/* values for BIOS Page 1 DeviceSettings field */
994#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
995#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
996#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
997#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
998#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
999
1000
1001/* BIOS Page 2 */
1002
1003typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1004{
1005 U32 Reserved1; /* 0x00 */
1006 U32 Reserved2; /* 0x04 */
1007 U32 Reserved3; /* 0x08 */
1008 U32 Reserved4; /* 0x0C */
1009 U32 Reserved5; /* 0x10 */
1010 U32 Reserved6; /* 0x14 */
1011} MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1012 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1013 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1014
1015typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1016{
1017 U64 SASAddress; /* 0x00 */
1018 U8 LUN[8]; /* 0x08 */
1019 U32 Reserved1; /* 0x10 */
1020 U32 Reserved2; /* 0x14 */
1021} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1022 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1023
1024typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1025{
1026 U64 EnclosureLogicalID; /* 0x00 */
1027 U32 Reserved1; /* 0x08 */
1028 U32 Reserved2; /* 0x0C */
1029 U16 SlotNumber; /* 0x10 */
1030 U16 Reserved3; /* 0x12 */
1031 U32 Reserved4; /* 0x14 */
1032} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1033 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1034 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1035
1036typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1037{
1038 U64 DeviceName; /* 0x00 */
1039 U8 LUN[8]; /* 0x08 */
1040 U32 Reserved1; /* 0x10 */
1041 U32 Reserved2; /* 0x14 */
1042} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1043 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1044
1045typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1046{
1047 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1048 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1049 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1050 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1051} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1052 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1053
1054typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1055{
1056 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1057 U32 Reserved1; /* 0x04 */
1058 U32 Reserved2; /* 0x08 */
1059 U32 Reserved3; /* 0x0C */
1060 U32 Reserved4; /* 0x10 */
1061 U32 Reserved5; /* 0x14 */
1062 U32 Reserved6; /* 0x18 */
1063 U8 ReqBootDeviceForm; /* 0x1C */
1064 U8 Reserved7; /* 0x1D */
1065 U16 Reserved8; /* 0x1E */
1066 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1067 U8 ReqAltBootDeviceForm; /* 0x38 */
1068 U8 Reserved9; /* 0x39 */
1069 U16 Reserved10; /* 0x3A */
1070 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1071 U8 CurrentBootDeviceForm; /* 0x58 */
1072 U8 Reserved11; /* 0x59 */
1073 U16 Reserved12; /* 0x5A */
1074 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1075} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1076 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1077
1078#define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1079
1080/* values for BIOS Page 2 BootDeviceForm fields */
1081#define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1082#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1083#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1084#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1085#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1086
1087
1088/* BIOS Page 3 */
1089
1090typedef struct _MPI2_ADAPTER_INFO
1091{
1092 U8 PciBusNumber; /* 0x00 */
1093 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1094 U16 AdapterFlags; /* 0x02 */
1095} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1096 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1097
1098#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1099#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1100
1101typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1102{
1103 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1104 U32 GlobalFlags; /* 0x04 */
1105 U32 BiosVersion; /* 0x08 */
1106 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1107 U32 Reserved1; /* 0x1C */
1108} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1109 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1110
1111#define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1112
1113/* values for BIOS Page 3 GlobalFlags */
1114#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1115#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1116#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1117
1118#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1119#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1120#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1121#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1122
1123
1124/* BIOS Page 4 */
1125
1126/*
1127 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1128 * one and check Header.PageLength or NumPhys at runtime.
1129 */
1130#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1131#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1132#endif
1133
1134typedef struct _MPI2_BIOS4_ENTRY
1135{
1136 U64 ReassignmentWWID; /* 0x00 */
1137 U64 ReassignmentDeviceName; /* 0x08 */
1138} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1139 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1140
1141typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1142{
1143 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1144 U8 NumPhys; /* 0x04 */
1145 U8 Reserved1; /* 0x05 */
1146 U16 Reserved2; /* 0x06 */
1147 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1148} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1149 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1150
1151#define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1152
1153
1154/****************************************************************************
1155* RAID Volume Config Pages
1156****************************************************************************/
1157
1158/* RAID Volume Page 0 */
1159
1160typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1161{
1162 U8 RAIDSetNum; /* 0x00 */
1163 U8 PhysDiskMap; /* 0x01 */
1164 U8 PhysDiskNum; /* 0x02 */
1165 U8 Reserved; /* 0x03 */
1166} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1167 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1168
1169/* defines for the PhysDiskMap field */
1170#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1171#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1172
1173typedef struct _MPI2_RAIDVOL0_SETTINGS
1174{
1175 U16 Settings; /* 0x00 */
1176 U8 HotSparePool; /* 0x01 */
1177 U8 Reserved; /* 0x02 */
1178} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1179 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1180
1181/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1182#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1183#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1184#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1185#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1186#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1187#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1188#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1189#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1190
1191/* RAID Volume Page 0 VolumeSettings defines */
1192#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1193#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1194
1195#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1196#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1197#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1198#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1199
1200/*
1201 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1202 * one and check Header.PageLength at runtime.
1203 */
1204#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1205#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1206#endif
1207
1208typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1209{
1210 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1211 U16 DevHandle; /* 0x04 */
1212 U8 VolumeState; /* 0x06 */
1213 U8 VolumeType; /* 0x07 */
1214 U32 VolumeStatusFlags; /* 0x08 */
1215 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1216 U64 MaxLBA; /* 0x10 */
1217 U32 StripeSize; /* 0x18 */
1218 U16 BlockSize; /* 0x1C */
1219 U16 Reserved1; /* 0x1E */
1220 U8 SupportedPhysDisks; /* 0x20 */
1221 U8 ResyncRate; /* 0x21 */
1222 U16 DataScrubDuration; /* 0x22 */
1223 U8 NumPhysDisks; /* 0x24 */
1224 U8 Reserved2; /* 0x25 */
1225 U8 Reserved3; /* 0x26 */
1226 U8 InactiveStatus; /* 0x27 */
1227 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1228} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1229 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1230
1231#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1232
1233/* values for RAID VolumeState */
1234#define MPI2_RAID_VOL_STATE_MISSING (0x00)
1235#define MPI2_RAID_VOL_STATE_FAILED (0x01)
1236#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1237#define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1238#define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1239#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1240
1241/* values for RAID VolumeType */
1242#define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1243#define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1244#define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1245#define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1246#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1247
1248/* values for RAID Volume Page 0 VolumeStatusFlags field */
1249#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1250#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1251#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1252#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1253#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1254#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1255#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1256#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1257#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1258#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1259#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1260#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1261#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1262#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1263#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1264#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1265#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1266#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1267
1268/* values for RAID Volume Page 0 SupportedPhysDisks field */
1269#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1270#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1271#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1272#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1273
1274/* values for RAID Volume Page 0 InactiveStatus field */
1275#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1276#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1277#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1278#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1279#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1280#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1281#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1282
1283
1284/* RAID Volume Page 1 */
1285
1286typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1287{
1288 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1289 U16 DevHandle; /* 0x04 */
1290 U16 Reserved0; /* 0x06 */
1291 U8 GUID[24]; /* 0x08 */
1292 U8 Name[16]; /* 0x20 */
1293 U64 WWID; /* 0x30 */
1294 U32 Reserved1; /* 0x38 */
1295 U32 Reserved2; /* 0x3C */
1296} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1297 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1298
1299#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1300
1301
1302/****************************************************************************
1303* RAID Physical Disk Config Pages
1304****************************************************************************/
1305
1306/* RAID Physical Disk Page 0 */
1307
1308typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1309{
1310 U16 Reserved1; /* 0x00 */
1311 U8 HotSparePool; /* 0x02 */
1312 U8 Reserved2; /* 0x03 */
1313} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1314 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1315
1316/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1317
1318typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1319{
1320 U8 VendorID[8]; /* 0x00 */
1321 U8 ProductID[16]; /* 0x08 */
1322 U8 ProductRevLevel[4]; /* 0x18 */
1323 U8 SerialNum[32]; /* 0x1C */
1324} MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1325 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1326 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1327
1328typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1329{
1330 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1331 U16 DevHandle; /* 0x04 */
1332 U8 Reserved1; /* 0x06 */
1333 U8 PhysDiskNum; /* 0x07 */
1334 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1335 U32 Reserved2; /* 0x0C */
1336 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1337 U32 Reserved3; /* 0x4C */
1338 U8 PhysDiskState; /* 0x50 */
1339 U8 OfflineReason; /* 0x51 */
1340 U8 IncompatibleReason; /* 0x52 */
1341 U8 PhysDiskAttributes; /* 0x53 */
1342 U32 PhysDiskStatusFlags; /* 0x54 */
1343 U64 DeviceMaxLBA; /* 0x58 */
1344 U64 HostMaxLBA; /* 0x60 */
1345 U64 CoercedMaxLBA; /* 0x68 */
1346 U16 BlockSize; /* 0x70 */
1347 U16 Reserved5; /* 0x72 */
1348 U32 Reserved6; /* 0x74 */
1349} MPI2_CONFIG_PAGE_RD_PDISK_0,
1350 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1351 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1352
1353#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1354
1355/* PhysDiskState defines */
1356#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1357#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1358#define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1359#define MPI2_RAID_PD_STATE_ONLINE (0x03)
1360#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1361#define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1362#define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1363#define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1364
1365/* OfflineReason defines */
1366#define MPI2_PHYSDISK0_ONLINE (0x00)
1367#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1368#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1369#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1370#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1371#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1372#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1373
1374/* IncompatibleReason defines */
1375#define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1376#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1377#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1378#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1379#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1380#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1381#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1382
1383/* PhysDiskAttributes defines */
1384#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1385#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1386#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1387#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1388
1389/* PhysDiskStatusFlags defines */
1390#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1391#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1392#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1393#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1394#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1395#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1396#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1397#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1398
1399
1400/* RAID Physical Disk Page 1 */
1401
1402/*
1403 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1404 * one and check Header.PageLength or NumPhysDiskPaths at runtime.
1405 */
1406#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1407#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1408#endif
1409
1410typedef struct _MPI2_RAIDPHYSDISK1_PATH
1411{
1412 U16 DevHandle; /* 0x00 */
1413 U16 Reserved1; /* 0x02 */
1414 U64 WWID; /* 0x04 */
1415 U64 OwnerWWID; /* 0x0C */
1416 U8 OwnerIdentifier; /* 0x14 */
1417 U8 Reserved2; /* 0x15 */
1418 U16 Flags; /* 0x16 */
1419} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1420 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1421
1422/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1423#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1424#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1425#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1426
1427typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1428{
1429 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1430 U8 NumPhysDiskPaths; /* 0x04 */
1431 U8 PhysDiskNum; /* 0x05 */
1432 U16 Reserved1; /* 0x06 */
1433 U32 Reserved2; /* 0x08 */
1434 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1435} MPI2_CONFIG_PAGE_RD_PDISK_1,
1436 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1437 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1438
1439#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1440
1441
1442/****************************************************************************
1443* values for fields used by several types of SAS Config Pages
1444****************************************************************************/
1445
1446/* values for NegotiatedLinkRates fields */
1447#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1448#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1449#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1450/* link rates used for Negotiated Physical and Logical Link Rate */
1451#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1452#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1453#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1454#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1455#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1456#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1457#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1458#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1459#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1460
1461
1462/* values for AttachedPhyInfo fields */
1463#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1464#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1465#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1466
1467#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1468#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1469#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1470#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1471#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1472#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1473#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1474#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1475#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1476#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1477
1478
1479/* values for PhyInfo fields */
1480#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1481#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1482#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1483#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1484#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1485#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1486#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1487
1488#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1489#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1490#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1491#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1492#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1493#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1494#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1495#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1496#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1497#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1498
1499#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1500#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1501#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1502#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1503
1504#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1505#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1506
1507#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1508#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1509#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1510#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1511
1512
1513/* values for SAS ProgrammedLinkRate fields */
1514#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1515#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1516#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1517#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1518#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1519#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1520#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1521#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1522#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1523#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1524
1525
1526/* values for SAS HwLinkRate fields */
1527#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1528#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1529#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1530#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1531#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1532#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1533#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1534#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1535
1536
1537
1538/****************************************************************************
1539* SAS IO Unit Config Pages
1540****************************************************************************/
1541
1542/* SAS IO Unit Page 0 */
1543
1544typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1545{
1546 U8 Port; /* 0x00 */
1547 U8 PortFlags; /* 0x01 */
1548 U8 PhyFlags; /* 0x02 */
1549 U8 NegotiatedLinkRate; /* 0x03 */
1550 U32 ControllerPhyDeviceInfo;/* 0x04 */
1551 U16 AttachedDevHandle; /* 0x08 */
1552 U16 ControllerDevHandle; /* 0x0A */
1553 U32 DiscoveryStatus; /* 0x0C */
1554 U32 Reserved; /* 0x10 */
1555} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1556 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1557
1558/*
1559 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1560 * one and check Header.ExtPageLength or NumPhys at runtime.
1561 */
1562#ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1563#define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1564#endif
1565
1566typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1567{
1568 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1569 U32 Reserved1; /* 0x08 */
1570 U8 NumPhys; /* 0x0C */
1571 U8 Reserved2; /* 0x0D */
1572 U16 Reserved3; /* 0x0E */
1573 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1574} MPI2_CONFIG_PAGE_SASIOUNIT_0,
1575 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1576 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1577
1578#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1579
1580/* values for SAS IO Unit Page 0 PortFlags */
1581#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1582#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1583
1584/* values for SAS IO Unit Page 0 PhyFlags */
1585#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1586#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1587
1588/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1589
1590/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1591
1592/* values for SAS IO Unit Page 0 DiscoveryStatus */
1593#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1594#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1595#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1596#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1597#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1598#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1599#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1600#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1601#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1602#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1603#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1604#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1605#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1606#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1607#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1608#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1609#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1610#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1611#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1612#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1613
1614
1615/* SAS IO Unit Page 1 */
1616
1617typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1618{
1619 U8 Port; /* 0x00 */
1620 U8 PortFlags; /* 0x01 */
1621 U8 PhyFlags; /* 0x02 */
1622 U8 MaxMinLinkRate; /* 0x03 */
1623 U32 ControllerPhyDeviceInfo; /* 0x04 */
1624 U16 MaxTargetPortConnectTime; /* 0x08 */
1625 U16 Reserved1; /* 0x0A */
1626} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1627 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1628
1629/*
1630 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1631 * one and check Header.ExtPageLength or NumPhys at runtime.
1632 */
1633#ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1634#define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1635#endif
1636
1637typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1638{
1639 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1640 U16 ControlFlags; /* 0x08 */
1641 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1642 U16 AdditionalControlFlags; /* 0x0C */
1643 U16 SASWideMaxQueueDepth; /* 0x0E */
1644 U8 NumPhys; /* 0x10 */
1645 U8 SATAMaxQDepth; /* 0x11 */
1646 U8 ReportDeviceMissingDelay; /* 0x12 */
1647 U8 IODeviceMissingDelay; /* 0x13 */
1648 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1649} MPI2_CONFIG_PAGE_SASIOUNIT_1,
1650 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1651 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1652
1653#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1654
1655/* values for SAS IO Unit Page 1 ControlFlags */
1656#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1657#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1658#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1659#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1660
1661#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1662#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1663#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1664#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1665#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1666
1667#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1668#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1669#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1670#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1671#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1672#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1673#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1674#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1675
1676/* values for SAS IO Unit Page 1 AdditionalControlFlags */
1677#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1678#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1679#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1680#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1681#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1682#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1683#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1684#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1685
1686/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1687#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1688#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1689
1690/* values for SAS IO Unit Page 1 PortFlags */
1691#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1692
1693/* values for SAS IO Unit Page 2 PhyFlags */
1694#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1695#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1696
1697/* values for SAS IO Unit Page 0 MaxMinLinkRate */
1698#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1699#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1700#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1701#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1702#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1703#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1704#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1705#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1706
1707/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1708
1709
1710/* SAS IO Unit Page 4 */
1711
1712typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1713{
1714 U8 MaxTargetSpinup; /* 0x00 */
1715 U8 SpinupDelay; /* 0x01 */
1716 U16 Reserved1; /* 0x02 */
1717} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1718 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1719
1720/*
1721 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1722 * four and check Header.ExtPageLength or NumPhys at runtime.
1723 */
1724#ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1725#define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1726#endif
1727
1728typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1729{
1730 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1731 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1732 U32 Reserved1; /* 0x18 */
1733 U32 Reserved2; /* 0x1C */
1734 U32 Reserved3; /* 0x20 */
1735 U8 BootDeviceWaitTime; /* 0x24 */
1736 U8 Reserved4; /* 0x25 */
1737 U16 Reserved5; /* 0x26 */
1738 U8 NumPhys; /* 0x28 */
1739 U8 PEInitialSpinupDelay; /* 0x29 */
1740 U8 PEReplyDelay; /* 0x2A */
1741 U8 Flags; /* 0x2B */
1742 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
1743} MPI2_CONFIG_PAGE_SASIOUNIT_4,
1744 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1745 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1746
1747#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
1748
1749/* defines for Flags field */
1750#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
1751
1752/* defines for PHY field */
1753#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1754
1755
1756/****************************************************************************
1757* SAS Expander Config Pages
1758****************************************************************************/
1759
1760/* SAS Expander Page 0 */
1761
1762typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
1763{
1764 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1765 U8 PhysicalPort; /* 0x08 */
1766 U8 ReportGenLength; /* 0x09 */
1767 U16 EnclosureHandle; /* 0x0A */
1768 U64 SASAddress; /* 0x0C */
1769 U32 DiscoveryStatus; /* 0x14 */
1770 U16 DevHandle; /* 0x18 */
1771 U16 ParentDevHandle; /* 0x1A */
1772 U16 ExpanderChangeCount; /* 0x1C */
1773 U16 ExpanderRouteIndexes; /* 0x1E */
1774 U8 NumPhys; /* 0x20 */
1775 U8 SASLevel; /* 0x21 */
1776 U16 Flags; /* 0x22 */
1777 U16 STPBusInactivityTimeLimit; /* 0x24 */
1778 U16 STPMaxConnectTimeLimit; /* 0x26 */
1779 U16 STP_SMP_NexusLossTime; /* 0x28 */
1780 U16 MaxNumRoutedSasAddresses; /* 0x2A */
1781 U64 ActiveZoneManagerSASAddress;/* 0x2C */
1782 U16 ZoneLockInactivityLimit; /* 0x34 */
1783 U16 Reserved1; /* 0x36 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]1784 U8 TimeToReducedFunc; /* 0x38 */
1785 U8 InitialTimeToReducedFunc; /* 0x39 */
1786 U8 MaxReducedFuncTime; /* 0x3A */
1787 U8 Reserved2; /* 0x3B */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1788} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
1789 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
1790
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]1791#define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1792
1793/* values for SAS Expander Page 0 DiscoveryStatus field */
1794#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1795#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1796#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
1797#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1798#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1799#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1800#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1801#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
1802#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1803#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
1804#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
1805#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
1806#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
1807#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
1808#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
1809#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1810#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
1811#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
1812#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1813#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
1814
1815/* values for SAS Expander Page 0 Flags field */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]1816#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1817#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
1818#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
1819#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
1820#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
1821#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
1822#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
1823#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
1824#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
1825#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
1826#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
1827
1828
1829/* SAS Expander Page 1 */
1830
1831typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
1832{
1833 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1834 U8 PhysicalPort; /* 0x08 */
1835 U8 Reserved1; /* 0x09 */
1836 U16 Reserved2; /* 0x0A */
1837 U8 NumPhys; /* 0x0C */
1838 U8 Phy; /* 0x0D */
1839 U16 NumTableEntriesProgrammed; /* 0x0E */
1840 U8 ProgrammedLinkRate; /* 0x10 */
1841 U8 HwLinkRate; /* 0x11 */
1842 U16 AttachedDevHandle; /* 0x12 */
1843 U32 PhyInfo; /* 0x14 */
1844 U32 AttachedDeviceInfo; /* 0x18 */
1845 U16 ExpanderDevHandle; /* 0x1C */
1846 U8 ChangeCount; /* 0x1E */
1847 U8 NegotiatedLinkRate; /* 0x1F */
1848 U8 PhyIdentifier; /* 0x20 */
1849 U8 AttachedPhyIdentifier; /* 0x21 */
1850 U8 Reserved3; /* 0x22 */
1851 U8 DiscoveryInfo; /* 0x23 */
1852 U32 AttachedPhyInfo; /* 0x24 */
1853 U8 ZoneGroup; /* 0x28 */
1854 U8 SelfConfigStatus; /* 0x29 */
1855 U16 Reserved4; /* 0x2A */
1856} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
1857 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
1858
1859#define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
1860
1861/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
1862
1863/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
1864
1865/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
1866
1867/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
1868
1869/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1870
1871/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
1872
1873/* values for SAS Expander Page 1 DiscoveryInfo field */
1874#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
1875#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
1876#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
1877
1878
1879/****************************************************************************
1880* SAS Device Config Pages
1881****************************************************************************/
1882
1883/* SAS Device Page 0 */
1884
1885typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
1886{
1887 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1888 U16 Slot; /* 0x08 */
1889 U16 EnclosureHandle; /* 0x0A */
1890 U64 SASAddress; /* 0x0C */
1891 U16 ParentDevHandle; /* 0x14 */
1892 U8 PhyNum; /* 0x16 */
1893 U8 AccessStatus; /* 0x17 */
1894 U16 DevHandle; /* 0x18 */
1895 U8 AttachedPhyIdentifier; /* 0x1A */
1896 U8 ZoneGroup; /* 0x1B */
1897 U32 DeviceInfo; /* 0x1C */
1898 U16 Flags; /* 0x20 */
1899 U8 PhysicalPort; /* 0x22 */
1900 U8 MaxPortConnections; /* 0x23 */
1901 U64 DeviceName; /* 0x24 */
1902 U8 PortGroups; /* 0x2C */
1903 U8 DmaGroup; /* 0x2D */
1904 U8 ControlGroup; /* 0x2E */
1905 U8 Reserved1; /* 0x2F */
1906 U32 Reserved2; /* 0x30 */
1907 U32 Reserved3; /* 0x34 */
1908} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
1909 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
1910
1911#define MPI2_SASDEVICE0_PAGEVERSION (0x08)
1912
1913/* values for SAS Device Page 0 AccessStatus field */
1914#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
1915#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
1916#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
1917#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
1918#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
1919#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
1920#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
1921#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
1922/* specific values for SATA Init failures */
1923#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
1924#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
1925#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
1926#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
1927#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
1928#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
1929#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
1930#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
1931#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
1932#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
1933#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
1934
1935/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
1936
1937/* values for SAS Device Page 0 Flags field */
1938#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
1939#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
1940#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
1941#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
1942#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
1943#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
1944#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
1945#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
1946#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
1947
1948
1949/* SAS Device Page 1 */
1950
1951typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
1952{
1953 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1954 U32 Reserved1; /* 0x08 */
1955 U64 SASAddress; /* 0x0C */
1956 U32 Reserved2; /* 0x14 */
1957 U16 DevHandle; /* 0x18 */
1958 U16 Reserved3; /* 0x1A */
1959 U8 InitialRegDeviceFIS[20];/* 0x1C */
1960} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
1961 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
1962
1963#define MPI2_SASDEVICE1_PAGEVERSION (0x01)
1964
1965
1966/****************************************************************************
1967* SAS PHY Config Pages
1968****************************************************************************/
1969
1970/* SAS PHY Page 0 */
1971
1972typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
1973{
1974 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1975 U16 OwnerDevHandle; /* 0x08 */
1976 U16 Reserved1; /* 0x0A */
1977 U16 AttachedDevHandle; /* 0x0C */
1978 U8 AttachedPhyIdentifier; /* 0x0E */
1979 U8 Reserved2; /* 0x0F */
1980 U32 AttachedPhyInfo; /* 0x10 */
1981 U8 ProgrammedLinkRate; /* 0x14 */
1982 U8 HwLinkRate; /* 0x15 */
1983 U8 ChangeCount; /* 0x16 */
1984 U8 Flags; /* 0x17 */
1985 U32 PhyInfo; /* 0x18 */
1986 U8 NegotiatedLinkRate; /* 0x1C */
1987 U8 Reserved3; /* 0x1D */
1988 U16 Reserved4; /* 0x1E */
1989} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
1990 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
1991
1992#define MPI2_SASPHY0_PAGEVERSION (0x03)
1993
1994/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
1995
1996/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
1997
1998/* values for SAS PHY Page 0 Flags field */
1999#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2000
2001/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2002
2003/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2004
2005/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2006
2007
2008/* SAS PHY Page 1 */
2009
2010typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2011{
2012 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2013 U32 Reserved1; /* 0x08 */
2014 U32 InvalidDwordCount; /* 0x0C */
2015 U32 RunningDisparityErrorCount; /* 0x10 */
2016 U32 LossDwordSynchCount; /* 0x14 */
2017 U32 PhyResetProblemCount; /* 0x18 */
2018} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2019 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2020
2021#define MPI2_SASPHY1_PAGEVERSION (0x01)
2022
2023
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2024/* SAS PHY Page 2 */
2025
2026typedef struct _MPI2_SASPHY2_PHY_EVENT {
2027 U8 PhyEventCode; /* 0x00 */
2028 U8 Reserved1; /* 0x01 */
2029 U16 Reserved2; /* 0x02 */
2030 U32 PhyEventInfo; /* 0x04 */
2031} MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2032 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2033
2034/* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2035
2036
2037/*
2038 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2039 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2040 */
2041#ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2042#define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2043#endif
2044
2045typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2046 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2047 U32 Reserved1; /* 0x08 */
2048 U8 NumPhyEvents; /* 0x0C */
2049 U8 Reserved2; /* 0x0D */
2050 U16 Reserved3; /* 0x0E */
2051 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2052 /* 0x10 */
2053} MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2054 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2055
2056#define MPI2_SASPHY2_PAGEVERSION (0x00)
2057
2058
2059/* SAS PHY Page 3 */
2060
2061typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2062 U8 PhyEventCode; /* 0x00 */
2063 U8 Reserved1; /* 0x01 */
2064 U16 Reserved2; /* 0x02 */
2065 U8 CounterType; /* 0x04 */
2066 U8 ThresholdWindow; /* 0x05 */
2067 U8 TimeUnits; /* 0x06 */
2068 U8 Reserved3; /* 0x07 */
2069 U32 EventThreshold; /* 0x08 */
2070 U16 ThresholdFlags; /* 0x0C */
2071 U16 Reserved4; /* 0x0E */
2072} MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2073 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2074
2075/* values for PhyEventCode field */
2076#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2077#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2078#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2079#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2080#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2081#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2082#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2083#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2084#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2085#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2086#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2087#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2088#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2089#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2090#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2091#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2092#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2093#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2094#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2095#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2096#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2097#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2098#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2099#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2100#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2101#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2102#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2103#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2104#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2105#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2106#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2107#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2108#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2109#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2110#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2111#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2112#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2113
2114/* values for the CounterType field */
2115#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2116#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2117#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2118
2119/* values for the TimeUnits field */
2120#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2121#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2122#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2123#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2124
2125/* values for the ThresholdFlags field */
2126#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2127#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2128
2129/*
2130 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2131 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2132 */
2133#ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2134#define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2135#endif
2136
2137typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2138 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2139 U32 Reserved1; /* 0x08 */
2140 U8 NumPhyEvents; /* 0x0C */
2141 U8 Reserved2; /* 0x0D */
2142 U16 Reserved3; /* 0x0E */
2143 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
2144 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2145} MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2146 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2147
2148#define MPI2_SASPHY3_PAGEVERSION (0x00)
2149
2150
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2151/****************************************************************************
2152* SAS Port Config Pages
2153****************************************************************************/
2154
2155/* SAS Port Page 0 */
2156
2157typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2158{
2159 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2160 U8 PortNumber; /* 0x08 */
2161 U8 PhysicalPort; /* 0x09 */
2162 U8 PortWidth; /* 0x0A */
2163 U8 PhysicalPortWidth; /* 0x0B */
2164 U8 ZoneGroup; /* 0x0C */
2165 U8 Reserved1; /* 0x0D */
2166 U16 Reserved2; /* 0x0E */
2167 U64 SASAddress; /* 0x10 */
2168 U32 DeviceInfo; /* 0x18 */
2169 U32 Reserved3; /* 0x1C */
2170 U32 Reserved4; /* 0x20 */
2171} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2172 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2173
2174#define MPI2_SASPORT0_PAGEVERSION (0x00)
2175
2176/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2177
2178
2179/****************************************************************************
2180* SAS Enclosure Config Pages
2181****************************************************************************/
2182
2183/* SAS Enclosure Page 0 */
2184
2185typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2186{
2187 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2188 U32 Reserved1; /* 0x08 */
2189 U64 EnclosureLogicalID; /* 0x0C */
2190 U16 Flags; /* 0x14 */
2191 U16 EnclosureHandle; /* 0x16 */
2192 U16 NumSlots; /* 0x18 */
2193 U16 StartSlot; /* 0x1A */
2194 U16 Reserved2; /* 0x1C */
2195 U16 SEPDevHandle; /* 0x1E */
2196 U32 Reserved3; /* 0x20 */
2197 U32 Reserved4; /* 0x24 */
2198} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2199 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2200 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2201
2202#define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2203
2204/* values for SAS Enclosure Page 0 Flags field */
2205#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2206#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2207#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2208#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2209#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2210#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2211#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2212
2213
2214/****************************************************************************
2215* Log Config Page
2216****************************************************************************/
2217
2218/* Log Page 0 */
2219
2220/*
2221 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2222 * one and check Header.ExtPageLength or NumPhys at runtime.
2223 */
2224#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2225#define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2226#endif
2227
2228#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2229
2230typedef struct _MPI2_LOG_0_ENTRY
2231{
2232 U64 TimeStamp; /* 0x00 */
2233 U32 Reserved1; /* 0x08 */
2234 U16 LogSequence; /* 0x0C */
2235 U16 LogEntryQualifier; /* 0x0E */
2236 U8 VP_ID; /* 0x10 */
2237 U8 VF_ID; /* 0x11 */
2238 U16 Reserved2; /* 0x12 */
2239 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2240} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2241 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2242
2243/* values for Log Page 0 LogEntry LogEntryQualifier field */
2244#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2245#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2246#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2247#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2248#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2249
2250typedef struct _MPI2_CONFIG_PAGE_LOG_0
2251{
2252 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2253 U32 Reserved1; /* 0x08 */
2254 U32 Reserved2; /* 0x0C */
2255 U16 NumLogEntries; /* 0x10 */
2256 U16 Reserved3; /* 0x12 */
2257 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2258} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2259 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2260
2261#define MPI2_LOG_0_PAGEVERSION (0x02)
2262
2263
2264/****************************************************************************
2265* RAID Config Page
2266****************************************************************************/
2267
2268/* RAID Page 0 */
2269
2270/*
2271 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2272 * one and check Header.ExtPageLength or NumPhys at runtime.
2273 */
2274#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2275#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2276#endif
2277
2278typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2279{
2280 U16 ElementFlags; /* 0x00 */
2281 U16 VolDevHandle; /* 0x02 */
2282 U8 HotSparePool; /* 0x04 */
2283 U8 PhysDiskNum; /* 0x05 */
2284 U16 PhysDiskDevHandle; /* 0x06 */
2285} MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2286 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2287 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2288
2289/* values for the ElementFlags field */
2290#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2291#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2292#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2293#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2294#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2295
2296
2297typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2298{
2299 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2300 U8 NumHotSpares; /* 0x08 */
2301 U8 NumPhysDisks; /* 0x09 */
2302 U8 NumVolumes; /* 0x0A */
2303 U8 ConfigNum; /* 0x0B */
2304 U32 Flags; /* 0x0C */
2305 U8 ConfigGUID[24]; /* 0x10 */
2306 U32 Reserved1; /* 0x28 */
2307 U8 NumElements; /* 0x2C */
2308 U8 Reserved2; /* 0x2D */
2309 U16 Reserved3; /* 0x2E */
2310 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2311} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2312 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2313 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2314
2315#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2316
2317/* values for RAID Configuration Page 0 Flags field */
2318#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2319
2320
2321/****************************************************************************
2322* Driver Persistent Mapping Config Pages
2323****************************************************************************/
2324
2325/* Driver Persistent Mapping Page 0 */
2326
2327typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2328{
2329 U64 PhysicalIdentifier; /* 0x00 */
2330 U16 MappingInformation; /* 0x08 */
2331 U16 DeviceIndex; /* 0x0A */
2332 U32 PhysicalBitsMapping; /* 0x0C */
2333 U32 Reserved1; /* 0x10 */
2334} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2335 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2336 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2337
2338typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2339{
2340 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2341 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2342} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2343 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2344 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2345
2346#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2347
2348/* values for Driver Persistent Mapping Page 0 MappingInformation field */
2349#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2350#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2351#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2352
2353
2354#endif
2355