blob: bb61b8e2dce9081e00963bad1fb9e50b97a20f3d [file] [log] [blame]
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001/*
2 * PHY functions
3 *
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03004 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
Nick Kossifidis33a31822009-02-09 06:00:34 +02005 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03006 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02007 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
Jiri Slabyfa1c1142007-08-12 17:33:16 +02008 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
Nick Kossifidisc6e387a2008-08-29 22:45:39 +030023#define _ATH5K_PHY
24
Jiri Slabyfa1c1142007-08-12 17:33:16 +020025#include <linux/delay.h>
26
27#include "ath5k.h"
28#include "reg.h"
29#include "base.h"
Nick Kossifidis33a31822009-02-09 06:00:34 +020030#include "rfbuffer.h"
31#include "rfgain.h"
Jiri Slabyfa1c1142007-08-12 17:33:16 +020032
33/*
34 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
35 */
Nick Kossifidis8892e4e2009-02-09 06:06:34 +020036static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
37 const struct ath5k_rf_reg *rf_regs,
38 u32 val, u8 reg_id, bool set)
Jiri Slabyfa1c1142007-08-12 17:33:16 +020039{
Nick Kossifidis8892e4e2009-02-09 06:06:34 +020040 const struct ath5k_rf_reg *rfreg = NULL;
41 u8 offset, bank, num_bits, col, position;
42 u16 entry;
43 u32 mask, data, last_bit, bits_shifted, first_bit;
44 u32 *rfb;
45 s32 bits_left;
Jiri Slabyfa1c1142007-08-12 17:33:16 +020046 int i;
47
48 data = 0;
Nick Kossifidis8892e4e2009-02-09 06:06:34 +020049 rfb = ah->ah_rf_banks;
Jiri Slabyfa1c1142007-08-12 17:33:16 +020050
Nick Kossifidis8892e4e2009-02-09 06:06:34 +020051 for (i = 0; i < ah->ah_rf_regs_count; i++) {
52 if (rf_regs[i].index == reg_id) {
53 rfreg = &rf_regs[i];
54 break;
55 }
56 }
57
58 if (rfb == NULL || rfreg == NULL) {
59 ATH5K_PRINTF("Rf register not found!\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +020060 /* should not happen */
61 return 0;
Nick Kossifidis8892e4e2009-02-09 06:06:34 +020062 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +020063
Nick Kossifidis8892e4e2009-02-09 06:06:34 +020064 bank = rfreg->bank;
65 num_bits = rfreg->field.len;
66 first_bit = rfreg->field.pos;
67 col = rfreg->field.col;
68
69 /* first_bit is an offset from bank's
70 * start. Since we have all banks on
71 * the same array, we use this offset
72 * to mark each bank's start */
73 offset = ah->ah_offset[bank];
74
75 /* Boundary check */
76 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +020077 ATH5K_PRINTF("invalid values at offset %u\n", offset);
78 return 0;
79 }
80
Nick Kossifidis8892e4e2009-02-09 06:06:34 +020081 entry = ((first_bit - 1) / 8) + offset;
82 position = (first_bit - 1) % 8;
Jiri Slabyfa1c1142007-08-12 17:33:16 +020083
Joe Perchese9010e22008-03-07 14:21:16 -080084 if (set)
Nick Kossifidis8892e4e2009-02-09 06:06:34 +020085 data = ath5k_hw_bitswap(val, num_bits);
Jiri Slabyfa1c1142007-08-12 17:33:16 +020086
Nick Kossifidis8892e4e2009-02-09 06:06:34 +020087 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
88 position = 0, entry++) {
89
90 last_bit = (position + bits_left > 8) ? 8 :
91 position + bits_left;
92
93 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
94 (col * 8);
Jiri Slabyfa1c1142007-08-12 17:33:16 +020095
Joe Perchese9010e22008-03-07 14:21:16 -080096 if (set) {
Nick Kossifidis8892e4e2009-02-09 06:06:34 +020097 rfb[entry] &= ~mask;
98 rfb[entry] |= ((data << position) << (col * 8)) & mask;
Jiri Slabyfa1c1142007-08-12 17:33:16 +020099 data >>= (8 - position);
100 } else {
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200101 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
102 << bits_shifted;
103 bits_shifted += last_bit - position;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200104 }
105
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200106 bits_left -= 8 - position;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200107 }
108
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200109 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200110
111 return data;
112}
113
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200114/**********************\
115* RF Gain optimization *
116\**********************/
117
118/*
119 * This code is used to optimize rf gain on different environments
120 * (temprature mostly) based on feedback from a power detector.
121 *
122 * It's only used on RF5111 and RF5112, later RF chips seem to have
123 * auto adjustment on hw -notice they have a much smaller BANK 7 and
124 * no gain optimization ladder-.
125 *
126 * For more infos check out this patent doc
127 * http://www.freepatentsonline.com/7400691.html
128 *
129 * This paper describes power drops as seen on the receiver due to
130 * probe packets
131 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
132 * %20of%20Power%20Control.pdf
133 *
134 * And this is the MadWiFi bug entry related to the above
135 * http://madwifi-project.org/ticket/1659
136 * with various measurements and diagrams
137 *
138 * TODO: Deal with power drops due to probes by setting an apropriate
139 * tx power on the probe packets ! Make this part of the calibration process.
140 */
141
142/* Initialize ah_gain durring attach */
143int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
144{
145 /* Initialize the gain optimization values */
146 switch (ah->ah_radio) {
147 case AR5K_RF5111:
148 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
149 ah->ah_gain.g_low = 20;
150 ah->ah_gain.g_high = 35;
151 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
152 break;
153 case AR5K_RF5112:
154 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
155 ah->ah_gain.g_low = 20;
156 ah->ah_gain.g_high = 85;
157 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
158 break;
159 default:
160 return -EINVAL;
161 }
162
163 return 0;
164}
165
166/* Schedule a gain probe check on the next transmited packet.
167 * That means our next packet is going to be sent with lower
168 * tx power and a Peak to Average Power Detector (PAPD) will try
169 * to measure the gain.
170 *
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200171 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
172 * just after we enable the probe so that we don't mess with
173 * standard traffic ? Maybe it's time to use sw interrupts and
174 * a probe tasklet !!!
175 */
176static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
177{
178
179 /* Skip if gain calibration is inactive or
180 * we already handle a probe request */
181 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
182 return;
183
Nick Kossifidis8f655dd2009-03-15 22:20:35 +0200184 /* Send the packet with 2dB below max power as
185 * patent doc suggest */
Nick Kossifidisa0823812009-04-30 15:55:44 -0400186 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200187 AR5K_PHY_PAPD_PROBE_TXPOWER) |
188 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
189
190 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
191
192}
193
194/* Calculate gain_F measurement correction
195 * based on the current step for RF5112 rev. 2 */
196static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200197{
198 u32 mix, step;
199 u32 *rf;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200200 const struct ath5k_gain_opt *go;
201 const struct ath5k_gain_opt_step *g_step;
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200202 const struct ath5k_rf_reg *rf_regs;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200203
204 /* Only RF5112 Rev. 2 supports it */
205 if ((ah->ah_radio != AR5K_RF5112) ||
206 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
207 return 0;
208
209 go = &rfgain_opt_5112;
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200210 rf_regs = rf_regs_5112a;
211 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200212
213 g_step = &go->go_step[ah->ah_gain.g_step_idx];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200214
215 if (ah->ah_rf_banks == NULL)
216 return 0;
217
218 rf = ah->ah_rf_banks;
219 ah->ah_gain.g_f_corr = 0;
220
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200221 /* No VGA (Variable Gain Amplifier) override, skip */
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200222 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200223 return 0;
224
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200225 /* Mix gain stepping */
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200226 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200227
228 /* Mix gain override */
229 mix = g_step->gos_param[0];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200230
231 switch (mix) {
232 case 3:
233 ah->ah_gain.g_f_corr = step * 2;
234 break;
235 case 2:
236 ah->ah_gain.g_f_corr = (step - 5) * 2;
237 break;
238 case 1:
239 ah->ah_gain.g_f_corr = step;
240 break;
241 default:
242 ah->ah_gain.g_f_corr = 0;
243 break;
244 }
245
246 return ah->ah_gain.g_f_corr;
247}
248
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200249/* Check if current gain_F measurement is in the range of our
250 * power detector windows. If we get a measurement outside range
251 * we know it's not accurate (detectors can't measure anything outside
252 * their detection window) so we must ignore it */
253static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200254{
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200255 const struct ath5k_rf_reg *rf_regs;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200256 u32 step, mix_ovr, level[4];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200257 u32 *rf;
258
259 if (ah->ah_rf_banks == NULL)
260 return false;
261
262 rf = ah->ah_rf_banks;
263
264 if (ah->ah_radio == AR5K_RF5111) {
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200265
266 rf_regs = rf_regs_5111;
267 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
268
269 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
270 false);
271
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200272 level[0] = 0;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200273 level[1] = (step == 63) ? 50 : step + 4;
274 level[2] = (step != 63) ? 64 : level[0];
275 level[3] = level[2] + 50 ;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200276
277 ah->ah_gain.g_high = level[3] -
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200278 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200279 ah->ah_gain.g_low = level[0] +
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200280 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200281 } else {
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200282
283 rf_regs = rf_regs_5112;
284 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
285
286 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
287 false);
288
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200289 level[0] = level[2] = 0;
290
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200291 if (mix_ovr == 1) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200292 level[1] = level[3] = 83;
293 } else {
294 level[1] = level[3] = 107;
295 ah->ah_gain.g_high = 55;
296 }
297 }
298
299 return (ah->ah_gain.g_current >= level[0] &&
300 ah->ah_gain.g_current <= level[1]) ||
301 (ah->ah_gain.g_current >= level[2] &&
302 ah->ah_gain.g_current <= level[3]);
303}
304
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200305/* Perform gain_F adjustment by choosing the right set
306 * of parameters from rf gain optimization ladder */
307static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200308{
309 const struct ath5k_gain_opt *go;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200310 const struct ath5k_gain_opt_step *g_step;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200311 int ret = 0;
312
313 switch (ah->ah_radio) {
314 case AR5K_RF5111:
315 go = &rfgain_opt_5111;
316 break;
317 case AR5K_RF5112:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200318 go = &rfgain_opt_5112;
319 break;
320 default:
321 return 0;
322 }
323
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200324 g_step = &go->go_step[ah->ah_gain.g_step_idx];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200325
326 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200327
328 /* Reached maximum */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200329 if (ah->ah_gain.g_step_idx == 0)
330 return -1;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200331
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200332 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
333 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
334 ah->ah_gain.g_step_idx > 0;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200335 g_step = &go->go_step[ah->ah_gain.g_step_idx])
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200336 ah->ah_gain.g_target -= 2 *
337 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200338 g_step->gos_gain);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200339
340 ret = 1;
341 goto done;
342 }
343
344 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200345
346 /* Reached minimum */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200347 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
348 return -2;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200349
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200350 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
351 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
352 ah->ah_gain.g_step_idx < go->go_steps_count-1;
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200353 g_step = &go->go_step[ah->ah_gain.g_step_idx])
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200354 ah->ah_gain.g_target -= 2 *
355 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200356 g_step->gos_gain);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200357
358 ret = 2;
359 goto done;
360 }
361
362done:
363 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
364 "ret %d, gain step %u, current gain %u, target gain %u\n",
365 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
366 ah->ah_gain.g_target);
367
368 return ret;
369}
370
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200371/* Main callback for thermal rf gain calibration engine
372 * Check for a new gain reading and schedule an adjustment
373 * if needed.
374 *
375 * TODO: Use sw interrupt to schedule reset if gain_F needs
376 * adjustment */
377enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
378{
379 u32 data, type;
380 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
381
382 ATH5K_TRACE(ah->ah_sc);
383
384 if (ah->ah_rf_banks == NULL ||
385 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
386 return AR5K_RFGAIN_INACTIVE;
387
388 /* No check requested, either engine is inactive
389 * or an adjustment is already requested */
390 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
391 goto done;
392
393 /* Read the PAPD (Peak to Average Power Detector)
394 * register */
395 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
396
397 /* No probe is scheduled, read gain_F measurement */
398 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
399 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
400 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
401
402 /* If tx packet is CCK correct the gain_F measurement
403 * by cck ofdm gain delta */
404 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
405 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
406 ah->ah_gain.g_current +=
407 ee->ee_cck_ofdm_gain_delta;
408 else
409 ah->ah_gain.g_current +=
410 AR5K_GAIN_CCK_PROBE_CORR;
411 }
412
413 /* Further correct gain_F measurement for
414 * RF5112A radios */
415 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
416 ath5k_hw_rf_gainf_corr(ah);
417 ah->ah_gain.g_current =
418 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
419 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
420 0;
421 }
422
423 /* Check if measurement is ok and if we need
424 * to adjust gain, schedule a gain adjustment,
425 * else switch back to the acive state */
426 if (ath5k_hw_rf_check_gainf_readback(ah) &&
427 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
428 ath5k_hw_rf_gainf_adjust(ah)) {
429 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
430 } else {
431 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
432 }
433 }
434
435done:
436 return ah->ah_gain.g_state;
437}
438
439/* Write initial rf gain table to set the RF sensitivity
440 * this one works on all RF chips and has nothing to do
441 * with gain_F calibration */
442int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
443{
444 const struct ath5k_ini_rfgain *ath5k_rfg;
445 unsigned int i, size;
446
447 switch (ah->ah_radio) {
448 case AR5K_RF5111:
449 ath5k_rfg = rfgain_5111;
450 size = ARRAY_SIZE(rfgain_5111);
451 break;
452 case AR5K_RF5112:
453 ath5k_rfg = rfgain_5112;
454 size = ARRAY_SIZE(rfgain_5112);
455 break;
456 case AR5K_RF2413:
457 ath5k_rfg = rfgain_2413;
458 size = ARRAY_SIZE(rfgain_2413);
459 break;
460 case AR5K_RF2316:
461 ath5k_rfg = rfgain_2316;
462 size = ARRAY_SIZE(rfgain_2316);
463 break;
464 case AR5K_RF5413:
465 ath5k_rfg = rfgain_5413;
466 size = ARRAY_SIZE(rfgain_5413);
467 break;
468 case AR5K_RF2317:
469 case AR5K_RF2425:
470 ath5k_rfg = rfgain_2425;
471 size = ARRAY_SIZE(rfgain_2425);
472 break;
473 default:
474 return -EINVAL;
475 }
476
477 switch (freq) {
478 case AR5K_INI_RFGAIN_2GHZ:
479 case AR5K_INI_RFGAIN_5GHZ:
480 break;
481 default:
482 return -EINVAL;
483 }
484
485 for (i = 0; i < size; i++) {
486 AR5K_REG_WAIT(i);
487 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
488 (u32)ath5k_rfg[i].rfg_register);
489 }
490
491 return 0;
492}
493
494
495
496/********************\
497* RF Registers setup *
498\********************/
499
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200500
501/*
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200502 * Setup RF registers by writing rf buffer on hw
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200503 */
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200504int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200505 unsigned int mode)
506{
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200507 const struct ath5k_rf_reg *rf_regs;
508 const struct ath5k_ini_rfbuffer *ini_rfb;
509 const struct ath5k_gain_opt *go = NULL;
510 const struct ath5k_gain_opt_step *g_step;
511 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
512 u8 ee_mode = 0;
513 u32 *rfb;
514 int i, obdb = -1, bank = -1;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200515
516 switch (ah->ah_radio) {
517 case AR5K_RF5111:
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200518 rf_regs = rf_regs_5111;
519 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
520 ini_rfb = rfb_5111;
521 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
522 go = &rfgain_opt_5111;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200523 break;
524 case AR5K_RF5112:
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200525 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
526 rf_regs = rf_regs_5112a;
527 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
528 ini_rfb = rfb_5112a;
529 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
530 } else {
531 rf_regs = rf_regs_5112;
532 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
533 ini_rfb = rfb_5112;
534 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
535 }
536 go = &rfgain_opt_5112;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200537 break;
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500538 case AR5K_RF2413:
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200539 rf_regs = rf_regs_2413;
540 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
541 ini_rfb = rfb_2413;
542 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
543 break;
544 case AR5K_RF2316:
545 rf_regs = rf_regs_2316;
546 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
547 ini_rfb = rfb_2316;
548 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
549 break;
550 case AR5K_RF5413:
551 rf_regs = rf_regs_5413;
552 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
553 ini_rfb = rfb_5413;
554 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
555 break;
556 case AR5K_RF2317:
557 rf_regs = rf_regs_2425;
558 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
559 ini_rfb = rfb_2317;
560 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500561 break;
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300562 case AR5K_RF2425:
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200563 rf_regs = rf_regs_2425;
564 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
565 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
566 ini_rfb = rfb_2425;
567 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
568 } else {
569 ini_rfb = rfb_2417;
570 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
571 }
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300572 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200573 default:
574 return -EINVAL;
575 }
576
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200577 /* If it's the first time we set rf buffer, allocate
578 * ah->ah_rf_banks based on ah->ah_rf_banks_size
579 * we set above */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200580 if (ah->ah_rf_banks == NULL) {
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200581 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
582 GFP_KERNEL);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200583 if (ah->ah_rf_banks == NULL) {
584 ATH5K_ERR(ah->ah_sc, "out of memory\n");
585 return -ENOMEM;
586 }
587 }
588
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200589 /* Copy values to modify them */
590 rfb = ah->ah_rf_banks;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200591
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200592 for (i = 0; i < ah->ah_rf_banks_size; i++) {
593 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
594 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
595 return -EINVAL;
596 }
597
598 /* Bank changed, write down the offset */
599 if (bank != ini_rfb[i].rfb_bank) {
600 bank = ini_rfb[i].rfb_bank;
601 ah->ah_offset[bank] = i;
602 }
603
604 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
605 }
606
607 /* Set Output and Driver bias current (OB/DB) */
608 if (channel->hw_value & CHANNEL_2GHZ) {
609
610 if (channel->hw_value & CHANNEL_CCK)
611 ee_mode = AR5K_EEPROM_MODE_11B;
612 else
613 ee_mode = AR5K_EEPROM_MODE_11G;
614
615 /* For RF511X/RF211X combination we
616 * use b_OB and b_DB parameters stored
617 * in eeprom on ee->ee_ob[ee_mode][0]
618 *
619 * For all other chips we use OB/DB for 2Ghz
620 * stored in the b/g modal section just like
621 * 802.11a on ee->ee_ob[ee_mode][1] */
622 if ((ah->ah_radio == AR5K_RF5111) ||
623 (ah->ah_radio == AR5K_RF5112))
624 obdb = 0;
625 else
626 obdb = 1;
627
628 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
629 AR5K_RF_OB_2GHZ, true);
630
631 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
632 AR5K_RF_DB_2GHZ, true);
633
634 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
635 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
636 (ah->ah_radio == AR5K_RF5111)) {
637
638 /* For 11a, Turbo and XR we need to choose
639 * OB/DB based on frequency range */
640 ee_mode = AR5K_EEPROM_MODE_11A;
641 obdb = channel->center_freq >= 5725 ? 3 :
642 (channel->center_freq >= 5500 ? 2 :
643 (channel->center_freq >= 5260 ? 1 :
644 (channel->center_freq > 4000 ? 0 : -1)));
645
646 if (obdb < 0)
647 return -EINVAL;
648
649 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
650 AR5K_RF_OB_5GHZ, true);
651
652 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
653 AR5K_RF_DB_5GHZ, true);
654 }
655
656 g_step = &go->go_step[ah->ah_gain.g_step_idx];
657
658 /* Bank Modifications (chip-specific) */
659 if (ah->ah_radio == AR5K_RF5111) {
660
661 /* Set gain_F settings according to current step */
662 if (channel->hw_value & CHANNEL_OFDM) {
663
664 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
665 AR5K_PHY_FRAME_CTL_TX_CLIP,
666 g_step->gos_param[0]);
667
668 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
669 AR5K_RF_PWD_90, true);
670
671 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
672 AR5K_RF_PWD_84, true);
673
674 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
675 AR5K_RF_RFGAIN_SEL, true);
676
677 /* We programmed gain_F parameters, switch back
678 * to active state */
679 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
680
681 }
682
683 /* Bank 6/7 setup */
684
685 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
686 AR5K_RF_PWD_XPD, true);
687
688 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
689 AR5K_RF_XPD_GAIN, true);
690
691 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
692 AR5K_RF_GAIN_I, true);
693
694 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
695 AR5K_RF_PLO_SEL, true);
696
697 /* TODO: Half/quarter channel support */
698 }
699
700 if (ah->ah_radio == AR5K_RF5112) {
701
702 /* Set gain_F settings according to current step */
703 if (channel->hw_value & CHANNEL_OFDM) {
704
705 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
706 AR5K_RF_MIXGAIN_OVR, true);
707
708 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
709 AR5K_RF_PWD_138, true);
710
711 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
712 AR5K_RF_PWD_137, true);
713
714 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
715 AR5K_RF_PWD_136, true);
716
717 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
718 AR5K_RF_PWD_132, true);
719
720 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
721 AR5K_RF_PWD_131, true);
722
723 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
724 AR5K_RF_PWD_130, true);
725
726 /* We programmed gain_F parameters, switch back
727 * to active state */
728 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
729 }
730
731 /* Bank 6/7 setup */
732
733 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
734 AR5K_RF_XPD_SEL, true);
735
736 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
737 /* Rev. 1 supports only one xpd */
738 ath5k_hw_rfb_op(ah, rf_regs,
739 ee->ee_x_gain[ee_mode],
740 AR5K_RF_XPD_GAIN, true);
741
742 } else {
743 /* TODO: Set high and low gain bits */
744 ath5k_hw_rfb_op(ah, rf_regs,
745 ee->ee_x_gain[ee_mode],
746 AR5K_RF_PD_GAIN_LO, true);
747 ath5k_hw_rfb_op(ah, rf_regs,
748 ee->ee_x_gain[ee_mode],
749 AR5K_RF_PD_GAIN_HI, true);
750
751 /* Lower synth voltage on Rev 2 */
752 ath5k_hw_rfb_op(ah, rf_regs, 2,
753 AR5K_RF_HIGH_VC_CP, true);
754
755 ath5k_hw_rfb_op(ah, rf_regs, 2,
756 AR5K_RF_MID_VC_CP, true);
757
758 ath5k_hw_rfb_op(ah, rf_regs, 2,
759 AR5K_RF_LOW_VC_CP, true);
760
761 ath5k_hw_rfb_op(ah, rf_regs, 2,
762 AR5K_RF_PUSH_UP, true);
763
764 /* Decrease power consumption on 5213+ BaseBand */
765 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
766 ath5k_hw_rfb_op(ah, rf_regs, 1,
767 AR5K_RF_PAD2GND, true);
768
769 ath5k_hw_rfb_op(ah, rf_regs, 1,
770 AR5K_RF_XB2_LVL, true);
771
772 ath5k_hw_rfb_op(ah, rf_regs, 1,
773 AR5K_RF_XB5_LVL, true);
774
775 ath5k_hw_rfb_op(ah, rf_regs, 1,
776 AR5K_RF_PWD_167, true);
777
778 ath5k_hw_rfb_op(ah, rf_regs, 1,
779 AR5K_RF_PWD_166, true);
780 }
781 }
782
783 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
784 AR5K_RF_GAIN_I, true);
785
786 /* TODO: Half/quarter channel support */
787
788 }
789
790 if (ah->ah_radio == AR5K_RF5413 &&
791 channel->hw_value & CHANNEL_2GHZ) {
792
793 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
794 true);
795
796 /* Set optimum value for early revisions (on pci-e chips) */
797 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
798 ah->ah_mac_srev < AR5K_SREV_AR5413)
799 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
800 AR5K_RF_PWD_ICLOBUF_2G, true);
801
802 }
803
804 /* Write RF banks on hw */
805 for (i = 0; i < ah->ah_rf_banks_size; i++) {
806 AR5K_REG_WAIT(i);
807 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
808 }
809
810 return 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200811}
812
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200813
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200814/**************************\
815 PHY/RF channel functions
816\**************************/
817
818/*
819 * Check if a channel is supported
820 */
821bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
822{
823 /* Check if the channel is in our supported range */
824 if (flags & CHANNEL_2GHZ) {
825 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
826 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
827 return true;
828 } else if (flags & CHANNEL_5GHZ)
829 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
830 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
831 return true;
832
833 return false;
834}
835
836/*
837 * Convertion needed for RF5110
838 */
839static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
840{
841 u32 athchan;
842
843 /*
844 * Convert IEEE channel/MHz to an internal channel value used
845 * by the AR5210 chipset. This has not been verified with
846 * newer chipsets like the AR5212A who have a completely
847 * different RF/PHY part.
848 */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500849 athchan = (ath5k_hw_bitswap(
850 (ieee80211_frequency_to_channel(
851 channel->center_freq) - 24) / 2, 5)
852 << 1) | (1 << 6) | 0x1;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200853 return athchan;
854}
855
856/*
857 * Set channel on RF5110
858 */
859static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
860 struct ieee80211_channel *channel)
861{
862 u32 data;
863
864 /*
865 * Set the channel and wait
866 */
867 data = ath5k_hw_rf5110_chan2athchan(channel);
868 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
869 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
870 mdelay(1);
871
872 return 0;
873}
874
875/*
876 * Convertion needed for 5111
877 */
878static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
879 struct ath5k_athchan_2ghz *athchan)
880{
881 int channel;
882
883 /* Cast this value to catch negative channel numbers (>= -19) */
884 channel = (int)ieee;
885
886 /*
887 * Map 2GHz IEEE channel to 5GHz Atheros channel
888 */
889 if (channel <= 13) {
890 athchan->a2_athchan = 115 + channel;
891 athchan->a2_flags = 0x46;
892 } else if (channel == 14) {
893 athchan->a2_athchan = 124;
894 athchan->a2_flags = 0x44;
895 } else if (channel >= 15 && channel <= 26) {
896 athchan->a2_athchan = ((channel - 14) * 4) + 132;
897 athchan->a2_flags = 0x46;
898 } else
899 return -EINVAL;
900
901 return 0;
902}
903
904/*
905 * Set channel on 5111
906 */
907static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
908 struct ieee80211_channel *channel)
909{
910 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500911 unsigned int ath5k_channel =
912 ieee80211_frequency_to_channel(channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200913 u32 data0, data1, clock;
914 int ret;
915
916 /*
917 * Set the channel on the RF5111 radio
918 */
919 data0 = data1 = 0;
920
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500921 if (channel->hw_value & CHANNEL_2GHZ) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200922 /* Map 2GHz channel to 5GHz Atheros channel ID */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500923 ret = ath5k_hw_rf5111_chan2athchan(
924 ieee80211_frequency_to_channel(channel->center_freq),
925 &ath5k_channel_2ghz);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200926 if (ret)
927 return ret;
928
929 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
930 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
931 << 5) | (1 << 4);
932 }
933
934 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
935 clock = 1;
936 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
937 (clock << 1) | (1 << 10) | 1;
938 } else {
939 clock = 0;
940 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
941 << 2) | (clock << 1) | (1 << 10) | 1;
942 }
943
944 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
945 AR5K_RF_BUFFER);
946 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
947 AR5K_RF_BUFFER_CONTROL_3);
948
949 return 0;
950}
951
952/*
953 * Set channel on 5112 and newer
954 */
955static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
956 struct ieee80211_channel *channel)
957{
958 u32 data, data0, data1, data2;
959 u16 c;
960
961 data = data0 = data1 = data2 = 0;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500962 c = channel->center_freq;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200963
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200964 if (c < 4800) {
965 if (!((c - 2224) % 5)) {
966 data0 = ((2 * (c - 704)) - 3040) / 10;
967 data1 = 1;
968 } else if (!((c - 2192) % 5)) {
969 data0 = ((2 * (c - 672)) - 3040) / 10;
970 data1 = 0;
971 } else
972 return -EINVAL;
973
974 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
Nick Kossifidiscc6323c2008-07-20 06:44:43 +0300975 } else if ((c - (c % 5)) != 2 || c > 5435) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200976 if (!(c % 20) && c >= 5120) {
977 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
978 data2 = ath5k_hw_bitswap(3, 2);
979 } else if (!(c % 10)) {
980 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
981 data2 = ath5k_hw_bitswap(2, 2);
982 } else if (!(c % 5)) {
983 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
984 data2 = ath5k_hw_bitswap(1, 2);
985 } else
986 return -EINVAL;
Nick Kossifidiscc6323c2008-07-20 06:44:43 +0300987 } else {
988 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
989 data2 = ath5k_hw_bitswap(0, 2);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200990 }
991
992 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
993
994 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
995 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
996
997 return 0;
998}
999
1000/*
Nick Kossifidiscc6323c2008-07-20 06:44:43 +03001001 * Set the channel on the RF2425
1002 */
1003static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1004 struct ieee80211_channel *channel)
1005{
1006 u32 data, data0, data2;
1007 u16 c;
1008
1009 data = data0 = data2 = 0;
1010 c = channel->center_freq;
1011
1012 if (c < 4800) {
1013 data0 = ath5k_hw_bitswap((c - 2272), 8);
1014 data2 = 0;
1015 /* ? 5GHz ? */
1016 } else if ((c - (c % 5)) != 2 || c > 5435) {
1017 if (!(c % 20) && c < 5120)
1018 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1019 else if (!(c % 10))
1020 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1021 else if (!(c % 5))
1022 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1023 else
1024 return -EINVAL;
1025 data2 = ath5k_hw_bitswap(1, 2);
1026 } else {
1027 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1028 data2 = ath5k_hw_bitswap(0, 2);
1029 }
1030
1031 data = (data0 << 4) | data2 << 2 | 0x1001;
1032
1033 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1034 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1035
1036 return 0;
1037}
1038
1039/*
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001040 * Set a channel on the radio chip
1041 */
1042int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1043{
1044 int ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001045 /*
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001046 * Check bounds supported by the PHY (we don't care about regultory
1047 * restrictions at this point). Note: hw_value already has the band
1048 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1049 * of the band by that */
1050 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001051 ATH5K_ERR(ah->ah_sc,
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001052 "channel frequency (%u MHz) out of supported "
1053 "band range\n",
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001054 channel->center_freq);
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001055 return -EINVAL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001056 }
1057
1058 /*
1059 * Set the channel and wait
1060 */
1061 switch (ah->ah_radio) {
1062 case AR5K_RF5110:
1063 ret = ath5k_hw_rf5110_channel(ah, channel);
1064 break;
1065 case AR5K_RF5111:
1066 ret = ath5k_hw_rf5111_channel(ah, channel);
1067 break;
Nick Kossifidiscc6323c2008-07-20 06:44:43 +03001068 case AR5K_RF2425:
1069 ret = ath5k_hw_rf2425_channel(ah, channel);
1070 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001071 default:
1072 ret = ath5k_hw_rf5112_channel(ah, channel);
1073 break;
1074 }
1075
1076 if (ret)
1077 return ret;
1078
Nick Kossifidiscc6323c2008-07-20 06:44:43 +03001079 /* Set JAPAN setting for channel 14 */
1080 if (channel->center_freq == 2484) {
1081 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1082 AR5K_PHY_CCKTXCTL_JAPAN);
1083 } else {
1084 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1085 AR5K_PHY_CCKTXCTL_WORLD);
1086 }
1087
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001088 ah->ah_current_channel.center_freq = channel->center_freq;
1089 ah->ah_current_channel.hw_value = channel->hw_value;
1090 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001091
1092 return 0;
1093}
1094
1095/*****************\
1096 PHY calibration
1097\*****************/
1098
1099/**
1100 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
1101 *
1102 * @ah: struct ath5k_hw pointer we are operating on
1103 * @freq: the channel frequency, just used for error logging
1104 *
1105 * This function performs a noise floor calibration of the PHY and waits for
1106 * it to complete. Then the noise floor value is compared to some maximum
1107 * noise floor we consider valid.
1108 *
1109 * Note that this is different from what the madwifi HAL does: it reads the
1110 * noise floor and afterwards initiates the calibration. Since the noise floor
1111 * calibration can take some time to finish, depending on the current channel
1112 * use, that avoids the occasional timeout warnings we are seeing now.
1113 *
1114 * See the following link for an Atheros patent on noise floor calibration:
1115 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
1116 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
1117 *
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001118 * XXX: Since during noise floor calibration antennas are detached according to
1119 * the patent, we should stop tx queues here.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001120 */
1121int
1122ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
1123{
1124 int ret;
1125 unsigned int i;
1126 s32 noise_floor;
1127
1128 /*
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001129 * Enable noise floor calibration
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001130 */
1131 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1132 AR5K_PHY_AGCCTL_NF);
1133
1134 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1135 AR5K_PHY_AGCCTL_NF, 0, false);
1136 if (ret) {
1137 ATH5K_ERR(ah->ah_sc,
1138 "noise floor calibration timeout (%uMHz)\n", freq);
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001139 return -EAGAIN;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001140 }
1141
1142 /* Wait until the noise floor is calibrated and read the value */
1143 for (i = 20; i > 0; i--) {
1144 mdelay(1);
1145 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1146 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
1147 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
1148 noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
1149
1150 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
1151 break;
1152 }
1153 }
1154
1155 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1156 "noise floor %d\n", noise_floor);
1157
1158 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
1159 ATH5K_ERR(ah->ah_sc,
1160 "noise floor calibration failed (%uMHz)\n", freq);
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001161 return -EAGAIN;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001162 }
1163
1164 ah->ah_noise_floor = noise_floor;
1165
1166 return 0;
1167}
1168
1169/*
1170 * Perform a PHY calibration on RF5110
1171 * -Fix BPSK/QAM Constellation (I/Q correction)
1172 * -Calculate Noise Floor
1173 */
1174static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1175 struct ieee80211_channel *channel)
1176{
1177 u32 phy_sig, phy_agc, phy_sat, beacon;
1178 int ret;
1179
1180 /*
1181 * Disable beacons and RX/TX queues, wait
1182 */
1183 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1184 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1185 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1186 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1187
Nick Kossifidis84e463f2008-09-17 03:33:19 +03001188 mdelay(2);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001189
1190 /*
1191 * Set the channel (with AGC turned off)
1192 */
1193 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1194 udelay(10);
1195 ret = ath5k_hw_channel(ah, channel);
1196
1197 /*
1198 * Activate PHY and wait
1199 */
1200 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1201 mdelay(1);
1202
1203 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1204
1205 if (ret)
1206 return ret;
1207
1208 /*
1209 * Calibrate the radio chip
1210 */
1211
1212 /* Remember normal state */
1213 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1214 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1215 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1216
1217 /* Update radio registers */
1218 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1219 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1220
1221 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1222 AR5K_PHY_AGCCOARSE_LO)) |
1223 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1224 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1225
1226 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1227 AR5K_PHY_ADCSAT_THR)) |
1228 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1229 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1230
1231 udelay(20);
1232
1233 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1234 udelay(10);
1235 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1236 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1237
1238 mdelay(1);
1239
1240 /*
1241 * Enable calibration and wait until completion
1242 */
1243 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1244
1245 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1246 AR5K_PHY_AGCCTL_CAL, 0, false);
1247
1248 /* Reset to normal state */
1249 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1250 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1251 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1252
1253 if (ret) {
1254 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001255 channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001256 return ret;
1257 }
1258
Felix Fietkau8b0162a2008-11-03 11:27:38 +01001259 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001260
1261 /*
1262 * Re-enable RX/TX and beacons
1263 */
1264 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1265 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1266 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1267
1268 return 0;
1269}
1270
1271/*
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001272 * Perform a PHY calibration on RF5111/5112 and newer chips
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001273 */
1274static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1275 struct ieee80211_channel *channel)
1276{
1277 u32 i_pwr, q_pwr;
1278 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001279 int i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001280 ATH5K_TRACE(ah->ah_sc);
1281
Joe Perchese9010e22008-03-07 14:21:16 -08001282 if (!ah->ah_calibration ||
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001283 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001284 goto done;
1285
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001286 /* Calibration has finished, get the results and re-run */
1287 for (i = 0; i <= 10; i++) {
1288 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1289 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1290 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1291 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001292
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001293 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001294 q_coffd = q_pwr >> 7;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001295
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001296 /* No correction */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001297 if (i_coffd == 0 || q_coffd == 0)
1298 goto done;
1299
1300 i_coff = ((-iq_corr) / i_coffd) & 0x3f;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001301
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001302 /* Boundary check */
1303 if (i_coff > 31)
1304 i_coff = 31;
1305 if (i_coff < -32)
1306 i_coff = -32;
1307
1308 q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f;
1309
1310 /* Boundary check */
1311 if (q_coff > 15)
1312 q_coff = 15;
1313 if (q_coff < -16)
1314 q_coff = -16;
1315
1316 /* Commit new I/Q value */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001317 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
1318 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
1319
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001320 /* Re-enable calibration -if we don't we'll commit
1321 * the same values again and again */
1322 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1323 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1324 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1325
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001326done:
Nick Kossifidisf860ee22008-07-20 06:47:12 +03001327
1328 /* TODO: Separate noise floor calibration from I/Q calibration
1329 * since noise floor calibration interrupts rx path while I/Q
1330 * calibration doesn't. We don't need to run noise floor calibration
1331 * as often as I/Q calibration.*/
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001332 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001333
Nick Kossifidis6f3b4142009-02-09 06:03:41 +02001334 /* Initiate a gain_F calibration */
1335 ath5k_hw_request_rfgain_probe(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001336
1337 return 0;
1338}
1339
1340/*
1341 * Perform a PHY calibration
1342 */
1343int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1344 struct ieee80211_channel *channel)
1345{
1346 int ret;
1347
1348 if (ah->ah_radio == AR5K_RF5110)
1349 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1350 else
1351 ret = ath5k_hw_rf511x_calibrate(ah, channel);
1352
1353 return ret;
1354}
1355
1356int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1357{
1358 ATH5K_TRACE(ah->ah_sc);
1359 /*Just a try M.F.*/
1360 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1361
1362 return 0;
1363}
1364
1365/********************\
1366 Misc PHY functions
1367\********************/
1368
1369/*
1370 * Get the PHY Chip revision
1371 */
1372u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1373{
1374 unsigned int i;
1375 u32 srev;
1376 u16 ret;
1377
1378 ATH5K_TRACE(ah->ah_sc);
1379
1380 /*
1381 * Set the radio chip access register
1382 */
1383 switch (chan) {
1384 case CHANNEL_2GHZ:
1385 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1386 break;
1387 case CHANNEL_5GHZ:
1388 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1389 break;
1390 default:
1391 return 0;
1392 }
1393
1394 mdelay(2);
1395
1396 /* ...wait until PHY is ready and read the selected radio revision */
1397 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1398
1399 for (i = 0; i < 8; i++)
1400 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1401
1402 if (ah->ah_version == AR5K_AR5210) {
1403 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1404 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1405 } else {
1406 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1407 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1408 ((srev & 0x0f) << 4), 8);
1409 }
1410
1411 /* Reset to the 5GHz mode */
1412 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1413
1414 return ret;
1415}
1416
1417void /*TODO:Boundary check*/
1418ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
1419{
1420 ATH5K_TRACE(ah->ah_sc);
1421 /*Just a try M.F.*/
1422 if (ah->ah_version != AR5K_AR5210)
1423 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
1424}
1425
1426unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
1427{
1428 ATH5K_TRACE(ah->ah_sc);
1429 /*Just a try M.F.*/
1430 if (ah->ah_version != AR5K_AR5210)
1431 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
1432
1433 return false; /*XXX: What do we return for 5210 ?*/
1434}
1435
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001436
1437/****************\
1438* TX power setup *
1439\****************/
1440
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001441/*
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001442 * Helper functions
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001443 */
1444
1445/*
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001446 * Do linear interpolation between two given (x, y) points
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001447 */
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001448static s16
1449ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
1450 s16 y_left, s16 y_right)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001451{
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001452 s16 ratio, result;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001453
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001454 /* Avoid divide by zero and skip interpolation
1455 * if we have the same point */
1456 if ((x_left == x_right) || (y_left == y_right))
1457 return y_left;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001458
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001459 /*
1460 * Since we use ints and not fps, we need to scale up in
1461 * order to get a sane ratio value (or else we 'll eg. get
1462 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1463 * to have some accuracy both for 0.5 and 0.25 steps.
1464 */
1465 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001466
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001467 /* Now scale down to be in range */
1468 result = y_left + (ratio * (target - x_left) / 100);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001469
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001470 return result;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001471}
1472
1473/*
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001474 * Find vertical boundary (min pwr) for the linear PCDAC curve.
1475 *
1476 * Since we have the top of the curve and we draw the line below
1477 * until we reach 1 (1 pcdac step) we need to know which point
1478 * (x value) that is so that we don't go below y axis and have negative
1479 * pcdac values when creating the curve, or fill the table with zeroes.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001480 */
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001481static s16
1482ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
1483 const s16 *pwrL, const s16 *pwrR)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001484{
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001485 s8 tmp;
1486 s16 min_pwrL, min_pwrR;
Fabio Rossi64cdb0e2009-04-01 20:37:50 +02001487 s16 pwr_i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001488
Fabio Rossi64cdb0e2009-04-01 20:37:50 +02001489 if (pwrL[0] == pwrL[1])
1490 min_pwrL = pwrL[0];
1491 else {
1492 pwr_i = pwrL[0];
1493 do {
1494 pwr_i--;
1495 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
1496 pwrL[0], pwrL[1],
1497 stepL[0], stepL[1]);
1498 } while (tmp > 1);
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001499
Fabio Rossi64cdb0e2009-04-01 20:37:50 +02001500 min_pwrL = pwr_i;
1501 }
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001502
Fabio Rossi64cdb0e2009-04-01 20:37:50 +02001503 if (pwrR[0] == pwrR[1])
1504 min_pwrR = pwrR[0];
1505 else {
1506 pwr_i = pwrR[0];
1507 do {
1508 pwr_i--;
1509 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
1510 pwrR[0], pwrR[1],
1511 stepR[0], stepR[1]);
1512 } while (tmp > 1);
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001513
Fabio Rossi64cdb0e2009-04-01 20:37:50 +02001514 min_pwrR = pwr_i;
1515 }
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001516
1517 /* Keep the right boundary so that it works for both curves */
1518 return max(min_pwrL, min_pwrR);
1519}
1520
1521/*
1522 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
1523 * Power to PCDAC curve.
1524 *
1525 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
1526 * steps (offsets) on y axis. Power can go up to 31.5dB and max
1527 * PCDAC/PDADC step for each curve is 64 but we can write more than
1528 * one curves on hw so we can go up to 128 (which is the max step we
1529 * can write on the final table).
1530 *
1531 * We write y values (PCDAC/PDADC steps) on hw.
1532 */
1533static void
1534ath5k_create_power_curve(s16 pmin, s16 pmax,
1535 const s16 *pwr, const u8 *vpd,
1536 u8 num_points,
1537 u8 *vpd_table, u8 type)
1538{
1539 u8 idx[2] = { 0, 1 };
1540 s16 pwr_i = 2*pmin;
1541 int i;
1542
1543 if (num_points < 2)
1544 return;
1545
1546 /* We want the whole line, so adjust boundaries
1547 * to cover the entire power range. Note that
1548 * power values are already 0.25dB so no need
1549 * to multiply pwr_i by 2 */
1550 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
1551 pwr_i = pmin;
1552 pmin = 0;
1553 pmax = 63;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001554 }
1555
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001556 /* Find surrounding turning points (TPs)
1557 * and interpolate between them */
1558 for (i = 0; (i <= (u16) (pmax - pmin)) &&
1559 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
1560
1561 /* We passed the right TP, move to the next set of TPs
1562 * if we pass the last TP, extrapolate above using the last
1563 * two TPs for ratio */
1564 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
1565 idx[0]++;
1566 idx[1]++;
1567 }
1568
1569 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
1570 pwr[idx[0]], pwr[idx[1]],
1571 vpd[idx[0]], vpd[idx[1]]);
1572
1573 /* Increase by 0.5dB
1574 * (0.25 dB units) */
1575 pwr_i += 2;
1576 }
1577}
1578
1579/*
1580 * Get the surrounding per-channel power calibration piers
1581 * for a given frequency so that we can interpolate between
1582 * them and come up with an apropriate dataset for our current
1583 * channel.
1584 */
1585static void
1586ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
1587 struct ieee80211_channel *channel,
1588 struct ath5k_chan_pcal_info **pcinfo_l,
1589 struct ath5k_chan_pcal_info **pcinfo_r)
1590{
1591 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1592 struct ath5k_chan_pcal_info *pcinfo;
1593 u8 idx_l, idx_r;
1594 u8 mode, max, i;
1595 u32 target = channel->center_freq;
1596
1597 idx_l = 0;
1598 idx_r = 0;
1599
1600 if (!(channel->hw_value & CHANNEL_OFDM)) {
1601 pcinfo = ee->ee_pwr_cal_b;
1602 mode = AR5K_EEPROM_MODE_11B;
1603 } else if (channel->hw_value & CHANNEL_2GHZ) {
1604 pcinfo = ee->ee_pwr_cal_g;
1605 mode = AR5K_EEPROM_MODE_11G;
1606 } else {
1607 pcinfo = ee->ee_pwr_cal_a;
1608 mode = AR5K_EEPROM_MODE_11A;
1609 }
1610 max = ee->ee_n_piers[mode] - 1;
1611
1612 /* Frequency is below our calibrated
1613 * range. Use the lowest power curve
1614 * we have */
1615 if (target < pcinfo[0].freq) {
1616 idx_l = idx_r = 0;
1617 goto done;
1618 }
1619
1620 /* Frequency is above our calibrated
1621 * range. Use the highest power curve
1622 * we have */
1623 if (target > pcinfo[max].freq) {
1624 idx_l = idx_r = max;
1625 goto done;
1626 }
1627
1628 /* Frequency is inside our calibrated
1629 * channel range. Pick the surrounding
1630 * calibration piers so that we can
1631 * interpolate */
1632 for (i = 0; i <= max; i++) {
1633
1634 /* Frequency matches one of our calibration
1635 * piers, no need to interpolate, just use
1636 * that calibration pier */
1637 if (pcinfo[i].freq == target) {
1638 idx_l = idx_r = i;
1639 goto done;
1640 }
1641
1642 /* We found a calibration pier that's above
1643 * frequency, use this pier and the previous
1644 * one to interpolate */
1645 if (target < pcinfo[i].freq) {
1646 idx_r = i;
1647 idx_l = idx_r - 1;
1648 goto done;
1649 }
1650 }
1651
1652done:
1653 *pcinfo_l = &pcinfo[idx_l];
1654 *pcinfo_r = &pcinfo[idx_r];
1655
1656 return;
1657}
1658
1659/*
1660 * Get the surrounding per-rate power calibration data
1661 * for a given frequency and interpolate between power
1662 * values to set max target power supported by hw for
1663 * each rate.
1664 */
1665static void
1666ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
1667 struct ieee80211_channel *channel,
1668 struct ath5k_rate_pcal_info *rates)
1669{
1670 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1671 struct ath5k_rate_pcal_info *rpinfo;
1672 u8 idx_l, idx_r;
1673 u8 mode, max, i;
1674 u32 target = channel->center_freq;
1675
1676 idx_l = 0;
1677 idx_r = 0;
1678
1679 if (!(channel->hw_value & CHANNEL_OFDM)) {
1680 rpinfo = ee->ee_rate_tpwr_b;
1681 mode = AR5K_EEPROM_MODE_11B;
1682 } else if (channel->hw_value & CHANNEL_2GHZ) {
1683 rpinfo = ee->ee_rate_tpwr_g;
1684 mode = AR5K_EEPROM_MODE_11G;
1685 } else {
1686 rpinfo = ee->ee_rate_tpwr_a;
1687 mode = AR5K_EEPROM_MODE_11A;
1688 }
1689 max = ee->ee_rate_target_pwr_num[mode] - 1;
1690
1691 /* Get the surrounding calibration
1692 * piers - same as above */
1693 if (target < rpinfo[0].freq) {
1694 idx_l = idx_r = 0;
1695 goto done;
1696 }
1697
1698 if (target > rpinfo[max].freq) {
1699 idx_l = idx_r = max;
1700 goto done;
1701 }
1702
1703 for (i = 0; i <= max; i++) {
1704
1705 if (rpinfo[i].freq == target) {
1706 idx_l = idx_r = i;
1707 goto done;
1708 }
1709
1710 if (target < rpinfo[i].freq) {
1711 idx_r = i;
1712 idx_l = idx_r - 1;
1713 goto done;
1714 }
1715 }
1716
1717done:
1718 /* Now interpolate power value, based on the frequency */
1719 rates->freq = target;
1720
1721 rates->target_power_6to24 =
1722 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
1723 rpinfo[idx_r].freq,
1724 rpinfo[idx_l].target_power_6to24,
1725 rpinfo[idx_r].target_power_6to24);
1726
1727 rates->target_power_36 =
1728 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
1729 rpinfo[idx_r].freq,
1730 rpinfo[idx_l].target_power_36,
1731 rpinfo[idx_r].target_power_36);
1732
1733 rates->target_power_48 =
1734 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
1735 rpinfo[idx_r].freq,
1736 rpinfo[idx_l].target_power_48,
1737 rpinfo[idx_r].target_power_48);
1738
1739 rates->target_power_54 =
1740 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
1741 rpinfo[idx_r].freq,
1742 rpinfo[idx_l].target_power_54,
1743 rpinfo[idx_r].target_power_54);
1744}
1745
1746/*
1747 * Get the max edge power for this channel if
1748 * we have such data from EEPROM's Conformance Test
1749 * Limits (CTL), and limit max power if needed.
1750 *
1751 * FIXME: Only works for world regulatory domains
1752 */
1753static void
1754ath5k_get_max_ctl_power(struct ath5k_hw *ah,
1755 struct ieee80211_channel *channel)
1756{
1757 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1758 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
1759 u8 *ctl_val = ee->ee_ctl;
1760 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
1761 s16 edge_pwr = 0;
1762 u8 rep_idx;
1763 u8 i, ctl_mode;
1764 u8 ctl_idx = 0xFF;
1765 u32 target = channel->center_freq;
1766
1767 /* Find out a CTL for our mode that's not mapped
1768 * on a specific reg domain.
Nick Kossifidis136bfc72008-04-16 18:42:48 +03001769 *
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001770 * TODO: Map our current reg domain to one of the 3 available
1771 * reg domain ids so that we can support more CTLs. */
1772 switch (channel->hw_value & CHANNEL_MODES) {
1773 case CHANNEL_A:
1774 ctl_mode = AR5K_CTL_11A | AR5K_CTL_NO_REGDOMAIN;
1775 break;
1776 case CHANNEL_G:
1777 ctl_mode = AR5K_CTL_11G | AR5K_CTL_NO_REGDOMAIN;
1778 break;
1779 case CHANNEL_B:
1780 ctl_mode = AR5K_CTL_11B | AR5K_CTL_NO_REGDOMAIN;
1781 break;
1782 case CHANNEL_T:
1783 ctl_mode = AR5K_CTL_TURBO | AR5K_CTL_NO_REGDOMAIN;
1784 break;
1785 case CHANNEL_TG:
1786 ctl_mode = AR5K_CTL_TURBOG | AR5K_CTL_NO_REGDOMAIN;
1787 break;
1788 case CHANNEL_XR:
1789 /* Fall through */
1790 default:
1791 return;
1792 }
Nick Kossifidis903b4742008-02-28 14:50:50 -05001793
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001794 for (i = 0; i < ee->ee_ctls; i++) {
1795 if (ctl_val[i] == ctl_mode) {
1796 ctl_idx = i;
1797 break;
1798 }
1799 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001800
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001801 /* If we have a CTL dataset available grab it and find the
1802 * edge power for our frequency */
1803 if (ctl_idx == 0xFF)
1804 return;
1805
1806 /* Edge powers are sorted by frequency from lower
1807 * to higher. Each CTL corresponds to 8 edge power
1808 * measurements. */
1809 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
1810
1811 /* Don't do boundaries check because we
1812 * might have more that one bands defined
1813 * for this mode */
1814
1815 /* Get the edge power that's closer to our
1816 * frequency */
1817 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
1818 rep_idx += i;
1819 if (target <= rep[rep_idx].freq)
1820 edge_pwr = (s16) rep[rep_idx].edge;
1821 }
1822
1823 if (edge_pwr)
1824 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
1825}
1826
1827
1828/*
1829 * Power to PCDAC table functions
1830 */
1831
1832/*
1833 * Fill Power to PCDAC table on RF5111
1834 *
1835 * No further processing is needed for RF5111, the only thing we have to
1836 * do is fill the values below and above calibration range since eeprom data
1837 * may not cover the entire PCDAC table.
1838 */
1839static void
1840ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
1841 s16 *table_max)
1842{
1843 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
1844 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
1845 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
1846 s16 min_pwr, max_pwr;
1847
1848 /* Get table boundaries */
1849 min_pwr = table_min[0];
1850 pcdac_0 = pcdac_tmp[0];
1851
1852 max_pwr = table_max[0];
1853 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
1854
1855 /* Extrapolate below minimum using pcdac_0 */
1856 pcdac_i = 0;
1857 for (i = 0; i < min_pwr; i++)
1858 pcdac_out[pcdac_i++] = pcdac_0;
1859
1860 /* Copy values from pcdac_tmp */
1861 pwr_idx = min_pwr;
1862 for (i = 0 ; pwr_idx <= max_pwr &&
1863 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
1864 pcdac_out[pcdac_i++] = pcdac_tmp[i];
1865 pwr_idx++;
1866 }
1867
1868 /* Extrapolate above maximum */
1869 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
1870 pcdac_out[pcdac_i++] = pcdac_n;
1871
1872}
1873
1874/*
1875 * Combine available XPD Curves and fill Linear Power to PCDAC table
1876 * on RF5112
1877 *
1878 * RFX112 can have up to 2 curves (one for low txpower range and one for
1879 * higher txpower range). We need to put them both on pcdac_out and place
1880 * them in the correct location. In case we only have one curve available
1881 * just fit it on pcdac_out (it's supposed to cover the entire range of
1882 * available pwr levels since it's always the higher power curve). Extrapolate
1883 * below and above final table if needed.
1884 */
1885static void
1886ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
1887 s16 *table_max, u8 pdcurves)
1888{
1889 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
1890 u8 *pcdac_low_pwr;
1891 u8 *pcdac_high_pwr;
1892 u8 *pcdac_tmp;
1893 u8 pwr;
1894 s16 max_pwr_idx;
1895 s16 min_pwr_idx;
1896 s16 mid_pwr_idx = 0;
1897 /* Edge flag turs on the 7nth bit on the PCDAC
1898 * to delcare the higher power curve (force values
1899 * to be greater than 64). If we only have one curve
1900 * we don't need to set this, if we have 2 curves and
1901 * fill the table backwards this can also be used to
1902 * switch from higher power curve to lower power curve */
1903 u8 edge_flag;
1904 int i;
1905
1906 /* When we have only one curve available
1907 * that's the higher power curve. If we have
1908 * two curves the first is the high power curve
1909 * and the next is the low power curve. */
1910 if (pdcurves > 1) {
1911 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
1912 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
1913 mid_pwr_idx = table_max[1] - table_min[1] - 1;
1914 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
1915
1916 /* If table size goes beyond 31.5dB, keep the
1917 * upper 31.5dB range when setting tx power.
1918 * Note: 126 = 31.5 dB in quarter dB steps */
1919 if (table_max[0] - table_min[1] > 126)
1920 min_pwr_idx = table_max[0] - 126;
1921 else
1922 min_pwr_idx = table_min[1];
1923
1924 /* Since we fill table backwards
1925 * start from high power curve */
1926 pcdac_tmp = pcdac_high_pwr;
1927
1928 edge_flag = 0x40;
1929#if 0
1930 /* If both min and max power limits are in lower
1931 * power curve's range, only use the low power curve.
1932 * TODO: min/max levels are related to target
1933 * power values requested from driver/user
1934 * XXX: Is this really needed ? */
1935 if (min_pwr < table_max[1] &&
1936 max_pwr < table_max[1]) {
1937 edge_flag = 0;
1938 pcdac_tmp = pcdac_low_pwr;
1939 max_pwr_idx = (table_max[1] - table_min[1])/2;
1940 }
1941#endif
1942 } else {
1943 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
1944 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
1945 min_pwr_idx = table_min[0];
1946 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
1947 pcdac_tmp = pcdac_high_pwr;
1948 edge_flag = 0;
1949 }
1950
1951 /* This is used when setting tx power*/
1952 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
1953
1954 /* Fill Power to PCDAC table backwards */
1955 pwr = max_pwr_idx;
1956 for (i = 63; i >= 0; i--) {
1957 /* Entering lower power range, reset
1958 * edge flag and set pcdac_tmp to lower
1959 * power curve.*/
1960 if (edge_flag == 0x40 &&
1961 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
1962 edge_flag = 0x00;
1963 pcdac_tmp = pcdac_low_pwr;
1964 pwr = mid_pwr_idx/2;
1965 }
1966
1967 /* Don't go below 1, extrapolate below if we have
1968 * already swithced to the lower power curve -or
1969 * we only have one curve and edge_flag is zero
1970 * anyway */
1971 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
1972 while (i >= 0) {
1973 pcdac_out[i] = pcdac_out[i + 1];
1974 i--;
1975 }
1976 break;
1977 }
1978
1979 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
1980
1981 /* Extrapolate above if pcdac is greater than
1982 * 126 -this can happen because we OR pcdac_out
1983 * value with edge_flag on high power curve */
1984 if (pcdac_out[i] > 126)
1985 pcdac_out[i] = 126;
1986
1987 /* Decrease by a 0.5dB step */
1988 pwr--;
1989 }
1990}
1991
1992/* Write PCDAC values on hw */
1993static void
1994ath5k_setup_pcdac_table(struct ath5k_hw *ah)
1995{
1996 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
1997 int i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001998
1999 /*
2000 * Write TX power values
2001 */
2002 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2003 ath5k_hw_reg_write(ah,
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002004 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2005 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002006 AR5K_PHY_PCDAC_TXPOWER(i));
2007 }
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002008}
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002009
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002010
2011/*
2012 * Power to PDADC table functions
2013 */
2014
2015/*
2016 * Set the gain boundaries and create final Power to PDADC table
2017 *
2018 * We can have up to 4 pd curves, we need to do a simmilar process
2019 * as we do for RF5112. This time we don't have an edge_flag but we
2020 * set the gain boundaries on a separate register.
2021 */
2022static void
2023ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2024 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2025{
2026 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2027 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2028 u8 *pdadc_tmp;
2029 s16 pdadc_0;
2030 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2031 u8 pd_gain_overlap;
2032
2033 /* Note: Register value is initialized on initvals
2034 * there is no feedback from hw.
2035 * XXX: What about pd_gain_overlap from EEPROM ? */
2036 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2037 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2038
2039 /* Create final PDADC table */
2040 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2041 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2042
2043 if (pdg == pdcurves - 1)
2044 /* 2 dB boundary stretch for last
2045 * (higher power) curve */
2046 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2047 else
2048 /* Set gain boundary in the middle
2049 * between this curve and the next one */
2050 gain_boundaries[pdg] =
2051 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2052
2053 /* Sanity check in case our 2 db stretch got out of
2054 * range. */
2055 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2056 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2057
2058 /* For the first curve (lower power)
2059 * start from 0 dB */
2060 if (pdg == 0)
2061 pdadc_0 = 0;
2062 else
2063 /* For the other curves use the gain overlap */
2064 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2065 pd_gain_overlap;
2066
2067 /* Force each power step to be at least 0.5 dB */
2068 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2069 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2070 else
2071 pwr_step = 1;
2072
2073 /* If pdadc_0 is negative, we need to extrapolate
2074 * below this pdgain by a number of pwr_steps */
2075 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2076 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2077 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2078 pdadc_0++;
2079 }
2080
2081 /* Set last pwr level, using gain boundaries */
2082 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2083 /* Limit it to be inside pwr range */
2084 table_size = pwr_max[pdg] - pwr_min[pdg];
2085 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2086
2087 /* Fill pdadc_out table */
2088 while (pdadc_0 < max_idx)
2089 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2090
2091 /* Need to extrapolate above this pdgain? */
2092 if (pdadc_n <= max_idx)
2093 continue;
2094
2095 /* Force each power step to be at least 0.5 dB */
2096 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2097 pwr_step = pdadc_tmp[table_size - 1] -
2098 pdadc_tmp[table_size - 2];
2099 else
2100 pwr_step = 1;
2101
2102 /* Extrapolate above */
2103 while ((pdadc_0 < (s16) pdadc_n) &&
2104 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2105 s16 tmp = pdadc_tmp[table_size - 1] +
2106 (pdadc_0 - max_idx) * pwr_step;
2107 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2108 pdadc_0++;
2109 }
2110 }
2111
2112 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2113 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2114 pdg++;
2115 }
2116
2117 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2118 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2119 pdadc_i++;
2120 }
2121
2122 /* Set gain boundaries */
2123 ath5k_hw_reg_write(ah,
2124 AR5K_REG_SM(pd_gain_overlap,
2125 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2126 AR5K_REG_SM(gain_boundaries[0],
2127 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2128 AR5K_REG_SM(gain_boundaries[1],
2129 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2130 AR5K_REG_SM(gain_boundaries[2],
2131 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2132 AR5K_REG_SM(gain_boundaries[3],
2133 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2134 AR5K_PHY_TPC_RG5);
2135
2136 /* Used for setting rate power table */
2137 ah->ah_txpower.txp_min_idx = pwr_min[0];
2138
2139}
2140
2141/* Write PDADC values on hw */
2142static void
2143ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2144 u8 pdcurves, u8 *pdg_to_idx)
2145{
2146 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2147 u32 reg;
2148 u8 i;
2149
2150 /* Select the right pdgain curves */
2151
2152 /* Clear current settings */
2153 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2154 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2155 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2156 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2157 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2158
2159 /*
2160 * Use pd_gains curve from eeprom
2161 *
2162 * This overrides the default setting from initvals
2163 * in case some vendors (e.g. Zcomax) don't use the default
2164 * curves. If we don't honor their settings we 'll get a
2165 * 5dB (1 * gain overlap ?) drop.
2166 */
2167 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2168
2169 switch (pdcurves) {
2170 case 3:
2171 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2172 /* Fall through */
2173 case 2:
2174 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2175 /* Fall through */
2176 case 1:
2177 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2178 break;
2179 }
2180 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2181
2182 /*
2183 * Write TX power values
2184 */
2185 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2186 ath5k_hw_reg_write(ah,
2187 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2188 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2189 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2190 ((pdadc_out[4*i + 3] & 0xff) << 24),
2191 AR5K_PHY_PDADC_TXPOWER(i));
2192 }
2193}
2194
2195
2196/*
2197 * Common code for PCDAC/PDADC tables
2198 */
2199
2200/*
2201 * This is the main function that uses all of the above
2202 * to set PCDAC/PDADC table on hw for the current channel.
2203 * This table is used for tx power calibration on the basband,
2204 * without it we get weird tx power levels and in some cases
2205 * distorted spectral mask
2206 */
2207static int
2208ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2209 struct ieee80211_channel *channel,
2210 u8 ee_mode, u8 type)
2211{
2212 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2213 struct ath5k_chan_pcal_info *pcinfo_L;
2214 struct ath5k_chan_pcal_info *pcinfo_R;
2215 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2216 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2217 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2218 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2219 u8 *tmpL;
2220 u8 *tmpR;
2221 u32 target = channel->center_freq;
2222 int pdg, i;
2223
2224 /* Get surounding freq piers for this channel */
2225 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2226 &pcinfo_L,
2227 &pcinfo_R);
2228
2229 /* Loop over pd gain curves on
2230 * surounding freq piers by index */
2231 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2232
2233 /* Fill curves in reverse order
2234 * from lower power (max gain)
2235 * to higher power. Use curve -> idx
2236 * backmaping we did on eeprom init */
2237 u8 idx = pdg_curve_to_idx[pdg];
2238
2239 /* Grab the needed curves by index */
2240 pdg_L = &pcinfo_L->pd_curves[idx];
2241 pdg_R = &pcinfo_R->pd_curves[idx];
2242
2243 /* Initialize the temp tables */
2244 tmpL = ah->ah_txpower.tmpL[pdg];
2245 tmpR = ah->ah_txpower.tmpR[pdg];
2246
2247 /* Set curve's x boundaries and create
2248 * curves so that they cover the same
2249 * range (if we don't do that one table
2250 * will have values on some range and the
2251 * other one won't have any so interpolation
2252 * will fail) */
2253 table_min[pdg] = min(pdg_L->pd_pwr[0],
2254 pdg_R->pd_pwr[0]) / 2;
2255
2256 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2257 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2258
2259 /* Now create the curves on surrounding channels
2260 * and interpolate if needed to get the final
2261 * curve for this gain on this channel */
2262 switch (type) {
2263 case AR5K_PWRTABLE_LINEAR_PCDAC:
2264 /* Override min/max so that we don't loose
2265 * accuracy (don't divide by 2) */
2266 table_min[pdg] = min(pdg_L->pd_pwr[0],
2267 pdg_R->pd_pwr[0]);
2268
2269 table_max[pdg] =
2270 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2271 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2272
2273 /* Override minimum so that we don't get
2274 * out of bounds while extrapolating
2275 * below. Don't do this when we have 2
2276 * curves and we are on the high power curve
2277 * because table_min is ok in this case */
2278 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2279
2280 table_min[pdg] =
2281 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2282 pdg_R->pd_step,
2283 pdg_L->pd_pwr,
2284 pdg_R->pd_pwr);
2285
2286 /* Don't go too low because we will
2287 * miss the upper part of the curve.
2288 * Note: 126 = 31.5dB (max power supported)
2289 * in 0.25dB units */
2290 if (table_max[pdg] - table_min[pdg] > 126)
2291 table_min[pdg] = table_max[pdg] - 126;
2292 }
2293
2294 /* Fall through */
2295 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2296 case AR5K_PWRTABLE_PWR_TO_PDADC:
2297
2298 ath5k_create_power_curve(table_min[pdg],
2299 table_max[pdg],
2300 pdg_L->pd_pwr,
2301 pdg_L->pd_step,
2302 pdg_L->pd_points, tmpL, type);
2303
2304 /* We are in a calibration
2305 * pier, no need to interpolate
2306 * between freq piers */
2307 if (pcinfo_L == pcinfo_R)
2308 continue;
2309
2310 ath5k_create_power_curve(table_min[pdg],
2311 table_max[pdg],
2312 pdg_R->pd_pwr,
2313 pdg_R->pd_step,
2314 pdg_R->pd_points, tmpR, type);
2315 break;
2316 default:
2317 return -EINVAL;
2318 }
2319
2320 /* Interpolate between curves
2321 * of surounding freq piers to
2322 * get the final curve for this
2323 * pd gain. Re-use tmpL for interpolation
2324 * output */
2325 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2326 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2327 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2328 (s16) pcinfo_L->freq,
2329 (s16) pcinfo_R->freq,
2330 (s16) tmpL[i],
2331 (s16) tmpR[i]);
2332 }
2333 }
2334
2335 /* Now we have a set of curves for this
2336 * channel on tmpL (x range is table_max - table_min
2337 * and y values are tmpL[pdg][]) sorted in the same
2338 * order as EEPROM (because we've used the backmaping).
2339 * So for RF5112 it's from higher power to lower power
2340 * and for RF2413 it's from lower power to higher power.
2341 * For RF5111 we only have one curve. */
2342
2343 /* Fill min and max power levels for this
2344 * channel by interpolating the values on
2345 * surounding channels to complete the dataset */
2346 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2347 (s16) pcinfo_L->freq,
2348 (s16) pcinfo_R->freq,
2349 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2350
2351 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2352 (s16) pcinfo_L->freq,
2353 (s16) pcinfo_R->freq,
2354 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2355
2356 /* We are ready to go, fill PCDAC/PDADC
2357 * table and write settings on hardware */
2358 switch (type) {
2359 case AR5K_PWRTABLE_LINEAR_PCDAC:
2360 /* For RF5112 we can have one or two curves
2361 * and each curve covers a certain power lvl
2362 * range so we need to do some more processing */
2363 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2364 ee->ee_pd_gains[ee_mode]);
2365
2366 /* Set txp.offset so that we can
2367 * match max power value with max
2368 * table index */
2369 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2370
2371 /* Write settings on hw */
2372 ath5k_setup_pcdac_table(ah);
2373 break;
2374 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2375 /* We are done for RF5111 since it has only
2376 * one curve, just fit the curve on the table */
2377 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2378
2379 /* No rate powertable adjustment for RF5111 */
2380 ah->ah_txpower.txp_min_idx = 0;
2381 ah->ah_txpower.txp_offset = 0;
2382
2383 /* Write settings on hw */
2384 ath5k_setup_pcdac_table(ah);
2385 break;
2386 case AR5K_PWRTABLE_PWR_TO_PDADC:
2387 /* Set PDADC boundaries and fill
2388 * final PDADC table */
2389 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2390 ee->ee_pd_gains[ee_mode]);
2391
2392 /* Write settings on hw */
2393 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2394
2395 /* Set txp.offset, note that table_min
2396 * can be negative */
2397 ah->ah_txpower.txp_offset = table_min[0];
2398 break;
2399 default:
2400 return -EINVAL;
2401 }
2402
2403 return 0;
2404}
2405
2406
2407/*
2408 * Per-rate tx power setting
2409 *
2410 * This is the code that sets the desired tx power (below
2411 * maximum) on hw for each rate (we also have TPC that sets
2412 * power per packet). We do that by providing an index on the
2413 * PCDAC/PDADC table we set up.
2414 */
2415
2416/*
2417 * Set rate power table
2418 *
2419 * For now we only limit txpower based on maximum tx power
2420 * supported by hw (what's inside rate_info). We need to limit
2421 * this even more, based on regulatory domain etc.
2422 *
2423 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2424 * and is indexed as follows:
2425 * rates[0] - rates[7] -> OFDM rates
2426 * rates[8] - rates[14] -> CCK rates
2427 * rates[15] -> XR rates (they all have the same power)
2428 */
2429static void
2430ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
2431 struct ath5k_rate_pcal_info *rate_info,
2432 u8 ee_mode)
2433{
2434 unsigned int i;
2435 u16 *rates;
2436
2437 /* max_pwr is power level we got from driver/user in 0.5dB
2438 * units, switch to 0.25dB units so we can compare */
2439 max_pwr *= 2;
2440 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
2441
2442 /* apply rate limits */
2443 rates = ah->ah_txpower.txp_rates_power_table;
2444
2445 /* OFDM rates 6 to 24Mb/s */
2446 for (i = 0; i < 5; i++)
2447 rates[i] = min(max_pwr, rate_info->target_power_6to24);
2448
2449 /* Rest OFDM rates */
2450 rates[5] = min(rates[0], rate_info->target_power_36);
2451 rates[6] = min(rates[0], rate_info->target_power_48);
2452 rates[7] = min(rates[0], rate_info->target_power_54);
2453
2454 /* CCK rates */
2455 /* 1L */
2456 rates[8] = min(rates[0], rate_info->target_power_6to24);
2457 /* 2L */
2458 rates[9] = min(rates[0], rate_info->target_power_36);
2459 /* 2S */
2460 rates[10] = min(rates[0], rate_info->target_power_36);
2461 /* 5L */
2462 rates[11] = min(rates[0], rate_info->target_power_48);
2463 /* 5S */
2464 rates[12] = min(rates[0], rate_info->target_power_48);
2465 /* 11L */
2466 rates[13] = min(rates[0], rate_info->target_power_54);
2467 /* 11S */
2468 rates[14] = min(rates[0], rate_info->target_power_54);
2469
2470 /* XR rates */
2471 rates[15] = min(rates[0], rate_info->target_power_6to24);
2472
2473 /* CCK rates have different peak to average ratio
2474 * so we have to tweak their power so that gainf
2475 * correction works ok. For this we use OFDM to
2476 * CCK delta from eeprom */
2477 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
2478 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
2479 for (i = 8; i <= 15; i++)
2480 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
2481
Nick Kossifidisa0823812009-04-30 15:55:44 -04002482 /* Now that we have all rates setup use table offset to
2483 * match the power range set by user with the power indices
2484 * on PCDAC/PDADC table */
2485 for (i = 0; i < 16; i++) {
2486 rates[i] += ah->ah_txpower.txp_offset;
2487 /* Don't get out of bounds */
2488 if (rates[i] > 63)
2489 rates[i] = 63;
2490 }
2491
2492 /* Min/max in 0.25dB units */
2493 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
2494 ah->ah_txpower.txp_max_pwr = 2 * rates[0];
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002495 ah->ah_txpower.txp_ofdm = rates[7];
2496}
2497
2498
2499/*
2500 * Set transmition power
2501 */
2502int
2503ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2504 u8 ee_mode, u8 txpower)
2505{
2506 struct ath5k_rate_pcal_info rate_info;
2507 u8 type;
2508 int ret;
2509
2510 ATH5K_TRACE(ah->ah_sc);
2511 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2512 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2513 return -EINVAL;
2514 }
2515 if (txpower == 0)
2516 txpower = AR5K_TUNE_DEFAULT_TXPOWER;
2517
2518 /* Reset TX power values */
2519 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2520 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
2521 ah->ah_txpower.txp_min_pwr = 0;
2522 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
2523
2524 /* Initialize TX power table */
2525 switch (ah->ah_radio) {
2526 case AR5K_RF5111:
2527 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
2528 break;
2529 case AR5K_RF5112:
2530 type = AR5K_PWRTABLE_LINEAR_PCDAC;
2531 break;
2532 case AR5K_RF2413:
2533 case AR5K_RF5413:
2534 case AR5K_RF2316:
2535 case AR5K_RF2317:
2536 case AR5K_RF2425:
2537 type = AR5K_PWRTABLE_PWR_TO_PDADC;
2538 break;
2539 default:
2540 return -EINVAL;
2541 }
2542
2543 /* FIXME: Only on channel/mode change */
2544 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
2545 if (ret)
2546 return ret;
2547
2548 /* Limit max power if we have a CTL available */
2549 ath5k_get_max_ctl_power(ah, channel);
2550
2551 /* FIXME: Tx power limit for this regdomain
2552 * XXX: Mac80211/CRDA will do that anyway ? */
2553
2554 /* FIXME: Antenna reduction stuff */
2555
2556 /* FIXME: Limit power on turbo modes */
2557
2558 /* FIXME: TPC scale reduction */
2559
2560 /* Get surounding channels for per-rate power table
2561 * calibration */
2562 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
2563
2564 /* Setup rate power table */
2565 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
2566
2567 /* Write rate power table on hw */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002568 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
2569 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
2570 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
2571
2572 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
2573 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
2574 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
2575
2576 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
2577 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
2578 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
2579
2580 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
2581 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2582 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
2583
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002584 /* FIXME: TPC support */
2585 if (ah->ah_txpower.txp_tpc) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002586 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
2587 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002588
2589 ath5k_hw_reg_write(ah,
2590 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
2591 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
2592 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
2593 AR5K_TPC);
2594 } else {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002595 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
2596 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002597 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002598
2599 return 0;
2600}
2601
Nick Kossifidisa0823812009-04-30 15:55:44 -04002602int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002603{
2604 /*Just a try M.F.*/
2605 struct ieee80211_channel *channel = &ah->ah_current_channel;
Nick Kossifidisa0823812009-04-30 15:55:44 -04002606 u8 ee_mode;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002607
2608 ATH5K_TRACE(ah->ah_sc);
Nick Kossifidisa0823812009-04-30 15:55:44 -04002609
2610 switch (channel->hw_value & CHANNEL_MODES) {
2611 case CHANNEL_A:
2612 case CHANNEL_T:
2613 case CHANNEL_XR:
2614 ee_mode = AR5K_EEPROM_MODE_11A;
2615 break;
2616 case CHANNEL_G:
2617 case CHANNEL_TG:
2618 ee_mode = AR5K_EEPROM_MODE_11G;
2619 break;
2620 case CHANNEL_B:
2621 ee_mode = AR5K_EEPROM_MODE_11B;
2622 break;
2623 default:
2624 ATH5K_ERR(ah->ah_sc,
2625 "invalid channel: %d\n", channel->center_freq);
2626 return -EINVAL;
2627 }
2628
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002629 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02002630 "changing txpower to %d\n", txpower);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002631
Nick Kossifidisa0823812009-04-30 15:55:44 -04002632 return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002633}
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03002634
2635#undef _ATH5K_PHY