blob: abe05ec85d501dbeaea089a19dd444fd079b0a4f [file] [log] [blame]
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001/*
Sujith Manoharan5b681382011-05-17 13:36:18 +05302 * Copyright (c) 2008-2011 Atheros Communications Inc.
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
Paul Gortmaker9d9779e2011-07-03 15:21:01 -040019#include <linux/module.h>
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070020#include <asm/unaligned.h>
21
Luis R. Rodriguezaf03abe2009-09-09 02:33:11 -070022#include "hw.h"
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -040023#include "hw-ops.h"
Luis R. Rodriguezcfe8cba2009-09-13 23:39:31 -070024#include "rc.h"
Luis R. Rodriguezb622a722010-04-15 17:39:28 -040025#include "ar9003_mac.h"
Sujith Manoharanf4701b52012-02-22 12:41:18 +053026#include "ar9003_mci.h"
Ben Greear462e58f2012-04-12 10:04:00 -070027#include "debug.h"
28#include "ath9k.h"
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070029
Sujithcbe61d82009-02-09 13:27:12 +053030static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070031
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040032MODULE_AUTHOR("Atheros Communications");
33MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
34MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
35MODULE_LICENSE("Dual BSD/GPL");
36
37static int __init ath9k_init(void)
38{
39 return 0;
40}
41module_init(ath9k_init);
42
43static void __exit ath9k_exit(void)
44{
45 return;
46}
47module_exit(ath9k_exit);
48
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -040049/* Private hardware callbacks */
50
51static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
52{
53 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
54}
55
56static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
57{
58 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
59}
60
Luis R. Rodriguez64773962010-04-15 17:38:17 -040061static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
62 struct ath9k_channel *chan)
63{
64 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
65}
66
Luis R. Rodriguez991312d2010-04-15 17:39:05 -040067static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
68{
69 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
70 return;
71
72 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
73}
74
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -040075static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
76{
77 /* You will not have this callback if using the old ANI */
78 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
79 return;
80
81 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
82}
83
Sujithf1dc5602008-10-29 10:16:30 +053084/********************/
85/* Helper Functions */
86/********************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070087
Ben Greear462e58f2012-04-12 10:04:00 -070088#ifdef CONFIG_ATH9K_DEBUGFS
89
90void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
91{
92 struct ath_softc *sc = common->priv;
93 if (sync_cause)
94 sc->debug.stats.istats.sync_cause_all++;
95 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
96 sc->debug.stats.istats.sync_rtc_irq++;
97 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
98 sc->debug.stats.istats.sync_mac_irq++;
99 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
100 sc->debug.stats.istats.eeprom_illegal_access++;
101 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
102 sc->debug.stats.istats.apb_timeout++;
103 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
104 sc->debug.stats.istats.pci_mode_conflict++;
105 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
106 sc->debug.stats.istats.host1_fatal++;
107 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
108 sc->debug.stats.istats.host1_perr++;
109 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
110 sc->debug.stats.istats.trcv_fifo_perr++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
112 sc->debug.stats.istats.radm_cpl_ep++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
114 sc->debug.stats.istats.radm_cpl_dllp_abort++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
116 sc->debug.stats.istats.radm_cpl_tlp_abort++;
117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
118 sc->debug.stats.istats.radm_cpl_ecrc_err++;
119 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
120 sc->debug.stats.istats.radm_cpl_timeout++;
121 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
122 sc->debug.stats.istats.local_timeout++;
123 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
124 sc->debug.stats.istats.pm_access++;
125 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
126 sc->debug.stats.istats.mac_awake++;
127 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
128 sc->debug.stats.istats.mac_asleep++;
129 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
130 sc->debug.stats.istats.mac_sleep_access++;
131}
132#endif
133
134
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200135static void ath9k_hw_set_clockrate(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530136{
Luis R. Rodriguezb002a4a2009-09-13 00:03:27 -0700137 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200138 struct ath_common *common = ath9k_hw_common(ah);
139 unsigned int clockrate;
Sujithcbe61d82009-02-09 13:27:12 +0530140
Felix Fietkau087b6ff2011-07-09 11:12:49 +0700141 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
142 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
143 clockrate = 117;
144 else if (!ah->curchan) /* should really check for CCK instead */
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200145 clockrate = ATH9K_CLOCK_RATE_CCK;
146 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
147 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
148 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
149 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
Vasanthakumar Thiagarajane5553722010-04-26 15:04:33 -0400150 else
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200151 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
152
153 if (conf_is_ht40(conf))
154 clockrate *= 2;
155
Felix Fietkau906c7202011-07-09 11:12:48 +0700156 if (ah->curchan) {
157 if (IS_CHAN_HALF_RATE(ah->curchan))
158 clockrate /= 2;
159 if (IS_CHAN_QUARTER_RATE(ah->curchan))
160 clockrate /= 4;
161 }
162
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200163 common->clockrate = clockrate;
Sujithf1dc5602008-10-29 10:16:30 +0530164}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700165
Sujithcbe61d82009-02-09 13:27:12 +0530166static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
Sujithf1dc5602008-10-29 10:16:30 +0530167{
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200168 struct ath_common *common = ath9k_hw_common(ah);
Sujithcbe61d82009-02-09 13:27:12 +0530169
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200170 return usecs * common->clockrate;
Sujithf1dc5602008-10-29 10:16:30 +0530171}
172
Sujith0caa7b12009-02-16 13:23:20 +0530173bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700174{
175 int i;
176
Sujith0caa7b12009-02-16 13:23:20 +0530177 BUG_ON(timeout < AH_TIME_QUANTUM);
178
179 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700180 if ((REG_READ(ah, reg) & mask) == val)
181 return true;
182
183 udelay(AH_TIME_QUANTUM);
184 }
Sujith04bd46382008-11-28 22:18:05 +0530185
Joe Perchesd2182b62011-12-15 14:55:53 -0800186 ath_dbg(ath9k_hw_common(ah), ANY,
Joe Perches226afe62010-12-02 19:12:37 -0800187 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
188 timeout, reg, REG_READ(ah, reg), mask, val);
Sujithf1dc5602008-10-29 10:16:30 +0530189
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700190 return false;
191}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400192EXPORT_SYMBOL(ath9k_hw_wait);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700193
Felix Fietkau7c5adc82012-04-19 21:18:26 +0200194void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
195 int hw_delay)
196{
197 if (IS_CHAN_B(chan))
198 hw_delay = (4 * hw_delay) / 22;
199 else
200 hw_delay /= 10;
201
202 if (IS_CHAN_HALF_RATE(chan))
203 hw_delay *= 2;
204 else if (IS_CHAN_QUARTER_RATE(chan))
205 hw_delay *= 4;
206
207 udelay(hw_delay + BASE_ACTIVATE_DELAY);
208}
209
Felix Fietkaua9b6b252011-03-23 20:57:27 +0100210void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
211 int column, unsigned int *writecnt)
212{
213 int r;
214
215 ENABLE_REGWRITE_BUFFER(ah);
216 for (r = 0; r < array->ia_rows; r++) {
217 REG_WRITE(ah, INI_RA(array, r, 0),
218 INI_RA(array, r, column));
219 DO_DELAY(*writecnt);
220 }
221 REGWRITE_BUFFER_FLUSH(ah);
222}
223
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700224u32 ath9k_hw_reverse_bits(u32 val, u32 n)
225{
226 u32 retval;
227 int i;
228
229 for (i = 0, retval = 0; i < n; i++) {
230 retval = (retval << 1) | (val & 1);
231 val >>= 1;
232 }
233 return retval;
234}
235
Sujithcbe61d82009-02-09 13:27:12 +0530236u16 ath9k_hw_computetxtime(struct ath_hw *ah,
Felix Fietkau545750d2009-11-23 22:21:01 +0100237 u8 phy, int kbps,
Sujithf1dc5602008-10-29 10:16:30 +0530238 u32 frameLen, u16 rateix,
239 bool shortPreamble)
240{
241 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
Sujithf1dc5602008-10-29 10:16:30 +0530242
243 if (kbps == 0)
244 return 0;
245
Felix Fietkau545750d2009-11-23 22:21:01 +0100246 switch (phy) {
Sujith46d14a52008-11-18 09:08:13 +0530247 case WLAN_RC_PHY_CCK:
Sujithf1dc5602008-10-29 10:16:30 +0530248 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
Felix Fietkau545750d2009-11-23 22:21:01 +0100249 if (shortPreamble)
Sujithf1dc5602008-10-29 10:16:30 +0530250 phyTime >>= 1;
251 numBits = frameLen << 3;
252 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
253 break;
Sujith46d14a52008-11-18 09:08:13 +0530254 case WLAN_RC_PHY_OFDM:
Sujith2660b812009-02-09 13:27:26 +0530255 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530256 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
257 numBits = OFDM_PLCP_BITS + (frameLen << 3);
258 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
259 txTime = OFDM_SIFS_TIME_QUARTER
260 + OFDM_PREAMBLE_TIME_QUARTER
261 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
Sujith2660b812009-02-09 13:27:26 +0530262 } else if (ah->curchan &&
263 IS_CHAN_HALF_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
265 numBits = OFDM_PLCP_BITS + (frameLen << 3);
266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
267 txTime = OFDM_SIFS_TIME_HALF +
268 OFDM_PREAMBLE_TIME_HALF
269 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
270 } else {
271 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
272 numBits = OFDM_PLCP_BITS + (frameLen << 3);
273 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
274 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
275 + (numSymbols * OFDM_SYMBOL_TIME);
276 }
277 break;
278 default:
Joe Perches38002762010-12-02 19:12:36 -0800279 ath_err(ath9k_hw_common(ah),
280 "Unknown phy %u (rate ix %u)\n", phy, rateix);
Sujithf1dc5602008-10-29 10:16:30 +0530281 txTime = 0;
282 break;
283 }
284
285 return txTime;
286}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400287EXPORT_SYMBOL(ath9k_hw_computetxtime);
Sujithf1dc5602008-10-29 10:16:30 +0530288
Sujithcbe61d82009-02-09 13:27:12 +0530289void ath9k_hw_get_channel_centers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530290 struct ath9k_channel *chan,
291 struct chan_centers *centers)
292{
293 int8_t extoff;
Sujithf1dc5602008-10-29 10:16:30 +0530294
295 if (!IS_CHAN_HT40(chan)) {
296 centers->ctl_center = centers->ext_center =
297 centers->synth_center = chan->channel;
298 return;
299 }
300
301 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
302 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
303 centers->synth_center =
304 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
305 extoff = 1;
306 } else {
307 centers->synth_center =
308 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
309 extoff = -1;
310 }
311
312 centers->ctl_center =
313 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700314 /* 25 MHz spacing is supported by hw but not on upper layers */
Sujithf1dc5602008-10-29 10:16:30 +0530315 centers->ext_center =
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700316 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
Sujithf1dc5602008-10-29 10:16:30 +0530317}
318
319/******************/
320/* Chip Revisions */
321/******************/
322
Sujithcbe61d82009-02-09 13:27:12 +0530323static void ath9k_hw_read_revisions(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530324{
325 u32 val;
326
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530327 switch (ah->hw_version.devid) {
328 case AR5416_AR9100_DEVID:
329 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
330 break;
Gabor Juhos37625612011-06-21 11:23:23 +0200331 case AR9300_DEVID_AR9330:
332 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
333 if (ah->get_mac_revision) {
334 ah->hw_version.macRev = ah->get_mac_revision();
335 } else {
336 val = REG_READ(ah, AR_SREV);
337 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
338 }
339 return;
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530340 case AR9300_DEVID_AR9340:
341 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
342 val = REG_READ(ah, AR_SREV);
343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
344 return;
345 }
346
Sujithf1dc5602008-10-29 10:16:30 +0530347 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
348
349 if (val == 0xFF) {
350 val = REG_READ(ah, AR_SREV);
Sujithd535a422009-02-09 13:27:06 +0530351 ah->hw_version.macVersion =
352 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
353 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
Mohammed Shafi Shajakhan76ed94b2011-09-30 11:31:28 +0530354
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530355 if (AR_SREV_9462(ah))
Mohammed Shafi Shajakhan76ed94b2011-09-30 11:31:28 +0530356 ah->is_pciexpress = true;
357 else
358 ah->is_pciexpress = (val &
359 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
Sujithf1dc5602008-10-29 10:16:30 +0530360 } else {
361 if (!AR_SREV_9100(ah))
Sujithd535a422009-02-09 13:27:06 +0530362 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
Sujithf1dc5602008-10-29 10:16:30 +0530363
Sujithd535a422009-02-09 13:27:06 +0530364 ah->hw_version.macRev = val & AR_SREV_REVISION;
Sujithf1dc5602008-10-29 10:16:30 +0530365
Sujithd535a422009-02-09 13:27:06 +0530366 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
Sujith2660b812009-02-09 13:27:26 +0530367 ah->is_pciexpress = true;
Sujithf1dc5602008-10-29 10:16:30 +0530368 }
369}
370
Sujithf1dc5602008-10-29 10:16:30 +0530371/************************************/
372/* HW Attach, Detach, Init Routines */
373/************************************/
374
Sujithcbe61d82009-02-09 13:27:12 +0530375static void ath9k_hw_disablepcie(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530376{
Felix Fietkau040b74f2010-12-12 00:51:07 +0100377 if (!AR_SREV_5416(ah))
Sujithf1dc5602008-10-29 10:16:30 +0530378 return;
379
380 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
385 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
386 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
387 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
388 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
389
390 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
391}
392
Stanislaw Gruszkad4930082011-07-29 15:59:08 +0200393static void ath9k_hw_aspm_init(struct ath_hw *ah)
394{
395 struct ath_common *common = ath9k_hw_common(ah);
396
397 if (common->bus_ops->aspm_init)
398 common->bus_ops->aspm_init(common);
399}
400
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400401/* This should work for all families including legacy */
Sujithcbe61d82009-02-09 13:27:12 +0530402static bool ath9k_hw_chip_test(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530403{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700404 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400405 u32 regAddr[2] = { AR_STA_ID0 };
Sujithf1dc5602008-10-29 10:16:30 +0530406 u32 regHold[2];
Joe Perches07b2fa52010-11-20 18:38:53 -0800407 static const u32 patternData[4] = {
408 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
409 };
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400410 int i, j, loop_max;
Sujithf1dc5602008-10-29 10:16:30 +0530411
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400412 if (!AR_SREV_9300_20_OR_LATER(ah)) {
413 loop_max = 2;
414 regAddr[1] = AR_PHY_BASE + (8 << 2);
415 } else
416 loop_max = 1;
417
418 for (i = 0; i < loop_max; i++) {
Sujithf1dc5602008-10-29 10:16:30 +0530419 u32 addr = regAddr[i];
420 u32 wrData, rdData;
421
422 regHold[i] = REG_READ(ah, addr);
423 for (j = 0; j < 0x100; j++) {
424 wrData = (j << 16) | j;
425 REG_WRITE(ah, addr, wrData);
426 rdData = REG_READ(ah, addr);
427 if (rdData != wrData) {
Joe Perches38002762010-12-02 19:12:36 -0800428 ath_err(common,
429 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
430 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530431 return false;
432 }
433 }
434 for (j = 0; j < 4; j++) {
435 wrData = patternData[j];
436 REG_WRITE(ah, addr, wrData);
437 rdData = REG_READ(ah, addr);
438 if (wrData != rdData) {
Joe Perches38002762010-12-02 19:12:36 -0800439 ath_err(common,
440 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
441 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530442 return false;
443 }
444 }
445 REG_WRITE(ah, regAddr[i], regHold[i]);
446 }
447 udelay(100);
Sujithcbe61d82009-02-09 13:27:12 +0530448
Sujithf1dc5602008-10-29 10:16:30 +0530449 return true;
450}
451
Luis R. Rodriguezb8b0f372009-08-03 12:24:43 -0700452static void ath9k_hw_init_config(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700453{
454 int i;
455
Felix Fietkau689e7562012-04-12 22:35:56 +0200456 ah->config.dma_beacon_response_time = 1;
457 ah->config.sw_beacon_response_time = 6;
Sujith2660b812009-02-09 13:27:26 +0530458 ah->config.additional_swba_backoff = 0;
459 ah->config.ack_6mb = 0x0;
460 ah->config.cwm_ignore_extcca = 0;
Sujith2660b812009-02-09 13:27:26 +0530461 ah->config.pcie_clock_req = 0;
Sujith2660b812009-02-09 13:27:26 +0530462 ah->config.pcie_waen = 0;
463 ah->config.analog_shiftreg = 1;
Luis R. Rodriguez03c72512010-06-12 00:33:46 -0400464 ah->config.enable_ani = true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700465
466 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530467 ah->config.spurchans[i][0] = AR_NO_SPUR;
468 ah->config.spurchans[i][1] = AR_NO_SPUR;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700469 }
470
Luis R. Rodriguez6f481012011-01-20 17:47:39 -0800471 /* PAPRD needs some more work to be enabled */
472 ah->config.paprd_disable = 1;
473
Sujith0ce024c2009-12-14 14:57:00 +0530474 ah->config.rx_intr_mitigation = true;
Luis R. Rodriguez6a0ec302010-06-21 18:38:49 -0400475 ah->config.pcieSerDesWrite = true;
Luis R. Rodriguez61584252009-03-12 18:18:49 -0400476
477 /*
478 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
479 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
480 * This means we use it for all AR5416 devices, and the few
481 * minor PCI AR9280 devices out there.
482 *
483 * Serialization is required because these devices do not handle
484 * well the case of two concurrent reads/writes due to the latency
485 * involved. During one read/write another read/write can be issued
486 * on another CPU while the previous read/write may still be working
487 * on our hardware, if we hit this case the hardware poops in a loop.
488 * We prevent this by serializing reads and writes.
489 *
490 * This issue is not present on PCI-Express devices or pre-AR5416
491 * devices (legacy, 802.11abg).
492 */
493 if (num_possible_cpus() > 1)
David S. Miller2d6a5e92009-03-17 15:01:30 -0700494 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700495}
496
Luis R. Rodriguez50aca252009-08-03 12:24:42 -0700497static void ath9k_hw_init_defaults(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700498{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700499 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
500
501 regulatory->country_code = CTRY_DEFAULT;
502 regulatory->power_limit = MAX_RATE_POWER;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700503
Sujithd535a422009-02-09 13:27:06 +0530504 ah->hw_version.magic = AR5416_MAGIC;
Sujithd535a422009-02-09 13:27:06 +0530505 ah->hw_version.subvendorid = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700506
Sujith2660b812009-02-09 13:27:26 +0530507 ah->atim_window = 0;
Felix Fietkau16f24112010-06-12 17:22:32 +0200508 ah->sta_id1_defaults =
509 AR_STA_ID1_CRPT_MIC_ENABLE |
510 AR_STA_ID1_MCAST_KSRCH;
Felix Fietkauf1717602011-03-19 13:55:41 +0100511 if (AR_SREV_9100(ah))
512 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
Rajkumar Manoharane3f2acc2011-08-27 11:22:59 +0530513 ah->slottime = ATH9K_SLOT_TIME_9;
Sujith2660b812009-02-09 13:27:26 +0530514 ah->globaltxtimeout = (u32) -1;
Gabor Juhoscbdec972009-07-24 17:27:22 +0200515 ah->power_mode = ATH9K_PM_UNDEFINED;
Felix Fietkau8efa7a82012-03-14 16:40:23 +0100516 ah->htc_reset_init = true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700517}
518
Sujithcbe61d82009-02-09 13:27:12 +0530519static int ath9k_hw_init_macaddr(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700520{
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700521 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530522 u32 sum;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700523 int i;
Sujithf1dc5602008-10-29 10:16:30 +0530524 u16 eeval;
Joe Perches07b2fa52010-11-20 18:38:53 -0800525 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700526
Sujithf1dc5602008-10-29 10:16:30 +0530527 sum = 0;
528 for (i = 0; i < 3; i++) {
Luis R. Rodriguez49101672010-04-15 17:39:13 -0400529 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530530 sum += eeval;
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700531 common->macaddr[2 * i] = eeval >> 8;
532 common->macaddr[2 * i + 1] = eeval & 0xff;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700533 }
Sujithd8baa932009-03-30 15:28:25 +0530534 if (sum == 0 || sum == 0xffff * 3)
Sujithf1dc5602008-10-29 10:16:30 +0530535 return -EADDRNOTAVAIL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700536
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700537 return 0;
538}
539
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700540static int ath9k_hw_post_init(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700541{
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530542 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700543 int ecode;
544
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530545 if (common->bus_ops->ath_bus_type != ATH_USB) {
Sujith527d4852010-03-17 14:25:16 +0530546 if (!ath9k_hw_chip_test(ah))
547 return -ENODEV;
548 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700549
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -0400550 if (!AR_SREV_9300_20_OR_LATER(ah)) {
551 ecode = ar9002_hw_rf_claim(ah);
552 if (ecode != 0)
553 return ecode;
554 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700555
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700556 ecode = ath9k_hw_eeprom_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700557 if (ecode != 0)
558 return ecode;
Sujith7d01b222009-03-13 08:55:55 +0530559
Joe Perchesd2182b62011-12-15 14:55:53 -0800560 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800561 ah->eep_ops->get_eeprom_ver(ah),
562 ah->eep_ops->get_eeprom_rev(ah));
Sujith7d01b222009-03-13 08:55:55 +0530563
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400564 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
565 if (ecode) {
Joe Perches38002762010-12-02 19:12:36 -0800566 ath_err(ath9k_hw_common(ah),
567 "Failed allocating banks for external radio\n");
Rajkumar Manoharan48a7c3d2010-11-08 20:40:53 +0530568 ath9k_hw_rf_free_ext_banks(ah);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400569 return ecode;
Luis R. Rodriguez574d6b12009-10-19 02:33:37 -0400570 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700571
Nikolay Martynov42794252011-12-02 22:39:16 -0500572 if (ah->config.enable_ani) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700573 ath9k_hw_ani_setup(ah);
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700574 ath9k_hw_ani_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700575 }
Sujithf1dc5602008-10-29 10:16:30 +0530576
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700577 return 0;
578}
579
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400580static void ath9k_hw_attach_ops(struct ath_hw *ah)
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700581{
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400582 if (AR_SREV_9300_20_OR_LATER(ah))
583 ar9003_hw_attach_ops(ah);
584 else
585 ar9002_hw_attach_ops(ah);
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700586}
587
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400588/* Called for all hardware families */
589static int __ath9k_hw_init(struct ath_hw *ah)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700590{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700591 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700592 int r = 0;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700593
Senthil Balasubramanianac45c122010-12-22 21:14:20 +0530594 ath9k_hw_read_revisions(ah);
595
Senthil Balasubramanian0a8d7cb2010-12-22 19:17:18 +0530596 /*
597 * Read back AR_WA into a permanent copy and set bits 14 and 17.
598 * We need to do this to avoid RMW of this register. We cannot
599 * read the reg when chip is asleep.
600 */
601 ah->WARegVal = REG_READ(ah, AR_WA);
602 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
603 AR_WA_ASPM_TIMER_BASED_DISABLE);
604
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700605 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
Joe Perches38002762010-12-02 19:12:36 -0800606 ath_err(common, "Couldn't reset chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700607 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700608 }
609
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530610 if (AR_SREV_9462(ah))
Rajkumar Manoharaneec353c2011-10-13 10:49:13 +0530611 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
612
Luis R. Rodriguezbab1f622010-04-15 17:38:20 -0400613 ath9k_hw_init_defaults(ah);
614 ath9k_hw_init_config(ah);
615
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400616 ath9k_hw_attach_ops(ah);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400617
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -0700618 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
Joe Perches38002762010-12-02 19:12:36 -0800619 ath_err(common, "Couldn't wakeup chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700620 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700621 }
622
Felix Fietkauf3eef642012-03-14 16:40:25 +0100623 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700624 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
John W. Linville4c85ab12010-07-28 10:06:35 -0400625 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
626 !ah->is_pciexpress)) {
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700627 ah->config.serialize_regmode =
628 SER_REG_MODE_ON;
629 } else {
630 ah->config.serialize_regmode =
631 SER_REG_MODE_OFF;
632 }
633 }
634
Joe Perchesd2182b62011-12-15 14:55:53 -0800635 ath_dbg(common, RESET, "serialize_regmode is %d\n",
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700636 ah->config.serialize_regmode);
637
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -0500638 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
639 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
640 else
641 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
642
Felix Fietkau6da5a722010-12-12 00:51:12 +0100643 switch (ah->hw_version.macVersion) {
644 case AR_SREV_VERSION_5416_PCI:
645 case AR_SREV_VERSION_5416_PCIE:
646 case AR_SREV_VERSION_9160:
647 case AR_SREV_VERSION_9100:
648 case AR_SREV_VERSION_9280:
649 case AR_SREV_VERSION_9285:
650 case AR_SREV_VERSION_9287:
651 case AR_SREV_VERSION_9271:
652 case AR_SREV_VERSION_9300:
Gabor Juhos2c8e5932011-06-21 11:23:21 +0200653 case AR_SREV_VERSION_9330:
Felix Fietkau6da5a722010-12-12 00:51:12 +0100654 case AR_SREV_VERSION_9485:
Vasanthakumar Thiagarajanbca04682011-04-19 19:29:20 +0530655 case AR_SREV_VERSION_9340:
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530656 case AR_SREV_VERSION_9462:
Felix Fietkau6da5a722010-12-12 00:51:12 +0100657 break;
658 default:
Joe Perches38002762010-12-02 19:12:36 -0800659 ath_err(common,
660 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
661 ah->hw_version.macVersion, ah->hw_version.macRev);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700662 return -EOPNOTSUPP;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700663 }
664
Gabor Juhos2c8e5932011-06-21 11:23:21 +0200665 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
666 AR_SREV_9330(ah))
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400667 ah->is_pciexpress = false;
668
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700669 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700670 ath9k_hw_init_cal_settings(ah);
671
672 ah->ani_function = ATH9K_ANI_ALL;
Felix Fietkau7a370812010-09-22 12:34:52 +0200673 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700674 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -0400675 if (!AR_SREV_9300_20_OR_LATER(ah))
676 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700677
Nikolay Martynov4f17c482011-12-06 21:57:17 -0500678 /* disable ANI for 9340 */
679 if (AR_SREV_9340(ah))
Nikolay Martynov42794252011-12-02 22:39:16 -0500680 ah->config.enable_ani = false;
681
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700682 ath9k_hw_init_mode_regs(ah);
683
Stanislaw Gruszka69ce6742011-08-05 13:10:34 +0200684 if (!ah->is_pciexpress)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700685 ath9k_hw_disablepcie(ah);
686
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700687 r = ath9k_hw_post_init(ah);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700688 if (r)
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700689 return r;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700690
691 ath9k_hw_init_mode_gain_regs(ah);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +0100692 r = ath9k_hw_fill_cap_info(ah);
693 if (r)
694 return r;
695
Stanislaw Gruszka69ce6742011-08-05 13:10:34 +0200696 if (ah->is_pciexpress)
697 ath9k_hw_aspm_init(ah);
698
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700699 r = ath9k_hw_init_macaddr(ah);
700 if (r) {
Joe Perches38002762010-12-02 19:12:36 -0800701 ath_err(common, "Failed to initialize MAC address\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700702 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700703 }
704
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400705 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
Sujith2660b812009-02-09 13:27:26 +0530706 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700707 else
Sujith2660b812009-02-09 13:27:26 +0530708 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700709
Gabor Juhos88e641d2011-06-21 11:23:30 +0200710 if (AR_SREV_9330(ah))
711 ah->bb_watchdog_timeout_ms = 85;
712 else
713 ah->bb_watchdog_timeout_ms = 25;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700714
Luis R. Rodriguez211f5852009-10-06 21:19:07 -0400715 common->state = ATH_HW_INITIALIZED;
716
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700717 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700718}
719
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400720int ath9k_hw_init(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530721{
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400722 int ret;
723 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530724
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400725 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
726 switch (ah->hw_version.devid) {
727 case AR5416_DEVID_PCI:
728 case AR5416_DEVID_PCIE:
729 case AR5416_AR9100_DEVID:
730 case AR9160_DEVID_PCI:
731 case AR9280_DEVID_PCI:
732 case AR9280_DEVID_PCIE:
733 case AR9285_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400734 case AR9287_DEVID_PCI:
735 case AR9287_DEVID_PCIE:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400736 case AR2427_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400737 case AR9300_DEVID_PCIE:
Vasanthakumar Thiagarajan3050c912010-12-06 04:27:36 -0800738 case AR9300_DEVID_AR9485_PCIE:
Gabor Juhos999a7a82011-06-21 11:23:52 +0200739 case AR9300_DEVID_AR9330:
Vasanthakumar Thiagarajanbca04682011-04-19 19:29:20 +0530740 case AR9300_DEVID_AR9340:
Luis R. Rodriguez5a63ef02011-08-24 15:36:08 -0700741 case AR9300_DEVID_AR9580:
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530742 case AR9300_DEVID_AR9462:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400743 break;
744 default:
745 if (common->bus_ops->ath_bus_type == ATH_USB)
746 break;
Joe Perches38002762010-12-02 19:12:36 -0800747 ath_err(common, "Hardware device ID 0x%04x not supported\n",
748 ah->hw_version.devid);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400749 return -EOPNOTSUPP;
750 }
Sujithf1dc5602008-10-29 10:16:30 +0530751
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400752 ret = __ath9k_hw_init(ah);
753 if (ret) {
Joe Perches38002762010-12-02 19:12:36 -0800754 ath_err(common,
755 "Unable to initialize hardware; initialization status: %d\n",
756 ret);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400757 return ret;
758 }
Sujithf1dc5602008-10-29 10:16:30 +0530759
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400760 return 0;
Sujithf1dc5602008-10-29 10:16:30 +0530761}
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400762EXPORT_SYMBOL(ath9k_hw_init);
Sujithf1dc5602008-10-29 10:16:30 +0530763
Sujithcbe61d82009-02-09 13:27:12 +0530764static void ath9k_hw_init_qos(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530765{
Sujith7d0d0df2010-04-16 11:53:57 +0530766 ENABLE_REGWRITE_BUFFER(ah);
767
Sujithf1dc5602008-10-29 10:16:30 +0530768 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
769 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
770
771 REG_WRITE(ah, AR_QOS_NO_ACK,
772 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
773 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
774 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
775
776 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
777 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
778 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
779 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
780 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
Sujith7d0d0df2010-04-16 11:53:57 +0530781
782 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530783}
784
Senthil Balasubramanianb84628e2011-04-22 11:32:12 +0530785u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
Vivek Natarajanb1415812011-01-27 14:45:07 +0530786{
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100787 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
788 udelay(100);
789 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
790
791 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
Vivek Natarajanb1415812011-01-27 14:45:07 +0530792 udelay(100);
Vivek Natarajanb1415812011-01-27 14:45:07 +0530793
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100794 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
Vivek Natarajanb1415812011-01-27 14:45:07 +0530795}
796EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
797
Sujithcbe61d82009-02-09 13:27:12 +0530798static void ath9k_hw_init_pll(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530799 struct ath9k_channel *chan)
800{
Vasanthakumar Thiagarajand09b17f2010-12-06 04:27:44 -0800801 u32 pll;
802
Vivek Natarajan22983c32011-01-27 14:45:09 +0530803 if (AR_SREV_9485(ah)) {
Vivek Natarajan22983c32011-01-27 14:45:09 +0530804
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530805 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
807 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
808 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
809 AR_CH0_DPLL2_KD, 0x40);
810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
811 AR_CH0_DPLL2_KI, 0x4);
Vivek Natarajan22983c32011-01-27 14:45:09 +0530812
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
814 AR_CH0_BB_DPLL1_REFDIV, 0x5);
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
816 AR_CH0_BB_DPLL1_NINI, 0x58);
817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
818 AR_CH0_BB_DPLL1_NFRAC, 0x0);
819
820 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
821 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
822 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
823 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
824 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
825 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
826
827 /* program BB PLL phase_shift to 0x6 */
828 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
829 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
830
831 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
832 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
Vivek Natarajan75e03512011-03-10 11:05:42 +0530833 udelay(1000);
Gabor Juhosa5415d62011-06-21 11:23:29 +0200834 } else if (AR_SREV_9330(ah)) {
835 u32 ddr_dpll2, pll_control2, kd;
836
837 if (ah->is_clk_25mhz) {
838 ddr_dpll2 = 0x18e82f01;
839 pll_control2 = 0xe04a3d;
840 kd = 0x1d;
841 } else {
842 ddr_dpll2 = 0x19e82f01;
843 pll_control2 = 0x886666;
844 kd = 0x3d;
845 }
846
847 /* program DDR PLL ki and kd value */
848 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
849
850 /* program DDR PLL phase_shift */
851 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
852 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
853
854 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
855 udelay(1000);
856
857 /* program refdiv, nint, frac to RTC register */
858 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
859
860 /* program BB PLL kd and ki value */
861 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
862 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
863
864 /* program BB PLL phase_shift */
865 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
866 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530867 } else if (AR_SREV_9340(ah)) {
868 u32 regval, pll2_divint, pll2_divfrac, refdiv;
869
870 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
871 udelay(1000);
872
873 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
874 udelay(100);
875
876 if (ah->is_clk_25mhz) {
877 pll2_divint = 0x54;
878 pll2_divfrac = 0x1eb85;
879 refdiv = 3;
880 } else {
881 pll2_divint = 88;
882 pll2_divfrac = 0;
883 refdiv = 5;
884 }
885
886 regval = REG_READ(ah, AR_PHY_PLL_MODE);
887 regval |= (0x1 << 16);
888 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
889 udelay(100);
890
891 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
892 (pll2_divint << 18) | pll2_divfrac);
893 udelay(100);
894
895 regval = REG_READ(ah, AR_PHY_PLL_MODE);
896 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
897 (0x4 << 26) | (0x18 << 19);
898 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
899 REG_WRITE(ah, AR_PHY_PLL_MODE,
900 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
901 udelay(1000);
Vivek Natarajan22983c32011-01-27 14:45:09 +0530902 }
Vasanthakumar Thiagarajand09b17f2010-12-06 04:27:44 -0800903
904 pll = ath9k_hw_compute_pll_control(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +0530905
Gabor Juhosd03a66c2009-01-14 20:17:09 +0100906 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
Sujithf1dc5602008-10-29 10:16:30 +0530907
Gabor Juhosa5415d62011-06-21 11:23:29 +0200908 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530909 udelay(1000);
910
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400911 /* Switch the core clock for ar9271 to 117Mhz */
912 if (AR_SREV_9271(ah)) {
Sujith25e2ab12010-03-17 14:25:22 +0530913 udelay(500);
914 REG_WRITE(ah, 0x50040, 0x304);
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400915 }
916
Sujithf1dc5602008-10-29 10:16:30 +0530917 udelay(RTC_PLL_SETTLE_DELAY);
918
919 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530920
921 if (AR_SREV_9340(ah)) {
922 if (ah->is_clk_25mhz) {
923 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
924 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
925 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
926 } else {
927 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
928 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
929 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
930 }
931 udelay(100);
932 }
Sujithf1dc5602008-10-29 10:16:30 +0530933}
934
Sujithcbe61d82009-02-09 13:27:12 +0530935static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
Colin McCabed97809d2008-12-01 13:38:55 -0800936 enum nl80211_iftype opmode)
Sujithf1dc5602008-10-29 10:16:30 +0530937{
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530938 u32 sync_default = AR_INTR_SYNC_DEFAULT;
Pavel Roskin152d5302010-03-31 18:05:37 -0400939 u32 imr_reg = AR_IMR_TXERR |
Sujithf1dc5602008-10-29 10:16:30 +0530940 AR_IMR_TXURN |
941 AR_IMR_RXERR |
942 AR_IMR_RXORN |
943 AR_IMR_BCNMISC;
944
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530945 if (AR_SREV_9340(ah))
946 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
947
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400948 if (AR_SREV_9300_20_OR_LATER(ah)) {
949 imr_reg |= AR_IMR_RXOK_HP;
950 if (ah->config.rx_intr_mitigation)
951 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
952 else
953 imr_reg |= AR_IMR_RXOK_LP;
Sujithf1dc5602008-10-29 10:16:30 +0530954
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400955 } else {
956 if (ah->config.rx_intr_mitigation)
957 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
958 else
959 imr_reg |= AR_IMR_RXOK;
960 }
961
962 if (ah->config.tx_intr_mitigation)
963 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
964 else
965 imr_reg |= AR_IMR_TXOK;
Sujithf1dc5602008-10-29 10:16:30 +0530966
Colin McCabed97809d2008-12-01 13:38:55 -0800967 if (opmode == NL80211_IFTYPE_AP)
Pavel Roskin152d5302010-03-31 18:05:37 -0400968 imr_reg |= AR_IMR_MIB;
Sujithf1dc5602008-10-29 10:16:30 +0530969
Sujith7d0d0df2010-04-16 11:53:57 +0530970 ENABLE_REGWRITE_BUFFER(ah);
971
Pavel Roskin152d5302010-03-31 18:05:37 -0400972 REG_WRITE(ah, AR_IMR, imr_reg);
Pavel Roskin74bad5c2010-02-23 18:15:27 -0500973 ah->imrs2_reg |= AR_IMR_S2_GTT;
974 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
Sujithf1dc5602008-10-29 10:16:30 +0530975
976 if (!AR_SREV_9100(ah)) {
977 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530978 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
Sujithf1dc5602008-10-29 10:16:30 +0530979 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
980 }
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400981
Sujith7d0d0df2010-04-16 11:53:57 +0530982 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530983
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400984 if (AR_SREV_9300_20_OR_LATER(ah)) {
985 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
986 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
987 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
988 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
989 }
Sujithf1dc5602008-10-29 10:16:30 +0530990}
991
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700992static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
993{
994 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
995 val = min(val, (u32) 0xFFFF);
996 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
997}
998
Felix Fietkau0005baf2010-01-15 02:33:40 +0100999static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +05301000{
Felix Fietkau0005baf2010-01-15 02:33:40 +01001001 u32 val = ath9k_hw_mac_to_clks(ah, us);
1002 val = min(val, (u32) 0xFFFF);
1003 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
Sujithf1dc5602008-10-29 10:16:30 +05301004}
1005
Felix Fietkau0005baf2010-01-15 02:33:40 +01001006static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +05301007{
Felix Fietkau0005baf2010-01-15 02:33:40 +01001008 u32 val = ath9k_hw_mac_to_clks(ah, us);
1009 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1010 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1011}
1012
1013static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1014{
1015 u32 val = ath9k_hw_mac_to_clks(ah, us);
1016 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1017 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
Sujithf1dc5602008-10-29 10:16:30 +05301018}
1019
Sujithcbe61d82009-02-09 13:27:12 +05301020static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
Sujithf1dc5602008-10-29 10:16:30 +05301021{
Sujithf1dc5602008-10-29 10:16:30 +05301022 if (tu > 0xFFFF) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001023 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1024 tu);
Sujith2660b812009-02-09 13:27:26 +05301025 ah->globaltxtimeout = (u32) -1;
Sujithf1dc5602008-10-29 10:16:30 +05301026 return false;
1027 } else {
1028 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
Sujith2660b812009-02-09 13:27:26 +05301029 ah->globaltxtimeout = tu;
Sujithf1dc5602008-10-29 10:16:30 +05301030 return true;
1031 }
1032}
1033
Felix Fietkau0005baf2010-01-15 02:33:40 +01001034void ath9k_hw_init_global_settings(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301035{
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001036 struct ath_common *common = ath9k_hw_common(ah);
1037 struct ieee80211_conf *conf = &common->hw->conf;
1038 const struct ath9k_channel *chan = ah->curchan;
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001039 int acktimeout, ctstimeout, ack_offset = 0;
Felix Fietkaue239d852010-01-15 02:34:58 +01001040 int slottime;
Felix Fietkau0005baf2010-01-15 02:33:40 +01001041 int sifstime;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001042 int rx_lat = 0, tx_lat = 0, eifs = 0;
1043 u32 reg;
Felix Fietkau0005baf2010-01-15 02:33:40 +01001044
Joe Perchesd2182b62011-12-15 14:55:53 -08001045 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
Joe Perches226afe62010-12-02 19:12:37 -08001046 ah->misc_mode);
Sujithf1dc5602008-10-29 10:16:30 +05301047
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001048 if (!chan)
1049 return;
1050
Sujith2660b812009-02-09 13:27:26 +05301051 if (ah->misc_mode != 0)
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001052 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
Felix Fietkau0005baf2010-01-15 02:33:40 +01001053
Rajkumar Manoharan81a91d52011-08-31 10:47:30 +05301054 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1055 rx_lat = 41;
1056 else
1057 rx_lat = 37;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001058 tx_lat = 54;
1059
Felix Fietkaue88e4862012-04-19 21:18:22 +02001060 if (IS_CHAN_5GHZ(chan))
1061 sifstime = 16;
1062 else
1063 sifstime = 10;
1064
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001065 if (IS_CHAN_HALF_RATE(chan)) {
1066 eifs = 175;
1067 rx_lat *= 2;
1068 tx_lat *= 2;
1069 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1070 tx_lat += 11;
1071
Felix Fietkaue88e4862012-04-19 21:18:22 +02001072 sifstime *= 2;
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001073 ack_offset = 16;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001074 slottime = 13;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001075 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1076 eifs = 340;
Rajkumar Manoharan81a91d52011-08-31 10:47:30 +05301077 rx_lat = (rx_lat * 4) - 1;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001078 tx_lat *= 4;
1079 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1080 tx_lat += 22;
1081
Felix Fietkaue88e4862012-04-19 21:18:22 +02001082 sifstime *= 4;
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001083 ack_offset = 32;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001084 slottime = 21;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001085 } else {
Rajkumar Manoharana7be0392011-08-27 12:13:21 +05301086 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1087 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1088 reg = AR_USEC_ASYNC_FIFO;
1089 } else {
1090 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1091 common->clockrate;
1092 reg = REG_READ(ah, AR_USEC);
1093 }
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001094 rx_lat = MS(reg, AR_USEC_RX_LAT);
1095 tx_lat = MS(reg, AR_USEC_TX_LAT);
1096
1097 slottime = ah->slottime;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001098 }
Felix Fietkau0005baf2010-01-15 02:33:40 +01001099
Felix Fietkaue239d852010-01-15 02:34:58 +01001100 /* As defined by IEEE 802.11-2007 17.3.8.6 */
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001101 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
Felix Fietkauadb50662011-08-28 01:52:10 +02001102 ctstimeout = acktimeout;
Felix Fietkau42c45682010-02-11 18:07:19 +01001103
1104 /*
1105 * Workaround for early ACK timeouts, add an offset to match the
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001106 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
Felix Fietkau42c45682010-02-11 18:07:19 +01001107 * This was initially only meant to work around an issue with delayed
1108 * BA frames in some implementations, but it has been found to fix ACK
1109 * timeout issues in other cases as well.
1110 */
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001111 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ &&
1112 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
Felix Fietkau42c45682010-02-11 18:07:19 +01001113 acktimeout += 64 - sifstime - ah->slottime;
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001114 ctstimeout += 48 - sifstime - ah->slottime;
1115 }
1116
Felix Fietkau42c45682010-02-11 18:07:19 +01001117
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001118 ath9k_hw_set_sifs_time(ah, sifstime);
1119 ath9k_hw_setslottime(ah, slottime);
Felix Fietkau0005baf2010-01-15 02:33:40 +01001120 ath9k_hw_set_ack_timeout(ah, acktimeout);
Felix Fietkauadb50662011-08-28 01:52:10 +02001121 ath9k_hw_set_cts_timeout(ah, ctstimeout);
Sujith2660b812009-02-09 13:27:26 +05301122 if (ah->globaltxtimeout != (u32) -1)
1123 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001124
1125 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1126 REG_RMW(ah, AR_USEC,
1127 (common->clockrate - 1) |
1128 SM(rx_lat, AR_USEC_RX_LAT) |
1129 SM(tx_lat, AR_USEC_TX_LAT),
1130 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1131
Sujithf1dc5602008-10-29 10:16:30 +05301132}
Felix Fietkau0005baf2010-01-15 02:33:40 +01001133EXPORT_SYMBOL(ath9k_hw_init_global_settings);
Sujithf1dc5602008-10-29 10:16:30 +05301134
Sujith285f2dd2010-01-08 10:36:07 +05301135void ath9k_hw_deinit(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001136{
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001137 struct ath_common *common = ath9k_hw_common(ah);
1138
Sujith736b3a22010-03-17 14:25:24 +05301139 if (common->state < ATH_HW_INITIALIZED)
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001140 goto free_hw;
1141
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001142 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001143
1144free_hw:
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001145 ath9k_hw_rf_free_ext_banks(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001146}
Sujith285f2dd2010-01-08 10:36:07 +05301147EXPORT_SYMBOL(ath9k_hw_deinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001148
Sujithf1dc5602008-10-29 10:16:30 +05301149/*******/
1150/* INI */
1151/*******/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001152
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001153u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Bob Copeland3a702e42009-03-30 22:30:29 -04001154{
1155 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1156
1157 if (IS_CHAN_B(chan))
1158 ctl |= CTL_11B;
1159 else if (IS_CHAN_G(chan))
1160 ctl |= CTL_11G;
1161 else
1162 ctl |= CTL_11A;
1163
1164 return ctl;
1165}
1166
Sujithf1dc5602008-10-29 10:16:30 +05301167/****************************************/
1168/* Reset and Channel Switching Routines */
1169/****************************************/
1170
Sujithcbe61d82009-02-09 13:27:12 +05301171static inline void ath9k_hw_set_dma(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301172{
Felix Fietkau57b32222010-04-15 17:39:22 -04001173 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301174
Sujith7d0d0df2010-04-16 11:53:57 +05301175 ENABLE_REGWRITE_BUFFER(ah);
1176
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001177 /*
1178 * set AHB_MODE not to do cacheline prefetches
1179 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001180 if (!AR_SREV_9300_20_OR_LATER(ah))
1181 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
Sujithf1dc5602008-10-29 10:16:30 +05301182
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001183 /*
1184 * let mac dma reads be in 128 byte chunks
1185 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001186 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05301187
Sujith7d0d0df2010-04-16 11:53:57 +05301188 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301189
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001190 /*
1191 * Restore TX Trigger Level to its pre-reset value.
1192 * The initial value depends on whether aggregation is enabled, and is
1193 * adjusted whenever underruns are detected.
1194 */
Felix Fietkau57b32222010-04-15 17:39:22 -04001195 if (!AR_SREV_9300_20_OR_LATER(ah))
1196 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
Sujithf1dc5602008-10-29 10:16:30 +05301197
Sujith7d0d0df2010-04-16 11:53:57 +05301198 ENABLE_REGWRITE_BUFFER(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301199
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001200 /*
1201 * let mac dma writes be in 128 byte chunks
1202 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001203 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05301204
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001205 /*
1206 * Setup receive FIFO threshold to hold off TX activities
1207 */
Sujithf1dc5602008-10-29 10:16:30 +05301208 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1209
Felix Fietkau57b32222010-04-15 17:39:22 -04001210 if (AR_SREV_9300_20_OR_LATER(ah)) {
1211 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1212 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1213
1214 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1215 ah->caps.rx_status_len);
1216 }
1217
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001218 /*
1219 * reduce the number of usable entries in PCU TXBUF to avoid
1220 * wrap around issues.
1221 */
Sujithf1dc5602008-10-29 10:16:30 +05301222 if (AR_SREV_9285(ah)) {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001223 /* For AR9285 the number of Fifos are reduced to half.
1224 * So set the usable tx buf size also to half to
1225 * avoid data/delimiter underruns
1226 */
Sujithf1dc5602008-10-29 10:16:30 +05301227 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1228 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001229 } else if (!AR_SREV_9271(ah)) {
Sujithf1dc5602008-10-29 10:16:30 +05301230 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1231 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1232 }
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -04001233
Sujith7d0d0df2010-04-16 11:53:57 +05301234 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301235
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -04001236 if (AR_SREV_9300_20_OR_LATER(ah))
1237 ath9k_hw_reset_txstatus_ring(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301238}
1239
Sujithcbe61d82009-02-09 13:27:12 +05301240static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
Sujithf1dc5602008-10-29 10:16:30 +05301241{
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001242 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1243 u32 set = AR_STA_ID1_KSRCH_MODE;
Sujithf1dc5602008-10-29 10:16:30 +05301244
Sujithf1dc5602008-10-29 10:16:30 +05301245 switch (opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08001246 case NL80211_IFTYPE_ADHOC:
Pat Erley9cb54122009-03-20 22:59:59 -04001247 case NL80211_IFTYPE_MESH_POINT:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001248 set |= AR_STA_ID1_ADHOC;
Sujithf1dc5602008-10-29 10:16:30 +05301249 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1250 break;
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001251 case NL80211_IFTYPE_AP:
1252 set |= AR_STA_ID1_STA_AP;
1253 /* fall through */
Colin McCabed97809d2008-12-01 13:38:55 -08001254 case NL80211_IFTYPE_STATION:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001255 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
Sujithf1dc5602008-10-29 10:16:30 +05301256 break;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +05301257 default:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001258 if (!ah->is_monitoring)
1259 set = 0;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +05301260 break;
Sujithf1dc5602008-10-29 10:16:30 +05301261 }
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001262 REG_RMW(ah, AR_STA_ID1, set, mask);
Sujithf1dc5602008-10-29 10:16:30 +05301263}
1264
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001265void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1266 u32 *coef_mantissa, u32 *coef_exponent)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001267{
1268 u32 coef_exp, coef_man;
1269
1270 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1271 if ((coef_scaled >> coef_exp) & 0x1)
1272 break;
1273
1274 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1275
1276 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1277
1278 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1279 *coef_exponent = coef_exp - 16;
1280}
1281
Sujithcbe61d82009-02-09 13:27:12 +05301282static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
Sujithf1dc5602008-10-29 10:16:30 +05301283{
1284 u32 rst_flags;
1285 u32 tmpReg;
1286
Sujith70768492009-02-16 13:23:12 +05301287 if (AR_SREV_9100(ah)) {
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001288 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1289 AR_RTC_DERIVED_CLK_PERIOD, 1);
Sujith70768492009-02-16 13:23:12 +05301290 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1291 }
1292
Sujith7d0d0df2010-04-16 11:53:57 +05301293 ENABLE_REGWRITE_BUFFER(ah);
1294
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001295 if (AR_SREV_9300_20_OR_LATER(ah)) {
1296 REG_WRITE(ah, AR_WA, ah->WARegVal);
1297 udelay(10);
1298 }
1299
Sujithf1dc5602008-10-29 10:16:30 +05301300 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1301 AR_RTC_FORCE_WAKE_ON_INT);
1302
1303 if (AR_SREV_9100(ah)) {
1304 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1305 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1306 } else {
1307 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1308 if (tmpReg &
1309 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1310 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001311 u32 val;
Sujithf1dc5602008-10-29 10:16:30 +05301312 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001313
1314 val = AR_RC_HOSTIF;
1315 if (!AR_SREV_9300_20_OR_LATER(ah))
1316 val |= AR_RC_AHB;
1317 REG_WRITE(ah, AR_RC, val);
1318
1319 } else if (!AR_SREV_9300_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05301320 REG_WRITE(ah, AR_RC, AR_RC_AHB);
Sujithf1dc5602008-10-29 10:16:30 +05301321
1322 rst_flags = AR_RTC_RC_MAC_WARM;
1323 if (type == ATH9K_RESET_COLD)
1324 rst_flags |= AR_RTC_RC_MAC_COLD;
1325 }
1326
Gabor Juhos7d95847c2011-06-21 11:23:51 +02001327 if (AR_SREV_9330(ah)) {
1328 int npend = 0;
1329 int i;
1330
1331 /* AR9330 WAR:
1332 * call external reset function to reset WMAC if:
1333 * - doing a cold reset
1334 * - we have pending frames in the TX queues
1335 */
1336
1337 for (i = 0; i < AR_NUM_QCU; i++) {
1338 npend = ath9k_hw_numtxpending(ah, i);
1339 if (npend)
1340 break;
1341 }
1342
1343 if (ah->external_reset &&
1344 (npend || type == ATH9K_RESET_COLD)) {
1345 int reset_err = 0;
1346
Joe Perchesd2182b62011-12-15 14:55:53 -08001347 ath_dbg(ath9k_hw_common(ah), RESET,
Gabor Juhos7d95847c2011-06-21 11:23:51 +02001348 "reset MAC via external reset\n");
1349
1350 reset_err = ah->external_reset();
1351 if (reset_err) {
1352 ath_err(ath9k_hw_common(ah),
1353 "External reset failed, err=%d\n",
1354 reset_err);
1355 return false;
1356 }
1357
1358 REG_WRITE(ah, AR_RTC_RESET, 1);
1359 }
1360 }
1361
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001362 REG_WRITE(ah, AR_RTC_RC, rst_flags);
Sujith7d0d0df2010-04-16 11:53:57 +05301363
1364 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301365
Sujithf1dc5602008-10-29 10:16:30 +05301366 udelay(50);
1367
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001368 REG_WRITE(ah, AR_RTC_RC, 0);
Sujith0caa7b12009-02-16 13:23:20 +05301369 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001370 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
Sujithf1dc5602008-10-29 10:16:30 +05301371 return false;
1372 }
1373
1374 if (!AR_SREV_9100(ah))
1375 REG_WRITE(ah, AR_RC, 0);
1376
Sujithf1dc5602008-10-29 10:16:30 +05301377 if (AR_SREV_9100(ah))
1378 udelay(50);
1379
1380 return true;
1381}
1382
Sujithcbe61d82009-02-09 13:27:12 +05301383static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301384{
Sujith7d0d0df2010-04-16 11:53:57 +05301385 ENABLE_REGWRITE_BUFFER(ah);
1386
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001387 if (AR_SREV_9300_20_OR_LATER(ah)) {
1388 REG_WRITE(ah, AR_WA, ah->WARegVal);
1389 udelay(10);
1390 }
1391
Sujithf1dc5602008-10-29 10:16:30 +05301392 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1393 AR_RTC_FORCE_WAKE_ON_INT);
1394
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001395 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301396 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1397
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001398 REG_WRITE(ah, AR_RTC_RESET, 0);
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301399
Sujith7d0d0df2010-04-16 11:53:57 +05301400 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301401
Senthil Balasubramanian84e21692010-04-15 17:38:30 -04001402 if (!AR_SREV_9300_20_OR_LATER(ah))
1403 udelay(2);
1404
1405 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301406 REG_WRITE(ah, AR_RC, 0);
1407
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001408 REG_WRITE(ah, AR_RTC_RESET, 1);
Sujithf1dc5602008-10-29 10:16:30 +05301409
1410 if (!ath9k_hw_wait(ah,
1411 AR_RTC_STATUS,
1412 AR_RTC_STATUS_M,
Sujith0caa7b12009-02-16 13:23:20 +05301413 AR_RTC_STATUS_ON,
1414 AH_WAIT_TIMEOUT)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001415 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
Sujithf1dc5602008-10-29 10:16:30 +05301416 return false;
1417 }
1418
Sujithf1dc5602008-10-29 10:16:30 +05301419 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1420}
1421
Sujithcbe61d82009-02-09 13:27:12 +05301422static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Sujithf1dc5602008-10-29 10:16:30 +05301423{
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301424 bool ret = false;
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301425
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001426 if (AR_SREV_9300_20_OR_LATER(ah)) {
1427 REG_WRITE(ah, AR_WA, ah->WARegVal);
1428 udelay(10);
1429 }
1430
Sujithf1dc5602008-10-29 10:16:30 +05301431 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1432 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1433
1434 switch (type) {
1435 case ATH9K_RESET_POWER_ON:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301436 ret = ath9k_hw_set_reset_power_on(ah);
1437 break;
Sujithf1dc5602008-10-29 10:16:30 +05301438 case ATH9K_RESET_WARM:
1439 case ATH9K_RESET_COLD:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301440 ret = ath9k_hw_set_reset(ah, type);
1441 break;
Sujithf1dc5602008-10-29 10:16:30 +05301442 default:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301443 break;
Sujithf1dc5602008-10-29 10:16:30 +05301444 }
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301445
1446 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1447 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1448
1449 return ret;
Sujithf1dc5602008-10-29 10:16:30 +05301450}
1451
Sujithcbe61d82009-02-09 13:27:12 +05301452static bool ath9k_hw_chip_reset(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301453 struct ath9k_channel *chan)
1454{
Felix Fietkau9c083af2012-03-03 15:17:02 +01001455 int reset_type = ATH9K_RESET_WARM;
1456
1457 if (AR_SREV_9280(ah)) {
1458 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1459 reset_type = ATH9K_RESET_POWER_ON;
1460 else
1461 reset_type = ATH9K_RESET_COLD;
1462 }
1463
1464 if (!ath9k_hw_set_reset_reg(ah, reset_type))
Sujithf1dc5602008-10-29 10:16:30 +05301465 return false;
1466
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001467 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05301468 return false;
1469
Sujith2660b812009-02-09 13:27:26 +05301470 ah->chip_fullsleep = false;
Sujithf1dc5602008-10-29 10:16:30 +05301471 ath9k_hw_init_pll(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301472 ath9k_hw_set_rfmode(ah, chan);
1473
1474 return true;
1475}
1476
Sujithcbe61d82009-02-09 13:27:12 +05301477static bool ath9k_hw_channel_change(struct ath_hw *ah,
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001478 struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301479{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001480 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001481 u32 qnum;
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001482 int r;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301483 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1484 bool band_switch, mode_diff;
1485 u8 ini_reloaded;
1486
1487 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1488 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1489 CHANNEL_5GHZ));
1490 mode_diff = (chan->chanmode != ah->curchan->chanmode);
Sujithf1dc5602008-10-29 10:16:30 +05301491
1492 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1493 if (ath9k_hw_numtxpending(ah, qnum)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001494 ath_dbg(common, QUEUE,
Joe Perches226afe62010-12-02 19:12:37 -08001495 "Transmit frames pending on queue %d\n", qnum);
Sujithf1dc5602008-10-29 10:16:30 +05301496 return false;
1497 }
1498 }
1499
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001500 if (!ath9k_hw_rfbus_req(ah)) {
Joe Perches38002762010-12-02 19:12:36 -08001501 ath_err(common, "Could not kill baseband RX\n");
Sujithf1dc5602008-10-29 10:16:30 +05301502 return false;
1503 }
1504
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301505 if (edma && (band_switch || mode_diff)) {
1506 ath9k_hw_mark_phy_inactive(ah);
1507 udelay(5);
1508
1509 ath9k_hw_init_pll(ah, NULL);
1510
1511 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1512 ath_err(common, "Failed to do fast channel change\n");
1513 return false;
1514 }
1515 }
1516
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001517 ath9k_hw_set_channel_regs(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301518
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001519 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001520 if (r) {
Joe Perches38002762010-12-02 19:12:36 -08001521 ath_err(common, "Failed to set channel\n");
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001522 return false;
Sujithf1dc5602008-10-29 10:16:30 +05301523 }
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001524 ath9k_hw_set_clockrate(ah);
Gabor Juhos64ea57d2012-04-15 20:38:05 +02001525 ath9k_hw_apply_txpower(ah, chan, false);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001526 ath9k_hw_rfbus_done(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301527
1528 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1529 ath9k_hw_set_delta_slope(ah, chan);
1530
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001531 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301532
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301533 if (edma && (band_switch || mode_diff)) {
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301534 ah->ah_flags |= AH_FASTCC;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301535 if (band_switch || ini_reloaded)
1536 ah->eep_ops->set_board_values(ah, chan);
1537
1538 ath9k_hw_init_bb(ah, chan);
1539
1540 if (band_switch || ini_reloaded)
1541 ath9k_hw_init_cal(ah, chan);
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301542 ah->ah_flags &= ~AH_FASTCC;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301543 }
1544
Sujithf1dc5602008-10-29 10:16:30 +05301545 return true;
1546}
1547
Felix Fietkau691680b2011-03-19 13:55:38 +01001548static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1549{
1550 u32 gpio_mask = ah->gpio_mask;
1551 int i;
1552
1553 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1554 if (!(gpio_mask & 1))
1555 continue;
1556
1557 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1558 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1559 }
1560}
1561
Rajkumar Manoharan01e18912012-03-15 05:34:27 +05301562static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1563 int *hang_state, int *hang_pos)
1564{
1565 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1566 u32 chain_state, dcs_pos, i;
1567
1568 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1569 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1570 for (i = 0; i < 3; i++) {
1571 if (chain_state == dcu_chain_state[i]) {
1572 *hang_state = chain_state;
1573 *hang_pos = dcs_pos;
1574 return true;
1575 }
1576 }
1577 }
1578 return false;
1579}
1580
1581#define DCU_COMPLETE_STATE 1
1582#define DCU_COMPLETE_STATE_MASK 0x3
1583#define NUM_STATUS_READS 50
1584static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1585{
1586 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1587 u32 i, hang_pos, hang_state, num_state = 6;
1588
1589 comp_state = REG_READ(ah, AR_DMADBG_6);
1590
1591 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1592 ath_dbg(ath9k_hw_common(ah), RESET,
1593 "MAC Hang signature not found at DCU complete\n");
1594 return false;
1595 }
1596
1597 chain_state = REG_READ(ah, dcs_reg);
1598 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1599 goto hang_check_iter;
1600
1601 dcs_reg = AR_DMADBG_5;
1602 num_state = 4;
1603 chain_state = REG_READ(ah, dcs_reg);
1604 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1605 goto hang_check_iter;
1606
1607 ath_dbg(ath9k_hw_common(ah), RESET,
1608 "MAC Hang signature 1 not found\n");
1609 return false;
1610
1611hang_check_iter:
1612 ath_dbg(ath9k_hw_common(ah), RESET,
1613 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1614 chain_state, comp_state, hang_state, hang_pos);
1615
1616 for (i = 0; i < NUM_STATUS_READS; i++) {
1617 chain_state = REG_READ(ah, dcs_reg);
1618 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1619 comp_state = REG_READ(ah, AR_DMADBG_6);
1620
1621 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1622 DCU_COMPLETE_STATE) ||
1623 (chain_state != hang_state))
1624 return false;
1625 }
1626
1627 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1628
1629 return true;
1630}
1631
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001632bool ath9k_hw_check_alive(struct ath_hw *ah)
Johannes Berg3b319aa2009-06-13 14:50:26 +05301633{
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001634 int count = 50;
1635 u32 reg;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301636
Rajkumar Manoharan01e18912012-03-15 05:34:27 +05301637 if (AR_SREV_9300(ah))
1638 return !ath9k_hw_detect_mac_hang(ah);
1639
Felix Fietkaue17f83e2010-09-22 12:34:53 +02001640 if (AR_SREV_9285_12_OR_LATER(ah))
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001641 return true;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301642
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001643 do {
1644 reg = REG_READ(ah, AR_OBS_BUS_1);
1645
1646 if ((reg & 0x7E7FFFEF) == 0x00702400)
1647 continue;
1648
1649 switch (reg & 0x7E000B00) {
1650 case 0x1E000000:
1651 case 0x52000B00:
1652 case 0x18000B00:
1653 continue;
1654 default:
1655 return true;
1656 }
1657 } while (count-- > 0);
1658
1659 return false;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301660}
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001661EXPORT_SYMBOL(ath9k_hw_check_alive);
Johannes Berg3b319aa2009-06-13 14:50:26 +05301662
Sujith Manoharancaed6572012-03-14 14:40:46 +05301663/*
1664 * Fast channel change:
1665 * (Change synthesizer based on channel freq without resetting chip)
1666 *
1667 * Don't do FCC when
1668 * - Flag is not set
1669 * - Chip is just coming out of full sleep
1670 * - Channel to be set is same as current channel
1671 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1672 */
1673static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1674{
1675 struct ath_common *common = ath9k_hw_common(ah);
1676 int ret;
1677
1678 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1679 goto fail;
1680
1681 if (ah->chip_fullsleep)
1682 goto fail;
1683
1684 if (!ah->curchan)
1685 goto fail;
1686
1687 if (chan->channel == ah->curchan->channel)
1688 goto fail;
1689
Felix Fietkaufeb7bc92012-04-19 21:18:28 +02001690 if ((ah->curchan->channelFlags | chan->channelFlags) &
1691 (CHANNEL_HALF | CHANNEL_QUARTER))
1692 goto fail;
1693
Sujith Manoharancaed6572012-03-14 14:40:46 +05301694 if ((chan->channelFlags & CHANNEL_ALL) !=
1695 (ah->curchan->channelFlags & CHANNEL_ALL))
1696 goto fail;
1697
1698 if (!ath9k_hw_check_alive(ah))
1699 goto fail;
1700
1701 /*
1702 * For AR9462, make sure that calibration data for
1703 * re-using are present.
1704 */
Sujith Manoharan8a905552012-05-04 13:23:59 +05301705 if (AR_SREV_9462(ah) && (ah->caldata &&
1706 (!ah->caldata->done_txiqcal_once ||
1707 !ah->caldata->done_txclcal_once ||
1708 !ah->caldata->rtt_done)))
Sujith Manoharancaed6572012-03-14 14:40:46 +05301709 goto fail;
1710
1711 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1712 ah->curchan->channel, chan->channel);
1713
1714 ret = ath9k_hw_channel_change(ah, chan);
1715 if (!ret)
1716 goto fail;
1717
1718 ath9k_hw_loadnf(ah, ah->curchan);
1719 ath9k_hw_start_nfcal(ah, true);
1720
1721 if ((ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && ar9003_mci_is_ready(ah))
1722 ar9003_mci_2g5g_switch(ah, true);
1723
1724 if (AR_SREV_9271(ah))
1725 ar9002_hw_load_ani_reg(ah, chan);
1726
1727 return 0;
1728fail:
1729 return -EINVAL;
1730}
1731
Sujithcbe61d82009-02-09 13:27:12 +05301732int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
Sujith Manoharancaed6572012-03-14 14:40:46 +05301733 struct ath9k_hw_cal_data *caldata, bool fastcc)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001734{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001735 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001736 u32 saveLedState;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001737 u32 saveDefAntenna;
1738 u32 macStaId1;
Sujith46fe7822009-09-17 09:25:25 +05301739 u64 tsf = 0;
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001740 int i, r;
Sujith Manoharancaed6572012-03-14 14:40:46 +05301741 bool start_mci_reset = false;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301742 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1743 bool save_fullsleep = ah->chip_fullsleep;
1744
1745 if (mci) {
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301746 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1747 if (start_mci_reset)
1748 return 0;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301749 }
1750
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001751 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001752 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001753
Sujith Manoharancaed6572012-03-14 14:40:46 +05301754 if (ah->curchan && !ah->chip_fullsleep)
1755 ath9k_hw_getnf(ah, ah->curchan);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001756
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001757 ah->caldata = caldata;
1758 if (caldata &&
1759 (chan->channel != caldata->channel ||
1760 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1761 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1762 /* Operating channel changed, reset channel calibration data */
1763 memset(caldata, 0, sizeof(*caldata));
1764 ath9k_init_nfcal_hist_buffer(ah, chan);
1765 }
Felix Fietkauf23fba42011-07-28 14:08:56 +02001766 ah->noise = ath9k_hw_getchan_noise(ah, chan);
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001767
Sujith Manoharancaed6572012-03-14 14:40:46 +05301768 if (fastcc) {
1769 r = ath9k_hw_do_fastcc(ah, chan);
1770 if (!r)
1771 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001772 }
1773
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301774 if (mci)
1775 ar9003_mci_stop_bt(ah, save_fullsleep);
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301776
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001777 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1778 if (saveDefAntenna == 0)
1779 saveDefAntenna = 1;
1780
1781 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1782
Sujith46fe7822009-09-17 09:25:25 +05301783 /* For chips on which RTC reset is done, save TSF before it gets cleared */
Felix Fietkauf860d522010-06-30 02:07:48 +02001784 if (AR_SREV_9100(ah) ||
1785 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
Sujith46fe7822009-09-17 09:25:25 +05301786 tsf = ath9k_hw_gettsf64(ah);
1787
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001788 saveLedState = REG_READ(ah, AR_CFG_LED) &
1789 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1790 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1791
1792 ath9k_hw_mark_phy_inactive(ah);
1793
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -08001794 ah->paprd_table_write_done = false;
1795
Sujith05020d22010-03-17 14:25:23 +05301796 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001797 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1798 REG_WRITE(ah,
1799 AR9271_RESET_POWER_DOWN_CONTROL,
1800 AR9271_RADIO_RF_RST);
1801 udelay(50);
1802 }
1803
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001804 if (!ath9k_hw_chip_reset(ah, chan)) {
Joe Perches38002762010-12-02 19:12:36 -08001805 ath_err(common, "Chip reset failed\n");
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001806 return -EINVAL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001807 }
1808
Sujith05020d22010-03-17 14:25:23 +05301809 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001810 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1811 ah->htc_reset_init = false;
1812 REG_WRITE(ah,
1813 AR9271_RESET_POWER_DOWN_CONTROL,
1814 AR9271_GATE_MAC_CTL);
1815 udelay(50);
1816 }
1817
Sujith46fe7822009-09-17 09:25:25 +05301818 /* Restore TSF */
Felix Fietkauf860d522010-06-30 02:07:48 +02001819 if (tsf)
Sujith46fe7822009-09-17 09:25:25 +05301820 ath9k_hw_settsf64(ah, tsf);
1821
Felix Fietkau7a370812010-09-22 12:34:52 +02001822 if (AR_SREV_9280_20_OR_LATER(ah))
Vasanthakumar Thiagarajan369391d2009-01-21 19:24:13 +05301823 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001824
Sujithe9141f72010-06-01 15:14:10 +05301825 if (!AR_SREV_9300_20_OR_LATER(ah))
1826 ar9002_hw_enable_async_fifo(ah);
1827
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001828 r = ath9k_hw_process_ini(ah, chan);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001829 if (r)
1830 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001831
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301832 if (mci)
1833 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1834
Felix Fietkauf860d522010-06-30 02:07:48 +02001835 /*
1836 * Some AR91xx SoC devices frequently fail to accept TSF writes
1837 * right after the chip reset. When that happens, write a new
1838 * value after the initvals have been applied, with an offset
1839 * based on measured time difference
1840 */
1841 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1842 tsf += 1500;
1843 ath9k_hw_settsf64(ah, tsf);
1844 }
1845
Jouni Malinen0ced0e12009-01-08 13:32:13 +02001846 /* Setup MFP options for CCMP */
1847 if (AR_SREV_9280_20_OR_LATER(ah)) {
1848 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1849 * frames when constructing CCMP AAD. */
1850 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1851 0xc7ff);
1852 ah->sw_mgmt_crypto = false;
1853 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1854 /* Disable hardware crypto for management frames */
1855 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1856 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1857 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1858 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1859 ah->sw_mgmt_crypto = true;
1860 } else
1861 ah->sw_mgmt_crypto = true;
1862
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001863 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1864 ath9k_hw_set_delta_slope(ah, chan);
1865
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001866 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithd6509152009-03-13 08:56:05 +05301867 ah->eep_ops->set_board_values(ah, chan);
Luis R. Rodrigueza7765822009-10-19 02:33:45 -04001868
Sujith7d0d0df2010-04-16 11:53:57 +05301869 ENABLE_REGWRITE_BUFFER(ah);
1870
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001871 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1872 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001873 | macStaId1
1874 | AR_STA_ID1_RTS_USE_DEF
Sujith2660b812009-02-09 13:27:26 +05301875 | (ah->config.
Sujith60b67f52008-08-07 10:52:38 +05301876 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
Sujith2660b812009-02-09 13:27:26 +05301877 | ah->sta_id1_defaults);
Luis R. Rodriguez13b81552009-09-10 17:52:45 -07001878 ath_hw_setbssidmask(common);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001879 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
Luis R. Rodriguez3453ad82009-09-10 08:57:00 -07001880 ath9k_hw_write_associd(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001881 REG_WRITE(ah, AR_ISR, ~0);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001882 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1883
Sujith7d0d0df2010-04-16 11:53:57 +05301884 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301885
Sujith Manoharan00e00032011-01-26 21:59:05 +05301886 ath9k_hw_set_operating_mode(ah, ah->opmode);
1887
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001888 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001889 if (r)
1890 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001891
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001892 ath9k_hw_set_clockrate(ah);
1893
Sujith7d0d0df2010-04-16 11:53:57 +05301894 ENABLE_REGWRITE_BUFFER(ah);
1895
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001896 for (i = 0; i < AR_NUM_DCU; i++)
1897 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1898
Sujith7d0d0df2010-04-16 11:53:57 +05301899 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301900
Sujith2660b812009-02-09 13:27:26 +05301901 ah->intr_txqs = 0;
Felix Fietkauf4c607d2011-03-23 20:57:28 +01001902 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001903 ath9k_hw_resettxqueue(ah, i);
1904
Sujith2660b812009-02-09 13:27:26 +05301905 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -04001906 ath9k_hw_ani_cache_ini_regs(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001907 ath9k_hw_init_qos(ah);
1908
Sujith2660b812009-02-09 13:27:26 +05301909 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Felix Fietkau55821322010-12-17 00:57:01 +01001910 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
Johannes Berg3b319aa2009-06-13 14:50:26 +05301911
Felix Fietkau0005baf2010-01-15 02:33:40 +01001912 ath9k_hw_init_global_settings(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001913
Felix Fietkaufe2b6af2011-07-09 11:12:51 +07001914 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1915 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1916 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1917 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1918 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1919 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1920 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301921 }
1922
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001923 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001924
1925 ath9k_hw_set_dma(ah);
1926
1927 REG_WRITE(ah, AR_OBS, 8);
1928
Sujith0ce024c2009-12-14 14:57:00 +05301929 if (ah->config.rx_intr_mitigation) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001930 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1931 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1932 }
1933
Vasanthakumar Thiagarajan7f62a132010-04-15 17:39:19 -04001934 if (ah->config.tx_intr_mitigation) {
1935 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1936 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1937 }
1938
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001939 ath9k_hw_init_bb(ah, chan);
1940
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301941 if (caldata) {
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301942 caldata->done_txiqcal_once = false;
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301943 caldata->done_txclcal_once = false;
1944 }
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001945 if (!ath9k_hw_init_cal(ah, chan))
Joe Perches6badaaf2009-06-28 09:26:32 -07001946 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001947
Rajkumar Manoharan93348922011-10-25 16:47:36 +05301948 ath9k_hw_loadnf(ah, chan);
1949 ath9k_hw_start_nfcal(ah, true);
1950
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301951 if (mci && ar9003_mci_end_reset(ah, chan, caldata))
1952 return -EIO;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301953
Sujith7d0d0df2010-04-16 11:53:57 +05301954 ENABLE_REGWRITE_BUFFER(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001955
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001956 ath9k_hw_restore_chainmask(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001957 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1958
Sujith7d0d0df2010-04-16 11:53:57 +05301959 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301960
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001961 /*
1962 * For big endian systems turn on swapping for descriptors
1963 */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001964 if (AR_SREV_9100(ah)) {
1965 u32 mask;
1966 mask = REG_READ(ah, AR_CFG);
1967 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001968 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1969 mask);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001970 } else {
1971 mask =
1972 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1973 REG_WRITE(ah, AR_CFG, mask);
Joe Perchesd2182b62011-12-15 14:55:53 -08001974 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1975 REG_READ(ah, AR_CFG));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001976 }
1977 } else {
Sujithcbba8cd2010-06-02 15:53:31 +05301978 if (common->bus_ops->ath_bus_type == ATH_USB) {
1979 /* Configure AR9271 target WLAN */
1980 if (AR_SREV_9271(ah))
1981 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1982 else
1983 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1984 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001985#ifdef __BIG_ENDIAN
Gabor Juhos4033bda2011-06-21 11:23:35 +02001986 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
Vasanthakumar Thiagarajan2be7bfe2011-04-19 19:29:14 +05301987 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1988 else
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001989 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001990#endif
1991 }
1992
Sujith Manoharandbccdd12012-02-22 17:55:47 +05301993 if (ath9k_hw_btcoex_is_enabled(ah))
Vasanthakumar Thiagarajan42cc41e2009-08-26 21:08:45 +05301994 ath9k_hw_btcoex_enable(ah);
1995
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301996 if (mci)
1997 ar9003_mci_check_bt(ah);
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301998
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +05301999 if (AR_SREV_9300_20_OR_LATER(ah)) {
Luis R. Rodriguezaea702b2010-05-13 13:33:43 -04002000 ar9003_hw_bb_watchdog_config(ah);
Vasanthakumar Thiagarajand8903a52010-04-15 17:39:25 -04002001
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +05302002 ar9003_hw_disable_phy_restart(ah);
2003 }
2004
Felix Fietkau691680b2011-03-19 13:55:38 +01002005 ath9k_hw_apply_gpio_override(ah);
2006
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08002007 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002008}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002009EXPORT_SYMBOL(ath9k_hw_reset);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002010
Sujithf1dc5602008-10-29 10:16:30 +05302011/******************************/
2012/* Power Management (Chipset) */
2013/******************************/
2014
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04002015/*
2016 * Notify Power Mgt is disabled in self-generated frames.
2017 * If requested, force chip to sleep.
2018 */
Sujithcbe61d82009-02-09 13:27:12 +05302019static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
Sujithf1dc5602008-10-29 10:16:30 +05302020{
2021 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2022 if (setChip) {
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302023 if (AR_SREV_9462(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302024 REG_WRITE(ah, AR_TIMER_MODE,
2025 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
2026 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
2027 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
2028 REG_WRITE(ah, AR_SLP32_INC,
2029 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
2030 /* xxx Required for WLAN only case ? */
2031 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2032 udelay(100);
2033 }
2034
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04002035 /*
2036 * Clear the RTC force wake bit to allow the
2037 * mac to go to sleep.
2038 */
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302039 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2040
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302041 if (AR_SREV_9462(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302042 udelay(100);
2043
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04002044 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302045 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2046
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04002047 /* Shutdown chip. Active low */
Sujith Manoharanc91ec462012-02-22 12:40:03 +05302048 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302049 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2050 udelay(2);
2051 }
Sujithf1dc5602008-10-29 10:16:30 +05302052 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04002053
2054 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
Rafael J. Wysockia7322812011-11-26 23:37:43 +01002055 if (AR_SREV_9300_20_OR_LATER(ah))
2056 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002057}
2058
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04002059/*
2060 * Notify Power Management is enabled in self-generating
2061 * frames. If request, set power mode of chip to
2062 * auto/normal. Duration in units of 128us (1/8 TU).
2063 */
Sujithcbe61d82009-02-09 13:27:12 +05302064static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002065{
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302066 u32 val;
2067
Sujithf1dc5602008-10-29 10:16:30 +05302068 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2069 if (setChip) {
Sujith2660b812009-02-09 13:27:26 +05302070 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002071
Sujithf1dc5602008-10-29 10:16:30 +05302072 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04002073 /* Set WakeOnInterrupt bit; clear ForceWake bit */
Sujithf1dc5602008-10-29 10:16:30 +05302074 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2075 AR_RTC_FORCE_WAKE_ON_INT);
2076 } else {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302077
2078 /* When chip goes into network sleep, it could be waken
2079 * up by MCI_INT interrupt caused by BT's HW messages
2080 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2081 * rate (~100us). This will cause chip to leave and
2082 * re-enter network sleep mode frequently, which in
2083 * consequence will have WLAN MCI HW to generate lots of
2084 * SYS_WAKING and SYS_SLEEPING messages which will make
2085 * BT CPU to busy to process.
2086 */
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302087 if (AR_SREV_9462(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302088 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
2089 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
2090 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
2091 }
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04002092 /*
2093 * Clear the RTC force wake bit to allow the
2094 * mac to go to sleep.
2095 */
Sujithf1dc5602008-10-29 10:16:30 +05302096 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2097 AR_RTC_FORCE_WAKE_EN);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302098
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302099 if (AR_SREV_9462(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302100 udelay(30);
Sujithf1dc5602008-10-29 10:16:30 +05302101 }
2102 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04002103
2104 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2105 if (AR_SREV_9300_20_OR_LATER(ah))
2106 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Sujithf1dc5602008-10-29 10:16:30 +05302107}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002108
Sujithcbe61d82009-02-09 13:27:12 +05302109static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
Sujithf1dc5602008-10-29 10:16:30 +05302110{
2111 u32 val;
2112 int i;
2113
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04002114 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2115 if (AR_SREV_9300_20_OR_LATER(ah)) {
2116 REG_WRITE(ah, AR_WA, ah->WARegVal);
2117 udelay(10);
2118 }
2119
Sujithf1dc5602008-10-29 10:16:30 +05302120 if (setChip) {
2121 if ((REG_READ(ah, AR_RTC_STATUS) &
2122 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
Joe Perches23677ce2012-02-09 11:17:23 +00002123 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
Sujithf1dc5602008-10-29 10:16:30 +05302124 return false;
2125 }
Luis R. Rodrigueze0412282010-04-15 17:38:15 -04002126 if (!AR_SREV_9300_20_OR_LATER(ah))
2127 ath9k_hw_init_pll(ah, NULL);
Sujithf1dc5602008-10-29 10:16:30 +05302128 }
2129 if (AR_SREV_9100(ah))
2130 REG_SET_BIT(ah, AR_RTC_RESET,
2131 AR_RTC_RESET_EN);
2132
2133 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2134 AR_RTC_FORCE_WAKE_EN);
2135 udelay(50);
2136
2137 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2138 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2139 if (val == AR_RTC_STATUS_ON)
2140 break;
2141 udelay(50);
2142 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2143 AR_RTC_FORCE_WAKE_EN);
2144 }
2145 if (i == 0) {
Joe Perches38002762010-12-02 19:12:36 -08002146 ath_err(ath9k_hw_common(ah),
2147 "Failed to wakeup in %uus\n",
2148 POWER_UP_TIME / 20);
Sujithf1dc5602008-10-29 10:16:30 +05302149 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002150 }
2151 }
2152
Sujithf1dc5602008-10-29 10:16:30 +05302153 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2154
2155 return true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002156}
2157
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002158bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Sujithf1dc5602008-10-29 10:16:30 +05302159{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002160 struct ath_common *common = ath9k_hw_common(ah);
Sujithcbe61d82009-02-09 13:27:12 +05302161 int status = true, setChip = true;
Sujithf1dc5602008-10-29 10:16:30 +05302162 static const char *modes[] = {
2163 "AWAKE",
2164 "FULL-SLEEP",
2165 "NETWORK SLEEP",
2166 "UNDEFINED"
2167 };
Sujithf1dc5602008-10-29 10:16:30 +05302168
Gabor Juhoscbdec972009-07-24 17:27:22 +02002169 if (ah->power_mode == mode)
2170 return status;
2171
Joe Perchesd2182b62011-12-15 14:55:53 -08002172 ath_dbg(common, RESET, "%s -> %s\n",
Joe Perches226afe62010-12-02 19:12:37 -08002173 modes[ah->power_mode], modes[mode]);
Sujithf1dc5602008-10-29 10:16:30 +05302174
2175 switch (mode) {
2176 case ATH9K_PM_AWAKE:
2177 status = ath9k_hw_set_power_awake(ah, setChip);
Mohammed Shafi Shajakhan10109112011-11-30 10:41:24 +05302178
2179 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2180 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2181
Sujithf1dc5602008-10-29 10:16:30 +05302182 break;
2183 case ATH9K_PM_FULL_SLEEP:
Sujith Manoharand1ca8b82012-02-22 12:41:01 +05302184 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2185 ar9003_mci_set_full_sleep(ah);
Mohammed Shafi Shajakhan10109112011-11-30 10:41:24 +05302186
Sujithf1dc5602008-10-29 10:16:30 +05302187 ath9k_set_power_sleep(ah, setChip);
Sujith2660b812009-02-09 13:27:26 +05302188 ah->chip_fullsleep = true;
Sujithf1dc5602008-10-29 10:16:30 +05302189 break;
2190 case ATH9K_PM_NETWORK_SLEEP:
Mohammed Shafi Shajakhan10109112011-11-30 10:41:24 +05302191
2192 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2193 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2194
Sujithf1dc5602008-10-29 10:16:30 +05302195 ath9k_set_power_network_sleep(ah, setChip);
2196 break;
2197 default:
Joe Perches38002762010-12-02 19:12:36 -08002198 ath_err(common, "Unknown power mode %u\n", mode);
Sujithf1dc5602008-10-29 10:16:30 +05302199 return false;
2200 }
Sujith2660b812009-02-09 13:27:26 +05302201 ah->power_mode = mode;
Sujithf1dc5602008-10-29 10:16:30 +05302202
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08002203 /*
2204 * XXX: If this warning never comes up after a while then
2205 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2206 * ath9k_hw_setpower() return type void.
2207 */
Sujith Manoharan97dcec52010-12-20 08:02:42 +05302208
2209 if (!(ah->ah_flags & AH_UNPLUGGED))
2210 ATH_DBG_WARN_ON_ONCE(!status);
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08002211
Sujithf1dc5602008-10-29 10:16:30 +05302212 return status;
2213}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002214EXPORT_SYMBOL(ath9k_hw_setpower);
Sujithf1dc5602008-10-29 10:16:30 +05302215
Sujithf1dc5602008-10-29 10:16:30 +05302216/*******************/
2217/* Beacon Handling */
2218/*******************/
2219
Sujithcbe61d82009-02-09 13:27:12 +05302220void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002221{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002222 int flags = 0;
2223
Sujith7d0d0df2010-04-16 11:53:57 +05302224 ENABLE_REGWRITE_BUFFER(ah);
2225
Sujith2660b812009-02-09 13:27:26 +05302226 switch (ah->opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08002227 case NL80211_IFTYPE_ADHOC:
Pat Erley9cb54122009-03-20 22:59:59 -04002228 case NL80211_IFTYPE_MESH_POINT:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002229 REG_SET_BIT(ah, AR_TXCFG,
2230 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
Felix Fietkaudd347f22011-03-22 21:54:17 +01002231 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2232 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002233 flags |= AR_NDP_TIMER_EN;
Colin McCabed97809d2008-12-01 13:38:55 -08002234 case NL80211_IFTYPE_AP:
Felix Fietkaudd347f22011-03-22 21:54:17 +01002235 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2236 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2237 TU_TO_USEC(ah->config.dma_beacon_response_time));
2238 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2239 TU_TO_USEC(ah->config.sw_beacon_response_time));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002240 flags |=
2241 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2242 break;
Colin McCabed97809d2008-12-01 13:38:55 -08002243 default:
Joe Perchesd2182b62011-12-15 14:55:53 -08002244 ath_dbg(ath9k_hw_common(ah), BEACON,
2245 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
Colin McCabed97809d2008-12-01 13:38:55 -08002246 return;
2247 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002248 }
2249
Felix Fietkaudd347f22011-03-22 21:54:17 +01002250 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2251 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2252 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2253 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002254
Sujith7d0d0df2010-04-16 11:53:57 +05302255 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302256
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002257 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2258}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002259EXPORT_SYMBOL(ath9k_hw_beaconinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002260
Sujithcbe61d82009-02-09 13:27:12 +05302261void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05302262 const struct ath9k_beacon_state *bs)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002263{
2264 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
Sujith2660b812009-02-09 13:27:26 +05302265 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002266 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002267
Sujith7d0d0df2010-04-16 11:53:57 +05302268 ENABLE_REGWRITE_BUFFER(ah);
2269
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002270 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2271
2272 REG_WRITE(ah, AR_BEACON_PERIOD,
Rajkumar Manoharanf29f5c02011-05-20 17:52:11 +05302273 TU_TO_USEC(bs->bs_intval));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002274 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
Rajkumar Manoharanf29f5c02011-05-20 17:52:11 +05302275 TU_TO_USEC(bs->bs_intval));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002276
Sujith7d0d0df2010-04-16 11:53:57 +05302277 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302278
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002279 REG_RMW_FIELD(ah, AR_RSSI_THR,
2280 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2281
Rajkumar Manoharanf29f5c02011-05-20 17:52:11 +05302282 beaconintval = bs->bs_intval;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002283
2284 if (bs->bs_sleepduration > beaconintval)
2285 beaconintval = bs->bs_sleepduration;
2286
2287 dtimperiod = bs->bs_dtimperiod;
2288 if (bs->bs_sleepduration > dtimperiod)
2289 dtimperiod = bs->bs_sleepduration;
2290
2291 if (beaconintval == dtimperiod)
2292 nextTbtt = bs->bs_nextdtim;
2293 else
2294 nextTbtt = bs->bs_nexttbtt;
2295
Joe Perchesd2182b62011-12-15 14:55:53 -08002296 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2297 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2298 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2299 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002300
Sujith7d0d0df2010-04-16 11:53:57 +05302301 ENABLE_REGWRITE_BUFFER(ah);
2302
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002303 REG_WRITE(ah, AR_NEXT_DTIM,
2304 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2305 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2306
2307 REG_WRITE(ah, AR_SLEEP1,
2308 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2309 | AR_SLEEP1_ASSUME_DTIM);
2310
Sujith60b67f52008-08-07 10:52:38 +05302311 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002312 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2313 else
2314 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2315
2316 REG_WRITE(ah, AR_SLEEP2,
2317 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2318
2319 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2320 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2321
Sujith7d0d0df2010-04-16 11:53:57 +05302322 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302323
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002324 REG_SET_BIT(ah, AR_TIMER_MODE,
2325 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2326 AR_DTIM_TIMER_EN);
2327
Sujith4af9cf42009-02-12 10:06:47 +05302328 /* TSF Out of Range Threshold */
2329 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002330}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002331EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002332
Sujithf1dc5602008-10-29 10:16:30 +05302333/*******************/
2334/* HW Capabilities */
2335/*******************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002336
Felix Fietkau60540692011-07-19 08:46:44 +02002337static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2338{
2339 eeprom_chainmask &= chip_chainmask;
2340 if (eeprom_chainmask)
2341 return eeprom_chainmask;
2342 else
2343 return chip_chainmask;
2344}
2345
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002346/**
2347 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2348 * @ah: the atheros hardware data structure
2349 *
2350 * We enable DFS support upstream on chipsets which have passed a series
2351 * of tests. The testing requirements are going to be documented. Desired
2352 * test requirements are documented at:
2353 *
2354 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2355 *
2356 * Once a new chipset gets properly tested an individual commit can be used
2357 * to document the testing for DFS for that chipset.
2358 */
2359static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2360{
2361
2362 switch (ah->hw_version.macVersion) {
2363 /* AR9580 will likely be our first target to get testing on */
2364 case AR_SREV_VERSION_9580:
2365 default:
2366 return false;
2367 }
2368}
2369
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002370int ath9k_hw_fill_cap_info(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002371{
Sujith2660b812009-02-09 13:27:26 +05302372 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002373 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002374 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau60540692011-07-19 08:46:44 +02002375 unsigned int chip_chainmask;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002376
Sujith Manoharan0ff2b5c2011-04-20 11:00:34 +05302377 u16 eeval;
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08002378 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002379
Sujithf74df6f2009-02-09 13:27:24 +05302380 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002381 regulatory->current_rd = eeval;
Sujithf1dc5602008-10-29 10:16:30 +05302382
Sujith2660b812009-02-09 13:27:26 +05302383 if (ah->opmode != NL80211_IFTYPE_AP &&
Sujithd535a422009-02-09 13:27:06 +05302384 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002385 if (regulatory->current_rd == 0x64 ||
2386 regulatory->current_rd == 0x65)
2387 regulatory->current_rd += 5;
2388 else if (regulatory->current_rd == 0x41)
2389 regulatory->current_rd = 0x43;
Joe Perchesd2182b62011-12-15 14:55:53 -08002390 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2391 regulatory->current_rd);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002392 }
Sujithdc2222a2008-08-14 13:26:55 +05302393
Sujithf74df6f2009-02-09 13:27:24 +05302394 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002395 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
Joe Perches38002762010-12-02 19:12:36 -08002396 ath_err(common,
2397 "no band has been marked as supported in EEPROM\n");
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002398 return -EINVAL;
2399 }
2400
Felix Fietkaud4659912010-10-14 16:02:39 +02002401 if (eeval & AR5416_OPFLAGS_11A)
2402 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002403
Felix Fietkaud4659912010-10-14 16:02:39 +02002404 if (eeval & AR5416_OPFLAGS_11G)
2405 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
Sujithf1dc5602008-10-29 10:16:30 +05302406
Felix Fietkau60540692011-07-19 08:46:44 +02002407 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2408 chip_chainmask = 1;
Mohammed Shafi Shajakhanba5736a2011-11-30 21:10:52 +05302409 else if (AR_SREV_9462(ah))
2410 chip_chainmask = 3;
Felix Fietkau60540692011-07-19 08:46:44 +02002411 else if (!AR_SREV_9280_20_OR_LATER(ah))
2412 chip_chainmask = 7;
2413 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2414 chip_chainmask = 3;
2415 else
2416 chip_chainmask = 7;
2417
Sujithf74df6f2009-02-09 13:27:24 +05302418 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002419 /*
2420 * For AR9271 we will temporarilly uses the rx chainmax as read from
2421 * the EEPROM.
2422 */
Sujith8147f5d2009-02-20 15:13:23 +05302423 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002424 !(eeval & AR5416_OPFLAGS_11A) &&
2425 !(AR_SREV_9271(ah)))
2426 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
Sujith8147f5d2009-02-20 15:13:23 +05302427 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
Felix Fietkau598cdd52011-03-19 13:55:42 +01002428 else if (AR_SREV_9100(ah))
2429 pCap->rx_chainmask = 0x7;
Sujith8147f5d2009-02-20 15:13:23 +05302430 else
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002431 /* Use rx_chainmask from EEPROM. */
Sujith8147f5d2009-02-20 15:13:23 +05302432 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05302433
Felix Fietkau60540692011-07-19 08:46:44 +02002434 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2435 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
Felix Fietkau82b2d332011-09-03 01:40:23 +02002436 ah->txchainmask = pCap->tx_chainmask;
2437 ah->rxchainmask = pCap->rx_chainmask;
Felix Fietkau60540692011-07-19 08:46:44 +02002438
Felix Fietkau7a370812010-09-22 12:34:52 +02002439 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
Sujithf1dc5602008-10-29 10:16:30 +05302440
Felix Fietkau02d2ebb2010-11-22 15:39:39 +01002441 /* enable key search for every frame in an aggregate */
2442 if (AR_SREV_9300_20_OR_LATER(ah))
2443 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2444
Bruno Randolfce2220d2010-09-17 11:36:25 +09002445 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2446
Felix Fietkau0db156e2011-03-23 20:57:29 +01002447 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
Sujithf1dc5602008-10-29 10:16:30 +05302448 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2449 else
2450 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2451
Sujith5b5fa352010-03-17 14:25:15 +05302452 if (AR_SREV_9271(ah))
2453 pCap->num_gpio_pins = AR9271_NUM_GPIO;
Sujith88c1f4f2010-06-30 14:46:31 +05302454 else if (AR_DEVID_7010(ah))
2455 pCap->num_gpio_pins = AR7010_NUM_GPIO;
Mohammed Shafi Shajakhan6321eb02011-09-30 11:31:27 +05302456 else if (AR_SREV_9300_20_OR_LATER(ah))
2457 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2458 else if (AR_SREV_9287_11_OR_LATER(ah))
2459 pCap->num_gpio_pins = AR9287_NUM_GPIO;
Felix Fietkaue17f83e2010-09-22 12:34:53 +02002460 else if (AR_SREV_9285_12_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302461 pCap->num_gpio_pins = AR9285_NUM_GPIO;
Felix Fietkau7a370812010-09-22 12:34:52 +02002462 else if (AR_SREV_9280_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302463 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2464 else
2465 pCap->num_gpio_pins = AR_NUM_GPIO;
2466
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +05302467 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302468 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +05302469 else
Sujithf1dc5602008-10-29 10:16:30 +05302470 pCap->rts_aggr_limit = (8 * 1024);
Sujithf1dc5602008-10-29 10:16:30 +05302471
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05302472#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Sujith2660b812009-02-09 13:27:26 +05302473 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2474 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2475 ah->rfkill_gpio =
2476 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2477 ah->rfkill_polarity =
2478 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
Sujithf1dc5602008-10-29 10:16:30 +05302479
2480 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2481 }
2482#endif
Vasanthakumar Thiagarajand5d11542010-05-17 18:57:56 -07002483 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
Vivek Natarajanbde748a2010-04-05 14:48:05 +05302484 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2485 else
2486 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
Sujithf1dc5602008-10-29 10:16:30 +05302487
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05302488 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302489 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2490 else
2491 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2492
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002493 if (AR_SREV_9300_20_OR_LATER(ah)) {
Vasanthakumar Thiagarajan784ad502010-12-06 04:27:40 -08002494 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
Gabor Juhos0e707a92011-06-21 11:23:31 +02002495 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
Vasanthakumar Thiagarajan784ad502010-12-06 04:27:40 -08002496 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2497
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002498 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2499 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2500 pCap->rx_status_len = sizeof(struct ar9003_rxs);
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04002501 pCap->tx_desc_len = sizeof(struct ar9003_txc);
Vasanthakumar Thiagarajan5088c2f2010-04-15 17:39:34 -04002502 pCap->txs_len = sizeof(struct ar9003_txs);
Luis R. Rodriguez6f481012011-01-20 17:47:39 -08002503 if (!ah->config.paprd_disable &&
2504 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
Felix Fietkau49352502010-06-12 00:33:59 -04002505 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04002506 } else {
2507 pCap->tx_desc_len = sizeof(struct ath_desc);
Felix Fietkaua949b172011-07-09 11:12:47 +07002508 if (AR_SREV_9280_20(ah))
Felix Fietkau6b42e8d2010-04-26 15:04:35 -04002509 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002510 }
Vasanthakumar Thiagarajan1adf02f2010-04-15 17:38:24 -04002511
Vasanthakumar Thiagarajan6c84ce02010-04-15 17:39:16 -04002512 if (AR_SREV_9300_20_OR_LATER(ah))
2513 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2514
Senthil Balasubramanian6ee63f52010-11-10 05:03:16 -08002515 if (AR_SREV_9300_20_OR_LATER(ah))
2516 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2517
Felix Fietkaua42acef2010-09-22 12:34:54 +02002518 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
Vasanthakumar Thiagarajan6473d242010-05-13 18:42:38 -07002519 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2520
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002521 if (AR_SREV_9285(ah))
2522 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2523 ant_div_ctl1 =
2524 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2525 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2526 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2527 }
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +05302528 if (AR_SREV_9300_20_OR_LATER(ah)) {
2529 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2530 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2531 }
2532
2533
Gabor Juhos431da562011-06-21 11:23:41 +02002534 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Mohammed Shafi Shajakhan21d2c632011-05-13 20:29:31 +05302535 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2536 /*
2537 * enable the diversity-combining algorithm only when
2538 * both enable_lna_div and enable_fast_div are set
2539 * Table for Diversity
2540 * ant_div_alt_lnaconf bit 0-1
2541 * ant_div_main_lnaconf bit 2-3
2542 * ant_div_alt_gaintb bit 4
2543 * ant_div_main_gaintb bit 5
2544 * enable_ant_div_lnadiv bit 6
2545 * enable_ant_fast_div bit 7
2546 */
2547 if ((ant_div_ctl1 >> 0x6) == 0x3)
2548 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2549 }
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002550
Vasanthakumar Thiagarajan8060e162010-12-06 04:27:42 -08002551 if (AR_SREV_9485_10(ah)) {
2552 pCap->pcie_lcr_extsync_en = true;
2553 pCap->pcie_lcr_offset = 0x80;
2554 }
2555
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002556 if (ath9k_hw_dfs_tested(ah))
2557 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2558
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08002559 tx_chainmask = pCap->tx_chainmask;
2560 rx_chainmask = pCap->rx_chainmask;
2561 while (tx_chainmask || rx_chainmask) {
2562 if (tx_chainmask & BIT(0))
2563 pCap->max_txchains++;
2564 if (rx_chainmask & BIT(0))
2565 pCap->max_rxchains++;
2566
2567 tx_chainmask >>= 1;
2568 rx_chainmask >>= 1;
2569 }
2570
Rajkumar Manoharan8ad74c42011-10-13 11:00:38 +05302571 if (AR_SREV_9300_20_OR_LATER(ah)) {
2572 ah->enabled_cals |= TX_IQ_CAL;
Mohammed Shafi Shajakhan6fea5932011-11-30 21:01:31 +05302573 if (AR_SREV_9485_OR_LATER(ah))
Rajkumar Manoharan8ad74c42011-10-13 11:00:38 +05302574 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2575 }
Mohammed Shafi Shajakhan3789d592012-03-09 12:01:55 +05302576
2577 if (AR_SREV_9462(ah)) {
2578
2579 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2580 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2581
2582 if (AR_SREV_9462_20(ah))
2583 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2584
2585 }
2586
Rajkumar Manoharan324c74a2011-10-13 11:00:41 +05302587
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002588 return 0;
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07002589}
2590
Sujithf1dc5602008-10-29 10:16:30 +05302591/****************************/
2592/* GPIO / RFKILL / Antennae */
2593/****************************/
2594
Sujithcbe61d82009-02-09 13:27:12 +05302595static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05302596 u32 gpio, u32 type)
2597{
2598 int addr;
2599 u32 gpio_shift, tmp;
2600
2601 if (gpio > 11)
2602 addr = AR_GPIO_OUTPUT_MUX3;
2603 else if (gpio > 5)
2604 addr = AR_GPIO_OUTPUT_MUX2;
2605 else
2606 addr = AR_GPIO_OUTPUT_MUX1;
2607
2608 gpio_shift = (gpio % 6) * 5;
2609
2610 if (AR_SREV_9280_20_OR_LATER(ah)
2611 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2612 REG_RMW(ah, addr, (type << gpio_shift),
2613 (0x1f << gpio_shift));
2614 } else {
2615 tmp = REG_READ(ah, addr);
2616 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2617 tmp &= ~(0x1f << gpio_shift);
2618 tmp |= (type << gpio_shift);
2619 REG_WRITE(ah, addr, tmp);
2620 }
2621}
2622
Sujithcbe61d82009-02-09 13:27:12 +05302623void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05302624{
2625 u32 gpio_shift;
2626
Luis R. Rodriguez9680e8a2009-09-13 23:28:00 -07002627 BUG_ON(gpio >= ah->caps.num_gpio_pins);
Sujithf1dc5602008-10-29 10:16:30 +05302628
Sujith88c1f4f2010-06-30 14:46:31 +05302629 if (AR_DEVID_7010(ah)) {
2630 gpio_shift = gpio;
2631 REG_RMW(ah, AR7010_GPIO_OE,
2632 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2633 (AR7010_GPIO_OE_MASK << gpio_shift));
2634 return;
2635 }
Sujithf1dc5602008-10-29 10:16:30 +05302636
Sujith88c1f4f2010-06-30 14:46:31 +05302637 gpio_shift = gpio << 1;
Sujithf1dc5602008-10-29 10:16:30 +05302638 REG_RMW(ah,
2639 AR_GPIO_OE_OUT,
2640 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2641 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2642}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002643EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
Sujithf1dc5602008-10-29 10:16:30 +05302644
Sujithcbe61d82009-02-09 13:27:12 +05302645u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05302646{
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302647#define MS_REG_READ(x, y) \
2648 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2649
Sujith2660b812009-02-09 13:27:26 +05302650 if (gpio >= ah->caps.num_gpio_pins)
Sujithf1dc5602008-10-29 10:16:30 +05302651 return 0xffffffff;
2652
Sujith88c1f4f2010-06-30 14:46:31 +05302653 if (AR_DEVID_7010(ah)) {
2654 u32 val;
2655 val = REG_READ(ah, AR7010_GPIO_IN);
2656 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2657 } else if (AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan93069902010-11-30 23:24:09 -08002658 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2659 AR_GPIO_BIT(gpio)) != 0;
Felix Fietkau783dfca2010-04-15 17:38:11 -04002660 else if (AR_SREV_9271(ah))
Sujith5b5fa352010-03-17 14:25:15 +05302661 return MS_REG_READ(AR9271, gpio) != 0;
Felix Fietkaua42acef2010-09-22 12:34:54 +02002662 else if (AR_SREV_9287_11_OR_LATER(ah))
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05302663 return MS_REG_READ(AR9287, gpio) != 0;
Felix Fietkaue17f83e2010-09-22 12:34:53 +02002664 else if (AR_SREV_9285_12_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302665 return MS_REG_READ(AR9285, gpio) != 0;
Felix Fietkau7a370812010-09-22 12:34:52 +02002666 else if (AR_SREV_9280_20_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302667 return MS_REG_READ(AR928X, gpio) != 0;
2668 else
2669 return MS_REG_READ(AR, gpio) != 0;
Sujithf1dc5602008-10-29 10:16:30 +05302670}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002671EXPORT_SYMBOL(ath9k_hw_gpio_get);
Sujithf1dc5602008-10-29 10:16:30 +05302672
Sujithcbe61d82009-02-09 13:27:12 +05302673void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
Sujithf1dc5602008-10-29 10:16:30 +05302674 u32 ah_signal_type)
2675{
2676 u32 gpio_shift;
2677
Sujith88c1f4f2010-06-30 14:46:31 +05302678 if (AR_DEVID_7010(ah)) {
2679 gpio_shift = gpio;
2680 REG_RMW(ah, AR7010_GPIO_OE,
2681 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2682 (AR7010_GPIO_OE_MASK << gpio_shift));
2683 return;
2684 }
2685
Sujithf1dc5602008-10-29 10:16:30 +05302686 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
Sujithf1dc5602008-10-29 10:16:30 +05302687 gpio_shift = 2 * gpio;
Sujithf1dc5602008-10-29 10:16:30 +05302688 REG_RMW(ah,
2689 AR_GPIO_OE_OUT,
2690 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2691 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2692}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002693EXPORT_SYMBOL(ath9k_hw_cfg_output);
Sujithf1dc5602008-10-29 10:16:30 +05302694
Sujithcbe61d82009-02-09 13:27:12 +05302695void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
Sujithf1dc5602008-10-29 10:16:30 +05302696{
Sujith88c1f4f2010-06-30 14:46:31 +05302697 if (AR_DEVID_7010(ah)) {
2698 val = val ? 0 : 1;
2699 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2700 AR_GPIO_BIT(gpio));
2701 return;
2702 }
2703
Sujith5b5fa352010-03-17 14:25:15 +05302704 if (AR_SREV_9271(ah))
2705 val = ~val;
2706
Sujithf1dc5602008-10-29 10:16:30 +05302707 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2708 AR_GPIO_BIT(gpio));
2709}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002710EXPORT_SYMBOL(ath9k_hw_set_gpio);
Sujithf1dc5602008-10-29 10:16:30 +05302711
Sujithcbe61d82009-02-09 13:27:12 +05302712void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
Sujithf1dc5602008-10-29 10:16:30 +05302713{
2714 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2715}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002716EXPORT_SYMBOL(ath9k_hw_setantenna);
Sujithf1dc5602008-10-29 10:16:30 +05302717
Sujithf1dc5602008-10-29 10:16:30 +05302718/*********************/
2719/* General Operation */
2720/*********************/
2721
Sujithcbe61d82009-02-09 13:27:12 +05302722u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302723{
2724 u32 bits = REG_READ(ah, AR_RX_FILTER);
2725 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2726
2727 if (phybits & AR_PHY_ERR_RADAR)
2728 bits |= ATH9K_RX_FILTER_PHYRADAR;
2729 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2730 bits |= ATH9K_RX_FILTER_PHYERR;
2731
2732 return bits;
2733}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002734EXPORT_SYMBOL(ath9k_hw_getrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302735
Sujithcbe61d82009-02-09 13:27:12 +05302736void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
Sujithf1dc5602008-10-29 10:16:30 +05302737{
2738 u32 phybits;
2739
Sujith7d0d0df2010-04-16 11:53:57 +05302740 ENABLE_REGWRITE_BUFFER(ah);
2741
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302742 if (AR_SREV_9462(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302743 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2744
Sujith7ea310b2009-09-03 12:08:43 +05302745 REG_WRITE(ah, AR_RX_FILTER, bits);
2746
Sujithf1dc5602008-10-29 10:16:30 +05302747 phybits = 0;
2748 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2749 phybits |= AR_PHY_ERR_RADAR;
2750 if (bits & ATH9K_RX_FILTER_PHYERR)
2751 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2752 REG_WRITE(ah, AR_PHY_ERR, phybits);
2753
2754 if (phybits)
Felix Fietkauca7a4de2011-03-23 20:57:26 +01002755 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
Sujithf1dc5602008-10-29 10:16:30 +05302756 else
Felix Fietkauca7a4de2011-03-23 20:57:26 +01002757 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
Sujith7d0d0df2010-04-16 11:53:57 +05302758
2759 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +05302760}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002761EXPORT_SYMBOL(ath9k_hw_setrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302762
Sujithcbe61d82009-02-09 13:27:12 +05302763bool ath9k_hw_phy_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302764{
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302765 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2766 return false;
2767
2768 ath9k_hw_init_pll(ah, NULL);
Felix Fietkau8efa7a82012-03-14 16:40:23 +01002769 ah->htc_reset_init = true;
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302770 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302771}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002772EXPORT_SYMBOL(ath9k_hw_phy_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302773
Sujithcbe61d82009-02-09 13:27:12 +05302774bool ath9k_hw_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302775{
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002776 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05302777 return false;
2778
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302779 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2780 return false;
2781
2782 ath9k_hw_init_pll(ah, NULL);
2783 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302784}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002785EXPORT_SYMBOL(ath9k_hw_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302786
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002787static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05302788{
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002789 enum eeprom_param gain_param;
Felix Fietkau9c204b42011-07-27 15:01:05 +02002790
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002791 if (IS_CHAN_2GHZ(chan))
2792 gain_param = EEP_ANTENNA_GAIN_2G;
2793 else
2794 gain_param = EEP_ANTENNA_GAIN_5G;
Sujithf1dc5602008-10-29 10:16:30 +05302795
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002796 return ah->eep_ops->get_eeprom(ah, gain_param);
2797}
2798
Gabor Juhos64ea57d2012-04-15 20:38:05 +02002799void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2800 bool test)
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002801{
2802 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2803 struct ieee80211_channel *channel;
2804 int chan_pwr, new_pwr, max_gain;
2805 int ant_gain, ant_reduction = 0;
2806
2807 if (!chan)
2808 return;
2809
2810 channel = chan->chan;
2811 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2812 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2813 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2814
2815 ant_gain = get_antenna_gain(ah, chan);
2816 if (ant_gain > max_gain)
2817 ant_reduction = ant_gain - max_gain;
Sujithf1dc5602008-10-29 10:16:30 +05302818
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07002819 ah->eep_ops->set_txpower(ah, chan,
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002820 ath9k_regd_get_ctl(reg, chan),
Gabor Juhos64ea57d2012-04-15 20:38:05 +02002821 ant_reduction, new_pwr, test);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002822}
2823
2824void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2825{
2826 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2827 struct ath9k_channel *chan = ah->curchan;
2828 struct ieee80211_channel *channel = chan->chan;
2829
Dan Carpenter48ef5c42011-10-17 10:28:23 +03002830 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002831 if (test)
2832 channel->max_power = MAX_RATE_POWER / 2;
2833
Gabor Juhos64ea57d2012-04-15 20:38:05 +02002834 ath9k_hw_apply_txpower(ah, chan, test);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002835
2836 if (test)
2837 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
Sujithf1dc5602008-10-29 10:16:30 +05302838}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002839EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
Sujithf1dc5602008-10-29 10:16:30 +05302840
Sujithcbe61d82009-02-09 13:27:12 +05302841void ath9k_hw_setopmode(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302842{
Sujith2660b812009-02-09 13:27:26 +05302843 ath9k_hw_set_operating_mode(ah, ah->opmode);
Sujithf1dc5602008-10-29 10:16:30 +05302844}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002845EXPORT_SYMBOL(ath9k_hw_setopmode);
Sujithf1dc5602008-10-29 10:16:30 +05302846
Sujithcbe61d82009-02-09 13:27:12 +05302847void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
Sujithf1dc5602008-10-29 10:16:30 +05302848{
2849 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2850 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2851}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002852EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302853
Luis R. Rodriguezf2b21432009-09-10 08:50:20 -07002854void ath9k_hw_write_associd(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302855{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07002856 struct ath_common *common = ath9k_hw_common(ah);
2857
2858 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2859 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2860 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
Sujithf1dc5602008-10-29 10:16:30 +05302861}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002862EXPORT_SYMBOL(ath9k_hw_write_associd);
Sujithf1dc5602008-10-29 10:16:30 +05302863
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002864#define ATH9K_MAX_TSF_READ 10
2865
Sujithcbe61d82009-02-09 13:27:12 +05302866u64 ath9k_hw_gettsf64(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302867{
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002868 u32 tsf_lower, tsf_upper1, tsf_upper2;
2869 int i;
Sujithf1dc5602008-10-29 10:16:30 +05302870
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002871 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2872 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2873 tsf_lower = REG_READ(ah, AR_TSF_L32);
2874 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2875 if (tsf_upper2 == tsf_upper1)
2876 break;
2877 tsf_upper1 = tsf_upper2;
2878 }
Sujithf1dc5602008-10-29 10:16:30 +05302879
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002880 WARN_ON( i == ATH9K_MAX_TSF_READ );
2881
2882 return (((u64)tsf_upper1 << 32) | tsf_lower);
Sujithf1dc5602008-10-29 10:16:30 +05302883}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002884EXPORT_SYMBOL(ath9k_hw_gettsf64);
Sujithf1dc5602008-10-29 10:16:30 +05302885
Sujithcbe61d82009-02-09 13:27:12 +05302886void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002887{
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002888 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
Alina Friedrichsenb9a16192009-03-02 23:28:38 +01002889 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002890}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002891EXPORT_SYMBOL(ath9k_hw_settsf64);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002892
Sujithcbe61d82009-02-09 13:27:12 +05302893void ath9k_hw_reset_tsf(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302894{
Gabor Juhosf9b604f2009-06-21 00:02:15 +02002895 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2896 AH_TSF_WRITE_TIMEOUT))
Joe Perchesd2182b62011-12-15 14:55:53 -08002897 ath_dbg(ath9k_hw_common(ah), RESET,
Joe Perches226afe62010-12-02 19:12:37 -08002898 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
Gabor Juhosf9b604f2009-06-21 00:02:15 +02002899
Sujithf1dc5602008-10-29 10:16:30 +05302900 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002901}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002902EXPORT_SYMBOL(ath9k_hw_reset_tsf);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002903
Sujith54e4cec2009-08-07 09:45:09 +05302904void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002905{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002906 if (setting)
Sujith2660b812009-02-09 13:27:26 +05302907 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002908 else
Sujith2660b812009-02-09 13:27:26 +05302909 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002910}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002911EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002912
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002913void ath9k_hw_set11nmac2040(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002914{
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002915 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Sujithf1dc5602008-10-29 10:16:30 +05302916 u32 macmode;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002917
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002918 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
Sujithf1dc5602008-10-29 10:16:30 +05302919 macmode = AR_2040_JOINED_RX_CLEAR;
2920 else
2921 macmode = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002922
Sujithf1dc5602008-10-29 10:16:30 +05302923 REG_WRITE(ah, AR_2040_MODE, macmode);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002924}
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302925
2926/* HW Generic timers configuration */
2927
2928static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2929{
2930 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2931 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2932 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2933 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2934 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2935 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2936 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2937 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2938 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2939 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2940 AR_NDP2_TIMER_MODE, 0x0002},
2941 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2942 AR_NDP2_TIMER_MODE, 0x0004},
2943 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2944 AR_NDP2_TIMER_MODE, 0x0008},
2945 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2946 AR_NDP2_TIMER_MODE, 0x0010},
2947 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2948 AR_NDP2_TIMER_MODE, 0x0020},
2949 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2950 AR_NDP2_TIMER_MODE, 0x0040},
2951 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2952 AR_NDP2_TIMER_MODE, 0x0080}
2953};
2954
2955/* HW generic timer primitives */
2956
2957/* compute and clear index of rightmost 1 */
2958static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2959{
2960 u32 b;
2961
2962 b = *mask;
2963 b &= (0-b);
2964 *mask &= ~b;
2965 b *= debruijn32;
2966 b >>= 27;
2967
2968 return timer_table->gen_timer_index[b];
2969}
2970
Felix Fietkaudd347f22011-03-22 21:54:17 +01002971u32 ath9k_hw_gettsf32(struct ath_hw *ah)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302972{
2973 return REG_READ(ah, AR_TSF_L32);
2974}
Felix Fietkaudd347f22011-03-22 21:54:17 +01002975EXPORT_SYMBOL(ath9k_hw_gettsf32);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302976
2977struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2978 void (*trigger)(void *),
2979 void (*overflow)(void *),
2980 void *arg,
2981 u8 timer_index)
2982{
2983 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2984 struct ath_gen_timer *timer;
2985
2986 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2987
2988 if (timer == NULL) {
Joe Perches38002762010-12-02 19:12:36 -08002989 ath_err(ath9k_hw_common(ah),
2990 "Failed to allocate memory for hw timer[%d]\n",
2991 timer_index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302992 return NULL;
2993 }
2994
2995 /* allocate a hardware generic timer slot */
2996 timer_table->timers[timer_index] = timer;
2997 timer->index = timer_index;
2998 timer->trigger = trigger;
2999 timer->overflow = overflow;
3000 timer->arg = arg;
3001
3002 return timer;
3003}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003004EXPORT_SYMBOL(ath_gen_timer_alloc);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303005
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07003006void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3007 struct ath_gen_timer *timer,
Vasanthakumar Thiagarajan788f6872011-04-21 18:33:27 +05303008 u32 trig_timeout,
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07003009 u32 timer_period)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303010{
3011 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
Vasanthakumar Thiagarajan788f6872011-04-21 18:33:27 +05303012 u32 tsf, timer_next;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303013
3014 BUG_ON(!timer_period);
3015
3016 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3017
3018 tsf = ath9k_hw_gettsf32(ah);
3019
Vasanthakumar Thiagarajan788f6872011-04-21 18:33:27 +05303020 timer_next = tsf + trig_timeout;
3021
Joe Perchesd2182b62011-12-15 14:55:53 -08003022 ath_dbg(ath9k_hw_common(ah), HWTIMER,
Joe Perches226afe62010-12-02 19:12:37 -08003023 "current tsf %x period %x timer_next %x\n",
3024 tsf, timer_period, timer_next);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303025
3026 /*
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303027 * Program generic timer registers
3028 */
3029 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3030 timer_next);
3031 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3032 timer_period);
3033 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3034 gen_tmr_configuration[timer->index].mode_mask);
3035
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05303036 if (AR_SREV_9462(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05303037 /*
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05303038 * Starting from AR9462, each generic timer can select which tsf
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05303039 * to use. But we still follow the old rule, 0 - 7 use tsf and
3040 * 8 - 15 use tsf2.
3041 */
3042 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3043 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3044 (1 << timer->index));
3045 else
3046 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3047 (1 << timer->index));
3048 }
3049
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303050 /* Enable both trigger and thresh interrupt masks */
3051 REG_SET_BIT(ah, AR_IMR_S5,
3052 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3053 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303054}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003055EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303056
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07003057void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303058{
3059 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3060
3061 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3062 (timer->index >= ATH_MAX_GEN_TIMER)) {
3063 return;
3064 }
3065
3066 /* Clear generic timer enable bits. */
3067 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3068 gen_tmr_configuration[timer->index].mode_mask);
3069
3070 /* Disable both trigger and thresh interrupt masks */
3071 REG_CLR_BIT(ah, AR_IMR_S5,
3072 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3073 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3074
3075 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303076}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003077EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303078
3079void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3080{
3081 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3082
3083 /* free the hardware generic timer slot */
3084 timer_table->timers[timer->index] = NULL;
3085 kfree(timer);
3086}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003087EXPORT_SYMBOL(ath_gen_timer_free);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303088
3089/*
3090 * Generic Timer Interrupts handling
3091 */
3092void ath_gen_timer_isr(struct ath_hw *ah)
3093{
3094 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3095 struct ath_gen_timer *timer;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07003096 struct ath_common *common = ath9k_hw_common(ah);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303097 u32 trigger_mask, thresh_mask, index;
3098
3099 /* get hardware generic timer interrupt status */
3100 trigger_mask = ah->intr_gen_timer_trigger;
3101 thresh_mask = ah->intr_gen_timer_thresh;
3102 trigger_mask &= timer_table->timer_mask.val;
3103 thresh_mask &= timer_table->timer_mask.val;
3104
3105 trigger_mask &= ~thresh_mask;
3106
3107 while (thresh_mask) {
3108 index = rightmost_index(timer_table, &thresh_mask);
3109 timer = timer_table->timers[index];
3110 BUG_ON(!timer);
Joe Perchesd2182b62011-12-15 14:55:53 -08003111 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3112 index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303113 timer->overflow(timer->arg);
3114 }
3115
3116 while (trigger_mask) {
3117 index = rightmost_index(timer_table, &trigger_mask);
3118 timer = timer_table->timers[index];
3119 BUG_ON(!timer);
Joe Perchesd2182b62011-12-15 14:55:53 -08003120 ath_dbg(common, HWTIMER,
Joe Perches226afe62010-12-02 19:12:37 -08003121 "Gen timer[%d] trigger\n", index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303122 timer->trigger(timer->arg);
3123 }
3124}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003125EXPORT_SYMBOL(ath_gen_timer_isr);
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003126
Sujith05020d22010-03-17 14:25:23 +05303127/********/
3128/* HTC */
3129/********/
3130
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003131static struct {
3132 u32 version;
3133 const char * name;
3134} ath_mac_bb_names[] = {
3135 /* Devices with external radios */
3136 { AR_SREV_VERSION_5416_PCI, "5416" },
3137 { AR_SREV_VERSION_5416_PCIE, "5418" },
3138 { AR_SREV_VERSION_9100, "9100" },
3139 { AR_SREV_VERSION_9160, "9160" },
3140 /* Single-chip solutions */
3141 { AR_SREV_VERSION_9280, "9280" },
3142 { AR_SREV_VERSION_9285, "9285" },
Luis R. Rodriguez11158472009-10-27 12:59:35 -04003143 { AR_SREV_VERSION_9287, "9287" },
3144 { AR_SREV_VERSION_9271, "9271" },
Luis R. Rodriguezec839032010-04-15 17:39:20 -04003145 { AR_SREV_VERSION_9300, "9300" },
Gabor Juhos2c8e5932011-06-21 11:23:21 +02003146 { AR_SREV_VERSION_9330, "9330" },
Florian Fainelli397e5d52011-08-25 21:33:48 +02003147 { AR_SREV_VERSION_9340, "9340" },
Senthil Balasubramanian8f06ca22011-04-01 17:16:33 +05303148 { AR_SREV_VERSION_9485, "9485" },
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05303149 { AR_SREV_VERSION_9462, "9462" },
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003150};
3151
3152/* For devices with external radios */
3153static struct {
3154 u16 version;
3155 const char * name;
3156} ath_rf_names[] = {
3157 { 0, "5133" },
3158 { AR_RAD5133_SREV_MAJOR, "5133" },
3159 { AR_RAD5122_SREV_MAJOR, "5122" },
3160 { AR_RAD2133_SREV_MAJOR, "2133" },
3161 { AR_RAD2122_SREV_MAJOR, "2122" }
3162};
3163
3164/*
3165 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3166 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003167static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003168{
3169 int i;
3170
3171 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3172 if (ath_mac_bb_names[i].version == mac_bb_version) {
3173 return ath_mac_bb_names[i].name;
3174 }
3175 }
3176
3177 return "????";
3178}
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003179
3180/*
3181 * Return the RF name. "????" is returned if the RF is unknown.
3182 * Used for devices with external radios.
3183 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003184static const char *ath9k_hw_rf_name(u16 rf_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003185{
3186 int i;
3187
3188 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3189 if (ath_rf_names[i].version == rf_version) {
3190 return ath_rf_names[i].name;
3191 }
3192 }
3193
3194 return "????";
3195}
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003196
3197void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3198{
3199 int used;
3200
3201 /* chipsets >= AR9280 are single-chip */
Felix Fietkau7a370812010-09-22 12:34:52 +02003202 if (AR_SREV_9280_20_OR_LATER(ah)) {
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003203 used = snprintf(hw_name, len,
3204 "Atheros AR%s Rev:%x",
3205 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3206 ah->hw_version.macRev);
3207 }
3208 else {
3209 used = snprintf(hw_name, len,
3210 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3211 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3212 ah->hw_version.macRev,
3213 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3214 AR_RADIO_SREV_MAJOR)),
3215 ah->hw_version.phyRev);
3216 }
3217
3218 hw_name[used] = '\0';
3219}
3220EXPORT_SYMBOL(ath9k_hw_name);