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gerrit-public.fairphone.software / kernel / msm-5.4 / a1047777323cc5da8f59d738708f554937be3193 / . / drivers / gpu / drm / amd / amdgpu / si_dpm.c
blob: 374d92b96519bc942e88a054ff169efc9f7c1cb4 [file] [log] [blame]
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_pm.h"
27#include "amdgpu_dpm.h"
28#include "amdgpu_atombios.h"
29#include "si/sid.h"
30#include "r600_dpm.h"
31#include "si_dpm.h"
32#include "atom.h"
33#include "../include/pptable.h"
34#include <linux/math64.h>
35#include <linux/seq_file.h>
36#include <linux/firmware.h>
37
38#define MC_CG_ARB_FREQ_F0 0x0a
39#define MC_CG_ARB_FREQ_F1 0x0b
40#define MC_CG_ARB_FREQ_F2 0x0c
41#define MC_CG_ARB_FREQ_F3 0x0d
42
43#define SMC_RAM_END 0x20000
44
45#define SCLK_MIN_DEEPSLEEP_FREQ 1350
46
47
48/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
49#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
50#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
51#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
52#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
53#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
54#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
55
56#define BIOS_SCRATCH_4 0x5cd
57
58MODULE_FIRMWARE("radeon/tahiti_smc.bin");
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]59MODULE_FIRMWARE("radeon/tahiti_k_smc.bin");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]60MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]61MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]62MODULE_FIRMWARE("radeon/verde_smc.bin");
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]63MODULE_FIRMWARE("radeon/verde_k_smc.bin");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]64MODULE_FIRMWARE("radeon/oland_smc.bin");
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]65MODULE_FIRMWARE("radeon/oland_k_smc.bin");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]66MODULE_FIRMWARE("radeon/hainan_smc.bin");
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]67MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]68
69union power_info {
70 struct _ATOM_POWERPLAY_INFO info;
71 struct _ATOM_POWERPLAY_INFO_V2 info_2;
72 struct _ATOM_POWERPLAY_INFO_V3 info_3;
73 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
74 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
75 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
76 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
77 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
78};
79
80union fan_info {
81 struct _ATOM_PPLIB_FANTABLE fan;
82 struct _ATOM_PPLIB_FANTABLE2 fan2;
83 struct _ATOM_PPLIB_FANTABLE3 fan3;
84};
85
86union pplib_clock_info {
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]87 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
88 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
89 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
90 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
91 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]92};
93
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]94static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]95{
96 R600_UTC_DFLT_00,
97 R600_UTC_DFLT_01,
98 R600_UTC_DFLT_02,
99 R600_UTC_DFLT_03,
100 R600_UTC_DFLT_04,
101 R600_UTC_DFLT_05,
102 R600_UTC_DFLT_06,
103 R600_UTC_DFLT_07,
104 R600_UTC_DFLT_08,
105 R600_UTC_DFLT_09,
106 R600_UTC_DFLT_10,
107 R600_UTC_DFLT_11,
108 R600_UTC_DFLT_12,
109 R600_UTC_DFLT_13,
110 R600_UTC_DFLT_14,
111};
112
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]113static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]114{
115 R600_DTC_DFLT_00,
116 R600_DTC_DFLT_01,
117 R600_DTC_DFLT_02,
118 R600_DTC_DFLT_03,
119 R600_DTC_DFLT_04,
120 R600_DTC_DFLT_05,
121 R600_DTC_DFLT_06,
122 R600_DTC_DFLT_07,
123 R600_DTC_DFLT_08,
124 R600_DTC_DFLT_09,
125 R600_DTC_DFLT_10,
126 R600_DTC_DFLT_11,
127 R600_DTC_DFLT_12,
128 R600_DTC_DFLT_13,
129 R600_DTC_DFLT_14,
130};
131
132static const struct si_cac_config_reg cac_weights_tahiti[] =
133{
134 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
135 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
136 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
137 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
138 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
139 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
140 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
141 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
142 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
143 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
144 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
145 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
146 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
147 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
148 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
149 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
150 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
151 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
152 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
153 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
154 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
155 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
156 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
157 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
158 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
159 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
160 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
161 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
162 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
163 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
164 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
165 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
166 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
167 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
168 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
169 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
170 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
171 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
172 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
173 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
174 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
180 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
182 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
183 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
184 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
185 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
188 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
190 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
191 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
192 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
193 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
194 { 0xFFFFFFFF }
195};
196
197static const struct si_cac_config_reg lcac_tahiti[] =
198{
199 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
200 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
201 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
202 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
203 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
204 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
205 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
206 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
207 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
209 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
210 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
211 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
212 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
213 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
214 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
215 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
216 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
217 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
218 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
219 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
220 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
221 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
222 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
223 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
224 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
225 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
226 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
227 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
228 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
229 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
230 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
231 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
232 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
233 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
234 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
235 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
236 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
238 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
240 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
242 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
244 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
246 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
252 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
254 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
256 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
258 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
260 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
262 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
264 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
266 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
268 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
270 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
272 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
274 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
276 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
277 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
278 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
279 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
280 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
281 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
282 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
283 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
284 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
285 { 0xFFFFFFFF }
286
287};
288
289static const struct si_cac_config_reg cac_override_tahiti[] =
290{
291 { 0xFFFFFFFF }
292};
293
294static const struct si_powertune_data powertune_data_tahiti =
295{
296 ((1 << 16) | 27027),
297 6,
298 0,
299 4,
300 95,
301 {
302 0UL,
303 0UL,
304 4521550UL,
305 309631529UL,
306 -1270850L,
307 4513710L,
308 40
309 },
310 595000000UL,
311 12,
312 {
313 0,
314 0,
315 0,
316 0,
317 0,
318 0,
319 0,
320 0
321 },
322 true
323};
324
325static const struct si_dte_data dte_data_tahiti =
326{
327 { 1159409, 0, 0, 0, 0 },
328 { 777, 0, 0, 0, 0 },
329 2,
330 54000,
331 127000,
332 25,
333 2,
334 10,
335 13,
336 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
337 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
338 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
339 85,
340 false
341};
342
Tom St Denise5c53042016-09-06 12:07:21 -0400[diff] [blame]343#if 0
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]344static const struct si_dte_data dte_data_tahiti_le =
345{
346 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
347 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
348 0x5,
349 0xAFC8,
350 0x64,
351 0x32,
352 1,
353 0,
354 0x10,
355 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
356 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
357 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
358 85,
359 true
360};
Tom St Denise5c53042016-09-06 12:07:21 -0400[diff] [blame]361#endif
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]362
363static const struct si_dte_data dte_data_tahiti_pro =
364{
365 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
366 { 0x0, 0x0, 0x0, 0x0, 0x0 },
367 5,
368 45000,
369 100,
370 0xA,
371 1,
372 0,
373 0x10,
374 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
375 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
376 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
377 90,
378 true
379};
380
381static const struct si_dte_data dte_data_new_zealand =
382{
383 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
384 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
385 0x5,
386 0xAFC8,
387 0x69,
388 0x32,
389 1,
390 0,
391 0x10,
392 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
393 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
394 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
395 85,
396 true
397};
398
399static const struct si_dte_data dte_data_aruba_pro =
400{
401 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
402 { 0x0, 0x0, 0x0, 0x0, 0x0 },
403 5,
404 45000,
405 100,
406 0xA,
407 1,
408 0,
409 0x10,
410 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
411 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
412 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
413 90,
414 true
415};
416
417static const struct si_dte_data dte_data_malta =
418{
419 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
420 { 0x0, 0x0, 0x0, 0x0, 0x0 },
421 5,
422 45000,
423 100,
424 0xA,
425 1,
426 0,
427 0x10,
428 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
429 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
430 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
431 90,
432 true
433};
434
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]435static const struct si_cac_config_reg cac_weights_pitcairn[] =
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]436{
437 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
438 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
439 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
440 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
441 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
442 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
443 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
444 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
445 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
446 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
447 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
448 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
449 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
450 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
451 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
452 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
453 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
454 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
455 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
456 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
457 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
458 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
459 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
460 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
461 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
463 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
464 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
465 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
466 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
467 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
468 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
470 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
471 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
472 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
473 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
474 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
475 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
476 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
479 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
480 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
484 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
486 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
488 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
489 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
490 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
492 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
493 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
494 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
495 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
496 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498};
499
500static const struct si_cac_config_reg lcac_pitcairn[] =
501{
502 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
503 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
504 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
505 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
506 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
507 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
508 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
509 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
510 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
511 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
512 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
513 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
514 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
515 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
516 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
517 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
518 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
519 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
521 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
523 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
525 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
527 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
529 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
531 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
533 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
535 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
537 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
539 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
541 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
543 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
545 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
547 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
549 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
551 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
555 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
557 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
559 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
561 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
563 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
565 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
567 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
569 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
571 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
573 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
575 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
579 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
580 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
581 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
583 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
584 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
585 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
586 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
587 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
588 { 0xFFFFFFFF }
589};
590
591static const struct si_cac_config_reg cac_override_pitcairn[] =
592{
593 { 0xFFFFFFFF }
594};
595
596static const struct si_powertune_data powertune_data_pitcairn =
597{
598 ((1 << 16) | 27027),
599 5,
600 0,
601 6,
602 100,
603 {
604 51600000UL,
605 1800000UL,
606 7194395UL,
607 309631529UL,
608 -1270850L,
609 4513710L,
610 100
611 },
612 117830498UL,
613 12,
614 {
615 0,
616 0,
617 0,
618 0,
619 0,
620 0,
621 0,
622 0
623 },
624 true
625};
626
627static const struct si_dte_data dte_data_pitcairn =
628{
629 { 0, 0, 0, 0, 0 },
630 { 0, 0, 0, 0, 0 },
631 0,
632 0,
633 0,
634 0,
635 0,
636 0,
637 0,
638 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
639 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
640 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
641 0,
642 false
643};
644
645static const struct si_dte_data dte_data_curacao_xt =
646{
647 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
648 { 0x0, 0x0, 0x0, 0x0, 0x0 },
649 5,
650 45000,
651 100,
652 0xA,
653 1,
654 0,
655 0x10,
656 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
657 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
658 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
659 90,
660 true
661};
662
663static const struct si_dte_data dte_data_curacao_pro =
664{
665 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
666 { 0x0, 0x0, 0x0, 0x0, 0x0 },
667 5,
668 45000,
669 100,
670 0xA,
671 1,
672 0,
673 0x10,
674 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
675 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
676 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
677 90,
678 true
679};
680
681static const struct si_dte_data dte_data_neptune_xt =
682{
683 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
684 { 0x0, 0x0, 0x0, 0x0, 0x0 },
685 5,
686 45000,
687 100,
688 0xA,
689 1,
690 0,
691 0x10,
692 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
693 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
694 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
695 90,
696 true
697};
698
699static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
700{
701 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
702 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
703 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
704 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
705 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
706 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
707 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
708 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
709 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
710 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
711 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
712 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
713 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
714 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
716 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
717 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
718 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
719 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
720 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
721 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
722 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
723 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
724 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
725 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
726 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
727 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
728 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
729 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
730 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
731 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
732 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
733 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
734 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
735 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
736 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
737 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
738 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
739 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
740 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
741 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
742 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
743 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
746 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
747 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
748 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
749 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
750 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
751 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
752 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
753 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
754 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
755 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
756 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
757 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
758 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
759 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
760 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
761 { 0xFFFFFFFF }
762};
763
764static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
765{
766 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
767 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
768 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
769 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
770 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
771 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
772 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
773 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
774 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
775 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
776 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
777 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
778 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
779 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
781 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
782 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
783 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
784 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
785 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
786 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
787 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
788 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
789 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
790 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
791 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
792 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
793 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
794 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
795 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
796 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
797 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
798 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
799 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
800 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
801 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
802 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
803 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
804 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
805 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
806 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
807 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
808 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
811 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
812 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
813 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
814 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
815 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
816 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
817 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
818 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
819 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
820 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
821 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
822 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
823 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
824 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
825 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
826 { 0xFFFFFFFF }
827};
828
829static const struct si_cac_config_reg cac_weights_heathrow[] =
830{
831 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
832 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
833 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
834 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
835 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
836 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
837 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
838 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
839 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
840 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
841 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
842 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
843 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
844 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
846 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
847 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
848 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
849 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
850 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
851 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
852 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
853 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
854 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
855 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
856 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
857 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
858 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
859 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
860 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
861 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
862 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
863 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
864 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
865 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
866 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
867 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
868 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
869 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
870 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
871 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
872 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
873 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
876 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
877 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
878 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
879 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
880 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
881 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
882 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
883 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
884 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
885 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
886 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
887 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
888 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
889 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
890 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
891 { 0xFFFFFFFF }
892};
893
894static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
895{
896 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
897 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
898 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
899 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
900 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
901 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
902 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
903 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
904 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
905 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
906 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
907 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
908 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
909 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
911 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
912 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
913 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
914 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
915 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
916 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
917 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
918 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
919 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
920 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
921 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
922 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
923 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
924 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
925 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
926 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
927 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
928 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
929 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
930 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
931 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
932 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
933 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
934 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
935 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
936 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
937 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
938 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
939 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
940 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
941 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
942 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
943 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
944 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
945 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
946 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
947 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
948 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
949 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
950 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
951 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
952 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
953 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
954 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
955 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
956 { 0xFFFFFFFF }
957};
958
959static const struct si_cac_config_reg cac_weights_cape_verde[] =
960{
961 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
962 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
963 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
964 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
965 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
966 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
967 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
968 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
969 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
970 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
971 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
972 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
973 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
974 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
975 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
976 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
977 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
978 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
979 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
980 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
981 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
982 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
983 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
984 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
985 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
986 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
987 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
988 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
989 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
990 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
991 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
992 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
993 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
994 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
995 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
996 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
997 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
998 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
999 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1001 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1002 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1004 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1006 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1007 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1015 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1017 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1018 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1019 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1020 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1021 { 0xFFFFFFFF }
1022};
1023
1024static const struct si_cac_config_reg lcac_cape_verde[] =
1025{
1026 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1027 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1029 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1031 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1033 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1037 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1039 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1041 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1043 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1045 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1047 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1049 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1065 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1075 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1077 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1079 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080 { 0xFFFFFFFF }
1081};
1082
1083static const struct si_cac_config_reg cac_override_cape_verde[] =
1084{
1085 { 0xFFFFFFFF }
1086};
1087
1088static const struct si_powertune_data powertune_data_cape_verde =
1089{
1090 ((1 << 16) | 0x6993),
1091 5,
1092 0,
1093 7,
1094 105,
1095 {
1096 0UL,
1097 0UL,
1098 7194395UL,
1099 309631529UL,
1100 -1270850L,
1101 4513710L,
1102 100
1103 },
1104 117830498UL,
1105 12,
1106 {
1107 0,
1108 0,
1109 0,
1110 0,
1111 0,
1112 0,
1113 0,
1114 0
1115 },
1116 true
1117};
1118
1119static const struct si_dte_data dte_data_cape_verde =
1120{
1121 { 0, 0, 0, 0, 0 },
1122 { 0, 0, 0, 0, 0 },
1123 0,
1124 0,
1125 0,
1126 0,
1127 0,
1128 0,
1129 0,
1130 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1131 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133 0,
1134 false
1135};
1136
1137static const struct si_dte_data dte_data_venus_xtx =
1138{
1139 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1140 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1141 5,
1142 55000,
1143 0x69,
1144 0xA,
1145 1,
1146 0,
1147 0x3,
1148 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1149 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151 90,
1152 true
1153};
1154
1155static const struct si_dte_data dte_data_venus_xt =
1156{
1157 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1158 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1159 5,
1160 55000,
1161 0x69,
1162 0xA,
1163 1,
1164 0,
1165 0x3,
1166 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169 90,
1170 true
1171};
1172
1173static const struct si_dte_data dte_data_venus_pro =
1174{
1175 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1176 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1177 5,
1178 55000,
1179 0x69,
1180 0xA,
1181 1,
1182 0,
1183 0x3,
1184 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187 90,
1188 true
1189};
1190
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]1191static const struct si_cac_config_reg cac_weights_oland[] =
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1192{
1193 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1194 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1195 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1196 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1197 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1198 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1199 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1200 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1201 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1202 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1203 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1204 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1205 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1206 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1207 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1208 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1209 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1210 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1211 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1212 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1213 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1214 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1215 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1216 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1217 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1218 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1219 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1220 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1222 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1223 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1224 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1225 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1226 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1227 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1228 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1229 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1231 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1233 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1234 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1247 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1249 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1250 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1251 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1253 { 0xFFFFFFFF }
1254};
1255
1256static const struct si_cac_config_reg cac_weights_mars_pro[] =
1257{
1258 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1259 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1260 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1261 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1262 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1263 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1264 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1265 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1266 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1267 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1268 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1269 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1270 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1271 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1272 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1273 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1274 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1275 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1276 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1277 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1278 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1279 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1280 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1281 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1282 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1283 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1284 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1285 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1286 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1287 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1288 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1289 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1290 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1291 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1292 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1293 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1294 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1296 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1298 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1299 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1305 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1307 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1308 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1309 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1310 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1312 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1313 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1314 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1315 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1316 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1318 { 0xFFFFFFFF }
1319};
1320
1321static const struct si_cac_config_reg cac_weights_mars_xt[] =
1322{
1323 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1324 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1325 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1326 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1327 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1328 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1329 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1330 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1331 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1332 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1333 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1334 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1335 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1336 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1337 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1338 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1339 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1340 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1341 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1342 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1343 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1344 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1345 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1346 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1347 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1348 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1349 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1350 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1351 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1352 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1353 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1354 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1355 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1356 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1357 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1358 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1359 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1361 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1363 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1364 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1370 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1372 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1373 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1374 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1375 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1377 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1378 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1379 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1380 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1381 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1383 { 0xFFFFFFFF }
1384};
1385
1386static const struct si_cac_config_reg cac_weights_oland_pro[] =
1387{
1388 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1389 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1390 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1391 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1392 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1393 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1394 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1395 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1396 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1397 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1398 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1399 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1400 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1401 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1402 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1403 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1404 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1405 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1406 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1407 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1408 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1409 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1410 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1411 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1412 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1413 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1414 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1415 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1416 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1417 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1418 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1419 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1420 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1421 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1422 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1423 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1424 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1426 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1428 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1429 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1432 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1435 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1437 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1438 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1439 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1440 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1442 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1443 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1444 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1445 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1446 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1447 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1448 { 0xFFFFFFFF }
1449};
1450
1451static const struct si_cac_config_reg cac_weights_oland_xt[] =
1452{
1453 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1454 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1455 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1456 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1457 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1458 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1459 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1460 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1461 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1462 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1463 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1464 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1465 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1466 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1467 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1468 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1469 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1470 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1471 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1472 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1473 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1474 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1475 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1476 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1477 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1478 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1479 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1480 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1481 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1483 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1484 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1485 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1486 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1487 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1488 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1489 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1491 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1493 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1500 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1503 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1504 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1507 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1508 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1509 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1510 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1511 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1512 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1513 { 0xFFFFFFFF }
1514};
1515
1516static const struct si_cac_config_reg lcac_oland[] =
1517{
1518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1531 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1533 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0xFFFFFFFF }
1561};
1562
1563static const struct si_cac_config_reg lcac_mars_pro[] =
1564{
1565 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1566 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1570 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1572 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1574 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1576 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1578 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1580 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607 { 0xFFFFFFFF }
1608};
1609
1610static const struct si_cac_config_reg cac_override_oland[] =
1611{
1612 { 0xFFFFFFFF }
1613};
1614
1615static const struct si_powertune_data powertune_data_oland =
1616{
1617 ((1 << 16) | 0x6993),
1618 5,
1619 0,
1620 7,
1621 105,
1622 {
1623 0UL,
1624 0UL,
1625 7194395UL,
1626 309631529UL,
1627 -1270850L,
1628 4513710L,
1629 100
1630 },
1631 117830498UL,
1632 12,
1633 {
1634 0,
1635 0,
1636 0,
1637 0,
1638 0,
1639 0,
1640 0,
1641 0
1642 },
1643 true
1644};
1645
1646static const struct si_powertune_data powertune_data_mars_pro =
1647{
1648 ((1 << 16) | 0x6993),
1649 5,
1650 0,
1651 7,
1652 105,
1653 {
1654 0UL,
1655 0UL,
1656 7194395UL,
1657 309631529UL,
1658 -1270850L,
1659 4513710L,
1660 100
1661 },
1662 117830498UL,
1663 12,
1664 {
1665 0,
1666 0,
1667 0,
1668 0,
1669 0,
1670 0,
1671 0,
1672 0
1673 },
1674 true
1675};
1676
1677static const struct si_dte_data dte_data_oland =
1678{
1679 { 0, 0, 0, 0, 0 },
1680 { 0, 0, 0, 0, 0 },
1681 0,
1682 0,
1683 0,
1684 0,
1685 0,
1686 0,
1687 0,
1688 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1689 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691 0,
1692 false
1693};
1694
1695static const struct si_dte_data dte_data_mars_pro =
1696{
1697 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1698 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1699 5,
1700 55000,
1701 105,
1702 0xA,
1703 1,
1704 0,
1705 0x10,
1706 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1707 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1708 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1709 90,
1710 true
1711};
1712
1713static const struct si_dte_data dte_data_sun_xt =
1714{
1715 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1716 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1717 5,
1718 55000,
1719 105,
1720 0xA,
1721 1,
1722 0,
1723 0x10,
1724 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1725 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1726 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1727 90,
1728 true
1729};
1730
1731
1732static const struct si_cac_config_reg cac_weights_hainan[] =
1733{
1734 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1735 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1736 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1737 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1738 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1740 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1743 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1744 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1745 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1746 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1747 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1748 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1749 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1751 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1752 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1753 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1754 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1755 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1756 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1757 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1758 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1760 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1761 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1763 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1765 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1769 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1770 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1771 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1774 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1776 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1777 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1790 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1791 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1792 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1793 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1794 { 0xFFFFFFFF }
1795};
1796
1797static const struct si_powertune_data powertune_data_hainan =
1798{
1799 ((1 << 16) | 0x6993),
1800 5,
1801 0,
1802 9,
1803 105,
1804 {
1805 0UL,
1806 0UL,
1807 7194395UL,
1808 309631529UL,
1809 -1270850L,
1810 4513710L,
1811 100
1812 },
1813 117830498UL,
1814 12,
1815 {
1816 0,
1817 0,
1818 0,
1819 0,
1820 0,
1821 0,
1822 0,
1823 0
1824 },
1825 true
1826};
1827
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]1828static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1829static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1830static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1831static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1832
1833static int si_populate_voltage_value(struct amdgpu_device *adev,
1834 const struct atom_voltage_table *table,
1835 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1836static int si_get_std_voltage_value(struct amdgpu_device *adev,
1837 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1838 u16 *std_voltage);
1839static int si_write_smc_soft_register(struct amdgpu_device *adev,
1840 u16 reg_offset, u32 value);
1841static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1842 struct rv7xx_pl *pl,
1843 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1844static int si_calculate_sclk_params(struct amdgpu_device *adev,
1845 u32 engine_clock,
1846 SISLANDS_SMC_SCLK_VALUE *sclk);
1847
1848static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1849static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1850static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1851static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1852
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1853static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1854{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1855 struct si_power_info *pi = adev->pm.dpm.priv;
1856 return pi;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1857}
1858
1859static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1860 u16 v, s32 t, u32 ileakage, u32 *leakage)
1861{
1862 s64 kt, kv, leakage_w, i_leakage, vddc;
1863 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1864 s64 tmp;
1865
1866 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1867 vddc = div64_s64(drm_int2fixp(v), 1000);
1868 temperature = div64_s64(drm_int2fixp(t), 1000);
1869
1870 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1871 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1872 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1873 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1874 t_ref = drm_int2fixp(coeff->t_ref);
1875
1876 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1877 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1878 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1879 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1880
1881 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1882
1883 *leakage = drm_fixp2int(leakage_w * 1000);
1884}
1885
1886static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1887 const struct ni_leakage_coeffients *coeff,
1888 u16 v,
1889 s32 t,
1890 u32 i_leakage,
1891 u32 *leakage)
1892{
1893 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1894}
1895
1896static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1897 const u32 fixed_kt, u16 v,
1898 u32 ileakage, u32 *leakage)
1899{
1900 s64 kt, kv, leakage_w, i_leakage, vddc;
1901
1902 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1903 vddc = div64_s64(drm_int2fixp(v), 1000);
1904
1905 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1906 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1907 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1908
1909 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1910
1911 *leakage = drm_fixp2int(leakage_w * 1000);
1912}
1913
1914static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1915 const struct ni_leakage_coeffients *coeff,
1916 const u32 fixed_kt,
1917 u16 v,
1918 u32 i_leakage,
1919 u32 *leakage)
1920{
1921 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1922}
1923
1924
1925static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1926 struct si_dte_data *dte_data)
1927{
1928 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1929 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1930 u32 k = dte_data->k;
1931 u32 t_max = dte_data->max_t;
1932 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1933 u32 t_0 = dte_data->t0;
1934 u32 i;
1935
1936 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1937 dte_data->tdep_count = 3;
1938
1939 for (i = 0; i < k; i++) {
1940 dte_data->r[i] =
1941 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1942 (p_limit2 * (u32)100);
1943 }
1944
1945 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1946
1947 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1948 dte_data->tdep_r[i] = dte_data->r[4];
1949 }
1950 } else {
1951 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1952 }
1953}
1954
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]1955static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1956{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1957 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1958
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1959 return pi;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1960}
1961
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]1962static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1963{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1964 struct ni_power_info *pi = adev->pm.dpm.priv;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1965
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1966 return pi;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1967}
1968
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]1969static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1970{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1971 struct si_ps *ps = aps->ps_priv;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1972
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1973 return ps;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1974}
1975
1976static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1977{
1978 struct ni_power_info *ni_pi = ni_get_pi(adev);
1979 struct si_power_info *si_pi = si_get_pi(adev);
1980 bool update_dte_from_pl2 = false;
1981
1982 if (adev->asic_type == CHIP_TAHITI) {
1983 si_pi->cac_weights = cac_weights_tahiti;
1984 si_pi->lcac_config = lcac_tahiti;
1985 si_pi->cac_override = cac_override_tahiti;
1986 si_pi->powertune_data = &powertune_data_tahiti;
1987 si_pi->dte_data = dte_data_tahiti;
1988
1989 switch (adev->pdev->device) {
1990 case 0x6798:
1991 si_pi->dte_data.enable_dte_by_default = true;
1992 break;
1993 case 0x6799:
1994 si_pi->dte_data = dte_data_new_zealand;
1995 break;
1996 case 0x6790:
1997 case 0x6791:
1998 case 0x6792:
1999 case 0x679E:
2000 si_pi->dte_data = dte_data_aruba_pro;
2001 update_dte_from_pl2 = true;
2002 break;
2003 case 0x679B:
2004 si_pi->dte_data = dte_data_malta;
2005 update_dte_from_pl2 = true;
2006 break;
2007 case 0x679A:
2008 si_pi->dte_data = dte_data_tahiti_pro;
2009 update_dte_from_pl2 = true;
2010 break;
2011 default:
2012 if (si_pi->dte_data.enable_dte_by_default == true)
2013 DRM_ERROR("DTE is not enabled!\n");
2014 break;
2015 }
2016 } else if (adev->asic_type == CHIP_PITCAIRN) {
Tom St Denisc3d986452016-09-06 09:44:47 -0400[diff] [blame]2017 si_pi->cac_weights = cac_weights_pitcairn;
2018 si_pi->lcac_config = lcac_pitcairn;
2019 si_pi->cac_override = cac_override_pitcairn;
2020 si_pi->powertune_data = &powertune_data_pitcairn;
2021
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2022 switch (adev->pdev->device) {
2023 case 0x6810:
2024 case 0x6818:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2025 si_pi->dte_data = dte_data_curacao_xt;
2026 update_dte_from_pl2 = true;
2027 break;
2028 case 0x6819:
2029 case 0x6811:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2030 si_pi->dte_data = dte_data_curacao_pro;
2031 update_dte_from_pl2 = true;
2032 break;
2033 case 0x6800:
2034 case 0x6806:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2035 si_pi->dte_data = dte_data_neptune_xt;
2036 update_dte_from_pl2 = true;
2037 break;
2038 default:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2039 si_pi->dte_data = dte_data_pitcairn;
2040 break;
2041 }
2042 } else if (adev->asic_type == CHIP_VERDE) {
2043 si_pi->lcac_config = lcac_cape_verde;
2044 si_pi->cac_override = cac_override_cape_verde;
2045 si_pi->powertune_data = &powertune_data_cape_verde;
2046
2047 switch (adev->pdev->device) {
2048 case 0x683B:
2049 case 0x683F:
2050 case 0x6829:
2051 case 0x6835:
2052 si_pi->cac_weights = cac_weights_cape_verde_pro;
2053 si_pi->dte_data = dte_data_cape_verde;
2054 break;
2055 case 0x682C:
2056 si_pi->cac_weights = cac_weights_cape_verde_pro;
2057 si_pi->dte_data = dte_data_sun_xt;
2058 break;
2059 case 0x6825:
2060 case 0x6827:
2061 si_pi->cac_weights = cac_weights_heathrow;
2062 si_pi->dte_data = dte_data_cape_verde;
2063 break;
2064 case 0x6824:
2065 case 0x682D:
2066 si_pi->cac_weights = cac_weights_chelsea_xt;
2067 si_pi->dte_data = dte_data_cape_verde;
2068 break;
2069 case 0x682F:
2070 si_pi->cac_weights = cac_weights_chelsea_pro;
2071 si_pi->dte_data = dte_data_cape_verde;
2072 break;
2073 case 0x6820:
2074 si_pi->cac_weights = cac_weights_heathrow;
2075 si_pi->dte_data = dte_data_venus_xtx;
2076 break;
2077 case 0x6821:
2078 si_pi->cac_weights = cac_weights_heathrow;
2079 si_pi->dte_data = dte_data_venus_xt;
2080 break;
2081 case 0x6823:
2082 case 0x682B:
2083 case 0x6822:
2084 case 0x682A:
2085 si_pi->cac_weights = cac_weights_chelsea_pro;
2086 si_pi->dte_data = dte_data_venus_pro;
2087 break;
2088 default:
2089 si_pi->cac_weights = cac_weights_cape_verde;
2090 si_pi->dte_data = dte_data_cape_verde;
2091 break;
2092 }
2093 } else if (adev->asic_type == CHIP_OLAND) {
Tom St Denisc3d986452016-09-06 09:44:47 -0400[diff] [blame]2094 si_pi->lcac_config = lcac_mars_pro;
2095 si_pi->cac_override = cac_override_oland;
2096 si_pi->powertune_data = &powertune_data_mars_pro;
2097 si_pi->dte_data = dte_data_mars_pro;
2098
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2099 switch (adev->pdev->device) {
2100 case 0x6601:
2101 case 0x6621:
2102 case 0x6603:
2103 case 0x6605:
2104 si_pi->cac_weights = cac_weights_mars_pro;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2105 update_dte_from_pl2 = true;
2106 break;
2107 case 0x6600:
2108 case 0x6606:
2109 case 0x6620:
2110 case 0x6604:
2111 si_pi->cac_weights = cac_weights_mars_xt;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2112 update_dte_from_pl2 = true;
2113 break;
2114 case 0x6611:
2115 case 0x6613:
2116 case 0x6608:
2117 si_pi->cac_weights = cac_weights_oland_pro;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2118 update_dte_from_pl2 = true;
2119 break;
2120 case 0x6610:
2121 si_pi->cac_weights = cac_weights_oland_xt;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2122 update_dte_from_pl2 = true;
2123 break;
2124 default:
2125 si_pi->cac_weights = cac_weights_oland;
2126 si_pi->lcac_config = lcac_oland;
2127 si_pi->cac_override = cac_override_oland;
2128 si_pi->powertune_data = &powertune_data_oland;
2129 si_pi->dte_data = dte_data_oland;
2130 break;
2131 }
2132 } else if (adev->asic_type == CHIP_HAINAN) {
2133 si_pi->cac_weights = cac_weights_hainan;
2134 si_pi->lcac_config = lcac_oland;
2135 si_pi->cac_override = cac_override_oland;
2136 si_pi->powertune_data = &powertune_data_hainan;
2137 si_pi->dte_data = dte_data_sun_xt;
2138 update_dte_from_pl2 = true;
2139 } else {
2140 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2141 return;
2142 }
2143
2144 ni_pi->enable_power_containment = false;
2145 ni_pi->enable_cac = false;
2146 ni_pi->enable_sq_ramping = false;
2147 si_pi->enable_dte = false;
2148
2149 if (si_pi->powertune_data->enable_powertune_by_default) {
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]2150 ni_pi->enable_power_containment = true;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2151 ni_pi->enable_cac = true;
2152 if (si_pi->dte_data.enable_dte_by_default) {
2153 si_pi->enable_dte = true;
2154 if (update_dte_from_pl2)
2155 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2156
2157 }
2158 ni_pi->enable_sq_ramping = true;
2159 }
2160
2161 ni_pi->driver_calculate_cac_leakage = true;
2162 ni_pi->cac_configuration_required = true;
2163
2164 if (ni_pi->cac_configuration_required) {
2165 ni_pi->support_cac_long_term_average = true;
2166 si_pi->dyn_powertune_data.l2_lta_window_size =
2167 si_pi->powertune_data->l2_lta_window_size_default;
2168 si_pi->dyn_powertune_data.lts_truncate =
2169 si_pi->powertune_data->lts_truncate_default;
2170 } else {
2171 ni_pi->support_cac_long_term_average = false;
2172 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2173 si_pi->dyn_powertune_data.lts_truncate = 0;
2174 }
2175
2176 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2177}
2178
2179static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2180{
2181 return 1;
2182}
2183
2184static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2185{
2186 u32 xclk;
2187 u32 wintime;
2188 u32 cac_window;
2189 u32 cac_window_size;
2190
2191 xclk = amdgpu_asic_get_xclk(adev);
2192
2193 if (xclk == 0)
2194 return 0;
2195
2196 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2197 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2198
2199 wintime = (cac_window_size * 100) / xclk;
2200
2201 return wintime;
2202}
2203
2204static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2205{
2206 return power_in_watts;
2207}
2208
2209static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2210 bool adjust_polarity,
2211 u32 tdp_adjustment,
2212 u32 *tdp_limit,
2213 u32 *near_tdp_limit)
2214{
2215 u32 adjustment_delta, max_tdp_limit;
2216
2217 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2218 return -EINVAL;
2219
2220 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2221
2222 if (adjust_polarity) {
2223 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2224 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2225 } else {
2226 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2227 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2228 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2229 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2230 else
2231 *near_tdp_limit = 0;
2232 }
2233
2234 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2235 return -EINVAL;
2236 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2237 return -EINVAL;
2238
2239 return 0;
2240}
2241
2242static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2243 struct amdgpu_ps *amdgpu_state)
2244{
2245 struct ni_power_info *ni_pi = ni_get_pi(adev);
2246 struct si_power_info *si_pi = si_get_pi(adev);
2247
2248 if (ni_pi->enable_power_containment) {
2249 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2250 PP_SIslands_PAPMParameters *papm_parm;
2251 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2252 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2253 u32 tdp_limit;
2254 u32 near_tdp_limit;
2255 int ret;
2256
2257 if (scaling_factor == 0)
2258 return -EINVAL;
2259
2260 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2261
2262 ret = si_calculate_adjusted_tdp_limits(adev,
2263 false, /* ??? */
2264 adev->pm.dpm.tdp_adjustment,
2265 &tdp_limit,
2266 &near_tdp_limit);
2267 if (ret)
2268 return ret;
2269
2270 smc_table->dpm2Params.TDPLimit =
2271 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2272 smc_table->dpm2Params.NearTDPLimit =
2273 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2274 smc_table->dpm2Params.SafePowerLimit =
2275 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2276
2277 ret = si_copy_bytes_to_smc(adev,
2278 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2279 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2280 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2281 sizeof(u32) * 3,
2282 si_pi->sram_end);
2283 if (ret)
2284 return ret;
2285
2286 if (si_pi->enable_ppm) {
2287 papm_parm = &si_pi->papm_parm;
2288 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2289 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2290 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2291 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2292 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2293 papm_parm->PlatformPowerLimit = 0xffffffff;
2294 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2295
2296 ret = si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2297 (u8 *)papm_parm,
2298 sizeof(PP_SIslands_PAPMParameters),
2299 si_pi->sram_end);
2300 if (ret)
2301 return ret;
2302 }
2303 }
2304 return 0;
2305}
2306
2307static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2308 struct amdgpu_ps *amdgpu_state)
2309{
2310 struct ni_power_info *ni_pi = ni_get_pi(adev);
2311 struct si_power_info *si_pi = si_get_pi(adev);
2312
2313 if (ni_pi->enable_power_containment) {
2314 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2315 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2316 int ret;
2317
2318 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2319
2320 smc_table->dpm2Params.NearTDPLimit =
2321 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2322 smc_table->dpm2Params.SafePowerLimit =
2323 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2324
2325 ret = si_copy_bytes_to_smc(adev,
2326 (si_pi->state_table_start +
2327 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2328 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2329 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2330 sizeof(u32) * 2,
2331 si_pi->sram_end);
2332 if (ret)
2333 return ret;
2334 }
2335
2336 return 0;
2337}
2338
2339static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2340 const u16 prev_std_vddc,
2341 const u16 curr_std_vddc)
2342{
2343 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2344 u64 prev_vddc = (u64)prev_std_vddc;
2345 u64 curr_vddc = (u64)curr_std_vddc;
2346 u64 pwr_efficiency_ratio, n, d;
2347
2348 if ((prev_vddc == 0) || (curr_vddc == 0))
2349 return 0;
2350
2351 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2352 d = prev_vddc * prev_vddc;
2353 pwr_efficiency_ratio = div64_u64(n, d);
2354
2355 if (pwr_efficiency_ratio > (u64)0xFFFF)
2356 return 0;
2357
2358 return (u16)pwr_efficiency_ratio;
2359}
2360
2361static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2362 struct amdgpu_ps *amdgpu_state)
2363{
2364 struct si_power_info *si_pi = si_get_pi(adev);
2365
2366 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2367 amdgpu_state->vclk && amdgpu_state->dclk)
2368 return true;
2369
2370 return false;
2371}
2372
2373struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2374{
2375 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2376
2377 return pi;
2378}
2379
2380static int si_populate_power_containment_values(struct amdgpu_device *adev,
2381 struct amdgpu_ps *amdgpu_state,
2382 SISLANDS_SMC_SWSTATE *smc_state)
2383{
2384 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2385 struct ni_power_info *ni_pi = ni_get_pi(adev);
2386 struct si_ps *state = si_get_ps(amdgpu_state);
2387 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2388 u32 prev_sclk;
2389 u32 max_sclk;
2390 u32 min_sclk;
2391 u16 prev_std_vddc;
2392 u16 curr_std_vddc;
2393 int i;
2394 u16 pwr_efficiency_ratio;
2395 u8 max_ps_percent;
2396 bool disable_uvd_power_tune;
2397 int ret;
2398
2399 if (ni_pi->enable_power_containment == false)
2400 return 0;
2401
2402 if (state->performance_level_count == 0)
2403 return -EINVAL;
2404
2405 if (smc_state->levelCount != state->performance_level_count)
2406 return -EINVAL;
2407
2408 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2409
2410 smc_state->levels[0].dpm2.MaxPS = 0;
2411 smc_state->levels[0].dpm2.NearTDPDec = 0;
2412 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2413 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2414 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2415
2416 for (i = 1; i < state->performance_level_count; i++) {
2417 prev_sclk = state->performance_levels[i-1].sclk;
2418 max_sclk = state->performance_levels[i].sclk;
2419 if (i == 1)
2420 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2421 else
2422 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2423
2424 if (prev_sclk > max_sclk)
2425 return -EINVAL;
2426
2427 if ((max_ps_percent == 0) ||
2428 (prev_sclk == max_sclk) ||
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]2429 disable_uvd_power_tune)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2430 min_sclk = max_sclk;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]2431 else if (i == 1)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2432 min_sclk = prev_sclk;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]2433 else
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2434 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2435
2436 if (min_sclk < state->performance_levels[0].sclk)
2437 min_sclk = state->performance_levels[0].sclk;
2438
2439 if (min_sclk == 0)
2440 return -EINVAL;
2441
2442 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2443 state->performance_levels[i-1].vddc, &vddc);
2444 if (ret)
2445 return ret;
2446
2447 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2448 if (ret)
2449 return ret;
2450
2451 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2452 state->performance_levels[i].vddc, &vddc);
2453 if (ret)
2454 return ret;
2455
2456 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2457 if (ret)
2458 return ret;
2459
2460 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2461 prev_std_vddc, curr_std_vddc);
2462
2463 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2464 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2465 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2466 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2467 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2468 }
2469
2470 return 0;
2471}
2472
2473static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2474 struct amdgpu_ps *amdgpu_state,
2475 SISLANDS_SMC_SWSTATE *smc_state)
2476{
2477 struct ni_power_info *ni_pi = ni_get_pi(adev);
2478 struct si_ps *state = si_get_ps(amdgpu_state);
2479 u32 sq_power_throttle, sq_power_throttle2;
2480 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2481 int i;
2482
2483 if (state->performance_level_count == 0)
2484 return -EINVAL;
2485
2486 if (smc_state->levelCount != state->performance_level_count)
2487 return -EINVAL;
2488
2489 if (adev->pm.dpm.sq_ramping_threshold == 0)
2490 return -EINVAL;
2491
2492 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2493 enable_sq_ramping = false;
2494
2495 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2496 enable_sq_ramping = false;
2497
2498 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2499 enable_sq_ramping = false;
2500
2501 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2502 enable_sq_ramping = false;
2503
2504 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2505 enable_sq_ramping = false;
2506
2507 for (i = 0; i < state->performance_level_count; i++) {
2508 sq_power_throttle = 0;
2509 sq_power_throttle2 = 0;
2510
2511 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2512 enable_sq_ramping) {
2513 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2514 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2515 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2516 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2517 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2518 } else {
2519 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2520 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2521 }
2522
2523 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2524 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2525 }
2526
2527 return 0;
2528}
2529
2530static int si_enable_power_containment(struct amdgpu_device *adev,
2531 struct amdgpu_ps *amdgpu_new_state,
2532 bool enable)
2533{
2534 struct ni_power_info *ni_pi = ni_get_pi(adev);
2535 PPSMC_Result smc_result;
2536 int ret = 0;
2537
2538 if (ni_pi->enable_power_containment) {
2539 if (enable) {
2540 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2541 smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2542 if (smc_result != PPSMC_Result_OK) {
2543 ret = -EINVAL;
2544 ni_pi->pc_enabled = false;
2545 } else {
2546 ni_pi->pc_enabled = true;
2547 }
2548 }
2549 } else {
2550 smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2551 if (smc_result != PPSMC_Result_OK)
2552 ret = -EINVAL;
2553 ni_pi->pc_enabled = false;
2554 }
2555 }
2556
2557 return ret;
2558}
2559
2560static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2561{
2562 struct si_power_info *si_pi = si_get_pi(adev);
2563 int ret = 0;
2564 struct si_dte_data *dte_data = &si_pi->dte_data;
2565 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2566 u32 table_size;
2567 u8 tdep_count;
2568 u32 i;
2569
2570 if (dte_data == NULL)
2571 si_pi->enable_dte = false;
2572
2573 if (si_pi->enable_dte == false)
2574 return 0;
2575
2576 if (dte_data->k <= 0)
2577 return -EINVAL;
2578
2579 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2580 if (dte_tables == NULL) {
2581 si_pi->enable_dte = false;
2582 return -ENOMEM;
2583 }
2584
2585 table_size = dte_data->k;
2586
2587 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2588 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2589
2590 tdep_count = dte_data->tdep_count;
2591 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2592 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2593
2594 dte_tables->K = cpu_to_be32(table_size);
2595 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2596 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2597 dte_tables->WindowSize = dte_data->window_size;
2598 dte_tables->temp_select = dte_data->temp_select;
2599 dte_tables->DTE_mode = dte_data->dte_mode;
2600 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2601
2602 if (tdep_count > 0)
2603 table_size--;
2604
2605 for (i = 0; i < table_size; i++) {
2606 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2607 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2608 }
2609
2610 dte_tables->Tdep_count = tdep_count;
2611
2612 for (i = 0; i < (u32)tdep_count; i++) {
2613 dte_tables->T_limits[i] = dte_data->t_limits[i];
2614 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2615 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2616 }
2617
2618 ret = si_copy_bytes_to_smc(adev, si_pi->dte_table_start, (u8 *)dte_tables,
2619 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2620 kfree(dte_tables);
2621
2622 return ret;
2623}
2624
2625static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2626 u16 *max, u16 *min)
2627{
2628 struct si_power_info *si_pi = si_get_pi(adev);
2629 struct amdgpu_cac_leakage_table *table =
2630 &adev->pm.dpm.dyn_state.cac_leakage_table;
2631 u32 i;
2632 u32 v0_loadline;
2633
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2634 if (table == NULL)
2635 return -EINVAL;
2636
2637 *max = 0;
2638 *min = 0xFFFF;
2639
2640 for (i = 0; i < table->count; i++) {
2641 if (table->entries[i].vddc > *max)
2642 *max = table->entries[i].vddc;
2643 if (table->entries[i].vddc < *min)
2644 *min = table->entries[i].vddc;
2645 }
2646
2647 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2648 return -EINVAL;
2649
2650 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2651
2652 if (v0_loadline > 0xFFFFUL)
2653 return -EINVAL;
2654
2655 *min = (u16)v0_loadline;
2656
2657 if ((*min > *max) || (*max == 0) || (*min == 0))
2658 return -EINVAL;
2659
2660 return 0;
2661}
2662
2663static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2664{
2665 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2666 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2667}
2668
2669static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2670 PP_SIslands_CacConfig *cac_tables,
2671 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2672 u16 t0, u16 t_step)
2673{
2674 struct si_power_info *si_pi = si_get_pi(adev);
2675 u32 leakage;
2676 unsigned int i, j;
2677 s32 t;
2678 u32 smc_leakage;
2679 u32 scaling_factor;
2680 u16 voltage;
2681
2682 scaling_factor = si_get_smc_power_scaling_factor(adev);
2683
2684 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2685 t = (1000 * (i * t_step + t0));
2686
2687 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2688 voltage = vddc_max - (vddc_step * j);
2689
2690 si_calculate_leakage_for_v_and_t(adev,
2691 &si_pi->powertune_data->leakage_coefficients,
2692 voltage,
2693 t,
2694 si_pi->dyn_powertune_data.cac_leakage,
2695 &leakage);
2696
2697 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2698
2699 if (smc_leakage > 0xFFFF)
2700 smc_leakage = 0xFFFF;
2701
2702 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2703 cpu_to_be16((u16)smc_leakage);
2704 }
2705 }
2706 return 0;
2707}
2708
2709static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2710 PP_SIslands_CacConfig *cac_tables,
2711 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2712{
2713 struct si_power_info *si_pi = si_get_pi(adev);
2714 u32 leakage;
2715 unsigned int i, j;
2716 u32 smc_leakage;
2717 u32 scaling_factor;
2718 u16 voltage;
2719
2720 scaling_factor = si_get_smc_power_scaling_factor(adev);
2721
2722 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2723 voltage = vddc_max - (vddc_step * j);
2724
2725 si_calculate_leakage_for_v(adev,
2726 &si_pi->powertune_data->leakage_coefficients,
2727 si_pi->powertune_data->fixed_kt,
2728 voltage,
2729 si_pi->dyn_powertune_data.cac_leakage,
2730 &leakage);
2731
2732 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2733
2734 if (smc_leakage > 0xFFFF)
2735 smc_leakage = 0xFFFF;
2736
2737 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2738 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2739 cpu_to_be16((u16)smc_leakage);
2740 }
2741 return 0;
2742}
2743
2744static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2745{
2746 struct ni_power_info *ni_pi = ni_get_pi(adev);
2747 struct si_power_info *si_pi = si_get_pi(adev);
2748 PP_SIslands_CacConfig *cac_tables = NULL;
2749 u16 vddc_max, vddc_min, vddc_step;
2750 u16 t0, t_step;
2751 u32 load_line_slope, reg;
2752 int ret = 0;
2753 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2754
2755 if (ni_pi->enable_cac == false)
2756 return 0;
2757
2758 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2759 if (!cac_tables)
2760 return -ENOMEM;
2761
2762 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2763 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2764 WREG32(CG_CAC_CTRL, reg);
2765
2766 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2767 si_pi->dyn_powertune_data.dc_pwr_value =
2768 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2769 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2770 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2771
2772 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2773
2774 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2775 if (ret)
2776 goto done_free;
2777
2778 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2779 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2780 t_step = 4;
2781 t0 = 60;
2782
2783 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2784 ret = si_init_dte_leakage_table(adev, cac_tables,
2785 vddc_max, vddc_min, vddc_step,
2786 t0, t_step);
2787 else
2788 ret = si_init_simplified_leakage_table(adev, cac_tables,
2789 vddc_max, vddc_min, vddc_step);
2790 if (ret)
2791 goto done_free;
2792
2793 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2794
2795 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2796 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2797 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2798 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2799 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2800 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2801 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2802 cac_tables->calculation_repeats = cpu_to_be32(2);
2803 cac_tables->dc_cac = cpu_to_be32(0);
2804 cac_tables->log2_PG_LKG_SCALE = 12;
2805 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2806 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2807 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2808
2809 ret = si_copy_bytes_to_smc(adev, si_pi->cac_table_start, (u8 *)cac_tables,
2810 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2811
2812 if (ret)
2813 goto done_free;
2814
2815 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2816
2817done_free:
2818 if (ret) {
2819 ni_pi->enable_cac = false;
2820 ni_pi->enable_power_containment = false;
2821 }
2822
2823 kfree(cac_tables);
2824
Tom St Denisad2473a2016-09-07 08:42:41 -0400[diff] [blame]2825 return ret;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2826}
2827
2828static int si_program_cac_config_registers(struct amdgpu_device *adev,
2829 const struct si_cac_config_reg *cac_config_regs)
2830{
2831 const struct si_cac_config_reg *config_regs = cac_config_regs;
2832 u32 data = 0, offset;
2833
2834 if (!config_regs)
2835 return -EINVAL;
2836
2837 while (config_regs->offset != 0xFFFFFFFF) {
2838 switch (config_regs->type) {
2839 case SISLANDS_CACCONFIG_CGIND:
2840 offset = SMC_CG_IND_START + config_regs->offset;
2841 if (offset < SMC_CG_IND_END)
2842 data = RREG32_SMC(offset);
2843 break;
2844 default:
2845 data = RREG32(config_regs->offset);
2846 break;
2847 }
2848
2849 data &= ~config_regs->mask;
2850 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2851
2852 switch (config_regs->type) {
2853 case SISLANDS_CACCONFIG_CGIND:
2854 offset = SMC_CG_IND_START + config_regs->offset;
2855 if (offset < SMC_CG_IND_END)
2856 WREG32_SMC(offset, data);
2857 break;
2858 default:
2859 WREG32(config_regs->offset, data);
2860 break;
2861 }
2862 config_regs++;
2863 }
2864 return 0;
2865}
2866
2867static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2868{
2869 struct ni_power_info *ni_pi = ni_get_pi(adev);
2870 struct si_power_info *si_pi = si_get_pi(adev);
2871 int ret;
2872
2873 if ((ni_pi->enable_cac == false) ||
2874 (ni_pi->cac_configuration_required == false))
2875 return 0;
2876
2877 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2878 if (ret)
2879 return ret;
2880 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2881 if (ret)
2882 return ret;
2883 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2884 if (ret)
2885 return ret;
2886
2887 return 0;
2888}
2889
2890static int si_enable_smc_cac(struct amdgpu_device *adev,
2891 struct amdgpu_ps *amdgpu_new_state,
2892 bool enable)
2893{
2894 struct ni_power_info *ni_pi = ni_get_pi(adev);
2895 struct si_power_info *si_pi = si_get_pi(adev);
2896 PPSMC_Result smc_result;
2897 int ret = 0;
2898
2899 if (ni_pi->enable_cac) {
2900 if (enable) {
2901 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2902 if (ni_pi->support_cac_long_term_average) {
2903 smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2904 if (smc_result != PPSMC_Result_OK)
2905 ni_pi->support_cac_long_term_average = false;
2906 }
2907
2908 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2909 if (smc_result != PPSMC_Result_OK) {
2910 ret = -EINVAL;
2911 ni_pi->cac_enabled = false;
2912 } else {
2913 ni_pi->cac_enabled = true;
2914 }
2915
2916 if (si_pi->enable_dte) {
2917 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2918 if (smc_result != PPSMC_Result_OK)
2919 ret = -EINVAL;
2920 }
2921 }
2922 } else if (ni_pi->cac_enabled) {
2923 if (si_pi->enable_dte)
2924 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2925
2926 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2927
2928 ni_pi->cac_enabled = false;
2929
2930 if (ni_pi->support_cac_long_term_average)
2931 smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2932 }
2933 }
2934 return ret;
2935}
2936
2937static int si_init_smc_spll_table(struct amdgpu_device *adev)
2938{
2939 struct ni_power_info *ni_pi = ni_get_pi(adev);
2940 struct si_power_info *si_pi = si_get_pi(adev);
2941 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2942 SISLANDS_SMC_SCLK_VALUE sclk_params;
2943 u32 fb_div, p_div;
2944 u32 clk_s, clk_v;
2945 u32 sclk = 0;
2946 int ret = 0;
2947 u32 tmp;
2948 int i;
2949
2950 if (si_pi->spll_table_start == 0)
2951 return -EINVAL;
2952
2953 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2954 if (spll_table == NULL)
2955 return -ENOMEM;
2956
2957 for (i = 0; i < 256; i++) {
2958 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2959 if (ret)
2960 break;
2961 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2962 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2963 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2964 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2965
2966 fb_div &= ~0x00001FFF;
2967 fb_div >>= 1;
2968 clk_v >>= 6;
2969
2970 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2971 ret = -EINVAL;
2972 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2973 ret = -EINVAL;
2974 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2975 ret = -EINVAL;
2976 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2977 ret = -EINVAL;
2978
2979 if (ret)
2980 break;
2981
2982 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2983 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2984 spll_table->freq[i] = cpu_to_be32(tmp);
2985
2986 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2987 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2988 spll_table->ss[i] = cpu_to_be32(tmp);
2989
2990 sclk += 512;
2991 }
2992
2993
2994 if (!ret)
2995 ret = si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
2996 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2997 si_pi->sram_end);
2998
2999 if (ret)
3000 ni_pi->enable_power_containment = false;
3001
3002 kfree(spll_table);
3003
3004 return ret;
3005}
3006
3007struct si_dpm_quirk {
3008 u32 chip_vendor;
3009 u32 chip_device;
3010 u32 subsys_vendor;
3011 u32 subsys_device;
3012 u32 max_sclk;
3013 u32 max_mclk;
3014};
3015
3016/* cards with dpm stability problems */
3017static struct si_dpm_quirk si_dpm_quirk_list[] = {
3018 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
3019 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
3020 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
3021 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
3022 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
3023 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
3024 { 0, 0, 0, 0 },
3025};
3026
3027static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3028 u16 vce_voltage)
3029{
3030 u16 highest_leakage = 0;
3031 struct si_power_info *si_pi = si_get_pi(adev);
3032 int i;
3033
3034 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3035 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3036 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3037 }
3038
3039 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3040 return highest_leakage;
3041
3042 return vce_voltage;
3043}
3044
3045static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3046 u32 evclk, u32 ecclk, u16 *voltage)
3047{
3048 u32 i;
3049 int ret = -EINVAL;
3050 struct amdgpu_vce_clock_voltage_dependency_table *table =
3051 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3052
3053 if (((evclk == 0) && (ecclk == 0)) ||
3054 (table && (table->count == 0))) {
3055 *voltage = 0;
3056 return 0;
3057 }
3058
3059 for (i = 0; i < table->count; i++) {
3060 if ((evclk <= table->entries[i].evclk) &&
3061 (ecclk <= table->entries[i].ecclk)) {
3062 *voltage = table->entries[i].v;
3063 ret = 0;
3064 break;
3065 }
3066 }
3067
3068 /* if no match return the highest voltage */
3069 if (ret)
3070 *voltage = table->entries[table->count - 1].v;
3071
3072 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3073
3074 return ret;
3075}
3076
3077static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3078{
3079
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3080 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3081 /* we never hit the non-gddr5 limit so disable it */
3082 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3083
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3084 if (vblank_time < switch_limit)
3085 return true;
3086 else
3087 return false;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3088
3089}
3090
3091static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3092 u32 arb_freq_src, u32 arb_freq_dest)
3093{
3094 u32 mc_arb_dram_timing;
3095 u32 mc_arb_dram_timing2;
3096 u32 burst_time;
3097 u32 mc_cg_config;
3098
3099 switch (arb_freq_src) {
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3100 case MC_CG_ARB_FREQ_F0:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3101 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3102 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3103 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3104 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3105 case MC_CG_ARB_FREQ_F1:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3106 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3107 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3108 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3109 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3110 case MC_CG_ARB_FREQ_F2:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3111 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3112 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3113 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3114 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3115 case MC_CG_ARB_FREQ_F3:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3116 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3117 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3118 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3119 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3120 default:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3121 return -EINVAL;
3122 }
3123
3124 switch (arb_freq_dest) {
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3125 case MC_CG_ARB_FREQ_F0:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3126 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3127 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3128 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3129 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3130 case MC_CG_ARB_FREQ_F1:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3131 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3132 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3133 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3134 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3135 case MC_CG_ARB_FREQ_F2:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3136 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3137 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3138 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3139 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3140 case MC_CG_ARB_FREQ_F3:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3141 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3142 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3143 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3144 break;
3145 default:
3146 return -EINVAL;
3147 }
3148
3149 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3150 WREG32(MC_CG_CONFIG, mc_cg_config);
3151 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3152
3153 return 0;
3154}
3155
3156static void ni_update_current_ps(struct amdgpu_device *adev,
3157 struct amdgpu_ps *rps)
3158{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3159 struct si_ps *new_ps = si_get_ps(rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3160 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3161 struct ni_power_info *ni_pi = ni_get_pi(adev);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3162
3163 eg_pi->current_rps = *rps;
3164 ni_pi->current_ps = *new_ps;
3165 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3166}
3167
3168static void ni_update_requested_ps(struct amdgpu_device *adev,
3169 struct amdgpu_ps *rps)
3170{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3171 struct si_ps *new_ps = si_get_ps(rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3172 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3173 struct ni_power_info *ni_pi = ni_get_pi(adev);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3174
3175 eg_pi->requested_rps = *rps;
3176 ni_pi->requested_ps = *new_ps;
3177 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3178}
3179
3180static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3181 struct amdgpu_ps *new_ps,
3182 struct amdgpu_ps *old_ps)
3183{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3184 struct si_ps *new_state = si_get_ps(new_ps);
3185 struct si_ps *current_state = si_get_ps(old_ps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3186
3187 if ((new_ps->vclk == old_ps->vclk) &&
3188 (new_ps->dclk == old_ps->dclk))
3189 return;
3190
3191 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3192 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3193 return;
3194
3195 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3196}
3197
3198static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3199 struct amdgpu_ps *new_ps,
3200 struct amdgpu_ps *old_ps)
3201{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3202 struct si_ps *new_state = si_get_ps(new_ps);
3203 struct si_ps *current_state = si_get_ps(old_ps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3204
3205 if ((new_ps->vclk == old_ps->vclk) &&
3206 (new_ps->dclk == old_ps->dclk))
3207 return;
3208
3209 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3210 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3211 return;
3212
3213 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3214}
3215
3216static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3217{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3218 unsigned int i;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3219
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3220 for (i = 0; i < table->count; i++)
3221 if (voltage <= table->entries[i].value)
3222 return table->entries[i].value;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3223
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3224 return table->entries[table->count - 1].value;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3225}
3226
3227static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3228 u32 max_clock, u32 requested_clock)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3229{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3230 unsigned int i;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3231
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3232 if ((clocks == NULL) || (clocks->count == 0))
3233 return (requested_clock < max_clock) ? requested_clock : max_clock;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3234
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3235 for (i = 0; i < clocks->count; i++) {
3236 if (clocks->values[i] >= requested_clock)
3237 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3238 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3239
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3240 return (clocks->values[clocks->count - 1] < max_clock) ?
3241 clocks->values[clocks->count - 1] : max_clock;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3242}
3243
3244static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3245 u32 max_mclk, u32 requested_mclk)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3246{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3247 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3248 max_mclk, requested_mclk);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3249}
3250
3251static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3252 u32 max_sclk, u32 requested_sclk)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3253{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3254 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3255 max_sclk, requested_sclk);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3256}
3257
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]3258static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3259 u32 *max_clock)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3260{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3261 u32 i, clock = 0;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3262
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3263 if ((table == NULL) || (table->count == 0)) {
3264 *max_clock = clock;
3265 return;
3266 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3267
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3268 for (i = 0; i < table->count; i++) {
3269 if (clock < table->entries[i].clk)
3270 clock = table->entries[i].clk;
3271 }
3272 *max_clock = clock;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3273}
3274
3275static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3276 u32 clock, u16 max_voltage, u16 *voltage)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3277{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3278 u32 i;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3279
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3280 if ((table == NULL) || (table->count == 0))
3281 return;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3282
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3283 for (i= 0; i < table->count; i++) {
3284 if (clock <= table->entries[i].clk) {
3285 if (*voltage < table->entries[i].v)
3286 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3287 table->entries[i].v : max_voltage);
3288 return;
3289 }
3290 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3291
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3292 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3293}
3294
3295static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3296 const struct amdgpu_clock_and_voltage_limits *max_limits,
3297 struct rv7xx_pl *pl)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3298{
3299
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3300 if ((pl->mclk == 0) || (pl->sclk == 0))
3301 return;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3302
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3303 if (pl->mclk == pl->sclk)
3304 return;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3305
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3306 if (pl->mclk > pl->sclk) {
3307 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3308 pl->sclk = btc_get_valid_sclk(adev,
3309 max_limits->sclk,
3310 (pl->mclk +
3311 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3312 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3313 } else {
3314 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3315 pl->mclk = btc_get_valid_mclk(adev,
3316 max_limits->mclk,
3317 pl->sclk -
3318 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3319 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3320}
3321
3322static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3323 u16 max_vddc, u16 max_vddci,
3324 u16 *vddc, u16 *vddci)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3325{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3326 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3327 u16 new_voltage;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3328
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3329 if ((0 == *vddc) || (0 == *vddci))
3330 return;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3331
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3332 if (*vddc > *vddci) {
3333 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3334 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3335 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3336 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3337 }
3338 } else {
3339 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3340 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3341 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3342 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3343 }
3344 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3345}
3346
3347static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3348 u32 sys_mask,
3349 enum amdgpu_pcie_gen asic_gen,
3350 enum amdgpu_pcie_gen default_gen)
3351{
3352 switch (asic_gen) {
3353 case AMDGPU_PCIE_GEN1:
3354 return AMDGPU_PCIE_GEN1;
3355 case AMDGPU_PCIE_GEN2:
3356 return AMDGPU_PCIE_GEN2;
3357 case AMDGPU_PCIE_GEN3:
3358 return AMDGPU_PCIE_GEN3;
3359 default:
3360 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3361 return AMDGPU_PCIE_GEN3;
3362 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3363 return AMDGPU_PCIE_GEN2;
3364 else
3365 return AMDGPU_PCIE_GEN1;
3366 }
3367 return AMDGPU_PCIE_GEN1;
3368}
3369
3370static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3371 u32 *p, u32 *u)
3372{
3373 u32 b_c = 0;
3374 u32 i_c;
3375 u32 tmp;
3376
3377 i_c = (i * r_c) / 100;
3378 tmp = i_c >> p_b;
3379
3380 while (tmp) {
3381 b_c++;
3382 tmp >>= 1;
3383 }
3384
3385 *u = (b_c + 1) / 2;
3386 *p = i_c / (1 << (2 * (*u)));
3387}
3388
3389static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3390{
3391 u32 k, a, ah, al;
3392 u32 t1;
3393
3394 if ((fl == 0) || (fh == 0) || (fl > fh))
3395 return -EINVAL;
3396
3397 k = (100 * fh) / fl;
3398 t1 = (t * (k - 100));
3399 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3400 a = (a + 5) / 10;
3401 ah = ((a * t) + 5000) / 10000;
3402 al = a - ah;
3403
3404 *th = t - ah;
3405 *tl = t + al;
3406
3407 return 0;
3408}
3409
3410static bool r600_is_uvd_state(u32 class, u32 class2)
3411{
3412 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3413 return true;
3414 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3415 return true;
3416 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3417 return true;
3418 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3419 return true;
3420 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3421 return true;
3422 return false;
3423}
3424
3425static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3426{
3427 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3428}
3429
3430static void rv770_get_max_vddc(struct amdgpu_device *adev)
3431{
3432 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3433 u16 vddc;
3434
3435 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3436 pi->max_vddc = 0;
3437 else
3438 pi->max_vddc = vddc;
3439}
3440
3441static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3442{
3443 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3444 struct amdgpu_atom_ss ss;
3445
3446 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3447 ASIC_INTERNAL_ENGINE_SS, 0);
3448 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3449 ASIC_INTERNAL_MEMORY_SS, 0);
3450
3451 if (pi->sclk_ss || pi->mclk_ss)
3452 pi->dynamic_ss = true;
3453 else
3454 pi->dynamic_ss = false;
3455}
3456
3457
3458static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3459 struct amdgpu_ps *rps)
3460{
3461 struct si_ps *ps = si_get_ps(rps);
3462 struct amdgpu_clock_and_voltage_limits *max_limits;
3463 bool disable_mclk_switching = false;
3464 bool disable_sclk_switching = false;
3465 u32 mclk, sclk;
3466 u16 vddc, vddci, min_vce_voltage = 0;
3467 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3468 u32 max_sclk = 0, max_mclk = 0;
3469 int i;
3470 struct si_dpm_quirk *p = si_dpm_quirk_list;
3471
3472 /* Apply dpm quirks */
3473 while (p && p->chip_device != 0) {
3474 if (adev->pdev->vendor == p->chip_vendor &&
3475 adev->pdev->device == p->chip_device &&
3476 adev->pdev->subsystem_vendor == p->subsys_vendor &&
3477 adev->pdev->subsystem_device == p->subsys_device) {
3478 max_sclk = p->max_sclk;
3479 max_mclk = p->max_mclk;
3480 break;
3481 }
3482 ++p;
3483 }
3484
3485 if (rps->vce_active) {
3486 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3487 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3488 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3489 &min_vce_voltage);
3490 } else {
3491 rps->evclk = 0;
3492 rps->ecclk = 0;
3493 }
3494
3495 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3496 si_dpm_vblank_too_short(adev))
3497 disable_mclk_switching = true;
3498
3499 if (rps->vclk || rps->dclk) {
3500 disable_mclk_switching = true;
3501 disable_sclk_switching = true;
3502 }
3503
3504 if (adev->pm.dpm.ac_power)
3505 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3506 else
3507 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3508
3509 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3510 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3511 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3512 }
3513 if (adev->pm.dpm.ac_power == false) {
3514 for (i = 0; i < ps->performance_level_count; i++) {
3515 if (ps->performance_levels[i].mclk > max_limits->mclk)
3516 ps->performance_levels[i].mclk = max_limits->mclk;
3517 if (ps->performance_levels[i].sclk > max_limits->sclk)
3518 ps->performance_levels[i].sclk = max_limits->sclk;
3519 if (ps->performance_levels[i].vddc > max_limits->vddc)
3520 ps->performance_levels[i].vddc = max_limits->vddc;
3521 if (ps->performance_levels[i].vddci > max_limits->vddci)
3522 ps->performance_levels[i].vddci = max_limits->vddci;
3523 }
3524 }
3525
3526 /* limit clocks to max supported clocks based on voltage dependency tables */
3527 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3528 &max_sclk_vddc);
3529 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3530 &max_mclk_vddci);
3531 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3532 &max_mclk_vddc);
3533
3534 for (i = 0; i < ps->performance_level_count; i++) {
3535 if (max_sclk_vddc) {
3536 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3537 ps->performance_levels[i].sclk = max_sclk_vddc;
3538 }
3539 if (max_mclk_vddci) {
3540 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3541 ps->performance_levels[i].mclk = max_mclk_vddci;
3542 }
3543 if (max_mclk_vddc) {
3544 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3545 ps->performance_levels[i].mclk = max_mclk_vddc;
3546 }
3547 if (max_mclk) {
3548 if (ps->performance_levels[i].mclk > max_mclk)
3549 ps->performance_levels[i].mclk = max_mclk;
3550 }
3551 if (max_sclk) {
3552 if (ps->performance_levels[i].sclk > max_sclk)
3553 ps->performance_levels[i].sclk = max_sclk;
3554 }
3555 }
3556
3557 /* XXX validate the min clocks required for display */
3558
3559 if (disable_mclk_switching) {
3560 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3561 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3562 } else {
3563 mclk = ps->performance_levels[0].mclk;
3564 vddci = ps->performance_levels[0].vddci;
3565 }
3566
3567 if (disable_sclk_switching) {
3568 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3569 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3570 } else {
3571 sclk = ps->performance_levels[0].sclk;
3572 vddc = ps->performance_levels[0].vddc;
3573 }
3574
3575 if (rps->vce_active) {
3576 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3577 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3578 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3579 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3580 }
3581
3582 /* adjusted low state */
3583 ps->performance_levels[0].sclk = sclk;
3584 ps->performance_levels[0].mclk = mclk;
3585 ps->performance_levels[0].vddc = vddc;
3586 ps->performance_levels[0].vddci = vddci;
3587
3588 if (disable_sclk_switching) {
3589 sclk = ps->performance_levels[0].sclk;
3590 for (i = 1; i < ps->performance_level_count; i++) {
3591 if (sclk < ps->performance_levels[i].sclk)
3592 sclk = ps->performance_levels[i].sclk;
3593 }
3594 for (i = 0; i < ps->performance_level_count; i++) {
3595 ps->performance_levels[i].sclk = sclk;
3596 ps->performance_levels[i].vddc = vddc;
3597 }
3598 } else {
3599 for (i = 1; i < ps->performance_level_count; i++) {
3600 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3601 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3602 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3603 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3604 }
3605 }
3606
3607 if (disable_mclk_switching) {
3608 mclk = ps->performance_levels[0].mclk;
3609 for (i = 1; i < ps->performance_level_count; i++) {
3610 if (mclk < ps->performance_levels[i].mclk)
3611 mclk = ps->performance_levels[i].mclk;
3612 }
3613 for (i = 0; i < ps->performance_level_count; i++) {
3614 ps->performance_levels[i].mclk = mclk;
3615 ps->performance_levels[i].vddci = vddci;
3616 }
3617 } else {
3618 for (i = 1; i < ps->performance_level_count; i++) {
3619 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3620 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3621 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3622 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3623 }
3624 }
3625
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3626 for (i = 0; i < ps->performance_level_count; i++)
3627 btc_adjust_clock_combinations(adev, max_limits,
3628 &ps->performance_levels[i]);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3629
3630 for (i = 0; i < ps->performance_level_count; i++) {
3631 if (ps->performance_levels[i].vddc < min_vce_voltage)
3632 ps->performance_levels[i].vddc = min_vce_voltage;
3633 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3634 ps->performance_levels[i].sclk,
3635 max_limits->vddc, &ps->performance_levels[i].vddc);
3636 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3637 ps->performance_levels[i].mclk,
3638 max_limits->vddci, &ps->performance_levels[i].vddci);
3639 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3640 ps->performance_levels[i].mclk,
3641 max_limits->vddc, &ps->performance_levels[i].vddc);
3642 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3643 adev->clock.current_dispclk,
3644 max_limits->vddc, &ps->performance_levels[i].vddc);
3645 }
3646
3647 for (i = 0; i < ps->performance_level_count; i++) {
3648 btc_apply_voltage_delta_rules(adev,
3649 max_limits->vddc, max_limits->vddci,
3650 &ps->performance_levels[i].vddc,
3651 &ps->performance_levels[i].vddci);
3652 }
3653
3654 ps->dc_compatible = true;
3655 for (i = 0; i < ps->performance_level_count; i++) {
3656 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3657 ps->dc_compatible = false;
3658 }
3659}
3660
3661#if 0
3662static int si_read_smc_soft_register(struct amdgpu_device *adev,
3663 u16 reg_offset, u32 *value)
3664{
3665 struct si_power_info *si_pi = si_get_pi(adev);
3666
3667 return si_read_smc_sram_dword(adev,
3668 si_pi->soft_regs_start + reg_offset, value,
3669 si_pi->sram_end);
3670}
3671#endif
3672
3673static int si_write_smc_soft_register(struct amdgpu_device *adev,
3674 u16 reg_offset, u32 value)
3675{
3676 struct si_power_info *si_pi = si_get_pi(adev);
3677
3678 return si_write_smc_sram_dword(adev,
3679 si_pi->soft_regs_start + reg_offset,
3680 value, si_pi->sram_end);
3681}
3682
3683static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3684{
3685 bool ret = false;
3686 u32 tmp, width, row, column, bank, density;
3687 bool is_memory_gddr5, is_special;
3688
3689 tmp = RREG32(MC_SEQ_MISC0);
3690 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3691 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3692 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3693
3694 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3695 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3696
3697 tmp = RREG32(MC_ARB_RAMCFG);
3698 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3699 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3700 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3701
3702 density = (1 << (row + column - 20 + bank)) * width;
3703
3704 if ((adev->pdev->device == 0x6819) &&
3705 is_memory_gddr5 && is_special && (density == 0x400))
3706 ret = true;
3707
3708 return ret;
3709}
3710
3711static void si_get_leakage_vddc(struct amdgpu_device *adev)
3712{
3713 struct si_power_info *si_pi = si_get_pi(adev);
3714 u16 vddc, count = 0;
3715 int i, ret;
3716
3717 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3718 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3719
3720 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3721 si_pi->leakage_voltage.entries[count].voltage = vddc;
3722 si_pi->leakage_voltage.entries[count].leakage_index =
3723 SISLANDS_LEAKAGE_INDEX0 + i;
3724 count++;
3725 }
3726 }
3727 si_pi->leakage_voltage.count = count;
3728}
3729
3730static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3731 u32 index, u16 *leakage_voltage)
3732{
3733 struct si_power_info *si_pi = si_get_pi(adev);
3734 int i;
3735
3736 if (leakage_voltage == NULL)
3737 return -EINVAL;
3738
3739 if ((index & 0xff00) != 0xff00)
3740 return -EINVAL;
3741
3742 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3743 return -EINVAL;
3744
3745 if (index < SISLANDS_LEAKAGE_INDEX0)
3746 return -EINVAL;
3747
3748 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3749 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3750 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3751 return 0;
3752 }
3753 }
3754 return -EAGAIN;
3755}
3756
3757static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3758{
3759 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3760 bool want_thermal_protection;
3761 enum amdgpu_dpm_event_src dpm_event_src;
3762
3763 switch (sources) {
3764 case 0:
3765 default:
3766 want_thermal_protection = false;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3767 break;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3768 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3769 want_thermal_protection = true;
3770 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3771 break;
3772 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3773 want_thermal_protection = true;
3774 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3775 break;
3776 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3777 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3778 want_thermal_protection = true;
3779 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3780 break;
3781 }
3782
3783 if (want_thermal_protection) {
3784 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3785 if (pi->thermal_protection)
3786 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3787 } else {
3788 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3789 }
3790}
3791
3792static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3793 enum amdgpu_dpm_auto_throttle_src source,
3794 bool enable)
3795{
3796 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3797
3798 if (enable) {
3799 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3800 pi->active_auto_throttle_sources |= 1 << source;
3801 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3802 }
3803 } else {
3804 if (pi->active_auto_throttle_sources & (1 << source)) {
3805 pi->active_auto_throttle_sources &= ~(1 << source);
3806 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3807 }
3808 }
3809}
3810
3811static void si_start_dpm(struct amdgpu_device *adev)
3812{
3813 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3814}
3815
3816static void si_stop_dpm(struct amdgpu_device *adev)
3817{
3818 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3819}
3820
3821static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3822{
3823 if (enable)
3824 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3825 else
3826 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3827
3828}
3829
3830#if 0
3831static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3832 u32 thermal_level)
3833{
3834 PPSMC_Result ret;
3835
3836 if (thermal_level == 0) {
3837 ret = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3838 if (ret == PPSMC_Result_OK)
3839 return 0;
3840 else
3841 return -EINVAL;
3842 }
3843 return 0;
3844}
3845
3846static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3847{
3848 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3849}
3850#endif
3851
3852#if 0
3853static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3854{
3855 if (ac_power)
3856 return (si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3857 0 : -EINVAL;
3858
3859 return 0;
3860}
3861#endif
3862
3863static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3864 PPSMC_Msg msg, u32 parameter)
3865{
3866 WREG32(SMC_SCRATCH0, parameter);
3867 return si_send_msg_to_smc(adev, msg);
3868}
3869
3870static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3871{
3872 if (si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3873 return -EINVAL;
3874
3875 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3876 0 : -EINVAL;
3877}
3878
3879static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3880 enum amdgpu_dpm_forced_level level)
3881{
3882 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3883 struct si_ps *ps = si_get_ps(rps);
3884 u32 levels = ps->performance_level_count;
3885
3886 if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
3887 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3888 return -EINVAL;
3889
3890 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3891 return -EINVAL;
3892 } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
3893 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3894 return -EINVAL;
3895
3896 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3897 return -EINVAL;
3898 } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
3899 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3900 return -EINVAL;
3901
3902 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3903 return -EINVAL;
3904 }
3905
3906 adev->pm.dpm.forced_level = level;
3907
3908 return 0;
3909}
3910
3911#if 0
3912static int si_set_boot_state(struct amdgpu_device *adev)
3913{
3914 return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3915 0 : -EINVAL;
3916}
3917#endif
3918
3919static int si_set_sw_state(struct amdgpu_device *adev)
3920{
3921 return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3922 0 : -EINVAL;
3923}
3924
3925static int si_halt_smc(struct amdgpu_device *adev)
3926{
3927 if (si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3928 return -EINVAL;
3929
3930 return (si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3931 0 : -EINVAL;
3932}
3933
3934static int si_resume_smc(struct amdgpu_device *adev)
3935{
3936 if (si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3937 return -EINVAL;
3938
3939 return (si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3940 0 : -EINVAL;
3941}
3942
3943static void si_dpm_start_smc(struct amdgpu_device *adev)
3944{
3945 si_program_jump_on_start(adev);
3946 si_start_smc(adev);
Tom St Denisf80c7382016-09-06 11:56:42 -0400[diff] [blame]3947 si_smc_clock(adev, true);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3948}
3949
3950static void si_dpm_stop_smc(struct amdgpu_device *adev)
3951{
3952 si_reset_smc(adev);
Tom St Denisf80c7382016-09-06 11:56:42 -0400[diff] [blame]3953 si_smc_clock(adev, false);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3954}
3955
3956static int si_process_firmware_header(struct amdgpu_device *adev)
3957{
3958 struct si_power_info *si_pi = si_get_pi(adev);
3959 u32 tmp;
3960 int ret;
3961
3962 ret = si_read_smc_sram_dword(adev,
3963 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3964 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3965 &tmp, si_pi->sram_end);
3966 if (ret)
3967 return ret;
3968
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3969 si_pi->state_table_start = tmp;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3970
3971 ret = si_read_smc_sram_dword(adev,
3972 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3973 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3974 &tmp, si_pi->sram_end);
3975 if (ret)
3976 return ret;
3977
3978 si_pi->soft_regs_start = tmp;
3979
3980 ret = si_read_smc_sram_dword(adev,
3981 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3982 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3983 &tmp, si_pi->sram_end);
3984 if (ret)
3985 return ret;
3986
3987 si_pi->mc_reg_table_start = tmp;
3988
3989 ret = si_read_smc_sram_dword(adev,
3990 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3991 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3992 &tmp, si_pi->sram_end);
3993 if (ret)
3994 return ret;
3995
3996 si_pi->fan_table_start = tmp;
3997
3998 ret = si_read_smc_sram_dword(adev,
3999 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4000 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4001 &tmp, si_pi->sram_end);
4002 if (ret)
4003 return ret;
4004
4005 si_pi->arb_table_start = tmp;
4006
4007 ret = si_read_smc_sram_dword(adev,
4008 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4009 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4010 &tmp, si_pi->sram_end);
4011 if (ret)
4012 return ret;
4013
4014 si_pi->cac_table_start = tmp;
4015
4016 ret = si_read_smc_sram_dword(adev,
4017 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4018 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4019 &tmp, si_pi->sram_end);
4020 if (ret)
4021 return ret;
4022
4023 si_pi->dte_table_start = tmp;
4024
4025 ret = si_read_smc_sram_dword(adev,
4026 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4027 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4028 &tmp, si_pi->sram_end);
4029 if (ret)
4030 return ret;
4031
4032 si_pi->spll_table_start = tmp;
4033
4034 ret = si_read_smc_sram_dword(adev,
4035 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4036 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4037 &tmp, si_pi->sram_end);
4038 if (ret)
4039 return ret;
4040
4041 si_pi->papm_cfg_table_start = tmp;
4042
4043 return ret;
4044}
4045
4046static void si_read_clock_registers(struct amdgpu_device *adev)
4047{
4048 struct si_power_info *si_pi = si_get_pi(adev);
4049
4050 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4051 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4052 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4053 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4054 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4055 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4056 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4057 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4058 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4059 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4060 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4061 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4062 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4063 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4064 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4065}
4066
4067static void si_enable_thermal_protection(struct amdgpu_device *adev,
4068 bool enable)
4069{
4070 if (enable)
4071 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4072 else
4073 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4074}
4075
4076static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4077{
4078 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4079}
4080
4081#if 0
4082static int si_enter_ulp_state(struct amdgpu_device *adev)
4083{
4084 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4085
4086 udelay(25000);
4087
4088 return 0;
4089}
4090
4091static int si_exit_ulp_state(struct amdgpu_device *adev)
4092{
4093 int i;
4094
4095 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4096
4097 udelay(7000);
4098
4099 for (i = 0; i < adev->usec_timeout; i++) {
4100 if (RREG32(SMC_RESP_0) == 1)
4101 break;
4102 udelay(1000);
4103 }
4104
4105 return 0;
4106}
4107#endif
4108
4109static int si_notify_smc_display_change(struct amdgpu_device *adev,
4110 bool has_display)
4111{
4112 PPSMC_Msg msg = has_display ?
4113 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4114
4115 return (si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4116 0 : -EINVAL;
4117}
4118
4119static void si_program_response_times(struct amdgpu_device *adev)
4120{
4121 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4122 u32 vddc_dly, acpi_dly, vbi_dly;
4123 u32 reference_clock;
4124
4125 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4126
4127 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]4128 backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4129
4130 if (voltage_response_time == 0)
4131 voltage_response_time = 1000;
4132
4133 acpi_delay_time = 15000;
4134 vbi_time_out = 100000;
4135
4136 reference_clock = amdgpu_asic_get_xclk(adev);
4137
4138 vddc_dly = (voltage_response_time * reference_clock) / 100;
4139 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4140 vbi_dly = (vbi_time_out * reference_clock) / 100;
4141
4142 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4143 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4144 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4145 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4146}
4147
4148static void si_program_ds_registers(struct amdgpu_device *adev)
4149{
4150 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4151 u32 tmp;
4152
4153 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4154 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4155 tmp = 0x10;
4156 else
4157 tmp = 0x1;
4158
4159 if (eg_pi->sclk_deep_sleep) {
4160 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4161 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4162 ~AUTOSCALE_ON_SS_CLEAR);
4163 }
4164}
4165
4166static void si_program_display_gap(struct amdgpu_device *adev)
4167{
4168 u32 tmp, pipe;
4169 int i;
4170
4171 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4172 if (adev->pm.dpm.new_active_crtc_count > 0)
4173 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4174 else
4175 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4176
4177 if (adev->pm.dpm.new_active_crtc_count > 1)
4178 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4179 else
4180 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4181
4182 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4183
4184 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4185 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4186
4187 if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4188 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4189 /* find the first active crtc */
4190 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4191 if (adev->pm.dpm.new_active_crtcs & (1 << i))
4192 break;
4193 }
4194 if (i == adev->mode_info.num_crtc)
4195 pipe = 0;
4196 else
4197 pipe = i;
4198
4199 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4200 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4201 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4202 }
4203
4204 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4205 * This can be a problem on PowerXpress systems or if you want to use the card
4206 * for offscreen rendering or compute if there are no crtcs enabled.
4207 */
4208 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4209}
4210
4211static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4212{
4213 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4214
4215 if (enable) {
4216 if (pi->sclk_ss)
4217 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4218 } else {
4219 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4220 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4221 }
4222}
4223
4224static void si_setup_bsp(struct amdgpu_device *adev)
4225{
4226 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4227 u32 xclk = amdgpu_asic_get_xclk(adev);
4228
4229 r600_calculate_u_and_p(pi->asi,
4230 xclk,
4231 16,
4232 &pi->bsp,
4233 &pi->bsu);
4234
4235 r600_calculate_u_and_p(pi->pasi,
4236 xclk,
4237 16,
4238 &pi->pbsp,
4239 &pi->pbsu);
4240
4241
4242 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4243 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4244
4245 WREG32(CG_BSP, pi->dsp);
4246}
4247
4248static void si_program_git(struct amdgpu_device *adev)
4249{
4250 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4251}
4252
4253static void si_program_tp(struct amdgpu_device *adev)
4254{
4255 int i;
4256 enum r600_td td = R600_TD_DFLT;
4257
4258 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4259 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4260
4261 if (td == R600_TD_AUTO)
4262 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4263 else
4264 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4265
4266 if (td == R600_TD_UP)
4267 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4268
4269 if (td == R600_TD_DOWN)
4270 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4271}
4272
4273static void si_program_tpp(struct amdgpu_device *adev)
4274{
4275 WREG32(CG_TPC, R600_TPC_DFLT);
4276}
4277
4278static void si_program_sstp(struct amdgpu_device *adev)
4279{
4280 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4281}
4282
4283static void si_enable_display_gap(struct amdgpu_device *adev)
4284{
4285 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4286
4287 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4288 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4289 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4290
4291 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4292 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4293 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4294 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4295}
4296
4297static void si_program_vc(struct amdgpu_device *adev)
4298{
4299 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4300
4301 WREG32(CG_FTV, pi->vrc);
4302}
4303
4304static void si_clear_vc(struct amdgpu_device *adev)
4305{
4306 WREG32(CG_FTV, 0);
4307}
4308
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]4309static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4310{
4311 u8 mc_para_index;
4312
4313 if (memory_clock < 10000)
4314 mc_para_index = 0;
4315 else if (memory_clock >= 80000)
4316 mc_para_index = 0x0f;
4317 else
4318 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4319 return mc_para_index;
4320}
4321
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]4322static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4323{
4324 u8 mc_para_index;
4325
4326 if (strobe_mode) {
4327 if (memory_clock < 12500)
4328 mc_para_index = 0x00;
4329 else if (memory_clock > 47500)
4330 mc_para_index = 0x0f;
4331 else
4332 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4333 } else {
4334 if (memory_clock < 65000)
4335 mc_para_index = 0x00;
4336 else if (memory_clock > 135000)
4337 mc_para_index = 0x0f;
4338 else
4339 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4340 }
4341 return mc_para_index;
4342}
4343
4344static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4345{
4346 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4347 bool strobe_mode = false;
4348 u8 result = 0;
4349
4350 if (mclk <= pi->mclk_strobe_mode_threshold)
4351 strobe_mode = true;
4352
4353 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4354 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4355 else
4356 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4357
4358 if (strobe_mode)
4359 result |= SISLANDS_SMC_STROBE_ENABLE;
4360
4361 return result;
4362}
4363
4364static int si_upload_firmware(struct amdgpu_device *adev)
4365{
4366 struct si_power_info *si_pi = si_get_pi(adev);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4367
4368 si_reset_smc(adev);
Tom St Denisf80c7382016-09-06 11:56:42 -0400[diff] [blame]4369 si_smc_clock(adev, false);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4370
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]4371 return si_load_smc_ucode(adev, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4372}
4373
4374static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4375 const struct atom_voltage_table *table,
4376 const struct amdgpu_phase_shedding_limits_table *limits)
4377{
4378 u32 data, num_bits, num_levels;
4379
4380 if ((table == NULL) || (limits == NULL))
4381 return false;
4382
4383 data = table->mask_low;
4384
4385 num_bits = hweight32(data);
4386
4387 if (num_bits == 0)
4388 return false;
4389
4390 num_levels = (1 << num_bits);
4391
4392 if (table->count != num_levels)
4393 return false;
4394
4395 if (limits->count != (num_levels - 1))
4396 return false;
4397
4398 return true;
4399}
4400
4401static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4402 u32 max_voltage_steps,
4403 struct atom_voltage_table *voltage_table)
4404{
4405 unsigned int i, diff;
4406
4407 if (voltage_table->count <= max_voltage_steps)
4408 return;
4409
4410 diff = voltage_table->count - max_voltage_steps;
4411
4412 for (i= 0; i < max_voltage_steps; i++)
4413 voltage_table->entries[i] = voltage_table->entries[i + diff];
4414
4415 voltage_table->count = max_voltage_steps;
4416}
4417
4418static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4419 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4420 struct atom_voltage_table *voltage_table)
4421{
4422 u32 i;
4423
4424 if (voltage_dependency_table == NULL)
4425 return -EINVAL;
4426
4427 voltage_table->mask_low = 0;
4428 voltage_table->phase_delay = 0;
4429
4430 voltage_table->count = voltage_dependency_table->count;
4431 for (i = 0; i < voltage_table->count; i++) {
4432 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4433 voltage_table->entries[i].smio_low = 0;
4434 }
4435
4436 return 0;
4437}
4438
4439static int si_construct_voltage_tables(struct amdgpu_device *adev)
4440{
4441 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4442 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4443 struct si_power_info *si_pi = si_get_pi(adev);
4444 int ret;
4445
4446 if (pi->voltage_control) {
4447 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4448 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4449 if (ret)
4450 return ret;
4451
4452 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4453 si_trim_voltage_table_to_fit_state_table(adev,
4454 SISLANDS_MAX_NO_VREG_STEPS,
4455 &eg_pi->vddc_voltage_table);
4456 } else if (si_pi->voltage_control_svi2) {
4457 ret = si_get_svi2_voltage_table(adev,
4458 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4459 &eg_pi->vddc_voltage_table);
4460 if (ret)
4461 return ret;
4462 } else {
4463 return -EINVAL;
4464 }
4465
4466 if (eg_pi->vddci_control) {
4467 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4468 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4469 if (ret)
4470 return ret;
4471
4472 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4473 si_trim_voltage_table_to_fit_state_table(adev,
4474 SISLANDS_MAX_NO_VREG_STEPS,
4475 &eg_pi->vddci_voltage_table);
4476 }
4477 if (si_pi->vddci_control_svi2) {
4478 ret = si_get_svi2_voltage_table(adev,
4479 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4480 &eg_pi->vddci_voltage_table);
4481 if (ret)
4482 return ret;
4483 }
4484
4485 if (pi->mvdd_control) {
4486 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4487 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4488
4489 if (ret) {
4490 pi->mvdd_control = false;
4491 return ret;
4492 }
4493
4494 if (si_pi->mvdd_voltage_table.count == 0) {
4495 pi->mvdd_control = false;
4496 return -EINVAL;
4497 }
4498
4499 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4500 si_trim_voltage_table_to_fit_state_table(adev,
4501 SISLANDS_MAX_NO_VREG_STEPS,
4502 &si_pi->mvdd_voltage_table);
4503 }
4504
4505 if (si_pi->vddc_phase_shed_control) {
4506 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4507 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4508 if (ret)
4509 si_pi->vddc_phase_shed_control = false;
4510
4511 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4512 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4513 si_pi->vddc_phase_shed_control = false;
4514 }
4515
4516 return 0;
4517}
4518
4519static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4520 const struct atom_voltage_table *voltage_table,
4521 SISLANDS_SMC_STATETABLE *table)
4522{
4523 unsigned int i;
4524
4525 for (i = 0; i < voltage_table->count; i++)
4526 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4527}
4528
4529static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4530 SISLANDS_SMC_STATETABLE *table)
4531{
4532 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4533 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4534 struct si_power_info *si_pi = si_get_pi(adev);
4535 u8 i;
4536
4537 if (si_pi->voltage_control_svi2) {
4538 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4539 si_pi->svc_gpio_id);
4540 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4541 si_pi->svd_gpio_id);
4542 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4543 2);
4544 } else {
4545 if (eg_pi->vddc_voltage_table.count) {
4546 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4547 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4548 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4549
4550 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4551 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4552 table->maxVDDCIndexInPPTable = i;
4553 break;
4554 }
4555 }
4556 }
4557
4558 if (eg_pi->vddci_voltage_table.count) {
4559 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4560
4561 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4562 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4563 }
4564
4565
4566 if (si_pi->mvdd_voltage_table.count) {
4567 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4568
4569 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4570 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4571 }
4572
4573 if (si_pi->vddc_phase_shed_control) {
4574 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4575 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4576 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4577
4578 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4579 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4580
4581 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4582 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4583 } else {
4584 si_pi->vddc_phase_shed_control = false;
4585 }
4586 }
4587 }
4588
4589 return 0;
4590}
4591
4592static int si_populate_voltage_value(struct amdgpu_device *adev,
4593 const struct atom_voltage_table *table,
4594 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4595{
4596 unsigned int i;
4597
4598 for (i = 0; i < table->count; i++) {
4599 if (value <= table->entries[i].value) {
4600 voltage->index = (u8)i;
4601 voltage->value = cpu_to_be16(table->entries[i].value);
4602 break;
4603 }
4604 }
4605
4606 if (i >= table->count)
4607 return -EINVAL;
4608
4609 return 0;
4610}
4611
4612static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4613 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4614{
4615 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4616 struct si_power_info *si_pi = si_get_pi(adev);
4617
4618 if (pi->mvdd_control) {
4619 if (mclk <= pi->mvdd_split_frequency)
4620 voltage->index = 0;
4621 else
4622 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4623
4624 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4625 }
4626 return 0;
4627}
4628
4629static int si_get_std_voltage_value(struct amdgpu_device *adev,
4630 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4631 u16 *std_voltage)
4632{
4633 u16 v_index;
4634 bool voltage_found = false;
4635 *std_voltage = be16_to_cpu(voltage->value);
4636
4637 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4638 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4639 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4640 return -EINVAL;
4641
4642 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4643 if (be16_to_cpu(voltage->value) ==
4644 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4645 voltage_found = true;
4646 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4647 *std_voltage =
4648 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4649 else
4650 *std_voltage =
4651 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4652 break;
4653 }
4654 }
4655
4656 if (!voltage_found) {
4657 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4658 if (be16_to_cpu(voltage->value) <=
4659 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4660 voltage_found = true;
4661 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4662 *std_voltage =
4663 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4664 else
4665 *std_voltage =
4666 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4667 break;
4668 }
4669 }
4670 }
4671 } else {
4672 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4673 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4674 }
4675 }
4676
4677 return 0;
4678}
4679
4680static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4681 u16 value, u8 index,
4682 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4683{
4684 voltage->index = index;
4685 voltage->value = cpu_to_be16(value);
4686
4687 return 0;
4688}
4689
4690static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4691 const struct amdgpu_phase_shedding_limits_table *limits,
4692 u16 voltage, u32 sclk, u32 mclk,
4693 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4694{
4695 unsigned int i;
4696
4697 for (i = 0; i < limits->count; i++) {
4698 if ((voltage <= limits->entries[i].voltage) &&
4699 (sclk <= limits->entries[i].sclk) &&
4700 (mclk <= limits->entries[i].mclk))
4701 break;
4702 }
4703
4704 smc_voltage->phase_settings = (u8)i;
4705
4706 return 0;
4707}
4708
4709static int si_init_arb_table_index(struct amdgpu_device *adev)
4710{
4711 struct si_power_info *si_pi = si_get_pi(adev);
4712 u32 tmp;
4713 int ret;
4714
4715 ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4716 if (ret)
4717 return ret;
4718
4719 tmp &= 0x00FFFFFF;
4720 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4721
4722 return si_write_smc_sram_dword(adev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4723}
4724
4725static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4726{
4727 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4728}
4729
4730static int si_reset_to_default(struct amdgpu_device *adev)
4731{
4732 return (si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4733 0 : -EINVAL;
4734}
4735
4736static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4737{
4738 struct si_power_info *si_pi = si_get_pi(adev);
4739 u32 tmp;
4740 int ret;
4741
4742 ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4743 &tmp, si_pi->sram_end);
4744 if (ret)
4745 return ret;
4746
4747 tmp = (tmp >> 24) & 0xff;
4748
4749 if (tmp == MC_CG_ARB_FREQ_F0)
4750 return 0;
4751
4752 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4753}
4754
4755static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4756 u32 engine_clock)
4757{
4758 u32 dram_rows;
4759 u32 dram_refresh_rate;
4760 u32 mc_arb_rfsh_rate;
4761 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4762
4763 if (tmp >= 4)
4764 dram_rows = 16384;
4765 else
4766 dram_rows = 1 << (tmp + 10);
4767
4768 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4769 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4770
4771 return mc_arb_rfsh_rate;
4772}
4773
4774static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4775 struct rv7xx_pl *pl,
4776 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4777{
4778 u32 dram_timing;
4779 u32 dram_timing2;
4780 u32 burst_time;
4781
4782 arb_regs->mc_arb_rfsh_rate =
4783 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4784
4785 amdgpu_atombios_set_engine_dram_timings(adev,
4786 pl->sclk,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]4787 pl->mclk);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4788
4789 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4790 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4791 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4792
4793 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4794 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4795 arb_regs->mc_arb_burst_time = (u8)burst_time;
4796
4797 return 0;
4798}
4799
4800static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4801 struct amdgpu_ps *amdgpu_state,
4802 unsigned int first_arb_set)
4803{
4804 struct si_power_info *si_pi = si_get_pi(adev);
4805 struct si_ps *state = si_get_ps(amdgpu_state);
4806 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4807 int i, ret = 0;
4808
4809 for (i = 0; i < state->performance_level_count; i++) {
4810 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4811 if (ret)
4812 break;
4813 ret = si_copy_bytes_to_smc(adev,
4814 si_pi->arb_table_start +
4815 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4816 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4817 (u8 *)&arb_regs,
4818 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4819 si_pi->sram_end);
4820 if (ret)
4821 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]4822 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4823
4824 return ret;
4825}
4826
4827static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4828 struct amdgpu_ps *amdgpu_new_state)
4829{
4830 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4831 SISLANDS_DRIVER_STATE_ARB_INDEX);
4832}
4833
4834static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4835 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4836{
4837 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4838 struct si_power_info *si_pi = si_get_pi(adev);
4839
4840 if (pi->mvdd_control)
4841 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4842 si_pi->mvdd_bootup_value, voltage);
4843
4844 return 0;
4845}
4846
4847static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4848 struct amdgpu_ps *amdgpu_initial_state,
4849 SISLANDS_SMC_STATETABLE *table)
4850{
4851 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4852 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4853 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4854 struct si_power_info *si_pi = si_get_pi(adev);
4855 u32 reg;
4856 int ret;
4857
4858 table->initialState.levels[0].mclk.vDLL_CNTL =
4859 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4860 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4861 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4862 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4863 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4864 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4865 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4866 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4867 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4868 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4869 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4870 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4871 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4872 table->initialState.levels[0].mclk.vMPLL_SS =
4873 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4874 table->initialState.levels[0].mclk.vMPLL_SS2 =
4875 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4876
4877 table->initialState.levels[0].mclk.mclk_value =
4878 cpu_to_be32(initial_state->performance_levels[0].mclk);
4879
4880 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4881 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4882 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4883 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4884 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4885 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4886 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4887 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4888 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4889 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4890 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4891 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4892
4893 table->initialState.levels[0].sclk.sclk_value =
4894 cpu_to_be32(initial_state->performance_levels[0].sclk);
4895
4896 table->initialState.levels[0].arbRefreshState =
4897 SISLANDS_INITIAL_STATE_ARB_INDEX;
4898
4899 table->initialState.levels[0].ACIndex = 0;
4900
4901 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4902 initial_state->performance_levels[0].vddc,
4903 &table->initialState.levels[0].vddc);
4904
4905 if (!ret) {
4906 u16 std_vddc;
4907
4908 ret = si_get_std_voltage_value(adev,
4909 &table->initialState.levels[0].vddc,
4910 &std_vddc);
4911 if (!ret)
4912 si_populate_std_voltage_value(adev, std_vddc,
4913 table->initialState.levels[0].vddc.index,
4914 &table->initialState.levels[0].std_vddc);
4915 }
4916
4917 if (eg_pi->vddci_control)
4918 si_populate_voltage_value(adev,
4919 &eg_pi->vddci_voltage_table,
4920 initial_state->performance_levels[0].vddci,
4921 &table->initialState.levels[0].vddci);
4922
4923 if (si_pi->vddc_phase_shed_control)
4924 si_populate_phase_shedding_value(adev,
4925 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4926 initial_state->performance_levels[0].vddc,
4927 initial_state->performance_levels[0].sclk,
4928 initial_state->performance_levels[0].mclk,
4929 &table->initialState.levels[0].vddc);
4930
4931 si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4932
4933 reg = CG_R(0xffff) | CG_L(0);
4934 table->initialState.levels[0].aT = cpu_to_be32(reg);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4935 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4936 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4937
4938 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4939 table->initialState.levels[0].strobeMode =
4940 si_get_strobe_mode_settings(adev,
4941 initial_state->performance_levels[0].mclk);
4942
4943 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4944 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4945 else
4946 table->initialState.levels[0].mcFlags = 0;
4947 }
4948
4949 table->initialState.levelCount = 1;
4950
4951 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4952
4953 table->initialState.levels[0].dpm2.MaxPS = 0;
4954 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4955 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4956 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4957 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4958
4959 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4960 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4961
4962 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4963 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4964
4965 return 0;
4966}
4967
4968static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4969 SISLANDS_SMC_STATETABLE *table)
4970{
4971 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4972 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4973 struct si_power_info *si_pi = si_get_pi(adev);
4974 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4975 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4976 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4977 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4978 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4979 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4980 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4981 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4982 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4983 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4984 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4985 u32 reg;
4986 int ret;
4987
4988 table->ACPIState = table->initialState;
4989
4990 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4991
4992 if (pi->acpi_vddc) {
4993 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4994 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4995 if (!ret) {
4996 u16 std_vddc;
4997
4998 ret = si_get_std_voltage_value(adev,
4999 &table->ACPIState.levels[0].vddc, &std_vddc);
5000 if (!ret)
5001 si_populate_std_voltage_value(adev, std_vddc,
5002 table->ACPIState.levels[0].vddc.index,
5003 &table->ACPIState.levels[0].std_vddc);
5004 }
5005 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5006
5007 if (si_pi->vddc_phase_shed_control) {
5008 si_populate_phase_shedding_value(adev,
5009 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5010 pi->acpi_vddc,
5011 0,
5012 0,
5013 &table->ACPIState.levels[0].vddc);
5014 }
5015 } else {
5016 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5017 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5018 if (!ret) {
5019 u16 std_vddc;
5020
5021 ret = si_get_std_voltage_value(adev,
5022 &table->ACPIState.levels[0].vddc, &std_vddc);
5023
5024 if (!ret)
5025 si_populate_std_voltage_value(adev, std_vddc,
5026 table->ACPIState.levels[0].vddc.index,
5027 &table->ACPIState.levels[0].std_vddc);
5028 }
5029 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5030 si_pi->sys_pcie_mask,
5031 si_pi->boot_pcie_gen,
5032 AMDGPU_PCIE_GEN1);
5033
5034 if (si_pi->vddc_phase_shed_control)
5035 si_populate_phase_shedding_value(adev,
5036 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5037 pi->min_vddc_in_table,
5038 0,
5039 0,
5040 &table->ACPIState.levels[0].vddc);
5041 }
5042
5043 if (pi->acpi_vddc) {
5044 if (eg_pi->acpi_vddci)
5045 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5046 eg_pi->acpi_vddci,
5047 &table->ACPIState.levels[0].vddci);
5048 }
5049
5050 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5051 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5052
5053 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5054
5055 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5056 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5057
5058 table->ACPIState.levels[0].mclk.vDLL_CNTL =
5059 cpu_to_be32(dll_cntl);
5060 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5061 cpu_to_be32(mclk_pwrmgt_cntl);
5062 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5063 cpu_to_be32(mpll_ad_func_cntl);
5064 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5065 cpu_to_be32(mpll_dq_func_cntl);
5066 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5067 cpu_to_be32(mpll_func_cntl);
5068 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5069 cpu_to_be32(mpll_func_cntl_1);
5070 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5071 cpu_to_be32(mpll_func_cntl_2);
5072 table->ACPIState.levels[0].mclk.vMPLL_SS =
5073 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5074 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5075 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5076
5077 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5078 cpu_to_be32(spll_func_cntl);
5079 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5080 cpu_to_be32(spll_func_cntl_2);
5081 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5082 cpu_to_be32(spll_func_cntl_3);
5083 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5084 cpu_to_be32(spll_func_cntl_4);
5085
5086 table->ACPIState.levels[0].mclk.mclk_value = 0;
5087 table->ACPIState.levels[0].sclk.sclk_value = 0;
5088
5089 si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5090
5091 if (eg_pi->dynamic_ac_timing)
5092 table->ACPIState.levels[0].ACIndex = 0;
5093
5094 table->ACPIState.levels[0].dpm2.MaxPS = 0;
5095 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5096 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5097 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5098 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5099
5100 reg = MIN_POWER_MASK | MAX_POWER_MASK;
5101 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5102
5103 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5104 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5105
5106 return 0;
5107}
5108
5109static int si_populate_ulv_state(struct amdgpu_device *adev,
5110 SISLANDS_SMC_SWSTATE *state)
5111{
5112 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5113 struct si_power_info *si_pi = si_get_pi(adev);
5114 struct si_ulv_param *ulv = &si_pi->ulv;
5115 u32 sclk_in_sr = 1350; /* ??? */
5116 int ret;
5117
5118 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5119 &state->levels[0]);
5120 if (!ret) {
5121 if (eg_pi->sclk_deep_sleep) {
5122 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5123 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5124 else
5125 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5126 }
5127 if (ulv->one_pcie_lane_in_ulv)
5128 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5129 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5130 state->levels[0].ACIndex = 1;
5131 state->levels[0].std_vddc = state->levels[0].vddc;
5132 state->levelCount = 1;
5133
5134 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5135 }
5136
5137 return ret;
5138}
5139
5140static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5141{
5142 struct si_power_info *si_pi = si_get_pi(adev);
5143 struct si_ulv_param *ulv = &si_pi->ulv;
5144 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5145 int ret;
5146
5147 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5148 &arb_regs);
5149 if (ret)
5150 return ret;
5151
5152 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5153 ulv->volt_change_delay);
5154
5155 ret = si_copy_bytes_to_smc(adev,
5156 si_pi->arb_table_start +
5157 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5158 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5159 (u8 *)&arb_regs,
5160 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5161 si_pi->sram_end);
5162
5163 return ret;
5164}
5165
5166static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5167{
5168 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5169
5170 pi->mvdd_split_frequency = 30000;
5171}
5172
5173static int si_init_smc_table(struct amdgpu_device *adev)
5174{
5175 struct si_power_info *si_pi = si_get_pi(adev);
5176 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5177 const struct si_ulv_param *ulv = &si_pi->ulv;
5178 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5179 int ret;
5180 u32 lane_width;
5181 u32 vr_hot_gpio;
5182
5183 si_populate_smc_voltage_tables(adev, table);
5184
5185 switch (adev->pm.int_thermal_type) {
5186 case THERMAL_TYPE_SI:
5187 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5188 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5189 break;
5190 case THERMAL_TYPE_NONE:
5191 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5192 break;
5193 default:
5194 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5195 break;
5196 }
5197
5198 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5199 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5200
5201 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5202 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5203 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5204 }
5205
5206 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5207 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5208
5209 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5210 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5211
5212 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5213 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5214
5215 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5216 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5217 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5218 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5219 vr_hot_gpio);
5220 }
5221
5222 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5223 if (ret)
5224 return ret;
5225
5226 ret = si_populate_smc_acpi_state(adev, table);
5227 if (ret)
5228 return ret;
5229
5230 table->driverState = table->initialState;
5231
5232 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5233 SISLANDS_INITIAL_STATE_ARB_INDEX);
5234 if (ret)
5235 return ret;
5236
5237 if (ulv->supported && ulv->pl.vddc) {
5238 ret = si_populate_ulv_state(adev, &table->ULVState);
5239 if (ret)
5240 return ret;
5241
5242 ret = si_program_ulv_memory_timing_parameters(adev);
5243 if (ret)
5244 return ret;
5245
5246 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5247 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5248
5249 lane_width = amdgpu_get_pcie_lanes(adev);
5250 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5251 } else {
5252 table->ULVState = table->initialState;
5253 }
5254
5255 return si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5256 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5257 si_pi->sram_end);
5258}
5259
5260static int si_calculate_sclk_params(struct amdgpu_device *adev,
5261 u32 engine_clock,
5262 SISLANDS_SMC_SCLK_VALUE *sclk)
5263{
5264 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5265 struct si_power_info *si_pi = si_get_pi(adev);
5266 struct atom_clock_dividers dividers;
5267 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5268 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5269 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5270 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5271 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5272 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5273 u64 tmp;
5274 u32 reference_clock = adev->clock.spll.reference_freq;
5275 u32 reference_divider;
5276 u32 fbdiv;
5277 int ret;
5278
5279 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5280 engine_clock, false, &dividers);
5281 if (ret)
5282 return ret;
5283
5284 reference_divider = 1 + dividers.ref_div;
5285
5286 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5287 do_div(tmp, reference_clock);
5288 fbdiv = (u32) tmp;
5289
5290 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5291 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5292 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5293
5294 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5295 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5296
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5297 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5298 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5299 spll_func_cntl_3 |= SPLL_DITHEN;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5300
5301 if (pi->sclk_ss) {
5302 struct amdgpu_atom_ss ss;
5303 u32 vco_freq = engine_clock * dividers.post_div;
5304
5305 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5306 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5307 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5308 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5309
5310 cg_spll_spread_spectrum &= ~CLK_S_MASK;
5311 cg_spll_spread_spectrum |= CLK_S(clk_s);
5312 cg_spll_spread_spectrum |= SSEN;
5313
5314 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5315 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5316 }
5317 }
5318
5319 sclk->sclk_value = engine_clock;
5320 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5321 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5322 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5323 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5324 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5325 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5326
5327 return 0;
5328}
5329
5330static int si_populate_sclk_value(struct amdgpu_device *adev,
5331 u32 engine_clock,
5332 SISLANDS_SMC_SCLK_VALUE *sclk)
5333{
5334 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5335 int ret;
5336
5337 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5338 if (!ret) {
5339 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5340 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5341 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5342 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5343 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5344 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5345 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5346 }
5347
5348 return ret;
5349}
5350
5351static int si_populate_mclk_value(struct amdgpu_device *adev,
5352 u32 engine_clock,
5353 u32 memory_clock,
5354 SISLANDS_SMC_MCLK_VALUE *mclk,
5355 bool strobe_mode,
5356 bool dll_state_on)
5357{
5358 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5359 struct si_power_info *si_pi = si_get_pi(adev);
5360 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5361 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5362 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5363 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5364 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5365 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5366 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5367 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5368 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5369 struct atom_mpll_param mpll_param;
5370 int ret;
5371
5372 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5373 if (ret)
5374 return ret;
5375
5376 mpll_func_cntl &= ~BWCTRL_MASK;
5377 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5378
5379 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5380 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5381 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5382
5383 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5384 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5385
5386 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5387 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5388 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5389 YCLK_POST_DIV(mpll_param.post_div);
5390 }
5391
5392 if (pi->mclk_ss) {
5393 struct amdgpu_atom_ss ss;
5394 u32 freq_nom;
5395 u32 tmp;
5396 u32 reference_clock = adev->clock.mpll.reference_freq;
5397
5398 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5399 freq_nom = memory_clock * 4;
5400 else
5401 freq_nom = memory_clock * 2;
5402
5403 tmp = freq_nom / reference_clock;
5404 tmp = tmp * tmp;
5405 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5406 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5407 u32 clks = reference_clock * 5 / ss.rate;
5408 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5409
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5410 mpll_ss1 &= ~CLKV_MASK;
5411 mpll_ss1 |= CLKV(clkv);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5412
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5413 mpll_ss2 &= ~CLKS_MASK;
5414 mpll_ss2 |= CLKS(clks);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5415 }
5416 }
5417
5418 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5419 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5420
5421 if (dll_state_on)
5422 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5423 else
5424 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5425
5426 mclk->mclk_value = cpu_to_be32(memory_clock);
5427 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5428 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5429 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5430 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5431 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5432 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5433 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5434 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5435 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5436
5437 return 0;
5438}
5439
5440static void si_populate_smc_sp(struct amdgpu_device *adev,
5441 struct amdgpu_ps *amdgpu_state,
5442 SISLANDS_SMC_SWSTATE *smc_state)
5443{
5444 struct si_ps *ps = si_get_ps(amdgpu_state);
5445 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5446 int i;
5447
5448 for (i = 0; i < ps->performance_level_count - 1; i++)
5449 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5450
5451 smc_state->levels[ps->performance_level_count - 1].bSP =
5452 cpu_to_be32(pi->psp);
5453}
5454
5455static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5456 struct rv7xx_pl *pl,
5457 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5458{
5459 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5460 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5461 struct si_power_info *si_pi = si_get_pi(adev);
5462 int ret;
5463 bool dll_state_on;
5464 u16 std_vddc;
5465 bool gmc_pg = false;
5466
5467 if (eg_pi->pcie_performance_request &&
5468 (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5469 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5470 else
5471 level->gen2PCIE = (u8)pl->pcie_gen;
5472
5473 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5474 if (ret)
5475 return ret;
5476
5477 level->mcFlags = 0;
5478
5479 if (pi->mclk_stutter_mode_threshold &&
5480 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5481 !eg_pi->uvd_enabled &&
5482 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5483 (adev->pm.dpm.new_active_crtc_count <= 2)) {
5484 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5485
5486 if (gmc_pg)
5487 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5488 }
5489
5490 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5491 if (pl->mclk > pi->mclk_edc_enable_threshold)
5492 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5493
5494 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5495 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5496
5497 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5498
5499 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5500 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5501 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5502 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5503 else
5504 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5505 } else {
5506 dll_state_on = false;
5507 }
5508 } else {
5509 level->strobeMode = si_get_strobe_mode_settings(adev,
5510 pl->mclk);
5511
5512 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5513 }
5514
5515 ret = si_populate_mclk_value(adev,
5516 pl->sclk,
5517 pl->mclk,
5518 &level->mclk,
5519 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5520 if (ret)
5521 return ret;
5522
5523 ret = si_populate_voltage_value(adev,
5524 &eg_pi->vddc_voltage_table,
5525 pl->vddc, &level->vddc);
5526 if (ret)
5527 return ret;
5528
5529
5530 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5531 if (ret)
5532 return ret;
5533
5534 ret = si_populate_std_voltage_value(adev, std_vddc,
5535 level->vddc.index, &level->std_vddc);
5536 if (ret)
5537 return ret;
5538
5539 if (eg_pi->vddci_control) {
5540 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5541 pl->vddci, &level->vddci);
5542 if (ret)
5543 return ret;
5544 }
5545
5546 if (si_pi->vddc_phase_shed_control) {
5547 ret = si_populate_phase_shedding_value(adev,
5548 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5549 pl->vddc,
5550 pl->sclk,
5551 pl->mclk,
5552 &level->vddc);
5553 if (ret)
5554 return ret;
5555 }
5556
5557 level->MaxPoweredUpCU = si_pi->max_cu;
5558
5559 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5560
5561 return ret;
5562}
5563
5564static int si_populate_smc_t(struct amdgpu_device *adev,
5565 struct amdgpu_ps *amdgpu_state,
5566 SISLANDS_SMC_SWSTATE *smc_state)
5567{
5568 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5569 struct si_ps *state = si_get_ps(amdgpu_state);
5570 u32 a_t;
5571 u32 t_l, t_h;
5572 u32 high_bsp;
5573 int i, ret;
5574
5575 if (state->performance_level_count >= 9)
5576 return -EINVAL;
5577
5578 if (state->performance_level_count < 2) {
5579 a_t = CG_R(0xffff) | CG_L(0);
5580 smc_state->levels[0].aT = cpu_to_be32(a_t);
5581 return 0;
5582 }
5583
5584 smc_state->levels[0].aT = cpu_to_be32(0);
5585
5586 for (i = 0; i <= state->performance_level_count - 2; i++) {
5587 ret = r600_calculate_at(
5588 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5589 100 * R600_AH_DFLT,
5590 state->performance_levels[i + 1].sclk,
5591 state->performance_levels[i].sclk,
5592 &t_l,
5593 &t_h);
5594
5595 if (ret) {
5596 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5597 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5598 }
5599
5600 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5601 a_t |= CG_R(t_l * pi->bsp / 20000);
5602 smc_state->levels[i].aT = cpu_to_be32(a_t);
5603
5604 high_bsp = (i == state->performance_level_count - 2) ?
5605 pi->pbsp : pi->bsp;
5606 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5607 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5608 }
5609
5610 return 0;
5611}
5612
5613static int si_disable_ulv(struct amdgpu_device *adev)
5614{
5615 struct si_power_info *si_pi = si_get_pi(adev);
5616 struct si_ulv_param *ulv = &si_pi->ulv;
5617
5618 if (ulv->supported)
5619 return (si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5620 0 : -EINVAL;
5621
5622 return 0;
5623}
5624
5625static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5626 struct amdgpu_ps *amdgpu_state)
5627{
5628 const struct si_power_info *si_pi = si_get_pi(adev);
5629 const struct si_ulv_param *ulv = &si_pi->ulv;
5630 const struct si_ps *state = si_get_ps(amdgpu_state);
5631 int i;
5632
5633 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5634 return false;
5635
5636 /* XXX validate against display requirements! */
5637
5638 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5639 if (adev->clock.current_dispclk <=
5640 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5641 if (ulv->pl.vddc <
5642 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5643 return false;
5644 }
5645 }
5646
5647 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5648 return false;
5649
5650 return true;
5651}
5652
5653static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5654 struct amdgpu_ps *amdgpu_new_state)
5655{
5656 const struct si_power_info *si_pi = si_get_pi(adev);
5657 const struct si_ulv_param *ulv = &si_pi->ulv;
5658
5659 if (ulv->supported) {
5660 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5661 return (si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5662 0 : -EINVAL;
5663 }
5664 return 0;
5665}
5666
5667static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5668 struct amdgpu_ps *amdgpu_state,
5669 SISLANDS_SMC_SWSTATE *smc_state)
5670{
5671 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5672 struct ni_power_info *ni_pi = ni_get_pi(adev);
5673 struct si_power_info *si_pi = si_get_pi(adev);
5674 struct si_ps *state = si_get_ps(amdgpu_state);
5675 int i, ret;
5676 u32 threshold;
5677 u32 sclk_in_sr = 1350; /* ??? */
5678
5679 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5680 return -EINVAL;
5681
5682 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5683
5684 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5685 eg_pi->uvd_enabled = true;
5686 if (eg_pi->smu_uvd_hs)
5687 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5688 } else {
5689 eg_pi->uvd_enabled = false;
5690 }
5691
5692 if (state->dc_compatible)
5693 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5694
5695 smc_state->levelCount = 0;
5696 for (i = 0; i < state->performance_level_count; i++) {
5697 if (eg_pi->sclk_deep_sleep) {
5698 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5699 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5700 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5701 else
5702 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5703 }
5704 }
5705
5706 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5707 &smc_state->levels[i]);
5708 smc_state->levels[i].arbRefreshState =
5709 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5710
5711 if (ret)
5712 return ret;
5713
5714 if (ni_pi->enable_power_containment)
5715 smc_state->levels[i].displayWatermark =
5716 (state->performance_levels[i].sclk < threshold) ?
5717 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5718 else
5719 smc_state->levels[i].displayWatermark = (i < 2) ?
5720 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5721
5722 if (eg_pi->dynamic_ac_timing)
5723 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5724 else
5725 smc_state->levels[i].ACIndex = 0;
5726
5727 smc_state->levelCount++;
5728 }
5729
5730 si_write_smc_soft_register(adev,
5731 SI_SMC_SOFT_REGISTER_watermark_threshold,
5732 threshold / 512);
5733
5734 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5735
5736 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5737 if (ret)
5738 ni_pi->enable_power_containment = false;
5739
5740 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5741 if (ret)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5742 ni_pi->enable_sq_ramping = false;
5743
5744 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5745}
5746
5747static int si_upload_sw_state(struct amdgpu_device *adev,
5748 struct amdgpu_ps *amdgpu_new_state)
5749{
5750 struct si_power_info *si_pi = si_get_pi(adev);
5751 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5752 int ret;
5753 u32 address = si_pi->state_table_start +
5754 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5755 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5756 ((new_state->performance_level_count - 1) *
5757 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5758 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5759
5760 memset(smc_state, 0, state_size);
5761
5762 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5763 if (ret)
5764 return ret;
5765
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5766 return si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5767 state_size, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5768}
5769
5770static int si_upload_ulv_state(struct amdgpu_device *adev)
5771{
5772 struct si_power_info *si_pi = si_get_pi(adev);
5773 struct si_ulv_param *ulv = &si_pi->ulv;
5774 int ret = 0;
5775
5776 if (ulv->supported && ulv->pl.vddc) {
5777 u32 address = si_pi->state_table_start +
5778 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5779 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5780 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5781
5782 memset(smc_state, 0, state_size);
5783
5784 ret = si_populate_ulv_state(adev, smc_state);
5785 if (!ret)
5786 ret = si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5787 state_size, si_pi->sram_end);
5788 }
5789
5790 return ret;
5791}
5792
5793static int si_upload_smc_data(struct amdgpu_device *adev)
5794{
5795 struct amdgpu_crtc *amdgpu_crtc = NULL;
5796 int i;
5797
5798 if (adev->pm.dpm.new_active_crtc_count == 0)
5799 return 0;
5800
5801 for (i = 0; i < adev->mode_info.num_crtc; i++) {
5802 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5803 amdgpu_crtc = adev->mode_info.crtcs[i];
5804 break;
5805 }
5806 }
5807
5808 if (amdgpu_crtc == NULL)
5809 return 0;
5810
5811 if (amdgpu_crtc->line_time <= 0)
5812 return 0;
5813
5814 if (si_write_smc_soft_register(adev,
5815 SI_SMC_SOFT_REGISTER_crtc_index,
5816 amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5817 return 0;
5818
5819 if (si_write_smc_soft_register(adev,
5820 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5821 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5822 return 0;
5823
5824 if (si_write_smc_soft_register(adev,
5825 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5826 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5827 return 0;
5828
5829 return 0;
5830}
5831
5832static int si_set_mc_special_registers(struct amdgpu_device *adev,
5833 struct si_mc_reg_table *table)
5834{
5835 u8 i, j, k;
5836 u32 temp_reg;
5837
5838 for (i = 0, j = table->last; i < table->last; i++) {
5839 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5840 return -EINVAL;
5841 switch (table->mc_reg_address[i].s1) {
5842 case MC_SEQ_MISC1:
5843 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5844 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5845 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5846 for (k = 0; k < table->num_entries; k++)
5847 table->mc_reg_table_entry[k].mc_data[j] =
5848 ((temp_reg & 0xffff0000)) |
5849 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5850 j++;
5851 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5852 return -EINVAL;
5853
5854 temp_reg = RREG32(MC_PMG_CMD_MRS);
5855 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5856 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5857 for (k = 0; k < table->num_entries; k++) {
5858 table->mc_reg_table_entry[k].mc_data[j] =
5859 (temp_reg & 0xffff0000) |
5860 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5861 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5862 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5863 }
5864 j++;
5865 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5866 return -EINVAL;
5867
5868 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5869 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5870 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5871 for (k = 0; k < table->num_entries; k++)
5872 table->mc_reg_table_entry[k].mc_data[j] =
5873 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5874 j++;
5875 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5876 return -EINVAL;
5877 }
5878 break;
5879 case MC_SEQ_RESERVE_M:
5880 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5881 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5882 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5883 for(k = 0; k < table->num_entries; k++)
5884 table->mc_reg_table_entry[k].mc_data[j] =
5885 (temp_reg & 0xffff0000) |
5886 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5887 j++;
5888 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5889 return -EINVAL;
5890 break;
5891 default:
5892 break;
5893 }
5894 }
5895
5896 table->last = j;
5897
5898 return 0;
5899}
5900
5901static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5902{
5903 bool result = true;
5904 switch (in_reg) {
5905 case MC_SEQ_RAS_TIMING:
5906 *out_reg = MC_SEQ_RAS_TIMING_LP;
5907 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5908 case MC_SEQ_CAS_TIMING:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5909 *out_reg = MC_SEQ_CAS_TIMING_LP;
5910 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5911 case MC_SEQ_MISC_TIMING:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5912 *out_reg = MC_SEQ_MISC_TIMING_LP;
5913 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5914 case MC_SEQ_MISC_TIMING2:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5915 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5916 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5917 case MC_SEQ_RD_CTL_D0:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5918 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5919 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5920 case MC_SEQ_RD_CTL_D1:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5921 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5922 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5923 case MC_SEQ_WR_CTL_D0:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5924 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5925 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5926 case MC_SEQ_WR_CTL_D1:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5927 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5928 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5929 case MC_PMG_CMD_EMRS:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5930 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5931 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5932 case MC_PMG_CMD_MRS:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5933 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5934 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5935 case MC_PMG_CMD_MRS1:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5936 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5937 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5938 case MC_SEQ_PMG_TIMING:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5939 *out_reg = MC_SEQ_PMG_TIMING_LP;
5940 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5941 case MC_PMG_CMD_MRS2:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5942 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5943 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5944 case MC_SEQ_WR_CTL_2:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5945 *out_reg = MC_SEQ_WR_CTL_2_LP;
5946 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5947 default:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5948 result = false;
5949 break;
5950 }
5951
5952 return result;
5953}
5954
5955static void si_set_valid_flag(struct si_mc_reg_table *table)
5956{
5957 u8 i, j;
5958
5959 for (i = 0; i < table->last; i++) {
5960 for (j = 1; j < table->num_entries; j++) {
5961 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5962 table->valid_flag |= 1 << i;
5963 break;
5964 }
5965 }
5966 }
5967}
5968
5969static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5970{
5971 u32 i;
5972 u16 address;
5973
5974 for (i = 0; i < table->last; i++)
5975 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5976 address : table->mc_reg_address[i].s1;
5977
5978}
5979
5980static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5981 struct si_mc_reg_table *si_table)
5982{
5983 u8 i, j;
5984
5985 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5986 return -EINVAL;
5987 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5988 return -EINVAL;
5989
5990 for (i = 0; i < table->last; i++)
5991 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5992 si_table->last = table->last;
5993
5994 for (i = 0; i < table->num_entries; i++) {
5995 si_table->mc_reg_table_entry[i].mclk_max =
5996 table->mc_reg_table_entry[i].mclk_max;
5997 for (j = 0; j < table->last; j++) {
5998 si_table->mc_reg_table_entry[i].mc_data[j] =
5999 table->mc_reg_table_entry[i].mc_data[j];
6000 }
6001 }
6002 si_table->num_entries = table->num_entries;
6003
6004 return 0;
6005}
6006
6007static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6008{
6009 struct si_power_info *si_pi = si_get_pi(adev);
6010 struct atom_mc_reg_table *table;
6011 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6012 u8 module_index = rv770_get_memory_module_index(adev);
6013 int ret;
6014
6015 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6016 if (!table)
6017 return -ENOMEM;
6018
6019 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6020 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6021 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6022 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6023 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6024 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6025 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6026 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6027 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6028 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6029 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6030 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6031 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6032 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6033
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6034 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6035 if (ret)
6036 goto init_mc_done;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6037
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6038 ret = si_copy_vbios_mc_reg_table(table, si_table);
6039 if (ret)
6040 goto init_mc_done;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6041
6042 si_set_s0_mc_reg_index(si_table);
6043
6044 ret = si_set_mc_special_registers(adev, si_table);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6045 if (ret)
6046 goto init_mc_done;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6047
6048 si_set_valid_flag(si_table);
6049
6050init_mc_done:
6051 kfree(table);
6052
6053 return ret;
6054
6055}
6056
6057static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6058 SMC_SIslands_MCRegisters *mc_reg_table)
6059{
6060 struct si_power_info *si_pi = si_get_pi(adev);
6061 u32 i, j;
6062
6063 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6064 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6065 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6066 break;
6067 mc_reg_table->address[i].s0 =
6068 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6069 mc_reg_table->address[i].s1 =
6070 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6071 i++;
6072 }
6073 }
6074 mc_reg_table->last = (u8)i;
6075}
6076
6077static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6078 SMC_SIslands_MCRegisterSet *data,
6079 u32 num_entries, u32 valid_flag)
6080{
6081 u32 i, j;
6082
6083 for(i = 0, j = 0; j < num_entries; j++) {
6084 if (valid_flag & (1 << j)) {
6085 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6086 i++;
6087 }
6088 }
6089}
6090
6091static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6092 struct rv7xx_pl *pl,
6093 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6094{
6095 struct si_power_info *si_pi = si_get_pi(adev);
6096 u32 i = 0;
6097
6098 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6099 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6100 break;
6101 }
6102
6103 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6104 --i;
6105
6106 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6107 mc_reg_table_data, si_pi->mc_reg_table.last,
6108 si_pi->mc_reg_table.valid_flag);
6109}
6110
6111static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6112 struct amdgpu_ps *amdgpu_state,
6113 SMC_SIslands_MCRegisters *mc_reg_table)
6114{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6115 struct si_ps *state = si_get_ps(amdgpu_state);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6116 int i;
6117
6118 for (i = 0; i < state->performance_level_count; i++) {
6119 si_convert_mc_reg_table_entry_to_smc(adev,
6120 &state->performance_levels[i],
6121 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6122 }
6123}
6124
6125static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6126 struct amdgpu_ps *amdgpu_boot_state)
6127{
6128 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6129 struct si_power_info *si_pi = si_get_pi(adev);
6130 struct si_ulv_param *ulv = &si_pi->ulv;
6131 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6132
6133 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6134
6135 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6136
6137 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6138
6139 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6140 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6141
6142 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6143 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6144 si_pi->mc_reg_table.last,
6145 si_pi->mc_reg_table.valid_flag);
6146
6147 if (ulv->supported && ulv->pl.vddc != 0)
6148 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6149 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6150 else
6151 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6152 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6153 si_pi->mc_reg_table.last,
6154 si_pi->mc_reg_table.valid_flag);
6155
6156 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6157
6158 return si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6159 (u8 *)smc_mc_reg_table,
6160 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6161}
6162
6163static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6164 struct amdgpu_ps *amdgpu_new_state)
6165{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6166 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6167 struct si_power_info *si_pi = si_get_pi(adev);
6168 u32 address = si_pi->mc_reg_table_start +
6169 offsetof(SMC_SIslands_MCRegisters,
6170 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6171 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6172
6173 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6174
6175 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6176
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6177 return si_copy_bytes_to_smc(adev, address,
6178 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6179 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6180 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6181}
6182
6183static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6184{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6185 if (enable)
6186 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6187 else
6188 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6189}
6190
6191static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6192 struct amdgpu_ps *amdgpu_state)
6193{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6194 struct si_ps *state = si_get_ps(amdgpu_state);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6195 int i;
6196 u16 pcie_speed, max_speed = 0;
6197
6198 for (i = 0; i < state->performance_level_count; i++) {
6199 pcie_speed = state->performance_levels[i].pcie_gen;
6200 if (max_speed < pcie_speed)
6201 max_speed = pcie_speed;
6202 }
6203 return max_speed;
6204}
6205
6206static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6207{
6208 u32 speed_cntl;
6209
6210 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6211 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6212
6213 return (u16)speed_cntl;
6214}
6215
6216static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6217 struct amdgpu_ps *amdgpu_new_state,
6218 struct amdgpu_ps *amdgpu_current_state)
6219{
6220 struct si_power_info *si_pi = si_get_pi(adev);
6221 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6222 enum amdgpu_pcie_gen current_link_speed;
6223
6224 if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6225 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6226 else
6227 current_link_speed = si_pi->force_pcie_gen;
6228
6229 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6230 si_pi->pspp_notify_required = false;
6231 if (target_link_speed > current_link_speed) {
6232 switch (target_link_speed) {
6233#if defined(CONFIG_ACPI)
6234 case AMDGPU_PCIE_GEN3:
6235 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6236 break;
6237 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6238 if (current_link_speed == AMDGPU_PCIE_GEN2)
6239 break;
6240 case AMDGPU_PCIE_GEN2:
6241 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6242 break;
6243#endif
6244 default:
6245 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6246 break;
6247 }
6248 } else {
6249 if (target_link_speed < current_link_speed)
6250 si_pi->pspp_notify_required = true;
6251 }
6252}
6253
6254static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6255 struct amdgpu_ps *amdgpu_new_state,
6256 struct amdgpu_ps *amdgpu_current_state)
6257{
6258 struct si_power_info *si_pi = si_get_pi(adev);
6259 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6260 u8 request;
6261
6262 if (si_pi->pspp_notify_required) {
6263 if (target_link_speed == AMDGPU_PCIE_GEN3)
6264 request = PCIE_PERF_REQ_PECI_GEN3;
6265 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6266 request = PCIE_PERF_REQ_PECI_GEN2;
6267 else
6268 request = PCIE_PERF_REQ_PECI_GEN1;
6269
6270 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6271 (si_get_current_pcie_speed(adev) > 0))
6272 return;
6273
6274#if defined(CONFIG_ACPI)
6275 amdgpu_acpi_pcie_performance_request(adev, request, false);
6276#endif
6277 }
6278}
6279
6280#if 0
6281static int si_ds_request(struct amdgpu_device *adev,
6282 bool ds_status_on, u32 count_write)
6283{
6284 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6285
6286 if (eg_pi->sclk_deep_sleep) {
6287 if (ds_status_on)
6288 return (si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6289 PPSMC_Result_OK) ?
6290 0 : -EINVAL;
6291 else
6292 return (si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6293 PPSMC_Result_OK) ? 0 : -EINVAL;
6294 }
6295 return 0;
6296}
6297#endif
6298
6299static void si_set_max_cu_value(struct amdgpu_device *adev)
6300{
6301 struct si_power_info *si_pi = si_get_pi(adev);
6302
6303 if (adev->asic_type == CHIP_VERDE) {
6304 switch (adev->pdev->device) {
6305 case 0x6820:
6306 case 0x6825:
6307 case 0x6821:
6308 case 0x6823:
6309 case 0x6827:
6310 si_pi->max_cu = 10;
6311 break;
6312 case 0x682D:
6313 case 0x6824:
6314 case 0x682F:
6315 case 0x6826:
6316 si_pi->max_cu = 8;
6317 break;
6318 case 0x6828:
6319 case 0x6830:
6320 case 0x6831:
6321 case 0x6838:
6322 case 0x6839:
6323 case 0x683D:
6324 si_pi->max_cu = 10;
6325 break;
6326 case 0x683B:
6327 case 0x683F:
6328 case 0x6829:
6329 si_pi->max_cu = 8;
6330 break;
6331 default:
6332 si_pi->max_cu = 0;
6333 break;
6334 }
6335 } else {
6336 si_pi->max_cu = 0;
6337 }
6338}
6339
6340static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6341 struct amdgpu_clock_voltage_dependency_table *table)
6342{
6343 u32 i;
6344 int j;
6345 u16 leakage_voltage;
6346
6347 if (table) {
6348 for (i = 0; i < table->count; i++) {
6349 switch (si_get_leakage_voltage_from_leakage_index(adev,
6350 table->entries[i].v,
6351 &leakage_voltage)) {
6352 case 0:
6353 table->entries[i].v = leakage_voltage;
6354 break;
6355 case -EAGAIN:
6356 return -EINVAL;
6357 case -EINVAL:
6358 default:
6359 break;
6360 }
6361 }
6362
6363 for (j = (table->count - 2); j >= 0; j--) {
6364 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6365 table->entries[j].v : table->entries[j + 1].v;
6366 }
6367 }
6368 return 0;
6369}
6370
6371static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6372{
6373 int ret = 0;
6374
6375 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6376 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
Tom St Denisad2473a2016-09-07 08:42:41 -0400[diff] [blame]6377 if (ret)
6378 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6379 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6380 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
Tom St Denisad2473a2016-09-07 08:42:41 -0400[diff] [blame]6381 if (ret)
6382 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6383 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6384 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
Tom St Denisad2473a2016-09-07 08:42:41 -0400[diff] [blame]6385 if (ret)
6386 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6387 return ret;
6388}
6389
6390static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6391 struct amdgpu_ps *amdgpu_new_state,
6392 struct amdgpu_ps *amdgpu_current_state)
6393{
6394 u32 lane_width;
6395 u32 new_lane_width =
6396 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6397 u32 current_lane_width =
6398 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6399
6400 if (new_lane_width != current_lane_width) {
6401 amdgpu_set_pcie_lanes(adev, new_lane_width);
6402 lane_width = amdgpu_get_pcie_lanes(adev);
6403 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6404 }
6405}
6406
6407static void si_dpm_setup_asic(struct amdgpu_device *adev)
6408{
6409 si_read_clock_registers(adev);
6410 si_enable_acpi_power_management(adev);
6411}
6412
6413static int si_thermal_enable_alert(struct amdgpu_device *adev,
6414 bool enable)
6415{
6416 u32 thermal_int = RREG32(CG_THERMAL_INT);
6417
6418 if (enable) {
6419 PPSMC_Result result;
6420
6421 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6422 WREG32(CG_THERMAL_INT, thermal_int);
6423 result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6424 if (result != PPSMC_Result_OK) {
6425 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6426 return -EINVAL;
6427 }
6428 } else {
6429 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6430 WREG32(CG_THERMAL_INT, thermal_int);
6431 }
6432
6433 return 0;
6434}
6435
6436static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6437 int min_temp, int max_temp)
6438{
6439 int low_temp = 0 * 1000;
6440 int high_temp = 255 * 1000;
6441
6442 if (low_temp < min_temp)
6443 low_temp = min_temp;
6444 if (high_temp > max_temp)
6445 high_temp = max_temp;
6446 if (high_temp < low_temp) {
6447 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6448 return -EINVAL;
6449 }
6450
6451 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6452 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6453 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6454
6455 adev->pm.dpm.thermal.min_temp = low_temp;
6456 adev->pm.dpm.thermal.max_temp = high_temp;
6457
6458 return 0;
6459}
6460
6461static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6462{
6463 struct si_power_info *si_pi = si_get_pi(adev);
6464 u32 tmp;
6465
6466 if (si_pi->fan_ctrl_is_in_default_mode) {
6467 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6468 si_pi->fan_ctrl_default_mode = tmp;
6469 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6470 si_pi->t_min = tmp;
6471 si_pi->fan_ctrl_is_in_default_mode = false;
6472 }
6473
6474 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6475 tmp |= TMIN(0);
6476 WREG32(CG_FDO_CTRL2, tmp);
6477
6478 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6479 tmp |= FDO_PWM_MODE(mode);
6480 WREG32(CG_FDO_CTRL2, tmp);
6481}
6482
6483static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6484{
6485 struct si_power_info *si_pi = si_get_pi(adev);
6486 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6487 u32 duty100;
6488 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6489 u16 fdo_min, slope1, slope2;
6490 u32 reference_clock, tmp;
6491 int ret;
6492 u64 tmp64;
6493
6494 if (!si_pi->fan_table_start) {
6495 adev->pm.dpm.fan.ucode_fan_control = false;
6496 return 0;
6497 }
6498
6499 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6500
6501 if (duty100 == 0) {
6502 adev->pm.dpm.fan.ucode_fan_control = false;
6503 return 0;
6504 }
6505
6506 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6507 do_div(tmp64, 10000);
6508 fdo_min = (u16)tmp64;
6509
6510 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6511 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6512
6513 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6514 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6515
6516 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6517 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6518
6519 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6520 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6521 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6522 fan_table.slope1 = cpu_to_be16(slope1);
6523 fan_table.slope2 = cpu_to_be16(slope2);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6524 fan_table.fdo_min = cpu_to_be16(fdo_min);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6525 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6526 fan_table.hys_up = cpu_to_be16(1);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6527 fan_table.hys_slope = cpu_to_be16(1);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6528 fan_table.temp_resp_lim = cpu_to_be16(5);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6529 reference_clock = amdgpu_asic_get_xclk(adev);
6530
6531 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6532 reference_clock) / 1600);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6533 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6534
6535 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6536 fan_table.temp_src = (uint8_t)tmp;
6537
6538 ret = si_copy_bytes_to_smc(adev,
6539 si_pi->fan_table_start,
6540 (u8 *)(&fan_table),
6541 sizeof(fan_table),
6542 si_pi->sram_end);
6543
6544 if (ret) {
6545 DRM_ERROR("Failed to load fan table to the SMC.");
6546 adev->pm.dpm.fan.ucode_fan_control = false;
6547 }
6548
Tom St Denisad2473a2016-09-07 08:42:41 -0400[diff] [blame]6549 return ret;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6550}
6551
6552static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6553{
6554 struct si_power_info *si_pi = si_get_pi(adev);
6555 PPSMC_Result ret;
6556
6557 ret = si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6558 if (ret == PPSMC_Result_OK) {
6559 si_pi->fan_is_controlled_by_smc = true;
6560 return 0;
6561 } else {
6562 return -EINVAL;
6563 }
6564}
6565
6566static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6567{
6568 struct si_power_info *si_pi = si_get_pi(adev);
6569 PPSMC_Result ret;
6570
6571 ret = si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6572
6573 if (ret == PPSMC_Result_OK) {
6574 si_pi->fan_is_controlled_by_smc = false;
6575 return 0;
6576 } else {
6577 return -EINVAL;
6578 }
6579}
6580
6581static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6582 u32 *speed)
6583{
6584 u32 duty, duty100;
6585 u64 tmp64;
6586
6587 if (adev->pm.no_fan)
6588 return -ENOENT;
6589
6590 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6591 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6592
6593 if (duty100 == 0)
6594 return -EINVAL;
6595
6596 tmp64 = (u64)duty * 100;
6597 do_div(tmp64, duty100);
6598 *speed = (u32)tmp64;
6599
6600 if (*speed > 100)
6601 *speed = 100;
6602
6603 return 0;
6604}
6605
6606static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6607 u32 speed)
6608{
6609 struct si_power_info *si_pi = si_get_pi(adev);
6610 u32 tmp;
6611 u32 duty, duty100;
6612 u64 tmp64;
6613
6614 if (adev->pm.no_fan)
6615 return -ENOENT;
6616
6617 if (si_pi->fan_is_controlled_by_smc)
6618 return -EINVAL;
6619
6620 if (speed > 100)
6621 return -EINVAL;
6622
6623 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6624
6625 if (duty100 == 0)
6626 return -EINVAL;
6627
6628 tmp64 = (u64)speed * duty100;
6629 do_div(tmp64, 100);
6630 duty = (u32)tmp64;
6631
6632 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6633 tmp |= FDO_STATIC_DUTY(duty);
6634 WREG32(CG_FDO_CTRL0, tmp);
6635
6636 return 0;
6637}
6638
6639static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6640{
6641 if (mode) {
6642 /* stop auto-manage */
6643 if (adev->pm.dpm.fan.ucode_fan_control)
6644 si_fan_ctrl_stop_smc_fan_control(adev);
6645 si_fan_ctrl_set_static_mode(adev, mode);
6646 } else {
6647 /* restart auto-manage */
6648 if (adev->pm.dpm.fan.ucode_fan_control)
6649 si_thermal_start_smc_fan_control(adev);
6650 else
6651 si_fan_ctrl_set_default_mode(adev);
6652 }
6653}
6654
6655static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6656{
6657 struct si_power_info *si_pi = si_get_pi(adev);
6658 u32 tmp;
6659
6660 if (si_pi->fan_is_controlled_by_smc)
6661 return 0;
6662
6663 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6664 return (tmp >> FDO_PWM_MODE_SHIFT);
6665}
6666
6667#if 0
6668static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6669 u32 *speed)
6670{
6671 u32 tach_period;
6672 u32 xclk = amdgpu_asic_get_xclk(adev);
6673
6674 if (adev->pm.no_fan)
6675 return -ENOENT;
6676
6677 if (adev->pm.fan_pulses_per_revolution == 0)
6678 return -ENOENT;
6679
6680 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6681 if (tach_period == 0)
6682 return -ENOENT;
6683
6684 *speed = 60 * xclk * 10000 / tach_period;
6685
6686 return 0;
6687}
6688
6689static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6690 u32 speed)
6691{
6692 u32 tach_period, tmp;
6693 u32 xclk = amdgpu_asic_get_xclk(adev);
6694
6695 if (adev->pm.no_fan)
6696 return -ENOENT;
6697
6698 if (adev->pm.fan_pulses_per_revolution == 0)
6699 return -ENOENT;
6700
6701 if ((speed < adev->pm.fan_min_rpm) ||
6702 (speed > adev->pm.fan_max_rpm))
6703 return -EINVAL;
6704
6705 if (adev->pm.dpm.fan.ucode_fan_control)
6706 si_fan_ctrl_stop_smc_fan_control(adev);
6707
6708 tach_period = 60 * xclk * 10000 / (8 * speed);
6709 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6710 tmp |= TARGET_PERIOD(tach_period);
6711 WREG32(CG_TACH_CTRL, tmp);
6712
6713 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6714
6715 return 0;
6716}
6717#endif
6718
6719static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6720{
6721 struct si_power_info *si_pi = si_get_pi(adev);
6722 u32 tmp;
6723
6724 if (!si_pi->fan_ctrl_is_in_default_mode) {
6725 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6726 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6727 WREG32(CG_FDO_CTRL2, tmp);
6728
6729 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6730 tmp |= TMIN(si_pi->t_min);
6731 WREG32(CG_FDO_CTRL2, tmp);
6732 si_pi->fan_ctrl_is_in_default_mode = true;
6733 }
6734}
6735
6736static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6737{
6738 if (adev->pm.dpm.fan.ucode_fan_control) {
6739 si_fan_ctrl_start_smc_fan_control(adev);
6740 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6741 }
6742}
6743
6744static void si_thermal_initialize(struct amdgpu_device *adev)
6745{
6746 u32 tmp;
6747
6748 if (adev->pm.fan_pulses_per_revolution) {
6749 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6750 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6751 WREG32(CG_TACH_CTRL, tmp);
6752 }
6753
6754 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6755 tmp |= TACH_PWM_RESP_RATE(0x28);
6756 WREG32(CG_FDO_CTRL2, tmp);
6757}
6758
6759static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6760{
6761 int ret;
6762
6763 si_thermal_initialize(adev);
6764 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6765 if (ret)
6766 return ret;
6767 ret = si_thermal_enable_alert(adev, true);
6768 if (ret)
6769 return ret;
6770 if (adev->pm.dpm.fan.ucode_fan_control) {
6771 ret = si_halt_smc(adev);
6772 if (ret)
6773 return ret;
6774 ret = si_thermal_setup_fan_table(adev);
6775 if (ret)
6776 return ret;
6777 ret = si_resume_smc(adev);
6778 if (ret)
6779 return ret;
6780 si_thermal_start_smc_fan_control(adev);
6781 }
6782
6783 return 0;
6784}
6785
6786static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6787{
6788 if (!adev->pm.no_fan) {
6789 si_fan_ctrl_set_default_mode(adev);
6790 si_fan_ctrl_stop_smc_fan_control(adev);
6791 }
6792}
6793
6794static int si_dpm_enable(struct amdgpu_device *adev)
6795{
6796 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6797 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6798 struct si_power_info *si_pi = si_get_pi(adev);
6799 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6800 int ret;
6801
6802 if (si_is_smc_running(adev))
6803 return -EINVAL;
6804 if (pi->voltage_control || si_pi->voltage_control_svi2)
6805 si_enable_voltage_control(adev, true);
6806 if (pi->mvdd_control)
6807 si_get_mvdd_configuration(adev);
6808 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6809 ret = si_construct_voltage_tables(adev);
6810 if (ret) {
6811 DRM_ERROR("si_construct_voltage_tables failed\n");
6812 return ret;
6813 }
6814 }
6815 if (eg_pi->dynamic_ac_timing) {
6816 ret = si_initialize_mc_reg_table(adev);
6817 if (ret)
6818 eg_pi->dynamic_ac_timing = false;
6819 }
6820 if (pi->dynamic_ss)
6821 si_enable_spread_spectrum(adev, true);
6822 if (pi->thermal_protection)
6823 si_enable_thermal_protection(adev, true);
6824 si_setup_bsp(adev);
6825 si_program_git(adev);
6826 si_program_tp(adev);
6827 si_program_tpp(adev);
6828 si_program_sstp(adev);
6829 si_enable_display_gap(adev);
6830 si_program_vc(adev);
6831 ret = si_upload_firmware(adev);
6832 if (ret) {
6833 DRM_ERROR("si_upload_firmware failed\n");
6834 return ret;
6835 }
6836 ret = si_process_firmware_header(adev);
6837 if (ret) {
6838 DRM_ERROR("si_process_firmware_header failed\n");
6839 return ret;
6840 }
6841 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6842 if (ret) {
6843 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6844 return ret;
6845 }
6846 ret = si_init_smc_table(adev);
6847 if (ret) {
6848 DRM_ERROR("si_init_smc_table failed\n");
6849 return ret;
6850 }
6851 ret = si_init_smc_spll_table(adev);
6852 if (ret) {
6853 DRM_ERROR("si_init_smc_spll_table failed\n");
6854 return ret;
6855 }
6856 ret = si_init_arb_table_index(adev);
6857 if (ret) {
6858 DRM_ERROR("si_init_arb_table_index failed\n");
6859 return ret;
6860 }
6861 if (eg_pi->dynamic_ac_timing) {
6862 ret = si_populate_mc_reg_table(adev, boot_ps);
6863 if (ret) {
6864 DRM_ERROR("si_populate_mc_reg_table failed\n");
6865 return ret;
6866 }
6867 }
6868 ret = si_initialize_smc_cac_tables(adev);
6869 if (ret) {
6870 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6871 return ret;
6872 }
6873 ret = si_initialize_hardware_cac_manager(adev);
6874 if (ret) {
6875 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6876 return ret;
6877 }
6878 ret = si_initialize_smc_dte_tables(adev);
6879 if (ret) {
6880 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6881 return ret;
6882 }
6883 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6884 if (ret) {
6885 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6886 return ret;
6887 }
6888 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6889 if (ret) {
6890 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6891 return ret;
6892 }
6893 si_program_response_times(adev);
6894 si_program_ds_registers(adev);
6895 si_dpm_start_smc(adev);
6896 ret = si_notify_smc_display_change(adev, false);
6897 if (ret) {
6898 DRM_ERROR("si_notify_smc_display_change failed\n");
6899 return ret;
6900 }
6901 si_enable_sclk_control(adev, true);
6902 si_start_dpm(adev);
6903
6904 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6905 si_thermal_start_thermal_controller(adev);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6906 ni_update_current_ps(adev, boot_ps);
6907
6908 return 0;
6909}
6910
6911static int si_set_temperature_range(struct amdgpu_device *adev)
6912{
6913 int ret;
6914
6915 ret = si_thermal_enable_alert(adev, false);
6916 if (ret)
6917 return ret;
6918 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6919 if (ret)
6920 return ret;
6921 ret = si_thermal_enable_alert(adev, true);
6922 if (ret)
6923 return ret;
6924
6925 return ret;
6926}
6927
6928static void si_dpm_disable(struct amdgpu_device *adev)
6929{
6930 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6931 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6932
6933 if (!si_is_smc_running(adev))
6934 return;
6935 si_thermal_stop_thermal_controller(adev);
6936 si_disable_ulv(adev);
6937 si_clear_vc(adev);
6938 if (pi->thermal_protection)
6939 si_enable_thermal_protection(adev, false);
6940 si_enable_power_containment(adev, boot_ps, false);
6941 si_enable_smc_cac(adev, boot_ps, false);
6942 si_enable_spread_spectrum(adev, false);
6943 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6944 si_stop_dpm(adev);
6945 si_reset_to_default(adev);
6946 si_dpm_stop_smc(adev);
6947 si_force_switch_to_arb_f0(adev);
6948
6949 ni_update_current_ps(adev, boot_ps);
6950}
6951
6952static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6953{
6954 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6955 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6956 struct amdgpu_ps *new_ps = &requested_ps;
6957
6958 ni_update_requested_ps(adev, new_ps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6959 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6960
6961 return 0;
6962}
6963
6964static int si_power_control_set_level(struct amdgpu_device *adev)
6965{
6966 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6967 int ret;
6968
6969 ret = si_restrict_performance_levels_before_switch(adev);
6970 if (ret)
6971 return ret;
6972 ret = si_halt_smc(adev);
6973 if (ret)
6974 return ret;
6975 ret = si_populate_smc_tdp_limits(adev, new_ps);
6976 if (ret)
6977 return ret;
6978 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6979 if (ret)
6980 return ret;
6981 ret = si_resume_smc(adev);
6982 if (ret)
6983 return ret;
6984 ret = si_set_sw_state(adev);
6985 if (ret)
6986 return ret;
6987 return 0;
6988}
6989
6990static int si_dpm_set_power_state(struct amdgpu_device *adev)
6991{
6992 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6993 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6994 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
6995 int ret;
6996
6997 ret = si_disable_ulv(adev);
6998 if (ret) {
6999 DRM_ERROR("si_disable_ulv failed\n");
7000 return ret;
7001 }
7002 ret = si_restrict_performance_levels_before_switch(adev);
7003 if (ret) {
7004 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7005 return ret;
7006 }
7007 if (eg_pi->pcie_performance_request)
7008 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7009 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7010 ret = si_enable_power_containment(adev, new_ps, false);
7011 if (ret) {
7012 DRM_ERROR("si_enable_power_containment failed\n");
7013 return ret;
7014 }
7015 ret = si_enable_smc_cac(adev, new_ps, false);
7016 if (ret) {
7017 DRM_ERROR("si_enable_smc_cac failed\n");
7018 return ret;
7019 }
7020 ret = si_halt_smc(adev);
7021 if (ret) {
7022 DRM_ERROR("si_halt_smc failed\n");
7023 return ret;
7024 }
7025 ret = si_upload_sw_state(adev, new_ps);
7026 if (ret) {
7027 DRM_ERROR("si_upload_sw_state failed\n");
7028 return ret;
7029 }
7030 ret = si_upload_smc_data(adev);
7031 if (ret) {
7032 DRM_ERROR("si_upload_smc_data failed\n");
7033 return ret;
7034 }
7035 ret = si_upload_ulv_state(adev);
7036 if (ret) {
7037 DRM_ERROR("si_upload_ulv_state failed\n");
7038 return ret;
7039 }
7040 if (eg_pi->dynamic_ac_timing) {
7041 ret = si_upload_mc_reg_table(adev, new_ps);
7042 if (ret) {
7043 DRM_ERROR("si_upload_mc_reg_table failed\n");
7044 return ret;
7045 }
7046 }
7047 ret = si_program_memory_timing_parameters(adev, new_ps);
7048 if (ret) {
7049 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7050 return ret;
7051 }
7052 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7053
7054 ret = si_resume_smc(adev);
7055 if (ret) {
7056 DRM_ERROR("si_resume_smc failed\n");
7057 return ret;
7058 }
7059 ret = si_set_sw_state(adev);
7060 if (ret) {
7061 DRM_ERROR("si_set_sw_state failed\n");
7062 return ret;
7063 }
7064 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7065 if (eg_pi->pcie_performance_request)
7066 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7067 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7068 if (ret) {
7069 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7070 return ret;
7071 }
7072 ret = si_enable_smc_cac(adev, new_ps, true);
7073 if (ret) {
7074 DRM_ERROR("si_enable_smc_cac failed\n");
7075 return ret;
7076 }
7077 ret = si_enable_power_containment(adev, new_ps, true);
7078 if (ret) {
7079 DRM_ERROR("si_enable_power_containment failed\n");
7080 return ret;
7081 }
7082
7083 ret = si_power_control_set_level(adev);
7084 if (ret) {
7085 DRM_ERROR("si_power_control_set_level failed\n");
7086 return ret;
7087 }
7088
7089 return 0;
7090}
7091
7092static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7093{
7094 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7095 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7096
7097 ni_update_current_ps(adev, new_ps);
7098}
7099
7100#if 0
7101void si_dpm_reset_asic(struct amdgpu_device *adev)
7102{
7103 si_restrict_performance_levels_before_switch(adev);
7104 si_disable_ulv(adev);
7105 si_set_boot_state(adev);
7106}
7107#endif
7108
7109static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7110{
7111 si_program_display_gap(adev);
7112}
7113
7114
7115static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7116 struct amdgpu_ps *rps,
7117 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7118 u8 table_rev)
7119{
7120 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7121 rps->class = le16_to_cpu(non_clock_info->usClassification);
7122 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7123
7124 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7125 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7126 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7127 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7128 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7129 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7130 } else {
7131 rps->vclk = 0;
7132 rps->dclk = 0;
7133 }
7134
7135 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7136 adev->pm.dpm.boot_ps = rps;
7137 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7138 adev->pm.dpm.uvd_ps = rps;
7139}
7140
7141static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7142 struct amdgpu_ps *rps, int index,
7143 union pplib_clock_info *clock_info)
7144{
7145 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7146 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7147 struct si_power_info *si_pi = si_get_pi(adev);
7148 struct si_ps *ps = si_get_ps(rps);
7149 u16 leakage_voltage;
7150 struct rv7xx_pl *pl = &ps->performance_levels[index];
7151 int ret;
7152
7153 ps->performance_level_count = index + 1;
7154
7155 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7156 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7157 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7158 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7159
7160 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7161 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7162 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7163 pl->pcie_gen = r600_get_pcie_gen_support(adev,
7164 si_pi->sys_pcie_mask,
7165 si_pi->boot_pcie_gen,
7166 clock_info->si.ucPCIEGen);
7167
7168 /* patch up vddc if necessary */
7169 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7170 &leakage_voltage);
7171 if (ret == 0)
7172 pl->vddc = leakage_voltage;
7173
7174 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7175 pi->acpi_vddc = pl->vddc;
7176 eg_pi->acpi_vddci = pl->vddci;
7177 si_pi->acpi_pcie_gen = pl->pcie_gen;
7178 }
7179
7180 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7181 index == 0) {
7182 /* XXX disable for A0 tahiti */
7183 si_pi->ulv.supported = false;
7184 si_pi->ulv.pl = *pl;
7185 si_pi->ulv.one_pcie_lane_in_ulv = false;
7186 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7187 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7188 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7189 }
7190
7191 if (pi->min_vddc_in_table > pl->vddc)
7192 pi->min_vddc_in_table = pl->vddc;
7193
7194 if (pi->max_vddc_in_table < pl->vddc)
7195 pi->max_vddc_in_table = pl->vddc;
7196
7197 /* patch up boot state */
7198 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7199 u16 vddc, vddci, mvdd;
7200 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7201 pl->mclk = adev->clock.default_mclk;
7202 pl->sclk = adev->clock.default_sclk;
7203 pl->vddc = vddc;
7204 pl->vddci = vddci;
7205 si_pi->mvdd_bootup_value = mvdd;
7206 }
7207
7208 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7209 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7210 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7211 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7212 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7213 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7214 }
7215}
7216
7217union pplib_power_state {
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7218 struct _ATOM_PPLIB_STATE v1;
7219 struct _ATOM_PPLIB_STATE_V2 v2;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7220};
7221
7222static int si_parse_power_table(struct amdgpu_device *adev)
7223{
7224 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7225 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7226 union pplib_power_state *power_state;
7227 int i, j, k, non_clock_array_index, clock_array_index;
7228 union pplib_clock_info *clock_info;
7229 struct _StateArray *state_array;
7230 struct _ClockInfoArray *clock_info_array;
7231 struct _NonClockInfoArray *non_clock_info_array;
7232 union power_info *power_info;
7233 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7234 u16 data_offset;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7235 u8 frev, crev;
7236 u8 *power_state_offset;
7237 struct si_ps *ps;
7238
7239 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7240 &frev, &crev, &data_offset))
7241 return -EINVAL;
7242 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7243
7244 amdgpu_add_thermal_controller(adev);
7245
7246 state_array = (struct _StateArray *)
7247 (mode_info->atom_context->bios + data_offset +
7248 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7249 clock_info_array = (struct _ClockInfoArray *)
7250 (mode_info->atom_context->bios + data_offset +
7251 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7252 non_clock_info_array = (struct _NonClockInfoArray *)
7253 (mode_info->atom_context->bios + data_offset +
7254 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7255
7256 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7257 state_array->ucNumEntries, GFP_KERNEL);
7258 if (!adev->pm.dpm.ps)
7259 return -ENOMEM;
7260 power_state_offset = (u8 *)state_array->states;
7261 for (i = 0; i < state_array->ucNumEntries; i++) {
7262 u8 *idx;
7263 power_state = (union pplib_power_state *)power_state_offset;
7264 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7265 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7266 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7267 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL);
7268 if (ps == NULL) {
7269 kfree(adev->pm.dpm.ps);
7270 return -ENOMEM;
7271 }
7272 adev->pm.dpm.ps[i].ps_priv = ps;
7273 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7274 non_clock_info,
7275 non_clock_info_array->ucEntrySize);
7276 k = 0;
7277 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7278 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7279 clock_array_index = idx[j];
7280 if (clock_array_index >= clock_info_array->ucNumEntries)
7281 continue;
7282 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7283 break;
7284 clock_info = (union pplib_clock_info *)
7285 ((u8 *)&clock_info_array->clockInfo[0] +
7286 (clock_array_index * clock_info_array->ucEntrySize));
7287 si_parse_pplib_clock_info(adev,
7288 &adev->pm.dpm.ps[i], k,
7289 clock_info);
7290 k++;
7291 }
7292 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7293 }
7294 adev->pm.dpm.num_ps = state_array->ucNumEntries;
7295
7296 /* fill in the vce power states */
7297 for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
7298 u32 sclk, mclk;
7299 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7300 clock_info = (union pplib_clock_info *)
7301 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7302 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7303 sclk |= clock_info->si.ucEngineClockHigh << 16;
7304 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7305 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7306 adev->pm.dpm.vce_states[i].sclk = sclk;
7307 adev->pm.dpm.vce_states[i].mclk = mclk;
7308 }
7309
7310 return 0;
7311}
7312
7313static int si_dpm_init(struct amdgpu_device *adev)
7314{
7315 struct rv7xx_power_info *pi;
7316 struct evergreen_power_info *eg_pi;
7317 struct ni_power_info *ni_pi;
7318 struct si_power_info *si_pi;
7319 struct atom_clock_dividers dividers;
7320 int ret;
7321 u32 mask;
7322
7323 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7324 if (si_pi == NULL)
7325 return -ENOMEM;
7326 adev->pm.dpm.priv = si_pi;
7327 ni_pi = &si_pi->ni;
7328 eg_pi = &ni_pi->eg;
7329 pi = &eg_pi->rv7xx;
7330
7331 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7332 if (ret)
7333 si_pi->sys_pcie_mask = 0;
7334 else
7335 si_pi->sys_pcie_mask = mask;
7336 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7337 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7338
7339 si_set_max_cu_value(adev);
7340
7341 rv770_get_max_vddc(adev);
7342 si_get_leakage_vddc(adev);
7343 si_patch_dependency_tables_based_on_leakage(adev);
7344
7345 pi->acpi_vddc = 0;
7346 eg_pi->acpi_vddci = 0;
7347 pi->min_vddc_in_table = 0;
7348 pi->max_vddc_in_table = 0;
7349
7350 ret = amdgpu_get_platform_caps(adev);
7351 if (ret)
7352 return ret;
7353
7354 ret = amdgpu_parse_extended_power_table(adev);
7355 if (ret)
7356 return ret;
7357
7358 ret = si_parse_power_table(adev);
7359 if (ret)
7360 return ret;
7361
7362 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7363 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7364 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7365 amdgpu_free_extended_power_table(adev);
7366 return -ENOMEM;
7367 }
7368 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7369 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7370 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7371 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7372 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7373 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7374 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7375 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7376 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7377
7378 if (adev->pm.dpm.voltage_response_time == 0)
7379 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7380 if (adev->pm.dpm.backbias_response_time == 0)
7381 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7382
7383 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7384 0, false, &dividers);
7385 if (ret)
7386 pi->ref_div = dividers.ref_div + 1;
7387 else
7388 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7389
7390 eg_pi->smu_uvd_hs = false;
7391
7392 pi->mclk_strobe_mode_threshold = 40000;
7393 if (si_is_special_1gb_platform(adev))
7394 pi->mclk_stutter_mode_threshold = 0;
7395 else
7396 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7397 pi->mclk_edc_enable_threshold = 40000;
7398 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7399
7400 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7401
7402 pi->voltage_control =
7403 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7404 VOLTAGE_OBJ_GPIO_LUT);
7405 if (!pi->voltage_control) {
7406 si_pi->voltage_control_svi2 =
7407 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7408 VOLTAGE_OBJ_SVID2);
7409 if (si_pi->voltage_control_svi2)
7410 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7411 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7412 }
7413
7414 pi->mvdd_control =
7415 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7416 VOLTAGE_OBJ_GPIO_LUT);
7417
7418 eg_pi->vddci_control =
7419 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7420 VOLTAGE_OBJ_GPIO_LUT);
7421 if (!eg_pi->vddci_control)
7422 si_pi->vddci_control_svi2 =
7423 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7424 VOLTAGE_OBJ_SVID2);
7425
7426 si_pi->vddc_phase_shed_control =
7427 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7428 VOLTAGE_OBJ_PHASE_LUT);
7429
7430 rv770_get_engine_memory_ss(adev);
7431
7432 pi->asi = RV770_ASI_DFLT;
7433 pi->pasi = CYPRESS_HASI_DFLT;
7434 pi->vrc = SISLANDS_VRC_DFLT;
7435
7436 pi->gfx_clock_gating = true;
7437
7438 eg_pi->sclk_deep_sleep = true;
7439 si_pi->sclk_deep_sleep_above_low = false;
7440
7441 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7442 pi->thermal_protection = true;
7443 else
7444 pi->thermal_protection = false;
7445
7446 eg_pi->dynamic_ac_timing = true;
7447
7448 eg_pi->light_sleep = true;
7449#if defined(CONFIG_ACPI)
7450 eg_pi->pcie_performance_request =
7451 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7452#else
7453 eg_pi->pcie_performance_request = false;
7454#endif
7455
7456 si_pi->sram_end = SMC_RAM_END;
7457
7458 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7459 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7460 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7461 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7462 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7463 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7464 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7465
7466 si_initialize_powertune_defaults(adev);
7467
7468 /* make sure dc limits are valid */
7469 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7470 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7471 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7472 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7473
7474 si_pi->fan_ctrl_is_in_default_mode = true;
7475
7476 return 0;
7477}
7478
7479static void si_dpm_fini(struct amdgpu_device *adev)
7480{
7481 int i;
7482
Tom St Denis9623e4b2016-09-06 09:42:55 -0400[diff] [blame]7483 if (adev->pm.dpm.ps)
7484 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7485 kfree(adev->pm.dpm.ps[i].ps_priv);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7486 kfree(adev->pm.dpm.ps);
7487 kfree(adev->pm.dpm.priv);
7488 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7489 amdgpu_free_extended_power_table(adev);
7490}
7491
7492static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7493 struct seq_file *m)
7494{
7495 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7496 struct amdgpu_ps *rps = &eg_pi->current_rps;
7497 struct si_ps *ps = si_get_ps(rps);
7498 struct rv7xx_pl *pl;
7499 u32 current_index =
7500 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7501 CURRENT_STATE_INDEX_SHIFT;
7502
7503 if (current_index >= ps->performance_level_count) {
7504 seq_printf(m, "invalid dpm profile %d\n", current_index);
7505 } else {
7506 pl = &ps->performance_levels[current_index];
7507 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7508 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7509 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7510 }
7511}
7512
7513static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7514 struct amdgpu_irq_src *source,
7515 unsigned type,
7516 enum amdgpu_interrupt_state state)
7517{
7518 u32 cg_thermal_int;
7519
7520 switch (type) {
7521 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7522 switch (state) {
7523 case AMDGPU_IRQ_STATE_DISABLE:
7524 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7525 cg_thermal_int |= THERM_INT_MASK_HIGH;
7526 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7527 break;
7528 case AMDGPU_IRQ_STATE_ENABLE:
7529 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7530 cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7531 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7532 break;
7533 default:
7534 break;
7535 }
7536 break;
7537
7538 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7539 switch (state) {
7540 case AMDGPU_IRQ_STATE_DISABLE:
7541 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7542 cg_thermal_int |= THERM_INT_MASK_LOW;
7543 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7544 break;
7545 case AMDGPU_IRQ_STATE_ENABLE:
7546 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7547 cg_thermal_int &= ~THERM_INT_MASK_LOW;
7548 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7549 break;
7550 default:
7551 break;
7552 }
7553 break;
7554
7555 default:
7556 break;
7557 }
7558 return 0;
7559}
7560
7561static int si_dpm_process_interrupt(struct amdgpu_device *adev,
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame^]7562 struct amdgpu_irq_src *source,
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7563 struct amdgpu_iv_entry *entry)
7564{
7565 bool queue_thermal = false;
7566
7567 if (entry == NULL)
7568 return -EINVAL;
7569
7570 switch (entry->src_id) {
7571 case 230: /* thermal low to high */
7572 DRM_DEBUG("IH: thermal low to high\n");
7573 adev->pm.dpm.thermal.high_to_low = false;
7574 queue_thermal = true;
7575 break;
7576 case 231: /* thermal high to low */
7577 DRM_DEBUG("IH: thermal high to low\n");
7578 adev->pm.dpm.thermal.high_to_low = true;
7579 queue_thermal = true;
7580 break;
7581 default:
7582 break;
7583 }
7584
7585 if (queue_thermal)
7586 schedule_work(&adev->pm.dpm.thermal.work);
7587
7588 return 0;
7589}
7590
7591static int si_dpm_late_init(void *handle)
7592{
7593 int ret;
7594 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7595
7596 if (!amdgpu_dpm)
7597 return 0;
7598
7599 /* init the sysfs and debugfs files late */
7600 ret = amdgpu_pm_sysfs_init(adev);
7601 if (ret)
7602 return ret;
7603
7604 ret = si_set_temperature_range(adev);
7605 if (ret)
7606 return ret;
7607#if 0 //TODO ?
7608 si_dpm_powergate_uvd(adev, true);
7609#endif
7610 return 0;
7611}
7612
7613/**
7614 * si_dpm_init_microcode - load ucode images from disk
7615 *
7616 * @adev: amdgpu_device pointer
7617 *
7618 * Use the firmware interface to load the ucode images into
7619 * the driver (not loaded into hw).
7620 * Returns 0 on success, error on failure.
7621 */
7622static int si_dpm_init_microcode(struct amdgpu_device *adev)
7623{
7624 const char *chip_name;
7625 char fw_name[30];
7626 int err;
7627
7628 DRM_DEBUG("\n");
7629 switch (adev->asic_type) {
7630 case CHIP_TAHITI:
7631 chip_name = "tahiti";
7632 break;
7633 case CHIP_PITCAIRN:
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]7634 if ((adev->pdev->revision == 0x81) ||
7635 (adev->pdev->device == 0x6810) ||
7636 (adev->pdev->device == 0x6811) ||
7637 (adev->pdev->device == 0x6816) ||
7638 (adev->pdev->device == 0x6817) ||
7639 (adev->pdev->device == 0x6806))
7640 chip_name = "pitcairn_k";
7641 else
7642 chip_name = "pitcairn";
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7643 break;
7644 case CHIP_VERDE:
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]7645 if ((adev->pdev->revision == 0x81) ||
7646 (adev->pdev->revision == 0x83) ||
7647 (adev->pdev->revision == 0x87) ||
7648 (adev->pdev->device == 0x6820) ||
7649 (adev->pdev->device == 0x6821) ||
7650 (adev->pdev->device == 0x6822) ||
7651 (adev->pdev->device == 0x6823) ||
7652 (adev->pdev->device == 0x682A) ||
7653 (adev->pdev->device == 0x682B))
7654 chip_name = "verde_k";
7655 else
7656 chip_name = "verde";
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7657 break;
7658 case CHIP_OLAND:
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]7659 if ((adev->pdev->revision == 0xC7) ||
7660 (adev->pdev->revision == 0x80) ||
7661 (adev->pdev->revision == 0x81) ||
7662 (adev->pdev->revision == 0x83) ||
7663 (adev->pdev->device == 0x6604) ||
7664 (adev->pdev->device == 0x6605))
7665 chip_name = "oland_k";
7666 else
7667 chip_name = "oland";
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7668 break;
7669 case CHIP_HAINAN:
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]7670 if ((adev->pdev->revision == 0x81) ||
7671 (adev->pdev->revision == 0x83) ||
7672 (adev->pdev->revision == 0xC3) ||
7673 (adev->pdev->device == 0x6664) ||
7674 (adev->pdev->device == 0x6665) ||
7675 (adev->pdev->device == 0x6667))
7676 chip_name = "hainan_k";
7677 else
7678 chip_name = "hainan";
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7679 break;
7680 default: BUG();
7681 }
7682
7683 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7684 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7685 if (err)
7686 goto out;
7687 err = amdgpu_ucode_validate(adev->pm.fw);
7688
7689out:
7690 if (err) {
Huang Rui84b77332016-08-31 13:23:18 +0800[diff] [blame]7691 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7692 err, fw_name);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7693 release_firmware(adev->pm.fw);
7694 adev->pm.fw = NULL;
7695 }
7696 return err;
7697
7698}
7699
7700static int si_dpm_sw_init(void *handle)
7701{
7702 int ret;
7703 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7704
7705 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
7706 if (ret)
7707 return ret;
7708
7709 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
7710 if (ret)
7711 return ret;
7712
7713 /* default to balanced state */
7714 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7715 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7716 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
7717 adev->pm.default_sclk = adev->clock.default_sclk;
7718 adev->pm.default_mclk = adev->clock.default_mclk;
7719 adev->pm.current_sclk = adev->clock.default_sclk;
7720 adev->pm.current_mclk = adev->clock.default_mclk;
7721 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7722
7723 if (amdgpu_dpm == 0)
7724 return 0;
7725
7726 ret = si_dpm_init_microcode(adev);
7727 if (ret)
7728 return ret;
7729
7730 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7731 mutex_lock(&adev->pm.mutex);
7732 ret = si_dpm_init(adev);
7733 if (ret)
7734 goto dpm_failed;
7735 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7736 if (amdgpu_dpm == 1)
7737 amdgpu_pm_print_power_states(adev);
7738 mutex_unlock(&adev->pm.mutex);
7739 DRM_INFO("amdgpu: dpm initialized\n");
7740
7741 return 0;
7742
7743dpm_failed:
7744 si_dpm_fini(adev);
7745 mutex_unlock(&adev->pm.mutex);
7746 DRM_ERROR("amdgpu: dpm initialization failed\n");
7747 return ret;
7748}
7749
7750static int si_dpm_sw_fini(void *handle)
7751{
7752 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7753
7754 mutex_lock(&adev->pm.mutex);
7755 amdgpu_pm_sysfs_fini(adev);
7756 si_dpm_fini(adev);
7757 mutex_unlock(&adev->pm.mutex);
7758
7759 return 0;
7760}
7761
7762static int si_dpm_hw_init(void *handle)
7763{
7764 int ret;
7765
7766 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7767
7768 if (!amdgpu_dpm)
7769 return 0;
7770
7771 mutex_lock(&adev->pm.mutex);
7772 si_dpm_setup_asic(adev);
7773 ret = si_dpm_enable(adev);
7774 if (ret)
7775 adev->pm.dpm_enabled = false;
7776 else
7777 adev->pm.dpm_enabled = true;
7778 mutex_unlock(&adev->pm.mutex);
7779
7780 return ret;
7781}
7782
7783static int si_dpm_hw_fini(void *handle)
7784{
7785 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7786
7787 if (adev->pm.dpm_enabled) {
7788 mutex_lock(&adev->pm.mutex);
7789 si_dpm_disable(adev);
7790 mutex_unlock(&adev->pm.mutex);
7791 }
7792
7793 return 0;
7794}
7795
7796static int si_dpm_suspend(void *handle)
7797{
7798 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7799
7800 if (adev->pm.dpm_enabled) {
7801 mutex_lock(&adev->pm.mutex);
7802 /* disable dpm */
7803 si_dpm_disable(adev);
7804 /* reset the power state */
7805 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7806 mutex_unlock(&adev->pm.mutex);
7807 }
7808 return 0;
7809}
7810
7811static int si_dpm_resume(void *handle)
7812{
7813 int ret;
7814 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7815
7816 if (adev->pm.dpm_enabled) {
7817 /* asic init will reset to the boot state */
7818 mutex_lock(&adev->pm.mutex);
7819 si_dpm_setup_asic(adev);
7820 ret = si_dpm_enable(adev);
7821 if (ret)
7822 adev->pm.dpm_enabled = false;
7823 else
7824 adev->pm.dpm_enabled = true;
7825 mutex_unlock(&adev->pm.mutex);
7826 if (adev->pm.dpm_enabled)
7827 amdgpu_pm_compute_clocks(adev);
7828 }
7829 return 0;
7830}
7831
7832static bool si_dpm_is_idle(void *handle)
7833{
7834 /* XXX */
7835 return true;
7836}
7837
7838static int si_dpm_wait_for_idle(void *handle)
7839{
7840 /* XXX */
7841 return 0;
7842}
7843
7844static int si_dpm_soft_reset(void *handle)
7845{
7846 return 0;
7847}
7848
7849static int si_dpm_set_clockgating_state(void *handle,
7850 enum amd_clockgating_state state)
7851{
7852 return 0;
7853}
7854
7855static int si_dpm_set_powergating_state(void *handle,
7856 enum amd_powergating_state state)
7857{
7858 return 0;
7859}
7860
7861/* get temperature in millidegrees */
7862static int si_dpm_get_temp(struct amdgpu_device *adev)
7863{
7864 u32 temp;
7865 int actual_temp = 0;
7866
7867 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7868 CTF_TEMP_SHIFT;
7869
7870 if (temp & 0x200)
7871 actual_temp = 255;
7872 else
7873 actual_temp = temp & 0x1ff;
7874
7875 actual_temp = (actual_temp * 1000);
7876
7877 return actual_temp;
7878}
7879
7880static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7881{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7882 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7883 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7884
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7885 if (low)
7886 return requested_state->performance_levels[0].sclk;
7887 else
7888 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7889}
7890
7891static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7892{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7893 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7894 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7895
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7896 if (low)
7897 return requested_state->performance_levels[0].mclk;
7898 else
7899 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7900}
7901
7902static void si_dpm_print_power_state(struct amdgpu_device *adev,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7903 struct amdgpu_ps *rps)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7904{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7905 struct si_ps *ps = si_get_ps(rps);
7906 struct rv7xx_pl *pl;
7907 int i;
7908
7909 amdgpu_dpm_print_class_info(rps->class, rps->class2);
7910 amdgpu_dpm_print_cap_info(rps->caps);
7911 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7912 for (i = 0; i < ps->performance_level_count; i++) {
7913 pl = &ps->performance_levels[i];
7914 if (adev->asic_type >= CHIP_TAHITI)
7915 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
Huang Rui84b77332016-08-31 13:23:18 +0800[diff] [blame]7916 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7917 else
7918 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
Huang Rui84b77332016-08-31 13:23:18 +0800[diff] [blame]7919 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7920 }
7921 amdgpu_dpm_print_ps_status(adev, rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7922}
7923
7924static int si_dpm_early_init(void *handle)
7925{
7926
7927 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7928
7929 si_dpm_set_dpm_funcs(adev);
7930 si_dpm_set_irq_funcs(adev);
7931 return 0;
7932}
7933
7934
7935const struct amd_ip_funcs si_dpm_ip_funcs = {
7936 .name = "si_dpm",
7937 .early_init = si_dpm_early_init,
7938 .late_init = si_dpm_late_init,
7939 .sw_init = si_dpm_sw_init,
7940 .sw_fini = si_dpm_sw_fini,
7941 .hw_init = si_dpm_hw_init,
7942 .hw_fini = si_dpm_hw_fini,
7943 .suspend = si_dpm_suspend,
7944 .resume = si_dpm_resume,
7945 .is_idle = si_dpm_is_idle,
7946 .wait_for_idle = si_dpm_wait_for_idle,
7947 .soft_reset = si_dpm_soft_reset,
7948 .set_clockgating_state = si_dpm_set_clockgating_state,
7949 .set_powergating_state = si_dpm_set_powergating_state,
7950};
7951
7952static const struct amdgpu_dpm_funcs si_dpm_funcs = {
7953 .get_temperature = &si_dpm_get_temp,
7954 .pre_set_power_state = &si_dpm_pre_set_power_state,
7955 .set_power_state = &si_dpm_set_power_state,
7956 .post_set_power_state = &si_dpm_post_set_power_state,
7957 .display_configuration_changed = &si_dpm_display_configuration_changed,
7958 .get_sclk = &si_dpm_get_sclk,
7959 .get_mclk = &si_dpm_get_mclk,
7960 .print_power_state = &si_dpm_print_power_state,
7961 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
7962 .force_performance_level = &si_dpm_force_performance_level,
7963 .vblank_too_short = &si_dpm_vblank_too_short,
7964 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
7965 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
7966 .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
7967 .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
7968};
7969
7970static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
7971{
7972 if (adev->pm.funcs == NULL)
7973 adev->pm.funcs = &si_dpm_funcs;
7974}
7975
7976static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
7977 .set = si_dpm_set_interrupt_state,
7978 .process = si_dpm_process_interrupt,
7979};
7980
7981static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
7982{
7983 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
7984 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
7985}
7986