| Sean Wang | a1a503a | 2018-09-08 19:07:17 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 MediaTek Inc. |
| 4 | * |
| 5 | * Author: Sean Wang <sean.wang@mediatek.com> |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | #ifndef __PINCTRL_MTK_COMMON_V2_H |
| 10 | #define __PINCTRL_MTK_COMMON_V2_H |
| 11 | |
| 12 | #define MTK_GPIO_MODE 1 |
| 13 | #define MTK_INPUT 0 |
| 14 | #define MTK_OUTPUT 1 |
| 15 | #define MTK_DISABLE 0 |
| 16 | #define MTK_ENABLE 1 |
| 17 | |
| 18 | /* List these attributes which could be modified for the pin */ |
| 19 | enum { |
| 20 | PINCTRL_PIN_REG_MODE, |
| 21 | PINCTRL_PIN_REG_DIR, |
| 22 | PINCTRL_PIN_REG_DI, |
| 23 | PINCTRL_PIN_REG_DO, |
| 24 | PINCTRL_PIN_REG_SR, |
| 25 | PINCTRL_PIN_REG_SMT, |
| 26 | PINCTRL_PIN_REG_PD, |
| 27 | PINCTRL_PIN_REG_PU, |
| 28 | PINCTRL_PIN_REG_E4, |
| 29 | PINCTRL_PIN_REG_E8, |
| 30 | PINCTRL_PIN_REG_TDSEL, |
| 31 | PINCTRL_PIN_REG_RDSEL, |
| 32 | PINCTRL_PIN_REG_MAX, |
| 33 | }; |
| 34 | |
| 35 | /* struct mtk_pin_field - the structure that holds the information of the field |
| 36 | * used to describe the attribute for the pin |
| 37 | * @offset: the register offset relative to the base address |
| 38 | * @mask: the mask used to filter out the field from the register |
| 39 | * @bitpos: the start bit relative to the register |
| 40 | * @next: the indication that the field would be extended to the |
| 41 | next register |
| 42 | */ |
| 43 | struct mtk_pin_field { |
| 44 | u32 offset; |
| 45 | u32 mask; |
| 46 | u8 bitpos; |
| 47 | u8 next; |
| 48 | }; |
| 49 | |
| 50 | /* struct mtk_pin_field_calc - the structure that holds the range providing |
| 51 | * the guide used to look up the relevant field |
| 52 | * @s_pin: the start pin within the range |
| 53 | * @e_pin: the end pin within the range |
| 54 | * @s_addr: the start address for the range |
| 55 | * @x_addrs: the address distance between two consecutive registers |
| 56 | * within the range |
| 57 | * @s_bit: the start bit for the first register within the range |
| 58 | * @x_bits: the bit distance between two consecutive pins within |
| 59 | * the range |
| 60 | */ |
| 61 | struct mtk_pin_field_calc { |
| 62 | u16 s_pin; |
| 63 | u16 e_pin; |
| 64 | u32 s_addr; |
| 65 | u8 x_addrs; |
| 66 | u8 s_bit; |
| 67 | u8 x_bits; |
| 68 | }; |
| 69 | |
| 70 | /* struct mtk_pin_reg_calc - the structure that holds all ranges used to |
| 71 | * determine which register the pin would make use of |
| 72 | * for certain pin attribute. |
| 73 | * @range: the start address for the range |
| 74 | * @nranges: the number of items in the range |
| 75 | */ |
| 76 | struct mtk_pin_reg_calc { |
| 77 | const struct mtk_pin_field_calc *range; |
| 78 | unsigned int nranges; |
| 79 | }; |
| 80 | |
| 81 | /* struct mtk_pin_soc - the structure that holds SoC-specific data */ |
| 82 | struct mtk_pin_soc { |
| 83 | const struct mtk_pin_reg_calc *reg_cal; |
| 84 | const struct pinctrl_pin_desc *pins; |
| 85 | unsigned int npins; |
| 86 | const struct group_desc *grps; |
| 87 | unsigned int ngrps; |
| 88 | const struct function_desc *funcs; |
| 89 | unsigned int nfuncs; |
| 90 | const struct mtk_eint_regs *eint_regs; |
| 91 | const struct mtk_eint_hw *eint_hw; |
| 92 | }; |
| 93 | |
| 94 | struct mtk_pinctrl { |
| 95 | struct pinctrl_dev *pctrl; |
| 96 | void __iomem *base; |
| 97 | struct device *dev; |
| 98 | struct gpio_chip chip; |
| 99 | const struct mtk_pin_soc *soc; |
| 100 | struct mtk_eint *eint; |
| 101 | }; |
| 102 | |
| 103 | void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set); |
| 104 | |
| 105 | int mtk_hw_set_value(struct mtk_pinctrl *hw, int pin, int field, int value); |
| 106 | int mtk_hw_get_value(struct mtk_pinctrl *hw, int pin, int field, int *value); |
| 107 | |
| 108 | #endif /* __PINCTRL_MTK_COMMON_V2_H */ |