Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1 | /* Intel Ethernet Switch Host Interface Driver |
| 2 | * Copyright(c) 2013 - 2014 Intel Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * The full GNU General Public License is included in this distribution in |
| 14 | * the file called "COPYING". |
| 15 | * |
| 16 | * Contact Information: |
| 17 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 18 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 19 | */ |
| 20 | |
| 21 | #include "fm10k_pf.h" |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 22 | #include "fm10k_vf.h" |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 23 | |
| 24 | /** |
| 25 | * fm10k_reset_hw_pf - PF hardware reset |
| 26 | * @hw: pointer to hardware structure |
| 27 | * |
| 28 | * This function should return the hardware to a state similar to the |
| 29 | * one it is in after being powered on. |
| 30 | **/ |
| 31 | static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw) |
| 32 | { |
| 33 | s32 err; |
| 34 | u32 reg; |
| 35 | u16 i; |
| 36 | |
| 37 | /* Disable interrupts */ |
| 38 | fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL)); |
| 39 | |
| 40 | /* Lock ITR2 reg 0 into itself and disable interrupt moderation */ |
| 41 | fm10k_write_reg(hw, FM10K_ITR2(0), 0); |
| 42 | fm10k_write_reg(hw, FM10K_INT_CTRL, 0); |
| 43 | |
| 44 | /* We assume here Tx and Rx queue 0 are owned by the PF */ |
| 45 | |
| 46 | /* Shut off VF access to their queues forcing them to queue 0 */ |
| 47 | for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) { |
| 48 | fm10k_write_reg(hw, FM10K_TQMAP(i), 0); |
| 49 | fm10k_write_reg(hw, FM10K_RQMAP(i), 0); |
| 50 | } |
| 51 | |
| 52 | /* shut down all rings */ |
| 53 | err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES); |
| 54 | if (err) |
| 55 | return err; |
| 56 | |
| 57 | /* Verify that DMA is no longer active */ |
| 58 | reg = fm10k_read_reg(hw, FM10K_DMA_CTRL); |
| 59 | if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE)) |
| 60 | return FM10K_ERR_DMA_PENDING; |
| 61 | |
| 62 | /* Inititate data path reset */ |
| 63 | reg |= FM10K_DMA_CTRL_DATAPATH_RESET; |
| 64 | fm10k_write_reg(hw, FM10K_DMA_CTRL, reg); |
| 65 | |
| 66 | /* Flush write and allow 100us for reset to complete */ |
| 67 | fm10k_write_flush(hw); |
| 68 | udelay(FM10K_RESET_TIMEOUT); |
| 69 | |
| 70 | /* Verify we made it out of reset */ |
| 71 | reg = fm10k_read_reg(hw, FM10K_IP); |
| 72 | if (!(reg & FM10K_IP_NOTINRESET)) |
| 73 | err = FM10K_ERR_RESET_FAILED; |
| 74 | |
| 75 | return err; |
| 76 | } |
| 77 | |
| 78 | /** |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 79 | * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support |
| 80 | * @hw: pointer to hardware structure |
| 81 | * |
| 82 | * Looks at the ARI hierarchy bit to determine whether ARI is supported or not. |
| 83 | **/ |
| 84 | static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw) |
| 85 | { |
| 86 | u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL); |
| 87 | |
| 88 | return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI); |
| 89 | } |
| 90 | |
| 91 | /** |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 92 | * fm10k_init_hw_pf - PF hardware initialization |
| 93 | * @hw: pointer to hardware structure |
| 94 | * |
| 95 | **/ |
| 96 | static s32 fm10k_init_hw_pf(struct fm10k_hw *hw) |
| 97 | { |
| 98 | u32 dma_ctrl, txqctl; |
| 99 | u16 i; |
| 100 | |
| 101 | /* Establish default VSI as valid */ |
| 102 | fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0); |
| 103 | fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default), |
| 104 | FM10K_DGLORTMAP_ANY); |
| 105 | |
| 106 | /* Invalidate all other GLORT entries */ |
| 107 | for (i = 1; i < FM10K_DGLORT_COUNT; i++) |
| 108 | fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE); |
| 109 | |
| 110 | /* reset ITR2(0) to point to itself */ |
| 111 | fm10k_write_reg(hw, FM10K_ITR2(0), 0); |
| 112 | |
| 113 | /* reset VF ITR2(0) to point to 0 avoid PF registers */ |
| 114 | fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0); |
| 115 | |
| 116 | /* loop through all PF ITR2 registers pointing them to the previous */ |
| 117 | for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++) |
| 118 | fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); |
| 119 | |
| 120 | /* Enable interrupt moderator if not already enabled */ |
| 121 | fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); |
| 122 | |
| 123 | /* compute the default txqctl configuration */ |
| 124 | txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW | |
| 125 | (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT); |
| 126 | |
| 127 | for (i = 0; i < FM10K_MAX_QUEUES; i++) { |
| 128 | /* configure rings for 256 Queue / 32 Descriptor cache mode */ |
| 129 | fm10k_write_reg(hw, FM10K_TQDLOC(i), |
| 130 | (i * FM10K_TQDLOC_BASE_32_DESC) | |
| 131 | FM10K_TQDLOC_SIZE_32_DESC); |
| 132 | fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); |
| 133 | |
| 134 | /* configure rings to provide TPH processing hints */ |
| 135 | fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i), |
| 136 | FM10K_TPH_TXCTRL_DESC_TPHEN | |
| 137 | FM10K_TPH_TXCTRL_DESC_RROEN | |
| 138 | FM10K_TPH_TXCTRL_DESC_WROEN | |
| 139 | FM10K_TPH_TXCTRL_DATA_RROEN); |
| 140 | fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i), |
| 141 | FM10K_TPH_RXCTRL_DESC_TPHEN | |
| 142 | FM10K_TPH_RXCTRL_DESC_RROEN | |
| 143 | FM10K_TPH_RXCTRL_DATA_WROEN | |
| 144 | FM10K_TPH_RXCTRL_HDR_WROEN); |
| 145 | } |
| 146 | |
| 147 | /* set max hold interval to align with 1.024 usec in all modes */ |
| 148 | switch (hw->bus.speed) { |
| 149 | case fm10k_bus_speed_2500: |
| 150 | dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1; |
| 151 | break; |
| 152 | case fm10k_bus_speed_5000: |
| 153 | dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2; |
| 154 | break; |
| 155 | case fm10k_bus_speed_8000: |
| 156 | dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3; |
| 157 | break; |
| 158 | default: |
| 159 | dma_ctrl = 0; |
| 160 | break; |
| 161 | } |
| 162 | |
| 163 | /* Configure TSO flags */ |
| 164 | fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW); |
| 165 | fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI); |
| 166 | |
| 167 | /* Enable DMA engine |
| 168 | * Set Rx Descriptor size to 32 |
| 169 | * Set Minimum MSS to 64 |
| 170 | * Set Maximum number of Rx queues to 256 / 32 Descriptor |
| 171 | */ |
| 172 | dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE | |
| 173 | FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 | |
| 174 | FM10K_DMA_CTRL_32_DESC; |
| 175 | |
| 176 | fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl); |
| 177 | |
| 178 | /* record maximum queue count, we limit ourselves to 128 */ |
| 179 | hw->mac.max_queues = FM10K_MAX_QUEUES_PF; |
| 180 | |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 181 | /* We support either 64 VFs or 7 VFs depending on if we have ARI */ |
| 182 | hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7; |
| 183 | |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 184 | return 0; |
| 185 | } |
| 186 | |
| 187 | /** |
| 188 | * fm10k_is_slot_appropriate_pf - Indicate appropriate slot for this SKU |
| 189 | * @hw: pointer to hardware structure |
| 190 | * |
| 191 | * Looks at the PCIe bus info to confirm whether or not this slot can support |
| 192 | * the necessary bandwidth for this device. |
| 193 | **/ |
| 194 | static bool fm10k_is_slot_appropriate_pf(struct fm10k_hw *hw) |
| 195 | { |
| 196 | return (hw->bus.speed == hw->bus_caps.speed) && |
| 197 | (hw->bus.width == hw->bus_caps.width); |
| 198 | } |
| 199 | |
| 200 | /** |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 201 | * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table |
| 202 | * @hw: pointer to hardware structure |
| 203 | * @vid: VLAN ID to add to table |
| 204 | * @vsi: Index indicating VF ID or PF ID in table |
| 205 | * @set: Indicates if this is a set or clear operation |
| 206 | * |
| 207 | * This function adds or removes the corresponding VLAN ID from the VLAN |
| 208 | * filter table for the corresponding function. In addition to the |
| 209 | * standard set/clear that supports one bit a multi-bit write is |
| 210 | * supported to set 64 bits at a time. |
| 211 | **/ |
| 212 | static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set) |
| 213 | { |
| 214 | u32 vlan_table, reg, mask, bit, len; |
| 215 | |
| 216 | /* verify the VSI index is valid */ |
| 217 | if (vsi > FM10K_VLAN_TABLE_VSI_MAX) |
| 218 | return FM10K_ERR_PARAM; |
| 219 | |
| 220 | /* VLAN multi-bit write: |
| 221 | * The multi-bit write has several parts to it. |
| 222 | * 3 2 1 0 |
| 223 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
| 224 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 225 | * | RSVD0 | Length |C|RSVD0| VLAN ID | |
| 226 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 227 | * |
| 228 | * VLAN ID: Vlan Starting value |
| 229 | * RSVD0: Reserved section, must be 0 |
| 230 | * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message) |
| 231 | * Length: Number of times to repeat the bit being set |
| 232 | */ |
| 233 | len = vid >> 16; |
| 234 | vid = (vid << 17) >> 17; |
| 235 | |
| 236 | /* verify the reserved 0 fields are 0 */ |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 237 | if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX) |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 238 | return FM10K_ERR_PARAM; |
| 239 | |
| 240 | /* Loop through the table updating all required VLANs */ |
| 241 | for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32; |
| 242 | len < FM10K_VLAN_TABLE_VID_MAX; |
| 243 | len -= 32 - bit, reg++, bit = 0) { |
| 244 | /* record the initial state of the register */ |
| 245 | vlan_table = fm10k_read_reg(hw, reg); |
| 246 | |
| 247 | /* truncate mask if we are at the start or end of the run */ |
| 248 | mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit; |
| 249 | |
| 250 | /* make necessary modifications to the register */ |
| 251 | mask &= set ? ~vlan_table : vlan_table; |
| 252 | if (mask) |
| 253 | fm10k_write_reg(hw, reg, vlan_table ^ mask); |
| 254 | } |
| 255 | |
| 256 | return 0; |
| 257 | } |
| 258 | |
| 259 | /** |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 260 | * fm10k_read_mac_addr_pf - Read device MAC address |
| 261 | * @hw: pointer to the HW structure |
| 262 | * |
| 263 | * Reads the device MAC address from the SM_AREA and stores the value. |
| 264 | **/ |
| 265 | static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw) |
| 266 | { |
| 267 | u8 perm_addr[ETH_ALEN]; |
| 268 | u32 serial_num; |
| 269 | int i; |
| 270 | |
| 271 | serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1)); |
| 272 | |
| 273 | /* last byte should be all 1's */ |
| 274 | if ((~serial_num) << 24) |
| 275 | return FM10K_ERR_INVALID_MAC_ADDR; |
| 276 | |
| 277 | perm_addr[0] = (u8)(serial_num >> 24); |
| 278 | perm_addr[1] = (u8)(serial_num >> 16); |
| 279 | perm_addr[2] = (u8)(serial_num >> 8); |
| 280 | |
| 281 | serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0)); |
| 282 | |
| 283 | /* first byte should be all 1's */ |
| 284 | if ((~serial_num) >> 24) |
| 285 | return FM10K_ERR_INVALID_MAC_ADDR; |
| 286 | |
| 287 | perm_addr[3] = (u8)(serial_num >> 16); |
| 288 | perm_addr[4] = (u8)(serial_num >> 8); |
| 289 | perm_addr[5] = (u8)(serial_num); |
| 290 | |
| 291 | for (i = 0; i < ETH_ALEN; i++) { |
| 292 | hw->mac.perm_addr[i] = perm_addr[i]; |
| 293 | hw->mac.addr[i] = perm_addr[i]; |
| 294 | } |
| 295 | |
| 296 | return 0; |
| 297 | } |
| 298 | |
| 299 | /** |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 300 | * fm10k_glort_valid_pf - Validate that the provided glort is valid |
| 301 | * @hw: pointer to the HW structure |
| 302 | * @glort: base glort to be validated |
| 303 | * |
| 304 | * This function will return an error if the provided glort is invalid |
| 305 | **/ |
| 306 | bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort) |
| 307 | { |
| 308 | glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT; |
| 309 | |
| 310 | return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE); |
| 311 | } |
| 312 | |
| 313 | /** |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 314 | * fm10k_update_xc_addr_pf - Update device addresses |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 315 | * @hw: pointer to the HW structure |
| 316 | * @glort: base resource tag for this request |
| 317 | * @mac: MAC address to add/remove from table |
| 318 | * @vid: VLAN ID to add/remove from table |
| 319 | * @add: Indicates if this is an add or remove operation |
| 320 | * @flags: flags field to indicate add and secure |
| 321 | * |
| 322 | * This function generates a message to the Switch API requesting |
| 323 | * that the given logical port add/remove the given L2 MAC/VLAN address. |
| 324 | **/ |
| 325 | static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort, |
| 326 | const u8 *mac, u16 vid, bool add, u8 flags) |
| 327 | { |
| 328 | struct fm10k_mbx_info *mbx = &hw->mbx; |
| 329 | struct fm10k_mac_update mac_update; |
| 330 | u32 msg[5]; |
| 331 | |
Jeff Kirsher | b32d15b | 2015-04-03 13:27:15 -0700 | [diff] [blame] | 332 | /* clear set bit from VLAN ID */ |
| 333 | vid &= ~FM10K_VLAN_CLEAR; |
| 334 | |
Matthew Vick | 33a44c2 | 2015-01-27 02:33:26 +0000 | [diff] [blame] | 335 | /* if glort or vlan are not valid return error */ |
| 336 | if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX) |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 337 | return FM10K_ERR_PARAM; |
| 338 | |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 339 | /* record fields */ |
| 340 | mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) | |
| 341 | ((u32)mac[3] << 16) | |
| 342 | ((u32)mac[4] << 8) | |
| 343 | ((u32)mac[5])); |
| 344 | mac_update.mac_upper = cpu_to_le16(((u32)mac[0] << 8) | |
| 345 | ((u32)mac[1])); |
| 346 | mac_update.vlan = cpu_to_le16(vid); |
| 347 | mac_update.glort = cpu_to_le16(glort); |
| 348 | mac_update.action = add ? 0 : 1; |
| 349 | mac_update.flags = flags; |
| 350 | |
| 351 | /* populate mac_update fields */ |
| 352 | fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE); |
| 353 | fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE, |
| 354 | &mac_update, sizeof(mac_update)); |
| 355 | |
| 356 | /* load onto outgoing mailbox */ |
| 357 | return mbx->ops.enqueue_tx(hw, mbx, msg); |
| 358 | } |
| 359 | |
| 360 | /** |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 361 | * fm10k_update_uc_addr_pf - Update device unicast addresses |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 362 | * @hw: pointer to the HW structure |
| 363 | * @glort: base resource tag for this request |
| 364 | * @mac: MAC address to add/remove from table |
| 365 | * @vid: VLAN ID to add/remove from table |
| 366 | * @add: Indicates if this is an add or remove operation |
| 367 | * @flags: flags field to indicate add and secure |
| 368 | * |
| 369 | * This function is used to add or remove unicast addresses for |
| 370 | * the PF. |
| 371 | **/ |
| 372 | static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort, |
| 373 | const u8 *mac, u16 vid, bool add, u8 flags) |
| 374 | { |
| 375 | /* verify MAC address is valid */ |
| 376 | if (!is_valid_ether_addr(mac)) |
| 377 | return FM10K_ERR_PARAM; |
| 378 | |
| 379 | return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags); |
| 380 | } |
| 381 | |
| 382 | /** |
| 383 | * fm10k_update_mc_addr_pf - Update device multicast addresses |
| 384 | * @hw: pointer to the HW structure |
| 385 | * @glort: base resource tag for this request |
| 386 | * @mac: MAC address to add/remove from table |
| 387 | * @vid: VLAN ID to add/remove from table |
| 388 | * @add: Indicates if this is an add or remove operation |
| 389 | * |
| 390 | * This function is used to add or remove multicast MAC addresses for |
| 391 | * the PF. |
| 392 | **/ |
| 393 | static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort, |
| 394 | const u8 *mac, u16 vid, bool add) |
| 395 | { |
| 396 | /* verify multicast address is valid */ |
| 397 | if (!is_multicast_ether_addr(mac)) |
| 398 | return FM10K_ERR_PARAM; |
| 399 | |
| 400 | return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0); |
| 401 | } |
| 402 | |
| 403 | /** |
| 404 | * fm10k_update_xcast_mode_pf - Request update of multicast mode |
| 405 | * @hw: pointer to hardware structure |
| 406 | * @glort: base resource tag for this request |
| 407 | * @mode: integer value indicating mode being requested |
| 408 | * |
| 409 | * This function will attempt to request a higher mode for the port |
| 410 | * so that it can enable either multicast, multicast promiscuous, or |
| 411 | * promiscuous mode of operation. |
| 412 | **/ |
| 413 | static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode) |
| 414 | { |
| 415 | struct fm10k_mbx_info *mbx = &hw->mbx; |
| 416 | u32 msg[3], xcast_mode; |
| 417 | |
| 418 | if (mode > FM10K_XCAST_MODE_NONE) |
| 419 | return FM10K_ERR_PARAM; |
| 420 | /* if glort is not valid return error */ |
| 421 | if (!fm10k_glort_valid_pf(hw, glort)) |
| 422 | return FM10K_ERR_PARAM; |
| 423 | |
| 424 | /* write xcast mode as a single u32 value, |
| 425 | * lower 16 bits: glort |
| 426 | * upper 16 bits: mode |
| 427 | */ |
| 428 | xcast_mode = ((u32)mode << 16) | glort; |
| 429 | |
| 430 | /* generate message requesting to change xcast mode */ |
| 431 | fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES); |
| 432 | fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode); |
| 433 | |
| 434 | /* load onto outgoing mailbox */ |
| 435 | return mbx->ops.enqueue_tx(hw, mbx, msg); |
| 436 | } |
| 437 | |
| 438 | /** |
| 439 | * fm10k_update_int_moderator_pf - Update interrupt moderator linked list |
| 440 | * @hw: pointer to hardware structure |
| 441 | * |
| 442 | * This function walks through the MSI-X vector table to determine the |
| 443 | * number of active interrupts and based on that information updates the |
| 444 | * interrupt moderator linked list. |
| 445 | **/ |
| 446 | static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw) |
| 447 | { |
| 448 | u32 i; |
| 449 | |
| 450 | /* Disable interrupt moderator */ |
| 451 | fm10k_write_reg(hw, FM10K_INT_CTRL, 0); |
| 452 | |
| 453 | /* loop through PF from last to first looking enabled vectors */ |
| 454 | for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) { |
| 455 | if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) |
| 456 | break; |
| 457 | } |
| 458 | |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 459 | /* always reset VFITR2[0] to point to last enabled PF vector */ |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 460 | fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i); |
| 461 | |
| 462 | /* reset ITR2[0] to point to last enabled PF vector */ |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 463 | if (!hw->iov.num_vfs) |
| 464 | fm10k_write_reg(hw, FM10K_ITR2(0), i); |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 465 | |
| 466 | /* Enable interrupt moderator */ |
| 467 | fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); |
| 468 | } |
| 469 | |
| 470 | /** |
| 471 | * fm10k_update_lport_state_pf - Notify the switch of a change in port state |
| 472 | * @hw: pointer to the HW structure |
| 473 | * @glort: base resource tag for this request |
| 474 | * @count: number of logical ports being updated |
| 475 | * @enable: boolean value indicating enable or disable |
| 476 | * |
| 477 | * This function is used to add/remove a logical port from the switch. |
| 478 | **/ |
| 479 | static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort, |
| 480 | u16 count, bool enable) |
| 481 | { |
| 482 | struct fm10k_mbx_info *mbx = &hw->mbx; |
| 483 | u32 msg[3], lport_msg; |
| 484 | |
| 485 | /* do nothing if we are being asked to create or destroy 0 ports */ |
| 486 | if (!count) |
| 487 | return 0; |
| 488 | |
| 489 | /* if glort is not valid return error */ |
| 490 | if (!fm10k_glort_valid_pf(hw, glort)) |
| 491 | return FM10K_ERR_PARAM; |
| 492 | |
| 493 | /* construct the lport message from the 2 pieces of data we have */ |
| 494 | lport_msg = ((u32)count << 16) | glort; |
| 495 | |
| 496 | /* generate lport create/delete message */ |
| 497 | fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE : |
| 498 | FM10K_PF_MSG_ID_LPORT_DELETE); |
| 499 | fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg); |
| 500 | |
| 501 | /* load onto outgoing mailbox */ |
| 502 | return mbx->ops.enqueue_tx(hw, mbx, msg); |
| 503 | } |
| 504 | |
| 505 | /** |
| 506 | * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues |
| 507 | * @hw: pointer to hardware structure |
| 508 | * @dglort: pointer to dglort configuration structure |
| 509 | * |
| 510 | * Reads the configuration structure contained in dglort_cfg and uses |
| 511 | * that information to then populate a DGLORTMAP/DEC entry and the queues |
| 512 | * to which it has been assigned. |
| 513 | **/ |
| 514 | static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw, |
| 515 | struct fm10k_dglort_cfg *dglort) |
| 516 | { |
| 517 | u16 glort, queue_count, vsi_count, pc_count; |
| 518 | u16 vsi, queue, pc, q_idx; |
| 519 | u32 txqctl, dglortdec, dglortmap; |
| 520 | |
| 521 | /* verify the dglort pointer */ |
| 522 | if (!dglort) |
| 523 | return FM10K_ERR_PARAM; |
| 524 | |
| 525 | /* verify the dglort values */ |
| 526 | if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) || |
| 527 | (dglort->vsi_l > 6) || (dglort->vsi_b > 64) || |
| 528 | (dglort->queue_l > 8) || (dglort->queue_b >= 256)) |
| 529 | return FM10K_ERR_PARAM; |
| 530 | |
| 531 | /* determine count of VSIs and queues */ |
| 532 | queue_count = 1 << (dglort->rss_l + dglort->pc_l); |
| 533 | vsi_count = 1 << (dglort->vsi_l + dglort->queue_l); |
| 534 | glort = dglort->glort; |
| 535 | q_idx = dglort->queue_b; |
| 536 | |
| 537 | /* configure SGLORT for queues */ |
| 538 | for (vsi = 0; vsi < vsi_count; vsi++, glort++) { |
| 539 | for (queue = 0; queue < queue_count; queue++, q_idx++) { |
| 540 | if (q_idx >= FM10K_MAX_QUEUES) |
| 541 | break; |
| 542 | |
| 543 | fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort); |
| 544 | fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort); |
| 545 | } |
| 546 | } |
| 547 | |
| 548 | /* determine count of PCs and queues */ |
| 549 | queue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l); |
| 550 | pc_count = 1 << dglort->pc_l; |
| 551 | |
| 552 | /* configure PC for Tx queues */ |
| 553 | for (pc = 0; pc < pc_count; pc++) { |
| 554 | q_idx = pc + dglort->queue_b; |
| 555 | for (queue = 0; queue < queue_count; queue++) { |
| 556 | if (q_idx >= FM10K_MAX_QUEUES) |
| 557 | break; |
| 558 | |
| 559 | txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx)); |
| 560 | txqctl &= ~FM10K_TXQCTL_PC_MASK; |
| 561 | txqctl |= pc << FM10K_TXQCTL_PC_SHIFT; |
| 562 | fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl); |
| 563 | |
| 564 | q_idx += pc_count; |
| 565 | } |
| 566 | } |
| 567 | |
| 568 | /* configure DGLORTDEC */ |
| 569 | dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | |
| 570 | ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) | |
| 571 | ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) | |
| 572 | ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) | |
| 573 | ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) | |
| 574 | ((u32)(dglort->queue_l)); |
| 575 | if (dglort->inner_rss) |
| 576 | dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE; |
| 577 | |
| 578 | /* configure DGLORTMAP */ |
| 579 | dglortmap = (dglort->idx == fm10k_dglort_default) ? |
| 580 | FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO; |
| 581 | dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l; |
| 582 | dglortmap |= dglort->glort; |
| 583 | |
| 584 | /* write values to hardware */ |
| 585 | fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec); |
| 586 | fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap); |
| 587 | |
| 588 | return 0; |
| 589 | } |
| 590 | |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 591 | u16 fm10k_queues_per_pool(struct fm10k_hw *hw) |
| 592 | { |
| 593 | u16 num_pools = hw->iov.num_pools; |
| 594 | |
| 595 | return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ? |
| 596 | 8 : FM10K_MAX_QUEUES_POOL; |
| 597 | } |
| 598 | |
| 599 | u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx) |
| 600 | { |
| 601 | u16 num_vfs = hw->iov.num_vfs; |
| 602 | u16 vf_q_idx = FM10K_MAX_QUEUES; |
| 603 | |
| 604 | vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx); |
| 605 | |
| 606 | return vf_q_idx; |
| 607 | } |
| 608 | |
| 609 | static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw) |
| 610 | { |
| 611 | u16 num_pools = hw->iov.num_pools; |
| 612 | |
| 613 | return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 : |
| 614 | FM10K_MAX_VECTORS_POOL; |
| 615 | } |
| 616 | |
| 617 | static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx) |
| 618 | { |
| 619 | u16 vf_v_idx = FM10K_MAX_VECTORS_PF; |
| 620 | |
| 621 | vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx; |
| 622 | |
| 623 | return vf_v_idx; |
| 624 | } |
| 625 | |
| 626 | /** |
| 627 | * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization |
| 628 | * @hw: pointer to the HW structure |
| 629 | * @num_vfs: number of VFs to be allocated |
| 630 | * @num_pools: number of virtualization pools to be allocated |
| 631 | * |
| 632 | * Allocates queues and traffic classes to virtualization entities to prepare |
| 633 | * the PF for SR-IOV and VMDq |
| 634 | **/ |
| 635 | static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs, |
| 636 | u16 num_pools) |
| 637 | { |
| 638 | u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx; |
| 639 | u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT; |
| 640 | int i, j; |
| 641 | |
| 642 | /* hardware only supports up to 64 pools */ |
| 643 | if (num_pools > 64) |
| 644 | return FM10K_ERR_PARAM; |
| 645 | |
| 646 | /* the number of VFs cannot exceed the number of pools */ |
| 647 | if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs)) |
| 648 | return FM10K_ERR_PARAM; |
| 649 | |
| 650 | /* record number of virtualization entities */ |
| 651 | hw->iov.num_vfs = num_vfs; |
| 652 | hw->iov.num_pools = num_pools; |
| 653 | |
| 654 | /* determine qmap offsets and counts */ |
| 655 | qmap_stride = (num_vfs > 8) ? 32 : 256; |
| 656 | qpp = fm10k_queues_per_pool(hw); |
| 657 | vpp = fm10k_vectors_per_pool(hw); |
| 658 | |
| 659 | /* calculate starting index for queues */ |
| 660 | vf_q_idx = fm10k_vf_queue_index(hw, 0); |
| 661 | qmap_idx = 0; |
| 662 | |
| 663 | /* establish TCs with -1 credits and no quanta to prevent transmit */ |
| 664 | for (i = 0; i < num_vfs; i++) { |
| 665 | fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0); |
| 666 | fm10k_write_reg(hw, FM10K_TC_RATE(i), 0); |
| 667 | fm10k_write_reg(hw, FM10K_TC_CREDIT(i), |
| 668 | FM10K_TC_CREDIT_CREDIT_MASK); |
| 669 | } |
| 670 | |
| 671 | /* zero out all mbmem registers */ |
| 672 | for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;) |
| 673 | fm10k_write_reg(hw, FM10K_MBMEM(i), 0); |
| 674 | |
| 675 | /* clear event notification of VF FLR */ |
| 676 | fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0); |
| 677 | fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0); |
| 678 | |
| 679 | /* loop through unallocated rings assigning them back to PF */ |
| 680 | for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) { |
| 681 | fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); |
Jeff Kirsher | ded8b20 | 2015-04-03 13:27:04 -0700 | [diff] [blame] | 682 | fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | |
| 683 | FM10K_TXQCTL_UNLIMITED_BW | vid); |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 684 | fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF); |
| 685 | } |
| 686 | |
| 687 | /* PF should have already updated VFITR2[0] */ |
| 688 | |
| 689 | /* update all ITR registers to flow to VFITR2[0] */ |
| 690 | for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) { |
| 691 | if (!(i & (vpp - 1))) |
| 692 | fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp); |
| 693 | else |
| 694 | fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); |
| 695 | } |
| 696 | |
| 697 | /* update PF ITR2[0] to reference the last vector */ |
| 698 | fm10k_write_reg(hw, FM10K_ITR2(0), |
| 699 | fm10k_vf_vector_index(hw, num_vfs - 1)); |
| 700 | |
| 701 | /* loop through rings populating rings and TCs */ |
| 702 | for (i = 0; i < num_vfs; i++) { |
| 703 | /* record index for VF queue 0 for use in end of loop */ |
| 704 | vf_q_idx0 = vf_q_idx; |
| 705 | |
| 706 | for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) { |
| 707 | /* assign VF and locked TC to queues */ |
| 708 | fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); |
| 709 | fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx), |
| 710 | (i << FM10K_TXQCTL_TC_SHIFT) | i | |
| 711 | FM10K_TXQCTL_VF | vid); |
| 712 | fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx), |
| 713 | FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | |
| 714 | FM10K_RXDCTL_DROP_ON_EMPTY); |
| 715 | fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx), |
| 716 | FM10K_RXQCTL_VF | |
| 717 | (i << FM10K_RXQCTL_VF_SHIFT)); |
| 718 | |
| 719 | /* map queue pair to VF */ |
| 720 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); |
| 721 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx); |
| 722 | } |
| 723 | |
| 724 | /* repeat the first ring for all of the remaining VF rings */ |
| 725 | for (; j < qmap_stride; j++, qmap_idx++) { |
| 726 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0); |
| 727 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0); |
| 728 | } |
| 729 | } |
| 730 | |
| 731 | /* loop through remaining indexes assigning all to queue 0 */ |
| 732 | while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) { |
| 733 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); |
| 734 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0); |
| 735 | qmap_idx++; |
| 736 | } |
| 737 | |
| 738 | return 0; |
| 739 | } |
| 740 | |
| 741 | /** |
| 742 | * fm10k_iov_configure_tc_pf - Configure the shaping group for VF |
| 743 | * @hw: pointer to the HW structure |
| 744 | * @vf_idx: index of VF receiving GLORT |
| 745 | * @rate: Rate indicated in Mb/s |
| 746 | * |
| 747 | * Configured the TC for a given VF to allow only up to a given number |
| 748 | * of Mb/s of outgoing Tx throughput. |
| 749 | **/ |
| 750 | static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate) |
| 751 | { |
| 752 | /* configure defaults */ |
| 753 | u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3; |
| 754 | u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK; |
| 755 | |
| 756 | /* verify vf is in range */ |
| 757 | if (vf_idx >= hw->iov.num_vfs) |
| 758 | return FM10K_ERR_PARAM; |
| 759 | |
| 760 | /* set interval to align with 4.096 usec in all modes */ |
| 761 | switch (hw->bus.speed) { |
| 762 | case fm10k_bus_speed_2500: |
| 763 | interval = FM10K_TC_RATE_INTERVAL_4US_GEN1; |
| 764 | break; |
| 765 | case fm10k_bus_speed_5000: |
| 766 | interval = FM10K_TC_RATE_INTERVAL_4US_GEN2; |
| 767 | break; |
| 768 | default: |
| 769 | break; |
| 770 | } |
| 771 | |
| 772 | if (rate) { |
| 773 | if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN) |
| 774 | return FM10K_ERR_PARAM; |
| 775 | |
| 776 | /* The quanta is measured in Bytes per 4.096 or 8.192 usec |
| 777 | * The rate is provided in Mbits per second |
| 778 | * To tralslate from rate to quanta we need to multiply the |
| 779 | * rate by 8.192 usec and divide by 8 bits/byte. To avoid |
| 780 | * dealing with floating point we can round the values up |
| 781 | * to the nearest whole number ratio which gives us 128 / 125. |
| 782 | */ |
| 783 | tc_rate = (rate * 128) / 125; |
| 784 | |
| 785 | /* try to keep the rate limiting accurate by increasing |
| 786 | * the number of credits and interval for rates less than 4Gb/s |
| 787 | */ |
| 788 | if (rate < 4000) |
| 789 | interval <<= 1; |
| 790 | else |
| 791 | tc_rate >>= 1; |
| 792 | } |
| 793 | |
| 794 | /* update rate limiter with new values */ |
| 795 | fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval); |
| 796 | fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); |
| 797 | fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); |
| 798 | |
| 799 | return 0; |
| 800 | } |
| 801 | |
| 802 | /** |
| 803 | * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list |
| 804 | * @hw: pointer to the HW structure |
| 805 | * @vf_idx: index of VF receiving GLORT |
| 806 | * |
| 807 | * Update the interrupt moderator linked list to include any MSI-X |
| 808 | * interrupts which the VF has enabled in the MSI-X vector table. |
| 809 | **/ |
| 810 | static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx) |
| 811 | { |
| 812 | u16 vf_v_idx, vf_v_limit, i; |
| 813 | |
| 814 | /* verify vf is in range */ |
| 815 | if (vf_idx >= hw->iov.num_vfs) |
| 816 | return FM10K_ERR_PARAM; |
| 817 | |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 818 | /* determine vector offset and count */ |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 819 | vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); |
| 820 | vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); |
| 821 | |
| 822 | /* search for first vector that is not masked */ |
| 823 | for (i = vf_v_limit - 1; i > vf_v_idx; i--) { |
| 824 | if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) |
| 825 | break; |
| 826 | } |
| 827 | |
| 828 | /* reset linked list so it now includes our active vectors */ |
| 829 | if (vf_idx == (hw->iov.num_vfs - 1)) |
| 830 | fm10k_write_reg(hw, FM10K_ITR2(0), i); |
| 831 | else |
| 832 | fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i); |
| 833 | |
| 834 | return 0; |
| 835 | } |
| 836 | |
| 837 | /** |
| 838 | * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF |
| 839 | * @hw: pointer to the HW structure |
| 840 | * @vf_info: pointer to VF information structure |
| 841 | * |
| 842 | * Assign a MAC address and default VLAN to a VF and notify it of the update |
| 843 | **/ |
| 844 | static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw, |
| 845 | struct fm10k_vf_info *vf_info) |
| 846 | { |
| 847 | u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i; |
| 848 | u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0; |
| 849 | s32 err = 0; |
| 850 | u16 vf_idx, vf_vid; |
| 851 | |
| 852 | /* verify vf is in range */ |
| 853 | if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs) |
| 854 | return FM10K_ERR_PARAM; |
| 855 | |
| 856 | /* determine qmap offsets and counts */ |
| 857 | qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; |
| 858 | queues_per_pool = fm10k_queues_per_pool(hw); |
| 859 | |
| 860 | /* calculate starting index for queues */ |
| 861 | vf_idx = vf_info->vf_idx; |
| 862 | vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); |
| 863 | qmap_idx = qmap_stride * vf_idx; |
| 864 | |
| 865 | /* MAP Tx queue back to 0 temporarily, and disable it */ |
| 866 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); |
| 867 | fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); |
| 868 | |
| 869 | /* determine correct default VLAN ID */ |
| 870 | if (vf_info->pf_vid) |
| 871 | vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR; |
| 872 | else |
| 873 | vf_vid = vf_info->sw_vid; |
| 874 | |
| 875 | /* generate MAC_ADDR request */ |
| 876 | fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN); |
| 877 | fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC, |
| 878 | vf_info->mac, vf_vid); |
| 879 | |
| 880 | /* load onto outgoing mailbox, ignore any errors on enqueue */ |
| 881 | if (vf_info->mbx.ops.enqueue_tx) |
| 882 | vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); |
| 883 | |
| 884 | /* verify ring has disabled before modifying base address registers */ |
| 885 | txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); |
| 886 | for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) { |
| 887 | /* limit ourselves to a 1ms timeout */ |
| 888 | if (timeout == 10) { |
| 889 | err = FM10K_ERR_DMA_PENDING; |
| 890 | goto err_out; |
| 891 | } |
| 892 | |
| 893 | usleep_range(100, 200); |
| 894 | txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); |
| 895 | } |
| 896 | |
| 897 | /* Update base address registers to contain MAC address */ |
| 898 | if (is_valid_ether_addr(vf_info->mac)) { |
| 899 | tdbal = (((u32)vf_info->mac[3]) << 24) | |
| 900 | (((u32)vf_info->mac[4]) << 16) | |
| 901 | (((u32)vf_info->mac[5]) << 8); |
| 902 | |
| 903 | tdbah = (((u32)0xFF) << 24) | |
| 904 | (((u32)vf_info->mac[0]) << 16) | |
| 905 | (((u32)vf_info->mac[1]) << 8) | |
| 906 | ((u32)vf_info->mac[2]); |
| 907 | } |
| 908 | |
| 909 | /* Record the base address into queue 0 */ |
| 910 | fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal); |
| 911 | fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah); |
| 912 | |
| 913 | err_out: |
| 914 | /* configure Queue control register */ |
| 915 | txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) & |
| 916 | FM10K_TXQCTL_VID_MASK; |
| 917 | txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) | |
| 918 | FM10K_TXQCTL_VF | vf_idx; |
| 919 | |
| 920 | /* assign VID */ |
| 921 | for (i = 0; i < queues_per_pool; i++) |
| 922 | fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl); |
| 923 | |
| 924 | /* restore the queue back to VF ownership */ |
| 925 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); |
| 926 | return err; |
| 927 | } |
| 928 | |
| 929 | /** |
| 930 | * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF |
| 931 | * @hw: pointer to the HW structure |
| 932 | * @vf_info: pointer to VF information structure |
| 933 | * |
| 934 | * Reassign the interrupts and queues to a VF following an FLR |
| 935 | **/ |
| 936 | static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw, |
| 937 | struct fm10k_vf_info *vf_info) |
| 938 | { |
| 939 | u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx; |
| 940 | u32 tdbal = 0, tdbah = 0, txqctl, rxqctl; |
| 941 | u16 vf_v_idx, vf_v_limit, vf_vid; |
| 942 | u8 vf_idx = vf_info->vf_idx; |
| 943 | int i; |
| 944 | |
| 945 | /* verify vf is in range */ |
| 946 | if (vf_idx >= hw->iov.num_vfs) |
| 947 | return FM10K_ERR_PARAM; |
| 948 | |
| 949 | /* clear event notification of VF FLR */ |
| 950 | fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32)); |
| 951 | |
| 952 | /* force timeout and then disconnect the mailbox */ |
| 953 | vf_info->mbx.timeout = 0; |
| 954 | if (vf_info->mbx.ops.disconnect) |
| 955 | vf_info->mbx.ops.disconnect(hw, &vf_info->mbx); |
| 956 | |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 957 | /* determine vector offset and count */ |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 958 | vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); |
| 959 | vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); |
| 960 | |
| 961 | /* determine qmap offsets and counts */ |
| 962 | qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; |
| 963 | queues_per_pool = fm10k_queues_per_pool(hw); |
| 964 | qmap_idx = qmap_stride * vf_idx; |
| 965 | |
| 966 | /* make all the queues inaccessible to the VF */ |
| 967 | for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) { |
| 968 | fm10k_write_reg(hw, FM10K_TQMAP(i), 0); |
| 969 | fm10k_write_reg(hw, FM10K_RQMAP(i), 0); |
| 970 | } |
| 971 | |
| 972 | /* calculate starting index for queues */ |
| 973 | vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); |
| 974 | |
| 975 | /* determine correct default VLAN ID */ |
| 976 | if (vf_info->pf_vid) |
| 977 | vf_vid = vf_info->pf_vid; |
| 978 | else |
| 979 | vf_vid = vf_info->sw_vid; |
| 980 | |
| 981 | /* configure Queue control register */ |
| 982 | txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) | |
| 983 | (vf_idx << FM10K_TXQCTL_TC_SHIFT) | |
| 984 | FM10K_TXQCTL_VF | vf_idx; |
| 985 | rxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT); |
| 986 | |
| 987 | /* stop further DMA and reset queue ownership back to VF */ |
| 988 | for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) { |
| 989 | fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); |
| 990 | fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); |
| 991 | fm10k_write_reg(hw, FM10K_RXDCTL(i), |
| 992 | FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | |
| 993 | FM10K_RXDCTL_DROP_ON_EMPTY); |
| 994 | fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl); |
| 995 | } |
| 996 | |
| 997 | /* reset TC with -1 credits and no quanta to prevent transmit */ |
| 998 | fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0); |
| 999 | fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0); |
| 1000 | fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), |
| 1001 | FM10K_TC_CREDIT_CREDIT_MASK); |
| 1002 | |
| 1003 | /* update our first entry in the table based on previous VF */ |
| 1004 | if (!vf_idx) |
| 1005 | hw->mac.ops.update_int_moderator(hw); |
| 1006 | else |
| 1007 | hw->iov.ops.assign_int_moderator(hw, vf_idx - 1); |
| 1008 | |
| 1009 | /* reset linked list so it now includes our active vectors */ |
| 1010 | if (vf_idx == (hw->iov.num_vfs - 1)) |
| 1011 | fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx); |
| 1012 | else |
| 1013 | fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx); |
| 1014 | |
| 1015 | /* link remaining vectors so that next points to previous */ |
| 1016 | for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++) |
| 1017 | fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1); |
| 1018 | |
| 1019 | /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */ |
| 1020 | for (i = FM10K_VFMBMEM_LEN; i--;) |
| 1021 | fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0); |
| 1022 | for (i = FM10K_VLAN_TABLE_SIZE; i--;) |
| 1023 | fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0); |
| 1024 | for (i = FM10K_RETA_SIZE; i--;) |
| 1025 | fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0); |
| 1026 | for (i = FM10K_RSSRK_SIZE; i--;) |
| 1027 | fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0); |
| 1028 | fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0); |
| 1029 | |
| 1030 | /* Update base address registers to contain MAC address */ |
| 1031 | if (is_valid_ether_addr(vf_info->mac)) { |
| 1032 | tdbal = (((u32)vf_info->mac[3]) << 24) | |
| 1033 | (((u32)vf_info->mac[4]) << 16) | |
| 1034 | (((u32)vf_info->mac[5]) << 8); |
| 1035 | tdbah = (((u32)0xFF) << 24) | |
| 1036 | (((u32)vf_info->mac[0]) << 16) | |
| 1037 | (((u32)vf_info->mac[1]) << 8) | |
| 1038 | ((u32)vf_info->mac[2]); |
| 1039 | } |
| 1040 | |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 1041 | /* map queue pairs back to VF from last to first */ |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1042 | for (i = queues_per_pool; i--;) { |
| 1043 | fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal); |
| 1044 | fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah); |
| 1045 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i); |
| 1046 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i); |
| 1047 | } |
| 1048 | |
| 1049 | return 0; |
| 1050 | } |
| 1051 | |
| 1052 | /** |
| 1053 | * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF |
| 1054 | * @hw: pointer to hardware structure |
| 1055 | * @vf_info: pointer to VF information structure |
| 1056 | * @lport_idx: Logical port offset from the hardware glort |
| 1057 | * @flags: Set of capability flags to extend port beyond basic functionality |
| 1058 | * |
| 1059 | * This function allows enabling a VF port by assigning it a GLORT and |
| 1060 | * setting the flags so that it can enable an Rx mode. |
| 1061 | **/ |
| 1062 | static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw, |
| 1063 | struct fm10k_vf_info *vf_info, |
| 1064 | u16 lport_idx, u8 flags) |
| 1065 | { |
| 1066 | u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE; |
| 1067 | |
| 1068 | /* if glort is not valid return error */ |
| 1069 | if (!fm10k_glort_valid_pf(hw, glort)) |
| 1070 | return FM10K_ERR_PARAM; |
| 1071 | |
| 1072 | vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE; |
| 1073 | vf_info->glort = glort; |
| 1074 | |
| 1075 | return 0; |
| 1076 | } |
| 1077 | |
| 1078 | /** |
| 1079 | * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF |
| 1080 | * @hw: pointer to hardware structure |
| 1081 | * @vf_info: pointer to VF information structure |
| 1082 | * |
| 1083 | * This function disables a VF port by stripping it of a GLORT and |
| 1084 | * setting the flags so that it cannot enable any Rx mode. |
| 1085 | **/ |
| 1086 | static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw, |
| 1087 | struct fm10k_vf_info *vf_info) |
| 1088 | { |
| 1089 | u32 msg[1]; |
| 1090 | |
| 1091 | /* need to disable the port if it is already enabled */ |
| 1092 | if (FM10K_VF_FLAG_ENABLED(vf_info)) { |
| 1093 | /* notify switch that this port has been disabled */ |
| 1094 | fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false); |
| 1095 | |
| 1096 | /* generate port state response to notify VF it is not ready */ |
| 1097 | fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); |
| 1098 | vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); |
| 1099 | } |
| 1100 | |
| 1101 | /* clear flags and glort if it exists */ |
| 1102 | vf_info->vf_flags = 0; |
| 1103 | vf_info->glort = 0; |
| 1104 | } |
| 1105 | |
| 1106 | /** |
| 1107 | * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs |
| 1108 | * @hw: pointer to hardware structure |
| 1109 | * @q: stats for all queues of a VF |
| 1110 | * @vf_idx: index of VF |
| 1111 | * |
| 1112 | * This function collects queue stats for VFs. |
| 1113 | **/ |
| 1114 | static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw, |
| 1115 | struct fm10k_hw_stats_q *q, |
| 1116 | u16 vf_idx) |
| 1117 | { |
| 1118 | u32 idx, qpp; |
| 1119 | |
| 1120 | /* get stats for all of the queues */ |
| 1121 | qpp = fm10k_queues_per_pool(hw); |
| 1122 | idx = fm10k_vf_queue_index(hw, vf_idx); |
| 1123 | fm10k_update_hw_stats_q(hw, q, idx, qpp); |
| 1124 | } |
| 1125 | |
Alexander Duyck | 5f226dd | 2014-09-20 19:53:40 -0400 | [diff] [blame] | 1126 | static s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw, |
| 1127 | struct fm10k_vf_info *vf_info, |
| 1128 | u64 timestamp) |
| 1129 | { |
| 1130 | u32 msg[4]; |
| 1131 | |
| 1132 | /* generate port state response to notify VF it is not ready */ |
| 1133 | fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588); |
| 1134 | fm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_TIMESTAMP, timestamp); |
| 1135 | |
| 1136 | return vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); |
| 1137 | } |
| 1138 | |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1139 | /** |
| 1140 | * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF |
| 1141 | * @hw: Pointer to hardware structure |
| 1142 | * @results: Pointer array to message, results[0] is pointer to message |
| 1143 | * @mbx: Pointer to mailbox information structure |
| 1144 | * |
| 1145 | * This function is a default handler for MSI-X requests from the VF. The |
| 1146 | * assumption is that in this case it is acceptable to just directly |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 1147 | * hand off the message from the VF to the underlying shared code. |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1148 | **/ |
| 1149 | s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results, |
| 1150 | struct fm10k_mbx_info *mbx) |
| 1151 | { |
| 1152 | struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; |
| 1153 | u8 vf_idx = vf_info->vf_idx; |
| 1154 | |
| 1155 | return hw->iov.ops.assign_int_moderator(hw, vf_idx); |
| 1156 | } |
| 1157 | |
| 1158 | /** |
| 1159 | * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF |
| 1160 | * @hw: Pointer to hardware structure |
| 1161 | * @results: Pointer array to message, results[0] is pointer to message |
| 1162 | * @mbx: Pointer to mailbox information structure |
| 1163 | * |
| 1164 | * This function is a default handler for MAC/VLAN requests from the VF. |
| 1165 | * The assumption is that in this case it is acceptable to just directly |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 1166 | * hand off the message from the VF to the underlying shared code. |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1167 | **/ |
| 1168 | s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results, |
| 1169 | struct fm10k_mbx_info *mbx) |
| 1170 | { |
| 1171 | struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; |
| 1172 | int err = 0; |
| 1173 | u8 mac[ETH_ALEN]; |
| 1174 | u32 *result; |
| 1175 | u16 vlan; |
| 1176 | u32 vid; |
| 1177 | |
| 1178 | /* we shouldn't be updating rules on a disabled interface */ |
| 1179 | if (!FM10K_VF_FLAG_ENABLED(vf_info)) |
| 1180 | err = FM10K_ERR_PARAM; |
| 1181 | |
| 1182 | if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) { |
| 1183 | result = results[FM10K_MAC_VLAN_MSG_VLAN]; |
| 1184 | |
| 1185 | /* record VLAN id requested */ |
| 1186 | err = fm10k_tlv_attr_get_u32(result, &vid); |
| 1187 | if (err) |
| 1188 | return err; |
| 1189 | |
| 1190 | /* if VLAN ID is 0, set the default VLAN ID instead of 0 */ |
| 1191 | if (!vid || (vid == FM10K_VLAN_CLEAR)) { |
| 1192 | if (vf_info->pf_vid) |
| 1193 | vid |= vf_info->pf_vid; |
| 1194 | else |
| 1195 | vid |= vf_info->sw_vid; |
| 1196 | } else if (vid != vf_info->pf_vid) { |
| 1197 | return FM10K_ERR_PARAM; |
| 1198 | } |
| 1199 | |
| 1200 | /* update VSI info for VF in regards to VLAN table */ |
| 1201 | err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, |
| 1202 | !(vid & FM10K_VLAN_CLEAR)); |
| 1203 | } |
| 1204 | |
| 1205 | if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) { |
| 1206 | result = results[FM10K_MAC_VLAN_MSG_MAC]; |
| 1207 | |
| 1208 | /* record unicast MAC address requested */ |
| 1209 | err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); |
| 1210 | if (err) |
| 1211 | return err; |
| 1212 | |
| 1213 | /* block attempts to set MAC for a locked device */ |
| 1214 | if (is_valid_ether_addr(vf_info->mac) && |
| 1215 | memcmp(mac, vf_info->mac, ETH_ALEN)) |
| 1216 | return FM10K_ERR_PARAM; |
| 1217 | |
| 1218 | /* if VLAN ID is 0, set the default VLAN ID instead of 0 */ |
| 1219 | if (!vlan || (vlan == FM10K_VLAN_CLEAR)) { |
| 1220 | if (vf_info->pf_vid) |
| 1221 | vlan |= vf_info->pf_vid; |
| 1222 | else |
| 1223 | vlan |= vf_info->sw_vid; |
| 1224 | } else if (vf_info->pf_vid) { |
| 1225 | return FM10K_ERR_PARAM; |
| 1226 | } |
| 1227 | |
| 1228 | /* notify switch of request for new unicast address */ |
| 1229 | err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, mac, vlan, |
| 1230 | !(vlan & FM10K_VLAN_CLEAR), 0); |
| 1231 | } |
| 1232 | |
| 1233 | if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) { |
| 1234 | result = results[FM10K_MAC_VLAN_MSG_MULTICAST]; |
| 1235 | |
| 1236 | /* record multicast MAC address requested */ |
| 1237 | err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); |
| 1238 | if (err) |
| 1239 | return err; |
| 1240 | |
| 1241 | /* verify that the VF is allowed to request multicast */ |
| 1242 | if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED)) |
| 1243 | return FM10K_ERR_PARAM; |
| 1244 | |
| 1245 | /* if VLAN ID is 0, set the default VLAN ID instead of 0 */ |
| 1246 | if (!vlan || (vlan == FM10K_VLAN_CLEAR)) { |
| 1247 | if (vf_info->pf_vid) |
| 1248 | vlan |= vf_info->pf_vid; |
| 1249 | else |
| 1250 | vlan |= vf_info->sw_vid; |
| 1251 | } else if (vf_info->pf_vid) { |
| 1252 | return FM10K_ERR_PARAM; |
| 1253 | } |
| 1254 | |
| 1255 | /* notify switch of request for new multicast address */ |
Jeff Kirsher | b32d15b | 2015-04-03 13:27:15 -0700 | [diff] [blame] | 1256 | err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, mac, vlan, |
| 1257 | !(vlan & FM10K_VLAN_CLEAR)); |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1258 | } |
| 1259 | |
| 1260 | return err; |
| 1261 | } |
| 1262 | |
| 1263 | /** |
| 1264 | * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode |
| 1265 | * @vf_info: VF info structure containing capability flags |
| 1266 | * @mode: Requested xcast mode |
| 1267 | * |
| 1268 | * This function outputs the mode that most closely matches the requested |
| 1269 | * mode. If not modes match it will request we disable the port |
| 1270 | **/ |
| 1271 | static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info, |
| 1272 | u8 mode) |
| 1273 | { |
| 1274 | u8 vf_flags = vf_info->vf_flags; |
| 1275 | |
| 1276 | /* match up mode to capabilities as best as possible */ |
| 1277 | switch (mode) { |
| 1278 | case FM10K_XCAST_MODE_PROMISC: |
| 1279 | if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE) |
| 1280 | return FM10K_XCAST_MODE_PROMISC; |
| 1281 | /* fallthough */ |
| 1282 | case FM10K_XCAST_MODE_ALLMULTI: |
| 1283 | if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE) |
| 1284 | return FM10K_XCAST_MODE_ALLMULTI; |
| 1285 | /* fallthough */ |
| 1286 | case FM10K_XCAST_MODE_MULTI: |
| 1287 | if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE) |
| 1288 | return FM10K_XCAST_MODE_MULTI; |
| 1289 | /* fallthough */ |
| 1290 | case FM10K_XCAST_MODE_NONE: |
| 1291 | if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE) |
| 1292 | return FM10K_XCAST_MODE_NONE; |
| 1293 | /* fallthough */ |
| 1294 | default: |
| 1295 | break; |
| 1296 | } |
| 1297 | |
| 1298 | /* disable interface as it should not be able to request any */ |
| 1299 | return FM10K_XCAST_MODE_DISABLE; |
| 1300 | } |
| 1301 | |
| 1302 | /** |
| 1303 | * fm10k_iov_msg_lport_state_pf - Message handler for port state requests |
| 1304 | * @hw: Pointer to hardware structure |
| 1305 | * @results: Pointer array to message, results[0] is pointer to message |
| 1306 | * @mbx: Pointer to mailbox information structure |
| 1307 | * |
| 1308 | * This function is a default handler for port state requests. The port |
| 1309 | * state requests for now are basic and consist of enabling or disabling |
| 1310 | * the port. |
| 1311 | **/ |
| 1312 | s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results, |
| 1313 | struct fm10k_mbx_info *mbx) |
| 1314 | { |
| 1315 | struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; |
| 1316 | u32 *result; |
| 1317 | s32 err = 0; |
| 1318 | u32 msg[2]; |
| 1319 | u8 mode = 0; |
| 1320 | |
| 1321 | /* verify VF is allowed to enable even minimal mode */ |
| 1322 | if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)) |
| 1323 | return FM10K_ERR_PARAM; |
| 1324 | |
| 1325 | if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) { |
| 1326 | result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE]; |
| 1327 | |
| 1328 | /* XCAST mode update requested */ |
| 1329 | err = fm10k_tlv_attr_get_u8(result, &mode); |
| 1330 | if (err) |
| 1331 | return FM10K_ERR_PARAM; |
| 1332 | |
| 1333 | /* prep for possible demotion depending on capabilities */ |
| 1334 | mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode); |
| 1335 | |
| 1336 | /* if mode is not currently enabled, enable it */ |
| 1337 | if (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode))) |
| 1338 | fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode); |
| 1339 | |
| 1340 | /* swap mode back to a bit flag */ |
| 1341 | mode = FM10K_VF_FLAG_SET_MODE(mode); |
| 1342 | } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) { |
| 1343 | /* need to disable the port if it is already enabled */ |
| 1344 | if (FM10K_VF_FLAG_ENABLED(vf_info)) |
| 1345 | err = fm10k_update_lport_state_pf(hw, vf_info->glort, |
| 1346 | 1, false); |
| 1347 | |
| 1348 | /* when enabling the port we should reset the rate limiters */ |
| 1349 | hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate); |
| 1350 | |
| 1351 | /* set mode for minimal functionality */ |
| 1352 | mode = FM10K_VF_FLAG_SET_MODE_NONE; |
| 1353 | |
| 1354 | /* generate port state response to notify VF it is ready */ |
| 1355 | fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); |
| 1356 | fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY); |
| 1357 | mbx->ops.enqueue_tx(hw, mbx, msg); |
| 1358 | } |
| 1359 | |
| 1360 | /* if enable state toggled note the update */ |
| 1361 | if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode)) |
| 1362 | err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1, |
| 1363 | !!mode); |
| 1364 | |
| 1365 | /* if state change succeeded, then update our stored state */ |
| 1366 | mode |= FM10K_VF_FLAG_CAPABLE(vf_info); |
| 1367 | if (!err) |
| 1368 | vf_info->vf_flags = mode; |
| 1369 | |
| 1370 | return err; |
| 1371 | } |
| 1372 | |
| 1373 | const struct fm10k_msg_data fm10k_iov_msg_data_pf[] = { |
| 1374 | FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test), |
| 1375 | FM10K_VF_MSG_MSIX_HANDLER(fm10k_iov_msg_msix_pf), |
| 1376 | FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_iov_msg_mac_vlan_pf), |
| 1377 | FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_iov_msg_lport_state_pf), |
| 1378 | FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error), |
| 1379 | }; |
| 1380 | |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1381 | /** |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1382 | * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF |
| 1383 | * @hw: pointer to hardware structure |
| 1384 | * @stats: pointer to the stats structure to update |
| 1385 | * |
| 1386 | * This function collects and aggregates global and per queue hardware |
| 1387 | * statistics. |
| 1388 | **/ |
| 1389 | static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw, |
| 1390 | struct fm10k_hw_stats *stats) |
| 1391 | { |
| 1392 | u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop; |
| 1393 | u32 id, id_prev; |
| 1394 | |
| 1395 | /* Use Tx queue 0 as a canary to detect a reset */ |
| 1396 | id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); |
| 1397 | |
| 1398 | /* Read Global Statistics */ |
| 1399 | do { |
| 1400 | timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT, |
| 1401 | &stats->timeout); |
| 1402 | ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur); |
| 1403 | ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca); |
| 1404 | um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um); |
| 1405 | xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec); |
| 1406 | vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP, |
| 1407 | &stats->vlan_drop); |
| 1408 | loopback_drop = fm10k_read_hw_stats_32b(hw, |
| 1409 | FM10K_STATS_LOOPBACK_DROP, |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 1410 | &stats->loopback_drop); |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1411 | nodesc_drop = fm10k_read_hw_stats_32b(hw, |
| 1412 | FM10K_STATS_NODESC_DROP, |
| 1413 | &stats->nodesc_drop); |
| 1414 | |
| 1415 | /* if value has not changed then we have consistent data */ |
| 1416 | id_prev = id; |
| 1417 | id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); |
| 1418 | } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK); |
| 1419 | |
| 1420 | /* drop non-ID bits and set VALID ID bit */ |
| 1421 | id &= FM10K_TXQCTL_ID_MASK; |
| 1422 | id |= FM10K_STAT_VALID; |
| 1423 | |
| 1424 | /* Update Global Statistics */ |
| 1425 | if (stats->stats_idx == id) { |
| 1426 | stats->timeout.count += timeout; |
| 1427 | stats->ur.count += ur; |
| 1428 | stats->ca.count += ca; |
| 1429 | stats->um.count += um; |
| 1430 | stats->xec.count += xec; |
| 1431 | stats->vlan_drop.count += vlan_drop; |
| 1432 | stats->loopback_drop.count += loopback_drop; |
| 1433 | stats->nodesc_drop.count += nodesc_drop; |
| 1434 | } |
| 1435 | |
| 1436 | /* Update bases and record current PF id */ |
| 1437 | fm10k_update_hw_base_32b(&stats->timeout, timeout); |
| 1438 | fm10k_update_hw_base_32b(&stats->ur, ur); |
| 1439 | fm10k_update_hw_base_32b(&stats->ca, ca); |
| 1440 | fm10k_update_hw_base_32b(&stats->um, um); |
| 1441 | fm10k_update_hw_base_32b(&stats->xec, xec); |
| 1442 | fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop); |
| 1443 | fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop); |
| 1444 | fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop); |
| 1445 | stats->stats_idx = id; |
| 1446 | |
| 1447 | /* Update Queue Statistics */ |
| 1448 | fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues); |
| 1449 | } |
| 1450 | |
| 1451 | /** |
| 1452 | * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF |
| 1453 | * @hw: pointer to hardware structure |
| 1454 | * @stats: pointer to the stats structure to update |
| 1455 | * |
| 1456 | * This function resets the base for global and per queue hardware |
| 1457 | * statistics. |
| 1458 | **/ |
| 1459 | static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw, |
| 1460 | struct fm10k_hw_stats *stats) |
| 1461 | { |
| 1462 | /* Unbind Global Statistics */ |
| 1463 | fm10k_unbind_hw_stats_32b(&stats->timeout); |
| 1464 | fm10k_unbind_hw_stats_32b(&stats->ur); |
| 1465 | fm10k_unbind_hw_stats_32b(&stats->ca); |
| 1466 | fm10k_unbind_hw_stats_32b(&stats->um); |
| 1467 | fm10k_unbind_hw_stats_32b(&stats->xec); |
| 1468 | fm10k_unbind_hw_stats_32b(&stats->vlan_drop); |
| 1469 | fm10k_unbind_hw_stats_32b(&stats->loopback_drop); |
| 1470 | fm10k_unbind_hw_stats_32b(&stats->nodesc_drop); |
| 1471 | |
| 1472 | /* Unbind Queue Statistics */ |
| 1473 | fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues); |
| 1474 | |
| 1475 | /* Reinitialize bases for all stats */ |
| 1476 | fm10k_update_hw_stats_pf(hw, stats); |
| 1477 | } |
| 1478 | |
| 1479 | /** |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1480 | * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system |
| 1481 | * @hw: pointer to hardware structure |
| 1482 | * @dma_mask: 64 bit DMA mask required for platform |
| 1483 | * |
| 1484 | * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order |
| 1485 | * to limit the access to memory beyond what is physically in the system. |
| 1486 | **/ |
| 1487 | static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask) |
| 1488 | { |
| 1489 | /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */ |
| 1490 | u32 phyaddr = (u32)(dma_mask >> 32); |
| 1491 | |
| 1492 | fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr); |
| 1493 | } |
| 1494 | |
| 1495 | /** |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1496 | * fm10k_get_fault_pf - Record a fault in one of the interface units |
| 1497 | * @hw: pointer to hardware structure |
| 1498 | * @type: pointer to fault type register offset |
| 1499 | * @fault: pointer to memory location to record the fault |
| 1500 | * |
| 1501 | * Record the fault register contents to the fault data structure and |
| 1502 | * clear the entry from the register. |
| 1503 | * |
| 1504 | * Returns ERR_PARAM if invalid register is specified or no error is present. |
| 1505 | **/ |
| 1506 | static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type, |
| 1507 | struct fm10k_fault *fault) |
| 1508 | { |
| 1509 | u32 func; |
| 1510 | |
| 1511 | /* verify the fault register is in range and is aligned */ |
| 1512 | switch (type) { |
| 1513 | case FM10K_PCA_FAULT: |
| 1514 | case FM10K_THI_FAULT: |
| 1515 | case FM10K_FUM_FAULT: |
| 1516 | break; |
| 1517 | default: |
| 1518 | return FM10K_ERR_PARAM; |
| 1519 | } |
| 1520 | |
| 1521 | /* only service faults that are valid */ |
| 1522 | func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC); |
| 1523 | if (!(func & FM10K_FAULT_FUNC_VALID)) |
| 1524 | return FM10K_ERR_PARAM; |
| 1525 | |
| 1526 | /* read remaining fields */ |
| 1527 | fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI); |
| 1528 | fault->address <<= 32; |
| 1529 | fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO); |
| 1530 | fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO); |
| 1531 | |
| 1532 | /* clear valid bit to allow for next error */ |
| 1533 | fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID); |
| 1534 | |
| 1535 | /* Record which function triggered the error */ |
| 1536 | if (func & FM10K_FAULT_FUNC_PF) |
| 1537 | fault->func = 0; |
| 1538 | else |
| 1539 | fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >> |
| 1540 | FM10K_FAULT_FUNC_VF_SHIFT); |
| 1541 | |
| 1542 | /* record fault type */ |
| 1543 | fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK; |
| 1544 | |
| 1545 | return 0; |
| 1546 | } |
| 1547 | |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1548 | /** |
| 1549 | * fm10k_request_lport_map_pf - Request LPORT map from the switch API |
| 1550 | * @hw: pointer to hardware structure |
| 1551 | * |
| 1552 | **/ |
| 1553 | static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw) |
| 1554 | { |
| 1555 | struct fm10k_mbx_info *mbx = &hw->mbx; |
| 1556 | u32 msg[1]; |
| 1557 | |
| 1558 | /* issue request asking for LPORT map */ |
| 1559 | fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP); |
| 1560 | |
| 1561 | /* load onto outgoing mailbox */ |
| 1562 | return mbx->ops.enqueue_tx(hw, mbx, msg); |
| 1563 | } |
| 1564 | |
| 1565 | /** |
| 1566 | * fm10k_get_host_state_pf - Returns the state of the switch and mailbox |
| 1567 | * @hw: pointer to hardware structure |
| 1568 | * @switch_ready: pointer to boolean value that will record switch state |
| 1569 | * |
| 1570 | * This funciton will check the DMA_CTRL2 register and mailbox in order |
| 1571 | * to determine if the switch is ready for the PF to begin requesting |
| 1572 | * addresses and mapping traffic to the local interface. |
| 1573 | **/ |
| 1574 | static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready) |
| 1575 | { |
| 1576 | s32 ret_val = 0; |
| 1577 | u32 dma_ctrl2; |
| 1578 | |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 1579 | /* verify the switch is ready for interaction */ |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1580 | dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2); |
| 1581 | if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY)) |
| 1582 | goto out; |
| 1583 | |
| 1584 | /* retrieve generic host state info */ |
| 1585 | ret_val = fm10k_get_host_state_generic(hw, switch_ready); |
| 1586 | if (ret_val) |
| 1587 | goto out; |
| 1588 | |
| 1589 | /* interface cannot receive traffic without logical ports */ |
| 1590 | if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE) |
| 1591 | ret_val = fm10k_request_lport_map_pf(hw); |
| 1592 | |
| 1593 | out: |
| 1594 | return ret_val; |
| 1595 | } |
| 1596 | |
| 1597 | /* This structure defines the attibutes to be parsed below */ |
| 1598 | const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = { |
| 1599 | FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP), |
| 1600 | FM10K_TLV_ATTR_LAST |
| 1601 | }; |
| 1602 | |
| 1603 | /** |
| 1604 | * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM |
| 1605 | * @hw: Pointer to hardware structure |
| 1606 | * @results: pointer array containing parsed data |
| 1607 | * @mbx: Pointer to mailbox information structure |
| 1608 | * |
| 1609 | * This handler configures the lport mapping based on the reply from the |
| 1610 | * switch API. |
| 1611 | **/ |
| 1612 | s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results, |
| 1613 | struct fm10k_mbx_info *mbx) |
| 1614 | { |
| 1615 | u16 glort, mask; |
| 1616 | u32 dglort_map; |
| 1617 | s32 err; |
| 1618 | |
| 1619 | err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP], |
| 1620 | &dglort_map); |
| 1621 | if (err) |
| 1622 | return err; |
| 1623 | |
| 1624 | /* extract values out of the header */ |
| 1625 | glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT); |
| 1626 | mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK); |
| 1627 | |
| 1628 | /* verify mask is set and none of the masked bits in glort are set */ |
| 1629 | if (!mask || (glort & ~mask)) |
| 1630 | return FM10K_ERR_PARAM; |
| 1631 | |
| 1632 | /* verify the mask is contiguous, and that it is 1's followed by 0's */ |
| 1633 | if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE) |
| 1634 | return FM10K_ERR_PARAM; |
| 1635 | |
| 1636 | /* record the glort, mask, and port count */ |
| 1637 | hw->mac.dglort_map = dglort_map; |
| 1638 | |
| 1639 | return 0; |
| 1640 | } |
| 1641 | |
| 1642 | const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = { |
| 1643 | FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID), |
| 1644 | FM10K_TLV_ATTR_LAST |
| 1645 | }; |
| 1646 | |
| 1647 | /** |
| 1648 | * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM |
| 1649 | * @hw: Pointer to hardware structure |
| 1650 | * @results: pointer array containing parsed data |
| 1651 | * @mbx: Pointer to mailbox information structure |
| 1652 | * |
| 1653 | * This handler configures the default VLAN for the PF |
| 1654 | **/ |
| 1655 | s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results, |
| 1656 | struct fm10k_mbx_info *mbx) |
| 1657 | { |
| 1658 | u16 glort, pvid; |
| 1659 | u32 pvid_update; |
| 1660 | s32 err; |
| 1661 | |
| 1662 | err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID], |
| 1663 | &pvid_update); |
| 1664 | if (err) |
| 1665 | return err; |
| 1666 | |
| 1667 | /* extract values from the pvid update */ |
| 1668 | glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT); |
| 1669 | pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID); |
| 1670 | |
| 1671 | /* if glort is not valid return error */ |
| 1672 | if (!fm10k_glort_valid_pf(hw, glort)) |
| 1673 | return FM10K_ERR_PARAM; |
| 1674 | |
| 1675 | /* verify VID is valid */ |
| 1676 | if (pvid >= FM10K_VLAN_TABLE_VID_MAX) |
| 1677 | return FM10K_ERR_PARAM; |
| 1678 | |
| 1679 | /* record the port VLAN ID value */ |
| 1680 | hw->mac.default_vid = pvid; |
| 1681 | |
| 1682 | return 0; |
| 1683 | } |
| 1684 | |
| 1685 | /** |
| 1686 | * fm10k_record_global_table_data - Move global table data to swapi table info |
| 1687 | * @from: pointer to source table data structure |
| 1688 | * @to: pointer to destination table info structure |
| 1689 | * |
| 1690 | * This function is will copy table_data to the table_info contained in |
| 1691 | * the hw struct. |
| 1692 | **/ |
| 1693 | static void fm10k_record_global_table_data(struct fm10k_global_table_data *from, |
| 1694 | struct fm10k_swapi_table_info *to) |
| 1695 | { |
| 1696 | /* convert from le32 struct to CPU byte ordered values */ |
| 1697 | to->used = le32_to_cpu(from->used); |
| 1698 | to->avail = le32_to_cpu(from->avail); |
| 1699 | } |
| 1700 | |
| 1701 | const struct fm10k_tlv_attr fm10k_err_msg_attr[] = { |
| 1702 | FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR, |
| 1703 | sizeof(struct fm10k_swapi_error)), |
| 1704 | FM10K_TLV_ATTR_LAST |
| 1705 | }; |
| 1706 | |
| 1707 | /** |
| 1708 | * fm10k_msg_err_pf - Message handler for error reply |
| 1709 | * @hw: Pointer to hardware structure |
| 1710 | * @results: pointer array containing parsed data |
| 1711 | * @mbx: Pointer to mailbox information structure |
| 1712 | * |
| 1713 | * This handler will capture the data for any error replies to previous |
| 1714 | * messages that the PF has sent. |
| 1715 | **/ |
| 1716 | s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results, |
| 1717 | struct fm10k_mbx_info *mbx) |
| 1718 | { |
| 1719 | struct fm10k_swapi_error err_msg; |
| 1720 | s32 err; |
| 1721 | |
| 1722 | /* extract structure from message */ |
| 1723 | err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR], |
| 1724 | &err_msg, sizeof(err_msg)); |
| 1725 | if (err) |
| 1726 | return err; |
| 1727 | |
| 1728 | /* record table status */ |
| 1729 | fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac); |
| 1730 | fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop); |
| 1731 | fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu); |
| 1732 | |
| 1733 | /* record SW API status value */ |
| 1734 | hw->swapi.status = le32_to_cpu(err_msg.status); |
| 1735 | |
| 1736 | return 0; |
| 1737 | } |
| 1738 | |
Alexander Duyck | 5f226dd | 2014-09-20 19:53:40 -0400 | [diff] [blame] | 1739 | const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = { |
| 1740 | FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP, |
| 1741 | sizeof(struct fm10k_swapi_1588_timestamp)), |
| 1742 | FM10K_TLV_ATTR_LAST |
| 1743 | }; |
| 1744 | |
| 1745 | /* currently there is no shared 1588 timestamp handler */ |
| 1746 | |
| 1747 | /** |
| 1748 | * fm10k_adjust_systime_pf - Adjust systime frequency |
| 1749 | * @hw: pointer to hardware structure |
| 1750 | * @ppb: adjustment rate in parts per billion |
| 1751 | * |
| 1752 | * This function will adjust the SYSTIME_CFG register contained in BAR 4 |
| 1753 | * if this function is supported for BAR 4 access. The adjustment amount |
| 1754 | * is based on the parts per billion value provided and adjusted to a |
| 1755 | * value based on parts per 2^48 clock cycles. |
| 1756 | * |
| 1757 | * If adjustment is not supported or the requested value is too large |
| 1758 | * we will return an error. |
| 1759 | **/ |
| 1760 | static s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb) |
| 1761 | { |
| 1762 | u64 systime_adjust; |
| 1763 | |
| 1764 | /* if sw_addr is not set we don't have switch register access */ |
| 1765 | if (!hw->sw_addr) |
| 1766 | return ppb ? FM10K_ERR_PARAM : 0; |
| 1767 | |
| 1768 | /* we must convert the value from parts per billion to parts per |
| 1769 | * 2^48 cycles. In addition I have opted to only use the 30 most |
| 1770 | * significant bits of the adjustment value as the 8 least |
| 1771 | * significant bits are located in another register and represent |
| 1772 | * a value significantly less than a part per billion, the result |
| 1773 | * of dropping the 8 least significant bits is that the adjustment |
| 1774 | * value is effectively multiplied by 2^8 when we write it. |
| 1775 | * |
| 1776 | * As a result of all this the math for this breaks down as follows: |
| 1777 | * ppb / 10^9 == adjust * 2^8 / 2^48 |
| 1778 | * If we solve this for adjust, and simplify it comes out as: |
| 1779 | * ppb * 2^31 / 5^9 == adjust |
| 1780 | */ |
| 1781 | systime_adjust = (ppb < 0) ? -ppb : ppb; |
| 1782 | systime_adjust <<= 31; |
| 1783 | do_div(systime_adjust, 1953125); |
| 1784 | |
| 1785 | /* verify the requested adjustment value is in range */ |
| 1786 | if (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK) |
| 1787 | return FM10K_ERR_PARAM; |
| 1788 | |
| 1789 | if (ppb < 0) |
| 1790 | systime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_NEGATIVE; |
| 1791 | |
| 1792 | fm10k_write_sw_reg(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust); |
| 1793 | |
| 1794 | return 0; |
| 1795 | } |
| 1796 | |
| 1797 | /** |
| 1798 | * fm10k_read_systime_pf - Reads value of systime registers |
| 1799 | * @hw: pointer to the hardware structure |
| 1800 | * |
| 1801 | * Function reads the content of 2 registers, combined to represent a 64 bit |
| 1802 | * value measured in nanosecods. In order to guarantee the value is accurate |
| 1803 | * we check the 32 most significant bits both before and after reading the |
| 1804 | * 32 least significant bits to verify they didn't change as we were reading |
| 1805 | * the registers. |
| 1806 | **/ |
| 1807 | static u64 fm10k_read_systime_pf(struct fm10k_hw *hw) |
| 1808 | { |
| 1809 | u32 systime_l, systime_h, systime_tmp; |
| 1810 | |
| 1811 | systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1); |
| 1812 | |
| 1813 | do { |
| 1814 | systime_tmp = systime_h; |
| 1815 | systime_l = fm10k_read_reg(hw, FM10K_SYSTIME); |
| 1816 | systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1); |
| 1817 | } while (systime_tmp != systime_h); |
| 1818 | |
| 1819 | return ((u64)systime_h << 32) | systime_l; |
| 1820 | } |
| 1821 | |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1822 | static const struct fm10k_msg_data fm10k_msg_data_pf[] = { |
| 1823 | FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf), |
| 1824 | FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf), |
| 1825 | FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf), |
| 1826 | FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf), |
| 1827 | FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf), |
| 1828 | FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf), |
| 1829 | FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error), |
| 1830 | }; |
| 1831 | |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1832 | static struct fm10k_mac_ops mac_ops_pf = { |
| 1833 | .get_bus_info = &fm10k_get_bus_info_generic, |
| 1834 | .reset_hw = &fm10k_reset_hw_pf, |
| 1835 | .init_hw = &fm10k_init_hw_pf, |
| 1836 | .start_hw = &fm10k_start_hw_generic, |
| 1837 | .stop_hw = &fm10k_stop_hw_generic, |
| 1838 | .is_slot_appropriate = &fm10k_is_slot_appropriate_pf, |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1839 | .update_vlan = &fm10k_update_vlan_pf, |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1840 | .read_mac_addr = &fm10k_read_mac_addr_pf, |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1841 | .update_uc_addr = &fm10k_update_uc_addr_pf, |
| 1842 | .update_mc_addr = &fm10k_update_mc_addr_pf, |
| 1843 | .update_xcast_mode = &fm10k_update_xcast_mode_pf, |
| 1844 | .update_int_moderator = &fm10k_update_int_moderator_pf, |
| 1845 | .update_lport_state = &fm10k_update_lport_state_pf, |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1846 | .update_hw_stats = &fm10k_update_hw_stats_pf, |
| 1847 | .rebind_hw_stats = &fm10k_rebind_hw_stats_pf, |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1848 | .configure_dglort_map = &fm10k_configure_dglort_map_pf, |
| 1849 | .set_dma_mask = &fm10k_set_dma_mask_pf, |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1850 | .get_fault = &fm10k_get_fault_pf, |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1851 | .get_host_state = &fm10k_get_host_state_pf, |
Alexander Duyck | 5f226dd | 2014-09-20 19:53:40 -0400 | [diff] [blame] | 1852 | .adjust_systime = &fm10k_adjust_systime_pf, |
| 1853 | .read_systime = &fm10k_read_systime_pf, |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1854 | }; |
| 1855 | |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1856 | static struct fm10k_iov_ops iov_ops_pf = { |
| 1857 | .assign_resources = &fm10k_iov_assign_resources_pf, |
| 1858 | .configure_tc = &fm10k_iov_configure_tc_pf, |
| 1859 | .assign_int_moderator = &fm10k_iov_assign_int_moderator_pf, |
| 1860 | .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf, |
| 1861 | .reset_resources = &fm10k_iov_reset_resources_pf, |
| 1862 | .set_lport = &fm10k_iov_set_lport_pf, |
| 1863 | .reset_lport = &fm10k_iov_reset_lport_pf, |
| 1864 | .update_stats = &fm10k_iov_update_stats_pf, |
Alexander Duyck | 5f226dd | 2014-09-20 19:53:40 -0400 | [diff] [blame] | 1865 | .report_timestamp = &fm10k_iov_report_timestamp_pf, |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1866 | }; |
| 1867 | |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1868 | static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw) |
| 1869 | { |
| 1870 | fm10k_get_invariants_generic(hw); |
| 1871 | |
| 1872 | return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf); |
| 1873 | } |
| 1874 | |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1875 | struct fm10k_info fm10k_pf_info = { |
| 1876 | .mac = fm10k_mac_pf, |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1877 | .get_invariants = &fm10k_get_invariants_pf, |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1878 | .mac_ops = &mac_ops_pf, |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1879 | .iov_ops = &iov_ops_pf, |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1880 | }; |