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gerrit-public.fairphone.software / kernel / msm-5.4 / a57350216d5d54dec387d8dd746ec73f2ea825a8 / . / arch / arm / boot / dts / imx53.dtsi
blob: 7ffeeed7c47c676a28144e5d6f2f3809aa95edd9 [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx53-pinfunc.h"
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]15
16/ {
17 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]30 };
31
32 tzic: tz-interrupt-controller@0fffc000 {
33 compatible = "fsl,imx53-tzic", "fsl,tzic";
34 interrupt-controller;
35 #interrupt-cells = <1>;
36 reg = <0x0fffc000 0x4000>;
37 };
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ckil {
44 compatible = "fsl,imx-ckil", "fixed-clock";
45 clock-frequency = <32768>;
46 };
47
48 ckih1 {
49 compatible = "fsl,imx-ckih1", "fixed-clock";
50 clock-frequency = <22579200>;
51 };
52
53 ckih2 {
54 compatible = "fsl,imx-ckih2", "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 osc {
59 compatible = "fsl,imx-osc", "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62 };
63
64 soc {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "simple-bus";
68 interrupt-parent = <&tzic>;
69 ranges;
70
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]71 ipu: ipu@18000000 {
72 #crtc-cells = <1>;
73 compatible = "fsl,imx53-ipu";
74 reg = <0x18000000 0x080000000>;
75 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]76 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
77 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]78 resets = <&src 2>;
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]79 };
80
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]81 aips@50000000 { /* AIPS1 */
82 compatible = "fsl,aips-bus", "simple-bus";
83 #address-cells = <1>;
84 #size-cells = <1>;
85 reg = <0x50000000 0x10000000>;
86 ranges;
87
88 spba@50000000 {
89 compatible = "fsl,spba-bus", "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 reg = <0x50000000 0x40000>;
93 ranges;
94
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]95 esdhc1: esdhc@50004000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]96 compatible = "fsl,imx53-esdhc";
97 reg = <0x50004000 0x4000>;
98 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]99 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
100 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]101 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]102 status = "disabled";
103 };
104
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]105 esdhc2: esdhc@50008000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]106 compatible = "fsl,imx53-esdhc";
107 reg = <0x50008000 0x4000>;
108 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]109 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
110 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]111 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]112 status = "disabled";
113 };
114
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]115 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]116 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
117 reg = <0x5000c000 0x4000>;
118 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]119 clocks = <&clks 32>, <&clks 33>;
120 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]121 status = "disabled";
122 };
123
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]124 ecspi1: ecspi@50010000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]125 #address-cells = <1>;
126 #size-cells = <0>;
127 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
128 reg = <0x50010000 0x4000>;
129 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]130 clocks = <&clks 51>, <&clks 52>;
131 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]132 status = "disabled";
133 };
134
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]135 ssi2: ssi@50014000 {
136 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
137 reg = <0x50014000 0x4000>;
138 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]139 clocks = <&clks 49>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]140 fsl,fifo-depth = <15>;
141 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
142 status = "disabled";
143 };
144
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]145 esdhc3: esdhc@50020000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]146 compatible = "fsl,imx53-esdhc";
147 reg = <0x50020000 0x4000>;
148 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]149 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
150 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]151 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]152 status = "disabled";
153 };
154
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]155 esdhc4: esdhc@50024000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]156 compatible = "fsl,imx53-esdhc";
157 reg = <0x50024000 0x4000>;
158 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]159 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
160 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]161 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]162 status = "disabled";
163 };
164 };
165
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]166 usbotg: usb@53f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]167 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
168 reg = <0x53f80000 0x0200>;
169 interrupts = <18>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame^]170 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]171 status = "disabled";
172 };
173
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]174 usbh1: usb@53f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]175 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
176 reg = <0x53f80200 0x0200>;
177 interrupts = <14>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame^]178 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]179 status = "disabled";
180 };
181
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]182 usbh2: usb@53f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]183 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
184 reg = <0x53f80400 0x0200>;
185 interrupts = <16>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame^]186 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]187 status = "disabled";
188 };
189
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]190 usbh3: usb@53f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]191 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
192 reg = <0x53f80600 0x0200>;
193 interrupts = <17>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame^]194 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]195 status = "disabled";
196 };
197
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame^]198 usbmisc: usbmisc@53f80800 {
199 #index-cells = <1>;
200 compatible = "fsl,imx53-usbmisc";
201 reg = <0x53f80800 0x200>;
202 };
203
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]204 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]205 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]206 reg = <0x53f84000 0x4000>;
207 interrupts = <50 51>;
208 gpio-controller;
209 #gpio-cells = <2>;
210 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]211 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]212 };
213
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]214 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]215 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]216 reg = <0x53f88000 0x4000>;
217 interrupts = <52 53>;
218 gpio-controller;
219 #gpio-cells = <2>;
220 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]221 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]222 };
223
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]224 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]225 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]226 reg = <0x53f8c000 0x4000>;
227 interrupts = <54 55>;
228 gpio-controller;
229 #gpio-cells = <2>;
230 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]231 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]232 };
233
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]234 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]235 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]236 reg = <0x53f90000 0x4000>;
237 interrupts = <56 57>;
238 gpio-controller;
239 #gpio-cells = <2>;
240 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]241 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]242 };
243
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]244 wdog1: wdog@53f98000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]245 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
246 reg = <0x53f98000 0x4000>;
247 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]248 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]249 };
250
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]251 wdog2: wdog@53f9c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]252 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
253 reg = <0x53f9c000 0x4000>;
254 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]255 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]256 status = "disabled";
257 };
258
Sascha Hauercc8aae92013-03-14 13:09:00 +0100[diff] [blame]259 gpt: timer@53fa0000 {
260 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
261 reg = <0x53fa0000 0x4000>;
262 interrupts = <39>;
263 clocks = <&clks 36>, <&clks 41>;
264 clock-names = "ipg", "per";
265 };
266
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]267 iomuxc: iomuxc@53fa8000 {
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]268 compatible = "fsl,imx53-iomuxc";
269 reg = <0x53fa8000 0x4000>;
270
271 audmux {
272 pinctrl_audmux_1: audmuxgrp-1 {
273 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]274 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
275 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
276 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
277 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]278 >;
279 };
280 };
281
282 fec {
283 pinctrl_fec_1: fecgrp-1 {
284 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]285 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
286 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
287 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
288 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
289 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
290 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
291 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
292 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
293 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
294 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]295 >;
296 };
297 };
298
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]299 csi {
300 pinctrl_csi_1: csigrp-1 {
301 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]302 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
303 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
304 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
305 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
306 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
307 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
308 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
309 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
310 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
311 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
312 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
313 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
314 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
315 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
316 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
317 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
318 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
319 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
320 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
321 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
322 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]323 >;
324 };
325 };
326
327 cspi {
328 pinctrl_cspi_1: cspigrp-1 {
329 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]330 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
331 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
332 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]333 >;
334 };
335 };
336
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]337 ecspi1 {
338 pinctrl_ecspi1_1: ecspi1grp-1 {
339 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]340 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
341 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
342 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]343 >;
344 };
345 };
346
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]347 esdhc1 {
348 pinctrl_esdhc1_1: esdhc1grp-1 {
349 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]350 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
351 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
352 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
353 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
354 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
355 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]356 >;
357 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]358
359 pinctrl_esdhc1_2: esdhc1grp-2 {
360 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]361 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
362 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
363 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
364 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
365 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
366 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
367 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
368 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
369 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
370 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]371 >;
372 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]373 };
374
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]375 esdhc2 {
376 pinctrl_esdhc2_1: esdhc2grp-1 {
377 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]378 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
379 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
380 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
381 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
382 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
383 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]384 >;
385 };
386 };
387
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]388 esdhc3 {
389 pinctrl_esdhc3_1: esdhc3grp-1 {
390 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]391 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
392 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
393 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
394 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
395 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
396 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
397 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
398 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
399 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
400 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]401 >;
402 };
403 };
404
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]405 can1 {
406 pinctrl_can1_1: can1grp-1 {
407 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]408 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
409 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]410 >;
411 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]412
413 pinctrl_can1_2: can1grp-2 {
414 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]415 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
416 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]417 >;
418 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]419 };
420
421 can2 {
422 pinctrl_can2_1: can2grp-1 {
423 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]424 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
425 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]426 >;
427 };
428 };
429
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]430 i2c1 {
431 pinctrl_i2c1_1: i2c1grp-1 {
432 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]433 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
434 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]435 >;
436 };
437 };
438
439 i2c2 {
440 pinctrl_i2c2_1: i2c2grp-1 {
441 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]442 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
443 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]444 >;
445 };
446 };
447
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]448 i2c3 {
449 pinctrl_i2c3_1: i2c3grp-1 {
450 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]451 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
452 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]453 >;
454 };
455 };
456
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]457 owire {
458 pinctrl_owire_1: owiregrp-1 {
459 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]460 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]461 >;
462 };
463 };
464
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]465 uart1 {
466 pinctrl_uart1_1: uart1grp-1 {
467 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]468 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
469 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]470 >;
471 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]472
473 pinctrl_uart1_2: uart1grp-2 {
474 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]475 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
476 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]477 >;
478 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]479 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]480
481 uart2 {
482 pinctrl_uart2_1: uart2grp-1 {
483 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]484 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
485 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]486 >;
487 };
488 };
489
490 uart3 {
491 pinctrl_uart3_1: uart3grp-1 {
492 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]493 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
494 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
495 MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
496 MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]497 >;
498 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]499
500 pinctrl_uart3_2: uart3grp-2 {
501 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]502 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
503 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]504 >;
505 };
506
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]507 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]508
509 uart4 {
510 pinctrl_uart4_1: uart4grp-1 {
511 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]512 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
513 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]514 >;
515 };
516 };
517
518 uart5 {
519 pinctrl_uart5_1: uart5grp-1 {
520 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]521 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
522 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]523 >;
524 };
525 };
526
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]527 };
528
Philipp Zabel5af9f142013-03-27 18:30:43 +0100[diff] [blame]529 gpr: iomuxc-gpr@53fa8000 {
530 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
531 reg = <0x53fa8000 0xc>;
532 };
533
Philipp Zabel420714a2013-03-27 18:30:44 +0100[diff] [blame]534 ldb: ldb@53fa8008 {
535 #address-cells = <1>;
536 #size-cells = <0>;
537 compatible = "fsl,imx53-ldb";
538 reg = <0x53fa8008 0x4>;
539 gpr = <&gpr>;
540 clocks = <&clks 122>, <&clks 120>,
541 <&clks 115>, <&clks 116>,
542 <&clks 123>, <&clks 85>;
543 clock-names = "di0_pll", "di1_pll",
544 "di0_sel", "di1_sel",
545 "di0", "di1";
546 status = "disabled";
547
548 lvds-channel@0 {
549 reg = <0>;
550 crtcs = <&ipu 0>;
551 status = "disabled";
552 };
553
554 lvds-channel@1 {
555 reg = <1>;
556 crtcs = <&ipu 1>;
557 status = "disabled";
558 };
559 };
560
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200[diff] [blame]561 pwm1: pwm@53fb4000 {
562 #pwm-cells = <2>;
563 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
564 reg = <0x53fb4000 0x4000>;
565 clocks = <&clks 37>, <&clks 38>;
566 clock-names = "ipg", "per";
567 interrupts = <61>;
568 };
569
570 pwm2: pwm@53fb8000 {
571 #pwm-cells = <2>;
572 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
573 reg = <0x53fb8000 0x4000>;
574 clocks = <&clks 39>, <&clks 40>;
575 clock-names = "ipg", "per";
576 interrupts = <94>;
577 };
578
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]579 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]580 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
581 reg = <0x53fbc000 0x4000>;
582 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]583 clocks = <&clks 28>, <&clks 29>;
584 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]585 status = "disabled";
586 };
587
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]588 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]589 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
590 reg = <0x53fc0000 0x4000>;
591 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]592 clocks = <&clks 30>, <&clks 31>;
593 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]594 status = "disabled";
595 };
596
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]597 can1: can@53fc8000 {
598 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
599 reg = <0x53fc8000 0x4000>;
600 interrupts = <82>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]601 clocks = <&clks 158>, <&clks 157>;
602 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]603 status = "disabled";
604 };
605
606 can2: can@53fcc000 {
607 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
608 reg = <0x53fcc000 0x4000>;
609 interrupts = <83>;
Marek Vasute37f0d52013-01-07 15:27:00 +0100[diff] [blame]610 clocks = <&clks 87>, <&clks 86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]611 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]612 status = "disabled";
613 };
614
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]615 src: src@53fd0000 {
616 compatible = "fsl,imx53-src", "fsl,imx51-src";
617 reg = <0x53fd0000 0x4000>;
618 #reset-cells = <1>;
619 };
620
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]621 clks: ccm@53fd4000{
622 compatible = "fsl,imx53-ccm";
623 reg = <0x53fd4000 0x4000>;
624 interrupts = <0 71 0x04 0 72 0x04>;
625 #clock-cells = <1>;
626 };
627
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]628 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]629 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]630 reg = <0x53fdc000 0x4000>;
631 interrupts = <103 104>;
632 gpio-controller;
633 #gpio-cells = <2>;
634 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]635 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]636 };
637
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]638 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]639 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]640 reg = <0x53fe0000 0x4000>;
641 interrupts = <105 106>;
642 gpio-controller;
643 #gpio-cells = <2>;
644 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]645 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]646 };
647
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]648 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]649 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]650 reg = <0x53fe4000 0x4000>;
651 interrupts = <107 108>;
652 gpio-controller;
653 #gpio-cells = <2>;
654 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]655 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]656 };
657
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]658 i2c3: i2c@53fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]659 #address-cells = <1>;
660 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]661 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]662 reg = <0x53fec000 0x4000>;
663 interrupts = <64>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]664 clocks = <&clks 88>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]665 status = "disabled";
666 };
667
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]668 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]669 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
670 reg = <0x53ff0000 0x4000>;
671 interrupts = <13>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]672 clocks = <&clks 65>, <&clks 66>;
673 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]674 status = "disabled";
675 };
676 };
677
678 aips@60000000 { /* AIPS2 */
679 compatible = "fsl,aips-bus", "simple-bus";
680 #address-cells = <1>;
681 #size-cells = <1>;
682 reg = <0x60000000 0x10000000>;
683 ranges;
684
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]685 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]686 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
687 reg = <0x63f90000 0x4000>;
688 interrupts = <86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]689 clocks = <&clks 67>, <&clks 68>;
690 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]691 status = "disabled";
692 };
693
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]694 owire: owire@63fa4000 {
695 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
696 reg = <0x63fa4000 0x4000>;
697 clocks = <&clks 159>;
698 status = "disabled";
699 };
700
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]701 ecspi2: ecspi@63fac000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]702 #address-cells = <1>;
703 #size-cells = <0>;
704 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
705 reg = <0x63fac000 0x4000>;
706 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]707 clocks = <&clks 53>, <&clks 54>;
708 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]709 status = "disabled";
710 };
711
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]712 sdma: sdma@63fb0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]713 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
714 reg = <0x63fb0000 0x4000>;
715 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]716 clocks = <&clks 56>, <&clks 56>;
717 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]718 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]719 };
720
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]721 cspi: cspi@63fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]722 #address-cells = <1>;
723 #size-cells = <0>;
724 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
725 reg = <0x63fc0000 0x4000>;
726 interrupts = <38>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200[diff] [blame]727 clocks = <&clks 55>, <&clks 55>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]728 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]729 status = "disabled";
730 };
731
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]732 i2c2: i2c@63fc4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]733 #address-cells = <1>;
734 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]735 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]736 reg = <0x63fc4000 0x4000>;
737 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]738 clocks = <&clks 35>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]739 status = "disabled";
740 };
741
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]742 i2c1: i2c@63fc8000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]743 #address-cells = <1>;
744 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]745 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]746 reg = <0x63fc8000 0x4000>;
747 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]748 clocks = <&clks 34>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]749 status = "disabled";
750 };
751
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]752 ssi1: ssi@63fcc000 {
753 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
754 reg = <0x63fcc000 0x4000>;
755 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]756 clocks = <&clks 48>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]757 fsl,fifo-depth = <15>;
758 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
759 status = "disabled";
760 };
761
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]762 audmux: audmux@63fd0000 {
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]763 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
764 reg = <0x63fd0000 0x4000>;
765 status = "disabled";
766 };
767
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]768 nfc: nand@63fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]769 compatible = "fsl,imx53-nand";
770 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
771 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]772 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]773 status = "disabled";
774 };
775
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]776 ssi3: ssi@63fe8000 {
777 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
778 reg = <0x63fe8000 0x4000>;
779 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]780 clocks = <&clks 50>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]781 fsl,fifo-depth = <15>;
782 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
783 status = "disabled";
784 };
785
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]786 fec: ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]787 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
788 reg = <0x63fec000 0x4000>;
789 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]790 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
791 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]792 status = "disabled";
793 };
794 };
795 };
796};