blob: 41195f1417f1f9f0f9aa77f1c8c971cdae8517a6 [file] [log] [blame]
Lennert Buytenhek2e16a772008-10-07 13:46:22 +00001/*
2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
Lennert Buytenheke84665c2009-03-20 09:52:09 +00003 * Copyright (c) 2008-2009 Marvell Semiconductor
Lennert Buytenhek2e16a772008-10-07 13:46:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
Barry Grussling19b2f972013-01-08 16:05:54 +000011#include <linux/delay.h>
12#include <linux/jiffies.h>
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000013#include <linux/list.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000014#include <linux/module.h>
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000015#include <linux/netdevice.h>
16#include <linux/phy.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000017#include <net/dsa.h>
Neil Armstrong6a4b2982015-11-10 16:51:36 +010018#include "mv88e6060.h"
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000019
20static int reg_read(struct dsa_switch *ds, int addr, int reg)
21{
Guenter Roeckb184e492014-10-17 12:30:58 -070022 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
23
24 if (bus == NULL)
25 return -EINVAL;
26
Neil Armstrongf0505612015-10-22 10:37:57 +020027 return mdiobus_read_nested(bus, ds->pd->sw_addr + addr, reg);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000028}
29
30#define REG_READ(addr, reg) \
31 ({ \
32 int __ret; \
33 \
34 __ret = reg_read(ds, addr, reg); \
35 if (__ret < 0) \
36 return __ret; \
37 __ret; \
38 })
39
40
41static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
42{
Guenter Roeckb184e492014-10-17 12:30:58 -070043 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
44
45 if (bus == NULL)
46 return -EINVAL;
47
Neil Armstrongf0505612015-10-22 10:37:57 +020048 return mdiobus_write_nested(bus, ds->pd->sw_addr + addr, reg, val);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000049}
50
51#define REG_WRITE(addr, reg, val) \
52 ({ \
53 int __ret; \
54 \
55 __ret = reg_write(ds, addr, reg, val); \
56 if (__ret < 0) \
57 return __ret; \
58 })
59
Andrew Lunnbbb8d792016-04-13 02:40:39 +020060static char *mv88e6060_probe(struct device *dsa_dev, struct device *host_dev,
Andrew Lunn7543a6d2016-04-13 02:40:40 +020061 int sw_addr, void **priv)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000062{
Alexander Duyckb4d23942014-09-15 13:00:27 -040063 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000064 int ret;
65
Andrew Lunn7543a6d2016-04-13 02:40:40 +020066 *priv = NULL;
Alexander Duyckb4d23942014-09-15 13:00:27 -040067 if (bus == NULL)
68 return NULL;
69
Neil Armstrong6a4b2982015-11-10 16:51:36 +010070 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000071 if (ret >= 0) {
Neil Armstrong6a4b2982015-11-10 16:51:36 +010072 if (ret == PORT_SWITCH_ID_6060)
Guenter Roeck3de6aa4c2014-10-29 10:44:54 -070073 return "Marvell 88E6060 (A0)";
Neil Armstrong6a4b2982015-11-10 16:51:36 +010074 if (ret == PORT_SWITCH_ID_6060_R1 ||
75 ret == PORT_SWITCH_ID_6060_R2)
Guenter Roeck3de6aa4c2014-10-29 10:44:54 -070076 return "Marvell 88E6060 (B0)";
Neil Armstrong6a4b2982015-11-10 16:51:36 +010077 if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000078 return "Marvell 88E6060";
79 }
80
81 return NULL;
82}
83
84static int mv88e6060_switch_reset(struct dsa_switch *ds)
85{
86 int i;
87 int ret;
Barry Grussling19b2f972013-01-08 16:05:54 +000088 unsigned long timeout;
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000089
Barry Grussling3675c8d2013-01-08 16:05:53 +000090 /* Set all ports to the disabled state. */
Neil Armstrong6a4b2982015-11-10 16:51:36 +010091 for (i = 0; i < MV88E6060_PORTS; i++) {
92 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
93 REG_WRITE(REG_PORT(i), PORT_CONTROL,
94 ret & ~PORT_CONTROL_STATE_MASK);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000095 }
96
Barry Grussling3675c8d2013-01-08 16:05:53 +000097 /* Wait for transmit queues to drain. */
Barry Grussling19b2f972013-01-08 16:05:54 +000098 usleep_range(2000, 4000);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000099
Barry Grussling3675c8d2013-01-08 16:05:53 +0000100 /* Reset the switch. */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100101 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
102 GLOBAL_ATU_CONTROL_SWRESET |
103 GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
104 GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000105
Barry Grussling3675c8d2013-01-08 16:05:53 +0000106 /* Wait up to one second for reset to complete. */
Barry Grussling19b2f972013-01-08 16:05:54 +0000107 timeout = jiffies + 1 * HZ;
108 while (time_before(jiffies, timeout)) {
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100109 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
110 if (ret & GLOBAL_STATUS_INIT_READY)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000111 break;
112
Barry Grussling19b2f972013-01-08 16:05:54 +0000113 usleep_range(1000, 2000);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000114 }
Barry Grussling19b2f972013-01-08 16:05:54 +0000115 if (time_after(jiffies, timeout))
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000116 return -ETIMEDOUT;
117
118 return 0;
119}
120
121static int mv88e6060_setup_global(struct dsa_switch *ds)
122{
Barry Grussling3675c8d2013-01-08 16:05:53 +0000123 /* Disable discarding of frames with excessive collisions,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000124 * set the maximum frame size to 1536 bytes, and mask all
125 * interrupt sources.
126 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100127 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000128
Barry Grussling3675c8d2013-01-08 16:05:53 +0000129 /* Enable automatic address learning, set the address
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000130 * database size to 1024 entries, and set the default aging
131 * time to 5 minutes.
132 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100133 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
134 GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
135 GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000136
137 return 0;
138}
139
140static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
141{
142 int addr = REG_PORT(p);
143
Barry Grussling3675c8d2013-01-08 16:05:53 +0000144 /* Do not force flow control, disable Ingress and Egress
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000145 * Header tagging, disable VLAN tunneling, and set the port
146 * state to Forwarding. Additionally, if this is the CPU
147 * port, enable Ingress and Egress Trailer tagging mode.
148 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100149 REG_WRITE(addr, PORT_CONTROL,
150 dsa_is_cpu_port(ds, p) ?
151 PORT_CONTROL_TRAILER |
152 PORT_CONTROL_INGRESS_MODE |
153 PORT_CONTROL_STATE_FORWARDING :
154 PORT_CONTROL_STATE_FORWARDING);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000155
Barry Grussling3675c8d2013-01-08 16:05:53 +0000156 /* Port based VLAN map: give each port its own address
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000157 * database, allow the CPU port to talk to each of the 'real'
158 * ports, and allow each of the 'real' ports to only talk to
159 * the CPU port.
160 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100161 REG_WRITE(addr, PORT_VLAN_MAP,
162 ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
163 (dsa_is_cpu_port(ds, p) ?
164 ds->phys_port_mask :
165 BIT(ds->dst->cpu_port)));
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000166
Barry Grussling3675c8d2013-01-08 16:05:53 +0000167 /* Port Association Vector: when learning source addresses
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000168 * of packets, add the address to the address database using
169 * a port bitmap that has only the bit for this port set and
170 * the other bits clear.
171 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100172 REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000173
174 return 0;
175}
176
177static int mv88e6060_setup(struct dsa_switch *ds)
178{
179 int i;
180 int ret;
181
182 ret = mv88e6060_switch_reset(ds);
183 if (ret < 0)
184 return ret;
185
186 /* @@@ initialise atu */
187
188 ret = mv88e6060_setup_global(ds);
189 if (ret < 0)
190 return ret;
191
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100192 for (i = 0; i < MV88E6060_PORTS; i++) {
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000193 ret = mv88e6060_setup_port(ds, i);
194 if (ret < 0)
195 return ret;
196 }
197
198 return 0;
199}
200
201static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
202{
Neil Armstrong83ea0f42015-11-10 16:51:32 +0100203 /* Use the same MAC Address as FD Pause frames for all ports */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100204 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
205 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
206 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000207
208 return 0;
209}
210
211static int mv88e6060_port_to_phy_addr(int port)
212{
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100213 if (port >= 0 && port < MV88E6060_PORTS)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000214 return port;
215 return -1;
216}
217
218static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
219{
220 int addr;
221
222 addr = mv88e6060_port_to_phy_addr(port);
223 if (addr == -1)
224 return 0xffff;
225
226 return reg_read(ds, addr, regnum);
227}
228
229static int
230mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
231{
232 int addr;
233
234 addr = mv88e6060_port_to_phy_addr(port);
235 if (addr == -1)
236 return 0xffff;
237
238 return reg_write(ds, addr, regnum, val);
239}
240
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000241static struct dsa_switch_driver mv88e6060_switch_driver = {
Florian Fainelliac7a04c2014-09-11 21:18:09 -0700242 .tag_protocol = DSA_TAG_PROTO_TRAILER,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000243 .probe = mv88e6060_probe,
244 .setup = mv88e6060_setup,
245 .set_addr = mv88e6060_set_addr,
246 .phy_read = mv88e6060_phy_read,
247 .phy_write = mv88e6060_phy_write,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000248};
249
Roel Kluin5eaa65b2008-12-10 15:18:31 -0800250static int __init mv88e6060_init(void)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000251{
252 register_switch_driver(&mv88e6060_switch_driver);
253 return 0;
254}
255module_init(mv88e6060_init);
256
Roel Kluin5eaa65b2008-12-10 15:18:31 -0800257static void __exit mv88e6060_cleanup(void)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000258{
259 unregister_switch_driver(&mv88e6060_switch_driver);
260}
261module_exit(mv88e6060_cleanup);
Ben Hutchings3d825ed2011-11-25 14:37:16 +0000262
263MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
264MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
265MODULE_LICENSE("GPL");
266MODULE_ALIAS("platform:mv88e6060");