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Lennert Buytenhek2e16a772008-10-07 13:46:22 +00001/*
2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
Lennert Buytenheke84665c2009-03-20 09:52:09 +00003 * Copyright (c) 2008-2009 Marvell Semiconductor
Lennert Buytenhek2e16a772008-10-07 13:46:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
Barry Grussling19b2f972013-01-08 16:05:54 +000011#include <linux/delay.h>
12#include <linux/jiffies.h>
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000013#include <linux/list.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000014#include <linux/module.h>
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000015#include <linux/netdevice.h>
16#include <linux/phy.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000017#include <net/dsa.h>
Neil Armstrong6a4b2982015-11-10 16:51:36 +010018#include "mv88e6060.h"
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000019
20static int reg_read(struct dsa_switch *ds, int addr, int reg)
21{
Guenter Roeckb184e492014-10-17 12:30:58 -070022 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
23
24 if (bus == NULL)
25 return -EINVAL;
26
Neil Armstrongf0505612015-10-22 10:37:57 +020027 return mdiobus_read_nested(bus, ds->pd->sw_addr + addr, reg);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000028}
29
30#define REG_READ(addr, reg) \
31 ({ \
32 int __ret; \
33 \
34 __ret = reg_read(ds, addr, reg); \
35 if (__ret < 0) \
36 return __ret; \
37 __ret; \
38 })
39
40
41static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
42{
Guenter Roeckb184e492014-10-17 12:30:58 -070043 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
44
45 if (bus == NULL)
46 return -EINVAL;
47
Neil Armstrongf0505612015-10-22 10:37:57 +020048 return mdiobus_write_nested(bus, ds->pd->sw_addr + addr, reg, val);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000049}
50
51#define REG_WRITE(addr, reg, val) \
52 ({ \
53 int __ret; \
54 \
55 __ret = reg_write(ds, addr, reg, val); \
56 if (__ret < 0) \
57 return __ret; \
58 })
59
Andrew Lunnbbb8d792016-04-13 02:40:39 +020060static char *mv88e6060_probe(struct device *dsa_dev, struct device *host_dev,
61 int sw_addr)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000062{
Alexander Duyckb4d23942014-09-15 13:00:27 -040063 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000064 int ret;
65
Alexander Duyckb4d23942014-09-15 13:00:27 -040066 if (bus == NULL)
67 return NULL;
68
Neil Armstrong6a4b2982015-11-10 16:51:36 +010069 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000070 if (ret >= 0) {
Neil Armstrong6a4b2982015-11-10 16:51:36 +010071 if (ret == PORT_SWITCH_ID_6060)
Guenter Roeck3de6aa4c2014-10-29 10:44:54 -070072 return "Marvell 88E6060 (A0)";
Neil Armstrong6a4b2982015-11-10 16:51:36 +010073 if (ret == PORT_SWITCH_ID_6060_R1 ||
74 ret == PORT_SWITCH_ID_6060_R2)
Guenter Roeck3de6aa4c2014-10-29 10:44:54 -070075 return "Marvell 88E6060 (B0)";
Neil Armstrong6a4b2982015-11-10 16:51:36 +010076 if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000077 return "Marvell 88E6060";
78 }
79
80 return NULL;
81}
82
83static int mv88e6060_switch_reset(struct dsa_switch *ds)
84{
85 int i;
86 int ret;
Barry Grussling19b2f972013-01-08 16:05:54 +000087 unsigned long timeout;
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000088
Barry Grussling3675c8d2013-01-08 16:05:53 +000089 /* Set all ports to the disabled state. */
Neil Armstrong6a4b2982015-11-10 16:51:36 +010090 for (i = 0; i < MV88E6060_PORTS; i++) {
91 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
92 REG_WRITE(REG_PORT(i), PORT_CONTROL,
93 ret & ~PORT_CONTROL_STATE_MASK);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000094 }
95
Barry Grussling3675c8d2013-01-08 16:05:53 +000096 /* Wait for transmit queues to drain. */
Barry Grussling19b2f972013-01-08 16:05:54 +000097 usleep_range(2000, 4000);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000098
Barry Grussling3675c8d2013-01-08 16:05:53 +000099 /* Reset the switch. */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100100 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
101 GLOBAL_ATU_CONTROL_SWRESET |
102 GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
103 GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000104
Barry Grussling3675c8d2013-01-08 16:05:53 +0000105 /* Wait up to one second for reset to complete. */
Barry Grussling19b2f972013-01-08 16:05:54 +0000106 timeout = jiffies + 1 * HZ;
107 while (time_before(jiffies, timeout)) {
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100108 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
109 if (ret & GLOBAL_STATUS_INIT_READY)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000110 break;
111
Barry Grussling19b2f972013-01-08 16:05:54 +0000112 usleep_range(1000, 2000);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000113 }
Barry Grussling19b2f972013-01-08 16:05:54 +0000114 if (time_after(jiffies, timeout))
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000115 return -ETIMEDOUT;
116
117 return 0;
118}
119
120static int mv88e6060_setup_global(struct dsa_switch *ds)
121{
Barry Grussling3675c8d2013-01-08 16:05:53 +0000122 /* Disable discarding of frames with excessive collisions,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000123 * set the maximum frame size to 1536 bytes, and mask all
124 * interrupt sources.
125 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100126 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000127
Barry Grussling3675c8d2013-01-08 16:05:53 +0000128 /* Enable automatic address learning, set the address
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000129 * database size to 1024 entries, and set the default aging
130 * time to 5 minutes.
131 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100132 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
133 GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
134 GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000135
136 return 0;
137}
138
139static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
140{
141 int addr = REG_PORT(p);
142
Barry Grussling3675c8d2013-01-08 16:05:53 +0000143 /* Do not force flow control, disable Ingress and Egress
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000144 * Header tagging, disable VLAN tunneling, and set the port
145 * state to Forwarding. Additionally, if this is the CPU
146 * port, enable Ingress and Egress Trailer tagging mode.
147 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100148 REG_WRITE(addr, PORT_CONTROL,
149 dsa_is_cpu_port(ds, p) ?
150 PORT_CONTROL_TRAILER |
151 PORT_CONTROL_INGRESS_MODE |
152 PORT_CONTROL_STATE_FORWARDING :
153 PORT_CONTROL_STATE_FORWARDING);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000154
Barry Grussling3675c8d2013-01-08 16:05:53 +0000155 /* Port based VLAN map: give each port its own address
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000156 * database, allow the CPU port to talk to each of the 'real'
157 * ports, and allow each of the 'real' ports to only talk to
158 * the CPU port.
159 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100160 REG_WRITE(addr, PORT_VLAN_MAP,
161 ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
162 (dsa_is_cpu_port(ds, p) ?
163 ds->phys_port_mask :
164 BIT(ds->dst->cpu_port)));
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000165
Barry Grussling3675c8d2013-01-08 16:05:53 +0000166 /* Port Association Vector: when learning source addresses
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000167 * of packets, add the address to the address database using
168 * a port bitmap that has only the bit for this port set and
169 * the other bits clear.
170 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100171 REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000172
173 return 0;
174}
175
176static int mv88e6060_setup(struct dsa_switch *ds)
177{
178 int i;
179 int ret;
180
181 ret = mv88e6060_switch_reset(ds);
182 if (ret < 0)
183 return ret;
184
185 /* @@@ initialise atu */
186
187 ret = mv88e6060_setup_global(ds);
188 if (ret < 0)
189 return ret;
190
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100191 for (i = 0; i < MV88E6060_PORTS; i++) {
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000192 ret = mv88e6060_setup_port(ds, i);
193 if (ret < 0)
194 return ret;
195 }
196
197 return 0;
198}
199
200static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
201{
Neil Armstrong83ea0f42015-11-10 16:51:32 +0100202 /* Use the same MAC Address as FD Pause frames for all ports */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100203 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
204 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
205 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000206
207 return 0;
208}
209
210static int mv88e6060_port_to_phy_addr(int port)
211{
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100212 if (port >= 0 && port < MV88E6060_PORTS)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000213 return port;
214 return -1;
215}
216
217static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
218{
219 int addr;
220
221 addr = mv88e6060_port_to_phy_addr(port);
222 if (addr == -1)
223 return 0xffff;
224
225 return reg_read(ds, addr, regnum);
226}
227
228static int
229mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
230{
231 int addr;
232
233 addr = mv88e6060_port_to_phy_addr(port);
234 if (addr == -1)
235 return 0xffff;
236
237 return reg_write(ds, addr, regnum, val);
238}
239
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000240static struct dsa_switch_driver mv88e6060_switch_driver = {
Florian Fainelliac7a04c2014-09-11 21:18:09 -0700241 .tag_protocol = DSA_TAG_PROTO_TRAILER,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000242 .probe = mv88e6060_probe,
243 .setup = mv88e6060_setup,
244 .set_addr = mv88e6060_set_addr,
245 .phy_read = mv88e6060_phy_read,
246 .phy_write = mv88e6060_phy_write,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000247};
248
Roel Kluin5eaa65b2008-12-10 15:18:31 -0800249static int __init mv88e6060_init(void)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000250{
251 register_switch_driver(&mv88e6060_switch_driver);
252 return 0;
253}
254module_init(mv88e6060_init);
255
Roel Kluin5eaa65b2008-12-10 15:18:31 -0800256static void __exit mv88e6060_cleanup(void)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000257{
258 unregister_switch_driver(&mv88e6060_switch_driver);
259}
260module_exit(mv88e6060_cleanup);
Ben Hutchings3d825ed2011-11-25 14:37:16 +0000261
262MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
263MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
264MODULE_LICENSE("GPL");
265MODULE_ALIAS("platform:mv88e6060");