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gerrit-public.fairphone.software / kernel / msm-5.4 / 8e388908e131aef967456e9cc7be7327e4079abd / . / arch / arm / boot / dts / imx51.dtsi
blob: 017491f09d3ada443e445072968f94128545d26a [file] [log] [blame]
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx51-pinfunc.h"
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]15
16/ {
17 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]25 };
26
27 tzic: tz-interrupt-controller@e0000000 {
28 compatible = "fsl,imx51-tzic", "fsl,tzic";
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 reg = <0xe0000000 0x4000>;
32 };
33
34 clocks {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 ckil {
39 compatible = "fsl,imx-ckil", "fixed-clock";
40 clock-frequency = <32768>;
41 };
42
43 ckih1 {
44 compatible = "fsl,imx-ckih1", "fixed-clock";
45 clock-frequency = <22579200>;
46 };
47
48 ckih2 {
49 compatible = "fsl,imx-ckih2", "fixed-clock";
50 clock-frequency = <0>;
51 };
52
53 osc {
54 compatible = "fsl,imx-osc", "fixed-clock";
55 clock-frequency = <24000000>;
56 };
57 };
58
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]59 cpus {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 cpu@0 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a8";
65 reg = <0>;
66 clock-latency = <61036>; /* two CLK32 periods */
67 clocks = <&clks 24>;
68 clock-names = "cpu";
69 operating-points = <
70 /* kHz uV (No regulator support) */
71 160000 0
72 800000 0
73 >;
74 };
75 };
76
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]77 soc {
78 #address-cells = <1>;
79 #size-cells = <1>;
80 compatible = "simple-bus";
81 interrupt-parent = <&tzic>;
82 ranges;
83
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]84 ipu: ipu@40000000 {
85 #crtc-cells = <1>;
86 compatible = "fsl,imx51-ipu";
87 reg = <0x40000000 0x20000000>;
88 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]89 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
90 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]91 resets = <&src 2>;
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]92 };
93
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]94 aips@70000000 { /* AIPS1 */
95 compatible = "fsl,aips-bus", "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 reg = <0x70000000 0x10000000>;
99 ranges;
100
101 spba@70000000 {
102 compatible = "fsl,spba-bus", "simple-bus";
103 #address-cells = <1>;
104 #size-cells = <1>;
105 reg = <0x70000000 0x40000>;
106 ranges;
107
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]108 esdhc1: esdhc@70004000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]109 compatible = "fsl,imx51-esdhc";
110 reg = <0x70004000 0x4000>;
111 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]112 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
113 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]114 status = "disabled";
115 };
116
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]117 esdhc2: esdhc@70008000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]118 compatible = "fsl,imx51-esdhc";
119 reg = <0x70008000 0x4000>;
120 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]121 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
122 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]123 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]124 status = "disabled";
125 };
126
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]127 uart3: serial@7000c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]128 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
129 reg = <0x7000c000 0x4000>;
130 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]131 clocks = <&clks 32>, <&clks 33>;
132 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]133 status = "disabled";
134 };
135
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]136 ecspi1: ecspi@70010000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]137 #address-cells = <1>;
138 #size-cells = <0>;
139 compatible = "fsl,imx51-ecspi";
140 reg = <0x70010000 0x4000>;
141 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]142 clocks = <&clks 51>, <&clks 52>;
143 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]144 status = "disabled";
145 };
146
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]147 ssi2: ssi@70014000 {
148 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
149 reg = <0x70014000 0x4000>;
150 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]151 clocks = <&clks 49>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]152 fsl,fifo-depth = <15>;
153 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
154 status = "disabled";
155 };
156
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]157 esdhc3: esdhc@70020000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]158 compatible = "fsl,imx51-esdhc";
159 reg = <0x70020000 0x4000>;
160 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]161 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
162 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]163 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]164 status = "disabled";
165 };
166
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]167 esdhc4: esdhc@70024000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]168 compatible = "fsl,imx51-esdhc";
169 reg = <0x70024000 0x4000>;
170 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]171 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
172 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]173 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]174 status = "disabled";
175 };
176 };
177
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]178 usbotg: usb@73f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]179 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
180 reg = <0x73f80000 0x0200>;
181 interrupts = <18>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame^]182 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]183 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]184 status = "disabled";
185 };
186
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]187 usbh1: usb@73f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]188 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
189 reg = <0x73f80200 0x0200>;
190 interrupts = <14>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame^]191 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]192 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]193 status = "disabled";
194 };
195
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]196 usbh2: usb@73f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]197 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
198 reg = <0x73f80400 0x0200>;
199 interrupts = <16>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame^]200 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]201 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]202 status = "disabled";
203 };
204
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]205 usbh3: usb@73f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]206 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
207 reg = <0x73f80600 0x0200>;
208 interrupts = <17>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame^]209 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]210 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]211 status = "disabled";
212 };
213
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]214 usbmisc: usbmisc@73f80800 {
215 #index-cells = <1>;
216 compatible = "fsl,imx51-usbmisc";
217 reg = <0x73f80800 0x200>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame^]218 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]219 };
220
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]221 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]222 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]223 reg = <0x73f84000 0x4000>;
224 interrupts = <50 51>;
225 gpio-controller;
226 #gpio-cells = <2>;
227 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]228 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]229 };
230
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]231 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]232 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]233 reg = <0x73f88000 0x4000>;
234 interrupts = <52 53>;
235 gpio-controller;
236 #gpio-cells = <2>;
237 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]238 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]239 };
240
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]241 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]242 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]243 reg = <0x73f8c000 0x4000>;
244 interrupts = <54 55>;
245 gpio-controller;
246 #gpio-cells = <2>;
247 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]248 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]249 };
250
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]251 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]252 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]253 reg = <0x73f90000 0x4000>;
254 interrupts = <56 57>;
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]258 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]259 };
260
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]261 kpp: kpp@73f94000 {
262 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
263 reg = <0x73f94000 0x4000>;
264 interrupts = <60>;
265 clocks = <&clks 0>;
266 status = "disabled";
267 };
268
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]269 wdog1: wdog@73f98000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]270 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
271 reg = <0x73f98000 0x4000>;
272 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]273 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]274 };
275
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]276 wdog2: wdog@73f9c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]277 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
278 reg = <0x73f9c000 0x4000>;
279 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]280 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]281 status = "disabled";
282 };
283
Sascha Hauered73c632013-03-14 13:08:59 +0100[diff] [blame]284 gpt: timer@73fa0000 {
285 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
286 reg = <0x73fa0000 0x4000>;
287 interrupts = <39>;
288 clocks = <&clks 36>, <&clks 41>;
289 clock-names = "ipg", "per";
290 };
291
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]292 iomuxc: iomuxc@73fa8000 {
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]293 compatible = "fsl,imx51-iomuxc";
294 reg = <0x73fa8000 0x4000>;
295
296 audmux {
297 pinctrl_audmux_1: audmuxgrp-1 {
298 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]299 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
300 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
301 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
302 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]303 >;
304 };
305 };
306
307 fec {
308 pinctrl_fec_1: fecgrp-1 {
309 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]310 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
311 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
312 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
313 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
314 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
315 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
316 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
317 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
318 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
319 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
320 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
321 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
322 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
323 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
324 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
325 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
326 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]327 >;
328 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]329
330 pinctrl_fec_2: fecgrp-2 {
331 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]332 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
333 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
334 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
335 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
336 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
337 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
338 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
339 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
340 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
341 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
342 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
343 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
344 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
345 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
346 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
347 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
348 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
349 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]350 >;
351 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]352 };
353
354 ecspi1 {
355 pinctrl_ecspi1_1: ecspi1grp-1 {
356 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]357 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
358 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
359 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]360 >;
361 };
362 };
363
Gwenhael Goavec-Meroua15ac4a2013-03-09 14:59:08 +0100[diff] [blame]364 ecspi2 {
365 pinctrl_ecspi2_1: ecspi2grp-1 {
366 fsl,pins = <
367 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
368 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
369 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
370 >;
371 };
372 };
373
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]374 esdhc1 {
375 pinctrl_esdhc1_1: esdhc1grp-1 {
376 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]377 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
378 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
379 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
380 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
381 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
382 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]383 >;
384 };
385 };
386
387 esdhc2 {
388 pinctrl_esdhc2_1: esdhc2grp-1 {
389 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]390 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
391 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
392 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
393 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
394 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
395 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]396 >;
397 };
398 };
399
400 i2c2 {
401 pinctrl_i2c2_1: i2c2grp-1 {
402 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]403 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
404 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]405 >;
406 };
Gwenhael Goavec-Merou52c9aa92013-03-09 15:04:19 +0100[diff] [blame]407
408 pinctrl_i2c2_2: i2c2grp-2 {
409 fsl,pins = <
410 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
411 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
412 >;
413 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]414 };
415
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]416 ipu_disp1 {
417 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
418 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]419 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
420 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
421 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
422 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
423 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
424 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
425 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
426 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
427 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
428 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
429 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
430 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
431 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
432 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
433 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
434 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
435 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
436 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
437 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
438 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
439 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
440 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
441 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
442 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
443 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
444 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]445 >;
446 };
447 };
448
449 ipu_disp2 {
450 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
451 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]452 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
453 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
454 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
455 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
456 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
457 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
458 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
459 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
460 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
461 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
462 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
463 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
464 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
465 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
466 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
467 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
468 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
469 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
470 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
471 MX51_PAD_DI_GP4__DI2_PIN15 0x5
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]472 >;
473 };
474 };
475
Sascha Hauer718a35002013-04-04 11:25:09 +0200[diff] [blame]476 pata {
477 pinctrl_pata_1: patagrp-1 {
478 fsl,pins = <
479 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
480 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
481 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
482 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
483 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
484 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
485 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
486 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
487 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
488 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
489 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
490 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
491 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
492 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
493 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
494 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
495 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
496 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
497 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
498 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
499 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
500 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
501 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
502 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
503 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
504 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
505 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
506 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
507 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
508 >;
509 };
510 };
511
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]512 uart1 {
513 pinctrl_uart1_1: uart1grp-1 {
514 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]515 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
516 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
517 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
518 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]519 >;
520 };
521 };
522
523 uart2 {
524 pinctrl_uart2_1: uart2grp-1 {
525 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]526 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
527 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]528 >;
529 };
530 };
531
532 uart3 {
533 pinctrl_uart3_1: uart3grp-1 {
534 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]535 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
536 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
537 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
538 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]539 >;
540 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]541
542 pinctrl_uart3_2: uart3grp-2 {
543 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]544 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
545 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]546 >;
547 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]548 };
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]549
550 kpp {
551 pinctrl_kpp_1: kppgrp-1 {
552 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]553 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
554 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
555 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
556 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
557 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
558 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
559 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
560 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]561 >;
562 };
563 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]564 };
565
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]566 pwm1: pwm@73fb4000 {
567 #pwm-cells = <2>;
568 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
569 reg = <0x73fb4000 0x4000>;
570 clocks = <&clks 37>, <&clks 38>;
571 clock-names = "ipg", "per";
572 interrupts = <61>;
573 };
574
575 pwm2: pwm@73fb8000 {
576 #pwm-cells = <2>;
577 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
578 reg = <0x73fb8000 0x4000>;
579 clocks = <&clks 39>, <&clks 40>;
580 clock-names = "ipg", "per";
581 interrupts = <94>;
582 };
583
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]584 uart1: serial@73fbc000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]585 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
586 reg = <0x73fbc000 0x4000>;
587 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]588 clocks = <&clks 28>, <&clks 29>;
589 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]590 status = "disabled";
591 };
592
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]593 uart2: serial@73fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]594 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
595 reg = <0x73fc0000 0x4000>;
596 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]597 clocks = <&clks 30>, <&clks 31>;
598 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]599 status = "disabled";
600 };
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]601
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]602 src: src@73fd0000 {
603 compatible = "fsl,imx51-src";
604 reg = <0x73fd0000 0x4000>;
605 #reset-cells = <1>;
606 };
607
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]608 clks: ccm@73fd4000{
609 compatible = "fsl,imx51-ccm";
610 reg = <0x73fd4000 0x4000>;
611 interrupts = <0 71 0x04 0 72 0x04>;
612 #clock-cells = <1>;
613 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]614 };
615
616 aips@80000000 { /* AIPS2 */
617 compatible = "fsl,aips-bus", "simple-bus";
618 #address-cells = <1>;
619 #size-cells = <1>;
620 reg = <0x80000000 0x10000000>;
621 ranges;
622
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]623 ecspi2: ecspi@83fac000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]624 #address-cells = <1>;
625 #size-cells = <0>;
626 compatible = "fsl,imx51-ecspi";
627 reg = <0x83fac000 0x4000>;
628 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]629 clocks = <&clks 53>, <&clks 54>;
630 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]631 status = "disabled";
632 };
633
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]634 sdma: sdma@83fb0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]635 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
636 reg = <0x83fb0000 0x4000>;
637 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]638 clocks = <&clks 56>, <&clks 56>;
639 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]640 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]641 };
642
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]643 cspi: cspi@83fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]644 #address-cells = <1>;
645 #size-cells = <0>;
646 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
647 reg = <0x83fc0000 0x4000>;
648 interrupts = <38>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200[diff] [blame]649 clocks = <&clks 55>, <&clks 55>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]650 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]651 status = "disabled";
652 };
653
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]654 i2c2: i2c@83fc4000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]655 #address-cells = <1>;
656 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]657 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]658 reg = <0x83fc4000 0x4000>;
659 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]660 clocks = <&clks 35>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]661 status = "disabled";
662 };
663
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]664 i2c1: i2c@83fc8000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]665 #address-cells = <1>;
666 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]667 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]668 reg = <0x83fc8000 0x4000>;
669 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]670 clocks = <&clks 34>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]671 status = "disabled";
672 };
673
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]674 ssi1: ssi@83fcc000 {
675 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
676 reg = <0x83fcc000 0x4000>;
677 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]678 clocks = <&clks 48>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]679 fsl,fifo-depth = <15>;
680 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
681 status = "disabled";
682 };
683
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]684 audmux: audmux@83fd0000 {
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]685 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
686 reg = <0x83fd0000 0x4000>;
687 status = "disabled";
688 };
689
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]690 nfc: nand@83fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]691 compatible = "fsl,imx51-nand";
692 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
693 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]694 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]695 status = "disabled";
696 };
697
Sascha Hauer718a35002013-04-04 11:25:09 +0200[diff] [blame]698 pata: pata@83fe0000 {
699 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
700 reg = <0x83fe0000 0x4000>;
701 interrupts = <70>;
702 clocks = <&clks 161>;
703 status = "disabled";
704 };
705
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]706 ssi3: ssi@83fe8000 {
707 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
708 reg = <0x83fe8000 0x4000>;
709 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]710 clocks = <&clks 50>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]711 fsl,fifo-depth = <15>;
712 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
713 status = "disabled";
714 };
715
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]716 fec: ethernet@83fec000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]717 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
718 reg = <0x83fec000 0x4000>;
719 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]720 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
721 clock-names = "ipg", "ahb", "ptp";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]722 status = "disabled";
723 };
724 };
725 };
726};