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gerrit-public.fairphone.software / kernel / msm-5.4 / b5af6b100c9fb4498051f831c90f69adebd82b88 / . / arch / arm / boot / dts / imx51.dtsi
blob: 44c7af791fa5cb21525b33c1cd23ea9fef51ad1e [file] [log] [blame]
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]24 };
25
26 tzic: tz-interrupt-controller@e0000000 {
27 compatible = "fsl,imx51-tzic", "fsl,tzic";
28 interrupt-controller;
29 #interrupt-cells = <1>;
30 reg = <0xe0000000 0x4000>;
31 };
32
33 clocks {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 ckil {
38 compatible = "fsl,imx-ckil", "fixed-clock";
39 clock-frequency = <32768>;
40 };
41
42 ckih1 {
43 compatible = "fsl,imx-ckih1", "fixed-clock";
44 clock-frequency = <22579200>;
45 };
46
47 ckih2 {
48 compatible = "fsl,imx-ckih2", "fixed-clock";
49 clock-frequency = <0>;
50 };
51
52 osc {
53 compatible = "fsl,imx-osc", "fixed-clock";
54 clock-frequency = <24000000>;
55 };
56 };
57
58 soc {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "simple-bus";
62 interrupt-parent = <&tzic>;
63 ranges;
64
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame^]65 ipu: ipu@40000000 {
66 #crtc-cells = <1>;
67 compatible = "fsl,imx51-ipu";
68 reg = <0x40000000 0x20000000>;
69 interrupts = <11 10>;
70 };
71
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]72 aips@70000000 { /* AIPS1 */
73 compatible = "fsl,aips-bus", "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 reg = <0x70000000 0x10000000>;
77 ranges;
78
79 spba@70000000 {
80 compatible = "fsl,spba-bus", "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 reg = <0x70000000 0x40000>;
84 ranges;
85
86 esdhc@70004000 { /* ESDHC1 */
87 compatible = "fsl,imx51-esdhc";
88 reg = <0x70004000 0x4000>;
89 interrupts = <1>;
90 status = "disabled";
91 };
92
93 esdhc@70008000 { /* ESDHC2 */
94 compatible = "fsl,imx51-esdhc";
95 reg = <0x70008000 0x4000>;
96 interrupts = <2>;
97 status = "disabled";
98 };
99
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]100 uart3: serial@7000c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]101 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
102 reg = <0x7000c000 0x4000>;
103 interrupts = <33>;
104 status = "disabled";
105 };
106
107 ecspi@70010000 { /* ECSPI1 */
108 #address-cells = <1>;
109 #size-cells = <0>;
110 compatible = "fsl,imx51-ecspi";
111 reg = <0x70010000 0x4000>;
112 interrupts = <36>;
113 status = "disabled";
114 };
115
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]116 ssi2: ssi@70014000 {
117 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
118 reg = <0x70014000 0x4000>;
119 interrupts = <30>;
120 fsl,fifo-depth = <15>;
121 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
122 status = "disabled";
123 };
124
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]125 esdhc@70020000 { /* ESDHC3 */
126 compatible = "fsl,imx51-esdhc";
127 reg = <0x70020000 0x4000>;
128 interrupts = <3>;
129 status = "disabled";
130 };
131
132 esdhc@70024000 { /* ESDHC4 */
133 compatible = "fsl,imx51-esdhc";
134 reg = <0x70024000 0x4000>;
135 interrupts = <4>;
136 status = "disabled";
137 };
138 };
139
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]140 usb@73f80000 {
141 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
142 reg = <0x73f80000 0x0200>;
143 interrupts = <18>;
144 status = "disabled";
145 };
146
147 usb@73f80200 {
148 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
149 reg = <0x73f80200 0x0200>;
150 interrupts = <14>;
151 status = "disabled";
152 };
153
154 usb@73f80400 {
155 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
156 reg = <0x73f80400 0x0200>;
157 interrupts = <16>;
158 status = "disabled";
159 };
160
161 usb@73f80600 {
162 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
163 reg = <0x73f80600 0x0200>;
164 interrupts = <17>;
165 status = "disabled";
166 };
167
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]168 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]169 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]170 reg = <0x73f84000 0x4000>;
171 interrupts = <50 51>;
172 gpio-controller;
173 #gpio-cells = <2>;
174 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]175 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]176 };
177
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]178 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]179 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]180 reg = <0x73f88000 0x4000>;
181 interrupts = <52 53>;
182 gpio-controller;
183 #gpio-cells = <2>;
184 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]185 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]186 };
187
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]188 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]189 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]190 reg = <0x73f8c000 0x4000>;
191 interrupts = <54 55>;
192 gpio-controller;
193 #gpio-cells = <2>;
194 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]195 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]196 };
197
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]198 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]199 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]200 reg = <0x73f90000 0x4000>;
201 interrupts = <56 57>;
202 gpio-controller;
203 #gpio-cells = <2>;
204 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]205 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]206 };
207
208 wdog@73f98000 { /* WDOG1 */
209 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
210 reg = <0x73f98000 0x4000>;
211 interrupts = <58>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]212 };
213
214 wdog@73f9c000 { /* WDOG2 */
215 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
216 reg = <0x73f9c000 0x4000>;
217 interrupts = <59>;
218 status = "disabled";
219 };
220
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]221 iomuxc@73fa8000 {
222 compatible = "fsl,imx51-iomuxc";
223 reg = <0x73fa8000 0x4000>;
224
225 audmux {
226 pinctrl_audmux_1: audmuxgrp-1 {
227 fsl,pins = <
228 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
229 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
230 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
231 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
232 >;
233 };
234 };
235
236 fec {
237 pinctrl_fec_1: fecgrp-1 {
238 fsl,pins = <
239 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
240 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
241 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
242 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
243 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
244 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
245 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
246 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
247 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
248 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
249 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
250 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
251 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
252 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
253 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
254 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
255 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
256 >;
257 };
258 };
259
260 ecspi1 {
261 pinctrl_ecspi1_1: ecspi1grp-1 {
262 fsl,pins = <
263 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
264 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
265 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
266 >;
267 };
268 };
269
270 esdhc1 {
271 pinctrl_esdhc1_1: esdhc1grp-1 {
272 fsl,pins = <
273 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
274 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
275 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
276 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
277 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
278 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
279 >;
280 };
281 };
282
283 esdhc2 {
284 pinctrl_esdhc2_1: esdhc2grp-1 {
285 fsl,pins = <
286 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
287 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
288 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
289 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
290 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
291 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
292 >;
293 };
294 };
295
296 i2c2 {
297 pinctrl_i2c2_1: i2c2grp-1 {
298 fsl,pins = <
299 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
300 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
301 >;
302 };
303 };
304
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame^]305 ipu_disp1 {
306 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
307 fsl,pins = <
308 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
309 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
310 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
311 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
312 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
313 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
314 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
315 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
316 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
317 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
318 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
319 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
320 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
321 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
322 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
323 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
324 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
325 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
326 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
327 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
328 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
329 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
330 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
331 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
332 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
333 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
334 >;
335 };
336 };
337
338 ipu_disp2 {
339 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
340 fsl,pins = <
341 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
342 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
343 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
344 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
345 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
346 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
347 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
348 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
349 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
350 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
351 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
352 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
353 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
354 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
355 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
356 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
357 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
358 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
359 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
360 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
361 >;
362 };
363 };
364
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]365 uart1 {
366 pinctrl_uart1_1: uart1grp-1 {
367 fsl,pins = <
368 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
369 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
370 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
371 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
372 >;
373 };
374 };
375
376 uart2 {
377 pinctrl_uart2_1: uart2grp-1 {
378 fsl,pins = <
379 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
380 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
381 >;
382 };
383 };
384
385 uart3 {
386 pinctrl_uart3_1: uart3grp-1 {
387 fsl,pins = <
388 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
389 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
390 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
391 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
392 >;
393 };
394 };
395 };
396
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]397 uart1: serial@73fbc000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]398 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
399 reg = <0x73fbc000 0x4000>;
400 interrupts = <31>;
401 status = "disabled";
402 };
403
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]404 uart2: serial@73fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]405 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
406 reg = <0x73fc0000 0x4000>;
407 interrupts = <32>;
408 status = "disabled";
409 };
410 };
411
412 aips@80000000 { /* AIPS2 */
413 compatible = "fsl,aips-bus", "simple-bus";
414 #address-cells = <1>;
415 #size-cells = <1>;
416 reg = <0x80000000 0x10000000>;
417 ranges;
418
419 ecspi@83fac000 { /* ECSPI2 */
420 #address-cells = <1>;
421 #size-cells = <0>;
422 compatible = "fsl,imx51-ecspi";
423 reg = <0x83fac000 0x4000>;
424 interrupts = <37>;
425 status = "disabled";
426 };
427
428 sdma@83fb0000 {
429 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
430 reg = <0x83fb0000 0x4000>;
431 interrupts = <6>;
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]432 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]433 };
434
435 cspi@83fc0000 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
439 reg = <0x83fc0000 0x4000>;
440 interrupts = <38>;
441 status = "disabled";
442 };
443
444 i2c@83fc4000 { /* I2C2 */
445 #address-cells = <1>;
446 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]447 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]448 reg = <0x83fc4000 0x4000>;
449 interrupts = <63>;
450 status = "disabled";
451 };
452
453 i2c@83fc8000 { /* I2C1 */
454 #address-cells = <1>;
455 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]456 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]457 reg = <0x83fc8000 0x4000>;
458 interrupts = <62>;
459 status = "disabled";
460 };
461
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]462 ssi1: ssi@83fcc000 {
463 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
464 reg = <0x83fcc000 0x4000>;
465 interrupts = <29>;
466 fsl,fifo-depth = <15>;
467 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
468 status = "disabled";
469 };
470
471 audmux@83fd0000 {
472 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
473 reg = <0x83fd0000 0x4000>;
474 status = "disabled";
475 };
476
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]477 nand@83fdb000 {
478 compatible = "fsl,imx51-nand";
479 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
480 interrupts = <8>;
481 status = "disabled";
482 };
483
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]484 ssi3: ssi@83fe8000 {
485 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
486 reg = <0x83fe8000 0x4000>;
487 interrupts = <96>;
488 fsl,fifo-depth = <15>;
489 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
490 status = "disabled";
491 };
492
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]493 ethernet@83fec000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]494 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
495 reg = <0x83fec000 0x4000>;
496 interrupts = <87>;
497 status = "disabled";
498 };
499 };
500 };
501};