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Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001/****************************************************************************
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002 * Driver for Solarflare network controllers and boards
3 * Copyright 2009-2013 Solarflare Communications Inc.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00004 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10
11#ifndef MCDI_PCOL_H
12#define MCDI_PCOL_H
13
14/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
15/* Power-on reset state */
16#define MC_FW_STATE_POR (1)
17/* If this is set in MC_RESET_STATE_REG then it should be
18 * possible to jump into IMEM without loading code from flash. */
19#define MC_FW_WARM_BOOT_OK (2)
20/* The MC main image has started to boot. */
21#define MC_FW_STATE_BOOTING (4)
22/* The Scheduler has started. */
23#define MC_FW_STATE_SCHED (8)
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +010024/* If this is set in MC_RESET_STATE_REG then it should be
25 * possible to jump into IMEM without loading code from flash.
26 * Unlike a warm boot, assume DMEM has been reloaded, so that
27 * the MC persistent data must be reinitialised. */
28#define MC_FW_TEPID_BOOT_OK (16)
29/* BIST state has been initialized */
30#define MC_FW_BIST_INIT_OK (128)
Steve Hodgsonf0d37f42009-11-29 15:15:07 +000031
Ben Hutchings05a93202011-12-20 00:44:06 +000032/* Siena MC shared memmory offsets */
33/* The 'doorbell' addresses are hard-wired to alert the MC when written */
34#define MC_SMEM_P0_DOORBELL_OFST 0x000
35#define MC_SMEM_P1_DOORBELL_OFST 0x004
36/* The rest of these are firmware-defined */
37#define MC_SMEM_P0_PDU_OFST 0x008
38#define MC_SMEM_P1_PDU_OFST 0x108
39#define MC_SMEM_PDU_LEN 0x100
40#define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
41#define MC_SMEM_P0_STATUS_OFST 0x7f8
42#define MC_SMEM_P1_STATUS_OFST 0x7fc
43
Steve Hodgsonf0d37f42009-11-29 15:15:07 +000044/* Values to be written to the per-port status dword in shared
45 * memory on reboot and assert */
46#define MC_STATUS_DWORD_REBOOT (0xb007b007)
47#define MC_STATUS_DWORD_ASSERT (0xdeaddead)
48
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +010049/* Check whether an mcfw version (in host order) belongs to a bootloader */
50#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
51
Steve Hodgsonf0d37f42009-11-29 15:15:07 +000052/* The current version of the MCDI protocol.
53 *
54 * Note that the ROM burnt into the card only talks V0, so at the very
55 * least every driver must support version 0 and MCDI_PCOL_VERSION
56 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +010057#define MCDI_PCOL_VERSION 2
Steve Hodgsonf0d37f42009-11-29 15:15:07 +000058
Ben Hutchings05a93202011-12-20 00:44:06 +000059/* Unused commands: 0x23, 0x27, 0x30, 0x31 */
60
Ben Hutchings1aa8b472012-07-10 10:56:59 +000061/* MCDI version 1
Steve Hodgsonf0d37f42009-11-29 15:15:07 +000062 *
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +010063 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
Steve Hodgsonf0d37f42009-11-29 15:15:07 +000064 * structure, filled in by the client.
65 *
66 * 0 7 8 16 20 22 23 24 31
67 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
68 * | | |
69 * | | \--- Response
70 * | \------- Error
71 * \------------------------------ Resync (always set)
72 *
73 * The client writes it's request into MC shared memory, and rings the
74 * doorbell. Each request is completed by either by the MC writting
75 * back into shared memory, or by writting out an event.
76 *
77 * All MCDI commands support completion by shared memory response. Each
78 * request may also contain additional data (accounted for by HEADER.LEN),
79 * and some response's may also contain additional data (again, accounted
80 * for by HEADER.LEN).
81 *
82 * Some MCDI commands support completion by event, in which any associated
83 * response data is included in the event.
84 *
85 * The protocol requires one response to be delivered for every request, a
86 * request should not be sent unless the response for the previous request
87 * has been received (either by polling shared memory, or by receiving
88 * an event).
89 */
90
91/** Request/Response structure */
92#define MCDI_HEADER_OFST 0
93#define MCDI_HEADER_CODE_LBN 0
94#define MCDI_HEADER_CODE_WIDTH 7
95#define MCDI_HEADER_RESYNC_LBN 7
96#define MCDI_HEADER_RESYNC_WIDTH 1
97#define MCDI_HEADER_DATALEN_LBN 8
98#define MCDI_HEADER_DATALEN_WIDTH 8
99#define MCDI_HEADER_SEQ_LBN 16
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000100#define MCDI_HEADER_SEQ_WIDTH 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100101#define MCDI_HEADER_RSVD_LBN 20
102#define MCDI_HEADER_RSVD_WIDTH 1
103#define MCDI_HEADER_NOT_EPOCH_LBN 21
104#define MCDI_HEADER_NOT_EPOCH_WIDTH 1
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000105#define MCDI_HEADER_ERROR_LBN 22
106#define MCDI_HEADER_ERROR_WIDTH 1
107#define MCDI_HEADER_RESPONSE_LBN 23
108#define MCDI_HEADER_RESPONSE_WIDTH 1
109#define MCDI_HEADER_XFLAGS_LBN 24
110#define MCDI_HEADER_XFLAGS_WIDTH 8
111/* Request response using event */
112#define MCDI_HEADER_XFLAGS_EVREQ 0x01
113
114/* Maximum number of payload bytes */
Ben Hutchingsd0c2ee92013-08-20 15:47:12 +0100115#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100116#define MCDI_CTL_SDU_LEN_MAX_V2 0x400
Ben Hutchingsd0c2ee92013-08-20 15:47:12 +0100117
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100118#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
119
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000120
121/* The MC can generate events for two reasons:
122 * - To complete a shared memory request if XFLAGS_EVREQ was set
123 * - As a notification (link state, i2c event), controlled
124 * via MC_CMD_LOG_CTRL
125 *
126 * Both events share a common structure:
127 *
128 * 0 32 33 36 44 52 60
129 * | Data | Cont | Level | Src | Code | Rsvd |
130 * |
131 * \ There is another event pending in this notification
132 *
133 * If Code==CMDDONE, then the fields are further interpreted as:
134 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300135 * - LEVEL==INFO Command succeeded
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000136 * - LEVEL==ERR Command failed
137 *
138 * 0 8 16 24 32
139 * | Seq | Datalen | Errno | Rsvd |
140 *
141 * These fields are taken directly out of the standard MCDI header, i.e.,
142 * LEVEL==ERR, Datalen == 0 => Reboot
143 *
144 * Events can be squirted out of the UART (using LOG_CTRL) without a
145 * MCDI header. An event can be distinguished from a MCDI response by
146 * examining the first byte which is 0xc0. This corresponds to the
147 * non-existent MCDI command MC_CMD_DEBUG_LOG.
148 *
149 * 0 7 8
150 * | command | Resync | = 0xc0
151 *
152 * Since the event is written in big-endian byte order, this works
153 * providing bits 56-63 of the event are 0xc0.
154 *
155 * 56 60 63
156 * | Rsvd | Code | = 0xc0
157 *
158 * Which means for convenience the event code is 0xc for all MC
159 * generated events.
160 */
161#define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
162
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000163
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100164/* Operation not permitted. */
165#define MC_CMD_ERR_EPERM 1
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000166/* Non-existent command target */
167#define MC_CMD_ERR_ENOENT 2
168/* assert() has killed the MC */
169#define MC_CMD_ERR_EINTR 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100170/* I/O failure */
171#define MC_CMD_ERR_EIO 5
172/* Try again */
173#define MC_CMD_ERR_EAGAIN 11
174/* Out of memory */
175#define MC_CMD_ERR_ENOMEM 12
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000176/* Caller does not hold required locks */
177#define MC_CMD_ERR_EACCES 13
178/* Resource is currently unavailable (e.g. lock contention) */
179#define MC_CMD_ERR_EBUSY 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100180/* No such device */
181#define MC_CMD_ERR_ENODEV 19
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000182/* Invalid argument to target */
183#define MC_CMD_ERR_EINVAL 22
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100184/* Out of range */
185#define MC_CMD_ERR_ERANGE 34
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000186/* Non-recursive resource is already acquired */
187#define MC_CMD_ERR_EDEADLK 35
188/* Operation not implemented */
189#define MC_CMD_ERR_ENOSYS 38
190/* Operation timed out */
191#define MC_CMD_ERR_ETIME 62
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100192/* Link has been severed */
193#define MC_CMD_ERR_ENOLINK 67
194/* Protocol error */
195#define MC_CMD_ERR_EPROTO 71
196/* Operation not supported */
197#define MC_CMD_ERR_ENOTSUP 95
198/* Address not available */
199#define MC_CMD_ERR_EADDRNOTAVAIL 99
200/* Not connected */
201#define MC_CMD_ERR_ENOTCONN 107
202/* Operation already in progress */
203#define MC_CMD_ERR_EALREADY 114
204
205/* Resource allocation failed. */
206#define MC_CMD_ERR_ALLOC_FAIL 0x1000
207/* V-adaptor not found. */
208#define MC_CMD_ERR_NO_VADAPTOR 0x1001
209/* EVB port not found. */
210#define MC_CMD_ERR_NO_EVB_PORT 0x1002
211/* V-switch not found. */
212#define MC_CMD_ERR_NO_VSWITCH 0x1003
213/* Too many VLAN tags. */
214#define MC_CMD_ERR_VLAN_LIMIT 0x1004
215/* Bad PCI function number. */
216#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
217/* Invalid VLAN mode. */
218#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
219/* Invalid v-switch type. */
220#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
221/* Invalid v-port type. */
222#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
223/* MAC address exists. */
224#define MC_CMD_ERR_MAC_EXIST 0x1009
225/* Slave core not present */
226#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
Ben Hutchings512bb062013-12-04 19:48:07 +0000227/* The datapath is disabled. */
228#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000229
230#define MC_CMD_ERR_CODE_OFST 0
231
Ben Hutchings05a93202011-12-20 00:44:06 +0000232/* We define 8 "escape" commands to allow
233 for command number space extension */
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000234
Ben Hutchings05a93202011-12-20 00:44:06 +0000235#define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
236#define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
237#define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
238#define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
239#define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
240#define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
241#define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
242#define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000243
244/* Vectors in the boot ROM */
245/* Point to the copycode entry point. */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100246#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
247#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000248/* Points to the recovery mode entry point. */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100249#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
250#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000251
Ben Hutchings05a93202011-12-20 00:44:06 +0000252/* The command set exported by the boot ROM (MCDI v0) */
253#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \
254 (1 << MC_CMD_READ32) | \
255 (1 << MC_CMD_WRITE32) | \
256 (1 << MC_CMD_COPYCODE) | \
257 (1 << MC_CMD_GET_VERSION), \
258 0, 0, 0 }
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000259
Ben Hutchings05a93202011-12-20 00:44:06 +0000260#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
261 (MC_CMD_SENSOR_ENTRY_OFST + (_x))
262
263#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \
264 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
265 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \
266 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
267
268#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \
269 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
270 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \
271 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
272
273#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \
274 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
275 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \
276 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
277
278
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100279/* Version 2 adds an optional argument to error returns: the errno value
280 * may be followed by the (0-based) number of the first argument that
281 * could not be processed.
282 */
283#define MC_CMD_ERR_ARG_OFST 4
284
285/* No space */
286#define MC_CMD_ERR_ENOSPC 28
287
Ben Hutchings05a93202011-12-20 00:44:06 +0000288/* MCDI_EVENT structuredef */
289#define MCDI_EVENT_LEN 8
290#define MCDI_EVENT_CONT_LBN 32
291#define MCDI_EVENT_CONT_WIDTH 1
292#define MCDI_EVENT_LEVEL_LBN 33
293#define MCDI_EVENT_LEVEL_WIDTH 3
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100294/* enum: Info. */
295#define MCDI_EVENT_LEVEL_INFO 0x0
296/* enum: Warning. */
297#define MCDI_EVENT_LEVEL_WARN 0x1
298/* enum: Error. */
299#define MCDI_EVENT_LEVEL_ERR 0x2
300/* enum: Fatal. */
301#define MCDI_EVENT_LEVEL_FATAL 0x3
Ben Hutchings05a93202011-12-20 00:44:06 +0000302#define MCDI_EVENT_DATA_OFST 0
303#define MCDI_EVENT_CMDDONE_SEQ_LBN 0
304#define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
305#define MCDI_EVENT_CMDDONE_DATALEN_LBN 8
306#define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
307#define MCDI_EVENT_CMDDONE_ERRNO_LBN 16
308#define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
309#define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
310#define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
311#define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
312#define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100313/* enum: 100Mbs */
314#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
315/* enum: 1Gbs */
316#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
317/* enum: 10Gbs */
318#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
319/* enum: 40Gbs */
320#define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
Ben Hutchings05a93202011-12-20 00:44:06 +0000321#define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
322#define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
323#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
324#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
325#define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
326#define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
327#define MCDI_EVENT_SENSOREVT_STATE_LBN 8
328#define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
329#define MCDI_EVENT_SENSOREVT_VALUE_LBN 16
330#define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
331#define MCDI_EVENT_FWALERT_DATA_LBN 8
332#define MCDI_EVENT_FWALERT_DATA_WIDTH 24
333#define MCDI_EVENT_FWALERT_REASON_LBN 0
334#define MCDI_EVENT_FWALERT_REASON_WIDTH 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100335/* enum: SRAM Access. */
336#define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
Ben Hutchings05a93202011-12-20 00:44:06 +0000337#define MCDI_EVENT_FLR_VF_LBN 0
338#define MCDI_EVENT_FLR_VF_WIDTH 8
339#define MCDI_EVENT_TX_ERR_TXQ_LBN 0
340#define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
341#define MCDI_EVENT_TX_ERR_TYPE_LBN 12
342#define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100343/* enum: Descriptor loader reported failure */
344#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
345/* enum: Descriptor ring empty and no EOP seen for packet */
346#define MCDI_EVENT_TX_ERR_NO_EOP 0x2
347/* enum: Overlength packet */
348#define MCDI_EVENT_TX_ERR_2BIG 0x3
349/* enum: Malformed option descriptor */
350#define MCDI_EVENT_TX_BAD_OPTDESC 0x5
351/* enum: Option descriptor part way through a packet */
352#define MCDI_EVENT_TX_OPT_IN_PKT 0x8
353/* enum: DMA or PIO data access error */
354#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
Ben Hutchings05a93202011-12-20 00:44:06 +0000355#define MCDI_EVENT_TX_ERR_INFO_LBN 16
356#define MCDI_EVENT_TX_ERR_INFO_WIDTH 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100357#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
358#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
Ben Hutchings05a93202011-12-20 00:44:06 +0000359#define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
360#define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
361#define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
362#define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100363/* enum: PLL lost lock */
364#define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
365/* enum: Filter overflow (PDMA) */
366#define MCDI_EVENT_PTP_ERR_FILTER 0x2
367/* enum: FIFO overflow (FPGA) */
368#define MCDI_EVENT_PTP_ERR_FIFO 0x3
369/* enum: Merge queue overflow */
370#define MCDI_EVENT_PTP_ERR_QUEUE 0x4
371#define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
372#define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
373/* enum: AOE failed to load - no valid image? */
374#define MCDI_EVENT_AOE_NO_LOAD 0x1
375/* enum: AOE FC reported an exception */
376#define MCDI_EVENT_AOE_FC_ASSERT 0x2
377/* enum: AOE FC watchdogged */
378#define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
379/* enum: AOE FC failed to start */
380#define MCDI_EVENT_AOE_FC_NO_START 0x4
381/* enum: Generic AOE fault - likely to have been reported via other means too
382 * but intended for use by aoex driver.
383 */
384#define MCDI_EVENT_AOE_FAULT 0x5
385/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
386#define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
387/* enum: AOE loaded successfully */
388#define MCDI_EVENT_AOE_LOAD 0x7
389/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
390#define MCDI_EVENT_AOE_DMA 0x8
391/* enum: AOE byteblaster connected/disconnected (Connection status in
392 * AOE_ERR_DATA)
393 */
394#define MCDI_EVENT_AOE_BYTEBLASTER 0x9
Ben Hutchings512bb062013-12-04 19:48:07 +0000395/* enum: DDR ECC status update */
396#define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100397#define MCDI_EVENT_AOE_ERR_DATA_LBN 8
398#define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
399#define MCDI_EVENT_RX_ERR_RXQ_LBN 0
400#define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
401#define MCDI_EVENT_RX_ERR_TYPE_LBN 12
402#define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
403#define MCDI_EVENT_RX_ERR_INFO_LBN 16
404#define MCDI_EVENT_RX_ERR_INFO_WIDTH 16
405#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
406#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
407#define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
408#define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
409#define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
410#define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
Ben Hutchings05a93202011-12-20 00:44:06 +0000411#define MCDI_EVENT_DATA_LBN 0
412#define MCDI_EVENT_DATA_WIDTH 32
413#define MCDI_EVENT_SRC_LBN 36
414#define MCDI_EVENT_SRC_WIDTH 8
415#define MCDI_EVENT_EV_CODE_LBN 60
416#define MCDI_EVENT_EV_CODE_WIDTH 4
417#define MCDI_EVENT_CODE_LBN 44
418#define MCDI_EVENT_CODE_WIDTH 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100419/* enum: Bad assert. */
420#define MCDI_EVENT_CODE_BADSSERT 0x1
421/* enum: PM Notice. */
422#define MCDI_EVENT_CODE_PMNOTICE 0x2
423/* enum: Command done. */
424#define MCDI_EVENT_CODE_CMDDONE 0x3
425/* enum: Link change. */
426#define MCDI_EVENT_CODE_LINKCHANGE 0x4
427/* enum: Sensor Event. */
428#define MCDI_EVENT_CODE_SENSOREVT 0x5
429/* enum: Schedule error. */
430#define MCDI_EVENT_CODE_SCHEDERR 0x6
431/* enum: Reboot. */
432#define MCDI_EVENT_CODE_REBOOT 0x7
433/* enum: Mac stats DMA. */
434#define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
435/* enum: Firmware alert. */
436#define MCDI_EVENT_CODE_FWALERT 0x9
437/* enum: Function level reset. */
438#define MCDI_EVENT_CODE_FLR 0xa
439/* enum: Transmit error */
440#define MCDI_EVENT_CODE_TX_ERR 0xb
441/* enum: Tx flush has completed */
442#define MCDI_EVENT_CODE_TX_FLUSH 0xc
443/* enum: PTP packet received timestamp */
444#define MCDI_EVENT_CODE_PTP_RX 0xd
445/* enum: PTP NIC failure */
446#define MCDI_EVENT_CODE_PTP_FAULT 0xe
447/* enum: PTP PPS event */
448#define MCDI_EVENT_CODE_PTP_PPS 0xf
449/* enum: Rx flush has completed */
450#define MCDI_EVENT_CODE_RX_FLUSH 0x10
451/* enum: Receive error */
452#define MCDI_EVENT_CODE_RX_ERR 0x11
453/* enum: AOE fault */
454#define MCDI_EVENT_CODE_AOE 0x12
455/* enum: Network port calibration failed (VCAL). */
456#define MCDI_EVENT_CODE_VCAL_FAIL 0x13
457/* enum: HW PPS event */
458#define MCDI_EVENT_CODE_HW_PPS 0x14
459/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
460 * a different format)
461 */
462#define MCDI_EVENT_CODE_MC_REBOOT 0x15
463/* enum: the MC has detected a parity error */
464#define MCDI_EVENT_CODE_PAR_ERR 0x16
465/* enum: the MC has detected a correctable error */
466#define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
467/* enum: the MC has detected an uncorrectable error */
468#define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
Ben Hutchings512bb062013-12-04 19:48:07 +0000469/* enum: The MC has entered offline BIST mode */
470#define MCDI_EVENT_CODE_MC_BIST 0x19
471/* enum: PTP tick event providing current NIC time */
472#define MCDI_EVENT_CODE_PTP_TIME 0x1a
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100473/* enum: Artificial event generated by host and posted via MC for test
474 * purposes.
475 */
476#define MCDI_EVENT_CODE_TESTGEN 0xfa
Ben Hutchings05a93202011-12-20 00:44:06 +0000477#define MCDI_EVENT_CMDDONE_DATA_OFST 0
478#define MCDI_EVENT_CMDDONE_DATA_LBN 0
479#define MCDI_EVENT_CMDDONE_DATA_WIDTH 32
480#define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
481#define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
482#define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
483#define MCDI_EVENT_SENSOREVT_DATA_OFST 0
484#define MCDI_EVENT_SENSOREVT_DATA_LBN 0
485#define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
486#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
487#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
488#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
489#define MCDI_EVENT_TX_ERR_DATA_OFST 0
490#define MCDI_EVENT_TX_ERR_DATA_LBN 0
491#define MCDI_EVENT_TX_ERR_DATA_WIDTH 32
Ben Hutchings512bb062013-12-04 19:48:07 +0000492/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of
493 * timestamp
494 */
Ben Hutchings05a93202011-12-20 00:44:06 +0000495#define MCDI_EVENT_PTP_SECONDS_OFST 0
496#define MCDI_EVENT_PTP_SECONDS_LBN 0
497#define MCDI_EVENT_PTP_SECONDS_WIDTH 32
Ben Hutchings512bb062013-12-04 19:48:07 +0000498/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of
499 * timestamp
500 */
501#define MCDI_EVENT_PTP_MAJOR_OFST 0
502#define MCDI_EVENT_PTP_MAJOR_LBN 0
503#define MCDI_EVENT_PTP_MAJOR_WIDTH 32
504/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field
505 * of timestamp
506 */
Ben Hutchings05a93202011-12-20 00:44:06 +0000507#define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
508#define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
509#define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
Ben Hutchings512bb062013-12-04 19:48:07 +0000510/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of
511 * timestamp
512 */
513#define MCDI_EVENT_PTP_MINOR_OFST 0
514#define MCDI_EVENT_PTP_MINOR_LBN 0
515#define MCDI_EVENT_PTP_MINOR_WIDTH 32
516/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
517 */
Ben Hutchings05a93202011-12-20 00:44:06 +0000518#define MCDI_EVENT_PTP_UUID_OFST 0
519#define MCDI_EVENT_PTP_UUID_LBN 0
520#define MCDI_EVENT_PTP_UUID_WIDTH 32
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100521#define MCDI_EVENT_RX_ERR_DATA_OFST 0
522#define MCDI_EVENT_RX_ERR_DATA_LBN 0
523#define MCDI_EVENT_RX_ERR_DATA_WIDTH 32
524#define MCDI_EVENT_PAR_ERR_DATA_OFST 0
525#define MCDI_EVENT_PAR_ERR_DATA_LBN 0
526#define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
527#define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
528#define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
529#define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
530#define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
531#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
532#define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
Ben Hutchings512bb062013-12-04 19:48:07 +0000533/* For CODE_PTP_TIME events, the major value of the PTP clock */
534#define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
535#define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
536#define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32
537/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
538#define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36
539#define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100540
541/* FCDI_EVENT structuredef */
542#define FCDI_EVENT_LEN 8
543#define FCDI_EVENT_CONT_LBN 32
544#define FCDI_EVENT_CONT_WIDTH 1
545#define FCDI_EVENT_LEVEL_LBN 33
546#define FCDI_EVENT_LEVEL_WIDTH 3
547/* enum: Info. */
548#define FCDI_EVENT_LEVEL_INFO 0x0
549/* enum: Warning. */
550#define FCDI_EVENT_LEVEL_WARN 0x1
551/* enum: Error. */
552#define FCDI_EVENT_LEVEL_ERR 0x2
553/* enum: Fatal. */
554#define FCDI_EVENT_LEVEL_FATAL 0x3
555#define FCDI_EVENT_DATA_OFST 0
556#define FCDI_EVENT_LINK_STATE_STATUS_LBN 0
557#define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
558#define FCDI_EVENT_LINK_DOWN 0x0 /* enum */
559#define FCDI_EVENT_LINK_UP 0x1 /* enum */
560#define FCDI_EVENT_DATA_LBN 0
561#define FCDI_EVENT_DATA_WIDTH 32
562#define FCDI_EVENT_SRC_LBN 36
563#define FCDI_EVENT_SRC_WIDTH 8
564#define FCDI_EVENT_EV_CODE_LBN 60
565#define FCDI_EVENT_EV_CODE_WIDTH 4
566#define FCDI_EVENT_CODE_LBN 44
567#define FCDI_EVENT_CODE_WIDTH 8
568/* enum: The FC was rebooted. */
569#define FCDI_EVENT_CODE_REBOOT 0x1
570/* enum: Bad assert. */
571#define FCDI_EVENT_CODE_ASSERT 0x2
572/* enum: DDR3 test result. */
573#define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
574/* enum: Link status. */
575#define FCDI_EVENT_CODE_LINK_STATE 0x4
576/* enum: A timed read is ready to be serviced. */
577#define FCDI_EVENT_CODE_TIMED_READ 0x5
578/* enum: One or more PPS IN events */
579#define FCDI_EVENT_CODE_PPS_IN 0x6
Ben Hutchings512bb062013-12-04 19:48:07 +0000580/* enum: Tick event from PTP clock */
581#define FCDI_EVENT_CODE_PTP_TICK 0x7
582/* enum: ECC error counters */
583#define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100584#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
585#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
586#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32
587#define FCDI_EVENT_ASSERT_TYPE_LBN 36
588#define FCDI_EVENT_ASSERT_TYPE_WIDTH 8
589#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36
590#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8
591#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
592#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
593#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32
594#define FCDI_EVENT_LINK_STATE_DATA_OFST 0
595#define FCDI_EVENT_LINK_STATE_DATA_LBN 0
596#define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32
Ben Hutchings512bb062013-12-04 19:48:07 +0000597#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36
598#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8
599#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
600#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
601#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100602
Ben Hutchings512bb062013-12-04 19:48:07 +0000603/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events
604 * to the MC. Note that this structure | is overlayed over a normal FCDI event
605 * such that bits 32-63 containing | event code, level, source etc remain the
606 * same. In this case the data | field of the header is defined to be the
607 * number of timestamps
608 */
609#define FCDI_EXTENDED_EVENT_PPS_LENMIN 16
610#define FCDI_EXTENDED_EVENT_PPS_LENMAX 248
611#define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100612/* Number of timestamps following */
613#define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
614#define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
615#define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32
616/* Seconds field of a timestamp record */
617#define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8
618#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64
619#define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32
620/* Nanoseconds field of a timestamp record */
621#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12
622#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96
623#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32
624/* Timestamp records comprising the event */
Ben Hutchings512bb062013-12-04 19:48:07 +0000625#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
626#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
627#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
628#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
629#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
630#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
631#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64
632#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64
Ben Hutchings05a93202011-12-20 00:44:06 +0000633
634
635/***********************************/
636/* MC_CMD_READ32
637 * Read multiple 32byte words from MC memory.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000638 */
Ben Hutchings05a93202011-12-20 00:44:06 +0000639#define MC_CMD_READ32 0x1
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000640
Shradha Shah75122ec2015-05-20 11:08:23 +0100641#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
642
Ben Hutchings05a93202011-12-20 00:44:06 +0000643/* MC_CMD_READ32_IN msgrequest */
644#define MC_CMD_READ32_IN_LEN 8
645#define MC_CMD_READ32_IN_ADDR_OFST 0
646#define MC_CMD_READ32_IN_NUMWORDS_OFST 4
647
648/* MC_CMD_READ32_OUT msgresponse */
649#define MC_CMD_READ32_OUT_LENMIN 4
650#define MC_CMD_READ32_OUT_LENMAX 252
651#define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
652#define MC_CMD_READ32_OUT_BUFFER_OFST 0
653#define MC_CMD_READ32_OUT_BUFFER_LEN 4
654#define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
655#define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
656
657
658/***********************************/
659/* MC_CMD_WRITE32
660 * Write multiple 32byte words to MC memory.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000661 */
Ben Hutchings05a93202011-12-20 00:44:06 +0000662#define MC_CMD_WRITE32 0x2
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000663
Shradha Shah75122ec2015-05-20 11:08:23 +0100664#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
665
Ben Hutchings05a93202011-12-20 00:44:06 +0000666/* MC_CMD_WRITE32_IN msgrequest */
667#define MC_CMD_WRITE32_IN_LENMIN 8
668#define MC_CMD_WRITE32_IN_LENMAX 252
669#define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
670#define MC_CMD_WRITE32_IN_ADDR_OFST 0
671#define MC_CMD_WRITE32_IN_BUFFER_OFST 4
672#define MC_CMD_WRITE32_IN_BUFFER_LEN 4
673#define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
674#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
675
676/* MC_CMD_WRITE32_OUT msgresponse */
677#define MC_CMD_WRITE32_OUT_LEN 0
678
679
680/***********************************/
681/* MC_CMD_COPYCODE
682 * Copy MC code between two locations and jump.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000683 */
Ben Hutchings05a93202011-12-20 00:44:06 +0000684#define MC_CMD_COPYCODE 0x3
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000685
Shradha Shah75122ec2015-05-20 11:08:23 +0100686#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
687
Ben Hutchings05a93202011-12-20 00:44:06 +0000688/* MC_CMD_COPYCODE_IN msgrequest */
689#define MC_CMD_COPYCODE_IN_LEN 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100690/* Source address */
Ben Hutchings05a93202011-12-20 00:44:06 +0000691#define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
Ben Hutchings512bb062013-12-04 19:48:07 +0000692/* enum: The main image should be entered via a copy of a single word from and
693 * to this address when none of the other magic behaviours are required.
694 */
695#define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100696/* enum: Entering the main image via a copy of a single word from and to this
697 * address indicates that it should not attempt to start the datapath CPUs.
698 * This is useful for certain soft rebooting scenarios. (Huntington only)
699 */
700#define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
701/* enum: Entering the main image via a copy of a single word from and to this
702 * address indicates that it should not attempt to parse any configuration from
703 * flash. (In addition, the datapath CPUs will not be started, as for
704 * MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR above.) This is useful for
705 * certain soft rebooting scenarios. (Huntington only)
706 */
707#define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
708/* Destination address */
Ben Hutchings05a93202011-12-20 00:44:06 +0000709#define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
710#define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100711/* Address of where to jump after copy. */
Ben Hutchings05a93202011-12-20 00:44:06 +0000712#define MC_CMD_COPYCODE_IN_JUMP_OFST 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100713/* enum: Control should return to the caller rather than jumping */
714#define MC_CMD_COPYCODE_JUMP_NONE 0x1
Ben Hutchings05a93202011-12-20 00:44:06 +0000715
716/* MC_CMD_COPYCODE_OUT msgresponse */
717#define MC_CMD_COPYCODE_OUT_LEN 0
718
719
720/***********************************/
721/* MC_CMD_SET_FUNC
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100722 * Select function for function-specific commands.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000723 */
Ben Hutchings05a93202011-12-20 00:44:06 +0000724#define MC_CMD_SET_FUNC 0x4
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000725
Shradha Shah75122ec2015-05-20 11:08:23 +0100726#define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
727
Ben Hutchings05a93202011-12-20 00:44:06 +0000728/* MC_CMD_SET_FUNC_IN msgrequest */
729#define MC_CMD_SET_FUNC_IN_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100730/* Set function */
Ben Hutchings05a93202011-12-20 00:44:06 +0000731#define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
732
733/* MC_CMD_SET_FUNC_OUT msgresponse */
734#define MC_CMD_SET_FUNC_OUT_LEN 0
735
736
737/***********************************/
738/* MC_CMD_GET_BOOT_STATUS
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100739 * Get the instruction address from which the MC booted.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000740 */
Ben Hutchings05a93202011-12-20 00:44:06 +0000741#define MC_CMD_GET_BOOT_STATUS 0x5
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000742
Shradha Shah75122ec2015-05-20 11:08:23 +0100743#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
744
Ben Hutchings05a93202011-12-20 00:44:06 +0000745/* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
746#define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
747
748/* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
749#define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100750/* ?? */
Ben Hutchings05a93202011-12-20 00:44:06 +0000751#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100752/* enum: indicates that the MC wasn't flash booted */
753#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
Ben Hutchings05a93202011-12-20 00:44:06 +0000754#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
755#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
756#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
757#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
758#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
759#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
760#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
761
762
763/***********************************/
764/* MC_CMD_GET_ASSERTS
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100765 * Get (and optionally clear) the current assertion status. Only
766 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other
767 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000768 */
Ben Hutchings05a93202011-12-20 00:44:06 +0000769#define MC_CMD_GET_ASSERTS 0x6
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000770
Shradha Shah75122ec2015-05-20 11:08:23 +0100771#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
772
Ben Hutchings05a93202011-12-20 00:44:06 +0000773/* MC_CMD_GET_ASSERTS_IN msgrequest */
774#define MC_CMD_GET_ASSERTS_IN_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100775/* Set to clear assertion */
Ben Hutchings05a93202011-12-20 00:44:06 +0000776#define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
777
778/* MC_CMD_GET_ASSERTS_OUT msgresponse */
779#define MC_CMD_GET_ASSERTS_OUT_LEN 140
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100780/* Assertion status flag. */
Ben Hutchings05a93202011-12-20 00:44:06 +0000781#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100782/* enum: No assertions have failed. */
783#define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
784/* enum: A system-level assertion has failed. */
785#define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
786/* enum: A thread-level assertion has failed. */
787#define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
788/* enum: The system was reset by the watchdog. */
789#define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
790/* enum: An illegal address trap stopped the system (huntington and later) */
791#define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
792/* Failing PC value */
Ben Hutchings05a93202011-12-20 00:44:06 +0000793#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100794/* Saved GP regs */
Ben Hutchings05a93202011-12-20 00:44:06 +0000795#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
796#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
797#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100798/* Failing thread address */
Ben Hutchings05a93202011-12-20 00:44:06 +0000799#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
800#define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
801
802
803/***********************************/
804/* MC_CMD_LOG_CTRL
805 * Configure the output stream for various events and messages.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000806 */
Ben Hutchings05a93202011-12-20 00:44:06 +0000807#define MC_CMD_LOG_CTRL 0x7
Steve Hodgsonf0d37f42009-11-29 15:15:07 +0000808
Shradha Shah75122ec2015-05-20 11:08:23 +0100809#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
810
Ben Hutchings05a93202011-12-20 00:44:06 +0000811/* MC_CMD_LOG_CTRL_IN msgrequest */
812#define MC_CMD_LOG_CTRL_IN_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100813/* Log destination */
Ben Hutchings05a93202011-12-20 00:44:06 +0000814#define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100815/* enum: UART. */
816#define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
817/* enum: Event queue. */
818#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
Ben Hutchings05a93202011-12-20 00:44:06 +0000819#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
820
821/* MC_CMD_LOG_CTRL_OUT msgresponse */
822#define MC_CMD_LOG_CTRL_OUT_LEN 0
823
824
825/***********************************/
826/* MC_CMD_GET_VERSION
827 * Get version information about the MC firmware.
828 */
829#define MC_CMD_GET_VERSION 0x8
830
Shradha Shah75122ec2015-05-20 11:08:23 +0100831#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
832
Ben Hutchings05a93202011-12-20 00:44:06 +0000833/* MC_CMD_GET_VERSION_IN msgrequest */
834#define MC_CMD_GET_VERSION_IN_LEN 0
835
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100836/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */
837#define MC_CMD_GET_VERSION_EXT_IN_LEN 4
838/* placeholder, set to 0 */
839#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
840
841/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */
Ben Hutchings05a93202011-12-20 00:44:06 +0000842#define MC_CMD_GET_VERSION_V0_OUT_LEN 4
843#define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100844/* enum: Reserved version number to indicate "any" version. */
845#define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
846/* enum: Bootrom version value for Siena. */
847#define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
848/* enum: Bootrom version value for Huntington. */
849#define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
Ben Hutchings05a93202011-12-20 00:44:06 +0000850
851/* MC_CMD_GET_VERSION_OUT msgresponse */
852#define MC_CMD_GET_VERSION_OUT_LEN 32
853/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
854/* Enum values, see field(s): */
855/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
856#define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100857/* 128bit mask of functions supported by the current firmware */
Ben Hutchings05a93202011-12-20 00:44:06 +0000858#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
859#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
860#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
861#define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
862#define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
863#define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
864
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100865/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
866#define MC_CMD_GET_VERSION_EXT_OUT_LEN 48
867/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
868/* Enum values, see field(s): */
869/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
870#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
871/* 128bit mask of functions supported by the current firmware */
872#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8
873#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16
874#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
875#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
876#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
877#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
878/* extra info */
879#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
880#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
Ben Hutchings05a93202011-12-20 00:44:06 +0000881
882
883/***********************************/
884/* MC_CMD_PTP
885 * Perform PTP operation
886 */
887#define MC_CMD_PTP 0xb
888
Shradha Shah75122ec2015-05-20 11:08:23 +0100889#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
890
Ben Hutchings05a93202011-12-20 00:44:06 +0000891/* MC_CMD_PTP_IN msgrequest */
892#define MC_CMD_PTP_IN_LEN 1
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100893/* PTP operation code */
Ben Hutchings05a93202011-12-20 00:44:06 +0000894#define MC_CMD_PTP_IN_OP_OFST 0
895#define MC_CMD_PTP_IN_OP_LEN 1
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100896/* enum: Enable PTP packet timestamping operation. */
897#define MC_CMD_PTP_OP_ENABLE 0x1
898/* enum: Disable PTP packet timestamping operation. */
899#define MC_CMD_PTP_OP_DISABLE 0x2
900/* enum: Send a PTP packet. */
901#define MC_CMD_PTP_OP_TRANSMIT 0x3
902/* enum: Read the current NIC time. */
903#define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
904/* enum: Get the current PTP status. */
905#define MC_CMD_PTP_OP_STATUS 0x5
906/* enum: Adjust the PTP NIC's time. */
907#define MC_CMD_PTP_OP_ADJUST 0x6
908/* enum: Synchronize host and NIC time. */
909#define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
910/* enum: Basic manufacturing tests. */
911#define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
912/* enum: Packet based manufacturing tests. */
913#define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
914/* enum: Reset some of the PTP related statistics */
915#define MC_CMD_PTP_OP_RESET_STATS 0xa
916/* enum: Debug operations to MC. */
917#define MC_CMD_PTP_OP_DEBUG 0xb
918/* enum: Read an FPGA register */
919#define MC_CMD_PTP_OP_FPGAREAD 0xc
920/* enum: Write an FPGA register */
921#define MC_CMD_PTP_OP_FPGAWRITE 0xd
922/* enum: Apply an offset to the NIC clock */
923#define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
924/* enum: Change Apply an offset to the NIC clock */
925#define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
926/* enum: Set the MC packet filter VLAN tags for received PTP packets */
927#define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
928/* enum: Set the MC packet filter UUID for received PTP packets */
929#define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
930/* enum: Set the MC packet filter Domain for received PTP packets */
931#define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
932/* enum: Set the clock source */
933#define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
934/* enum: Reset value of Timer Reg. */
935#define MC_CMD_PTP_OP_RST_CLK 0x14
936/* enum: Enable the forwarding of PPS events to the host */
937#define MC_CMD_PTP_OP_PPS_ENABLE 0x15
Ben Hutchings512bb062013-12-04 19:48:07 +0000938/* enum: Get the time format used by this NIC for PTP operations */
939#define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
940/* enum: Get the clock attributes. NOTE- extended version of
941 * MC_CMD_PTP_OP_GET_TIME_FORMAT
942 */
943#define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
944/* enum: Get corrections that should be applied to the various different
945 * timestamps
946 */
947#define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
948/* enum: Subscribe to receive periodic time events indicating the current NIC
949 * time
950 */
951#define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
952/* enum: Unsubscribe to stop receiving time events */
953#define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
954/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS
955 * input on the same NIC.
956 */
957#define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100958/* enum: Above this for future use. */
Ben Hutchings512bb062013-12-04 19:48:07 +0000959#define MC_CMD_PTP_OP_MAX 0x1b
Ben Hutchings05a93202011-12-20 00:44:06 +0000960
961/* MC_CMD_PTP_IN_ENABLE msgrequest */
962#define MC_CMD_PTP_IN_ENABLE_LEN 16
963#define MC_CMD_PTP_IN_CMD_OFST 0
964#define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100965/* Event queue for PTP events */
Ben Hutchings05a93202011-12-20 00:44:06 +0000966#define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100967/* PTP timestamping mode */
Ben Hutchings05a93202011-12-20 00:44:06 +0000968#define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100969/* enum: PTP, version 1 */
970#define MC_CMD_PTP_MODE_V1 0x0
971/* enum: PTP, version 1, with VLAN headers - deprecated */
972#define MC_CMD_PTP_MODE_V1_VLAN 0x1
973/* enum: PTP, version 2 */
974#define MC_CMD_PTP_MODE_V2 0x2
975/* enum: PTP, version 2, with VLAN headers - deprecated */
976#define MC_CMD_PTP_MODE_V2_VLAN 0x3
977/* enum: PTP, version 2, with improved UUID filtering */
978#define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
979/* enum: FCoE (seconds and microseconds) */
980#define MC_CMD_PTP_MODE_FCOE 0x5
Ben Hutchings05a93202011-12-20 00:44:06 +0000981
982/* MC_CMD_PTP_IN_DISABLE msgrequest */
983#define MC_CMD_PTP_IN_DISABLE_LEN 8
984/* MC_CMD_PTP_IN_CMD_OFST 0 */
985/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
986
987/* MC_CMD_PTP_IN_TRANSMIT msgrequest */
988#define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
Ben Hutchings576eda82012-09-19 02:46:37 +0100989#define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
Ben Hutchings05a93202011-12-20 00:44:06 +0000990#define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
991/* MC_CMD_PTP_IN_CMD_OFST 0 */
992/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100993/* Transmit packet length */
Ben Hutchings05a93202011-12-20 00:44:06 +0000994#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +0100995/* Transmit packet data */
Ben Hutchings05a93202011-12-20 00:44:06 +0000996#define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
997#define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
998#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
Ben Hutchings576eda82012-09-19 02:46:37 +0100999#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
Ben Hutchings05a93202011-12-20 00:44:06 +00001000
1001/* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
1002#define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
1003/* MC_CMD_PTP_IN_CMD_OFST 0 */
1004/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1005
1006/* MC_CMD_PTP_IN_STATUS msgrequest */
1007#define MC_CMD_PTP_IN_STATUS_LEN 8
1008/* MC_CMD_PTP_IN_CMD_OFST 0 */
1009/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1010
1011/* MC_CMD_PTP_IN_ADJUST msgrequest */
1012#define MC_CMD_PTP_IN_ADJUST_LEN 24
1013/* MC_CMD_PTP_IN_CMD_OFST 0 */
1014/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001015/* Frequency adjustment 40 bit fixed point ns */
Ben Hutchings05a93202011-12-20 00:44:06 +00001016#define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
1017#define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
1018#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
1019#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001020/* enum: Number of fractional bits in frequency adjustment */
1021#define MC_CMD_PTP_IN_ADJUST_BITS 0x28
1022/* Time adjustment in seconds */
Ben Hutchings05a93202011-12-20 00:44:06 +00001023#define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
Ben Hutchings512bb062013-12-04 19:48:07 +00001024/* Time adjustment major value */
1025#define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001026/* Time adjustment in nanoseconds */
Ben Hutchings05a93202011-12-20 00:44:06 +00001027#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
Ben Hutchings512bb062013-12-04 19:48:07 +00001028/* Time adjustment minor value */
1029#define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20
Ben Hutchings05a93202011-12-20 00:44:06 +00001030
1031/* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
1032#define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
1033/* MC_CMD_PTP_IN_CMD_OFST 0 */
1034/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001035/* Number of time readings to capture */
Ben Hutchings05a93202011-12-20 00:44:06 +00001036#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001037/* Host address in which to write "synchronization started" indication (64
1038 * bits)
1039 */
Ben Hutchings05a93202011-12-20 00:44:06 +00001040#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
1041#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
1042#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
1043#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
1044
1045/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
1046#define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
1047/* MC_CMD_PTP_IN_CMD_OFST 0 */
1048/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1049
1050/* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
1051#define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
1052/* MC_CMD_PTP_IN_CMD_OFST 0 */
1053/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001054/* Enable or disable packet testing */
Ben Hutchings05a93202011-12-20 00:44:06 +00001055#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
1056
1057/* MC_CMD_PTP_IN_RESET_STATS msgrequest */
1058#define MC_CMD_PTP_IN_RESET_STATS_LEN 8
1059/* MC_CMD_PTP_IN_CMD_OFST 0 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001060/* Reset PTP statistics */
Ben Hutchings05a93202011-12-20 00:44:06 +00001061/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1062
1063/* MC_CMD_PTP_IN_DEBUG msgrequest */
1064#define MC_CMD_PTP_IN_DEBUG_LEN 12
1065/* MC_CMD_PTP_IN_CMD_OFST 0 */
1066/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001067/* Debug operations */
Ben Hutchings05a93202011-12-20 00:44:06 +00001068#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
1069
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001070/* MC_CMD_PTP_IN_FPGAREAD msgrequest */
1071#define MC_CMD_PTP_IN_FPGAREAD_LEN 16
1072/* MC_CMD_PTP_IN_CMD_OFST 0 */
1073/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1074#define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8
1075#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12
1076
1077/* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
1078#define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
1079#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
1080#define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
1081/* MC_CMD_PTP_IN_CMD_OFST 0 */
1082/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1083#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8
1084#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12
1085#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
1086#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
1087#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
1088
1089/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
1090#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
1091/* MC_CMD_PTP_IN_CMD_OFST 0 */
1092/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1093/* Time adjustment in seconds */
1094#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
Ben Hutchings512bb062013-12-04 19:48:07 +00001095/* Time adjustment major value */
1096#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001097/* Time adjustment in nanoseconds */
1098#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
Ben Hutchings512bb062013-12-04 19:48:07 +00001099/* Time adjustment minor value */
1100#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001101
1102/* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
1103#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
1104/* MC_CMD_PTP_IN_CMD_OFST 0 */
1105/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1106/* Frequency adjustment 40 bit fixed point ns */
1107#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
1108#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
1109#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
1110#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
1111/* enum: Number of fractional bits in frequency adjustment */
1112/* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
1113
1114/* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
1115#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
1116/* MC_CMD_PTP_IN_CMD_OFST 0 */
1117/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1118/* Number of VLAN tags, 0 if not VLAN */
1119#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
1120/* Set of VLAN tags to filter against */
1121#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
1122#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
1123#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3
1124
1125/* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */
1126#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
1127/* MC_CMD_PTP_IN_CMD_OFST 0 */
1128/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1129/* 1 to enable UUID filtering, 0 to disable */
1130#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
1131/* UUID to filter against */
1132#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
1133#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
1134#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
1135#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
1136
1137/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
1138#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
1139/* MC_CMD_PTP_IN_CMD_OFST 0 */
1140/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1141/* 1 to enable Domain filtering, 0 to disable */
1142#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
1143/* Domain number to filter against */
1144#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
1145
1146/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */
1147#define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12
1148/* MC_CMD_PTP_IN_CMD_OFST 0 */
1149/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1150/* Set the clock source. */
1151#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8
1152/* enum: Internal. */
1153#define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
1154/* enum: External. */
1155#define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
1156
1157/* MC_CMD_PTP_IN_RST_CLK msgrequest */
1158#define MC_CMD_PTP_IN_RST_CLK_LEN 8
1159/* MC_CMD_PTP_IN_CMD_OFST 0 */
1160/* Reset value of Timer Reg. */
1161/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1162
1163/* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
1164#define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
1165/* MC_CMD_PTP_IN_CMD_OFST 0 */
1166/* Enable or disable */
1167#define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
1168/* enum: Enable */
1169#define MC_CMD_PTP_ENABLE_PPS 0x0
1170/* enum: Disable */
1171#define MC_CMD_PTP_DISABLE_PPS 0x1
Ben Hutchings512bb062013-12-04 19:48:07 +00001172/* Queue id to send events back */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001173#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
1174
Ben Hutchings512bb062013-12-04 19:48:07 +00001175/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */
1176#define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8
1177/* MC_CMD_PTP_IN_CMD_OFST 0 */
1178/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1179
1180/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */
1181#define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8
1182/* MC_CMD_PTP_IN_CMD_OFST 0 */
1183/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1184
1185/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */
1186#define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8
1187/* MC_CMD_PTP_IN_CMD_OFST 0 */
1188/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1189
1190/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */
1191#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12
1192/* MC_CMD_PTP_IN_CMD_OFST 0 */
1193/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1194/* Event queue to send PTP time events to */
1195#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8
1196
1197/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */
1198#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16
1199/* MC_CMD_PTP_IN_CMD_OFST 0 */
1200/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1201/* Unsubscribe options */
1202#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8
1203/* enum: Unsubscribe a single queue */
1204#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
1205/* enum: Unsubscribe all queues */
1206#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
1207/* Event queue ID */
1208#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
1209
1210/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
1211#define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
1212/* MC_CMD_PTP_IN_CMD_OFST 0 */
1213/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1214/* 1 to enable PPS test mode, 0 to disable and return result. */
1215#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8
1216
Ben Hutchings05a93202011-12-20 00:44:06 +00001217/* MC_CMD_PTP_OUT msgresponse */
1218#define MC_CMD_PTP_OUT_LEN 0
1219
1220/* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
1221#define MC_CMD_PTP_OUT_TRANSMIT_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001222/* Value of seconds timestamp */
Ben Hutchings05a93202011-12-20 00:44:06 +00001223#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
Ben Hutchings512bb062013-12-04 19:48:07 +00001224/* Timestamp major value */
1225#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001226/* Value of nanoseconds timestamp */
Ben Hutchings05a93202011-12-20 00:44:06 +00001227#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
Ben Hutchings512bb062013-12-04 19:48:07 +00001228/* Timestamp minor value */
1229#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
1230
1231/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */
1232#define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
1233
1234/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */
1235#define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
Ben Hutchings05a93202011-12-20 00:44:06 +00001236
1237/* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
1238#define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001239/* Value of seconds timestamp */
Ben Hutchings05a93202011-12-20 00:44:06 +00001240#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
Ben Hutchings512bb062013-12-04 19:48:07 +00001241/* Timestamp major value */
1242#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001243/* Value of nanoseconds timestamp */
Ben Hutchings05a93202011-12-20 00:44:06 +00001244#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
Ben Hutchings512bb062013-12-04 19:48:07 +00001245/* Timestamp minor value */
1246#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
Ben Hutchings05a93202011-12-20 00:44:06 +00001247
1248/* MC_CMD_PTP_OUT_STATUS msgresponse */
1249#define MC_CMD_PTP_OUT_STATUS_LEN 64
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001250/* Frequency of NIC's hardware clock */
Ben Hutchings05a93202011-12-20 00:44:06 +00001251#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001252/* Number of packets transmitted and timestamped */
Ben Hutchings05a93202011-12-20 00:44:06 +00001253#define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001254/* Number of packets received and timestamped */
Ben Hutchings05a93202011-12-20 00:44:06 +00001255#define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001256/* Number of packets timestamped by the FPGA */
Ben Hutchings05a93202011-12-20 00:44:06 +00001257#define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001258/* Number of packets filter matched */
Ben Hutchings05a93202011-12-20 00:44:06 +00001259#define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001260/* Number of packets not filter matched */
Ben Hutchings05a93202011-12-20 00:44:06 +00001261#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001262/* Number of PPS overflows (noise on input?) */
Ben Hutchings05a93202011-12-20 00:44:06 +00001263#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001264/* Number of PPS bad periods */
Ben Hutchings05a93202011-12-20 00:44:06 +00001265#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
Ben Hutchings512bb062013-12-04 19:48:07 +00001266/* Minimum period of PPS pulse in nanoseconds */
Ben Hutchings05a93202011-12-20 00:44:06 +00001267#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
Ben Hutchings512bb062013-12-04 19:48:07 +00001268/* Maximum period of PPS pulse in nanoseconds */
Ben Hutchings05a93202011-12-20 00:44:06 +00001269#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
Ben Hutchings512bb062013-12-04 19:48:07 +00001270/* Last period of PPS pulse in nanoseconds */
Ben Hutchings05a93202011-12-20 00:44:06 +00001271#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
Ben Hutchings512bb062013-12-04 19:48:07 +00001272/* Mean period of PPS pulse in nanoseconds */
Ben Hutchings05a93202011-12-20 00:44:06 +00001273#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
Ben Hutchings512bb062013-12-04 19:48:07 +00001274/* Minimum offset of PPS pulse in nanoseconds (signed) */
Ben Hutchings05a93202011-12-20 00:44:06 +00001275#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
Ben Hutchings512bb062013-12-04 19:48:07 +00001276/* Maximum offset of PPS pulse in nanoseconds (signed) */
Ben Hutchings05a93202011-12-20 00:44:06 +00001277#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
Ben Hutchings512bb062013-12-04 19:48:07 +00001278/* Last offset of PPS pulse in nanoseconds (signed) */
Ben Hutchings05a93202011-12-20 00:44:06 +00001279#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
Ben Hutchings512bb062013-12-04 19:48:07 +00001280/* Mean offset of PPS pulse in nanoseconds (signed) */
Ben Hutchings05a93202011-12-20 00:44:06 +00001281#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
1282
1283/* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
1284#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
1285#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
1286#define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001287/* A set of host and NIC times */
Ben Hutchings05a93202011-12-20 00:44:06 +00001288#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
1289#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
1290#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
1291#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001292/* Host time immediately before NIC's hardware clock read */
Ben Hutchings05a93202011-12-20 00:44:06 +00001293#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001294/* Value of seconds timestamp */
Ben Hutchings05a93202011-12-20 00:44:06 +00001295#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
Ben Hutchings512bb062013-12-04 19:48:07 +00001296/* Timestamp major value */
1297#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001298/* Value of nanoseconds timestamp */
Ben Hutchings05a93202011-12-20 00:44:06 +00001299#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
Ben Hutchings512bb062013-12-04 19:48:07 +00001300/* Timestamp minor value */
1301#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001302/* Host time immediately after NIC's hardware clock read */
Ben Hutchings05a93202011-12-20 00:44:06 +00001303#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001304/* Number of nanoseconds waited after reading NIC's hardware clock */
Ben Hutchings05a93202011-12-20 00:44:06 +00001305#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
1306
1307/* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
1308#define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001309/* Results of testing */
Ben Hutchings05a93202011-12-20 00:44:06 +00001310#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001311/* enum: Successful test */
1312#define MC_CMD_PTP_MANF_SUCCESS 0x0
1313/* enum: FPGA load failed */
1314#define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
1315/* enum: FPGA version invalid */
1316#define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
1317/* enum: FPGA registers incorrect */
1318#define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
1319/* enum: Oscillator possibly not working? */
1320#define MC_CMD_PTP_MANF_OSCILLATOR 0x4
1321/* enum: Timestamps not increasing */
1322#define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
1323/* enum: Mismatched packet count */
1324#define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
1325/* enum: Mismatched packet count (Siena filter and FPGA) */
1326#define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
1327/* enum: Not enough packets to perform timestamp check */
1328#define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
1329/* enum: Timestamp trigger GPIO not working */
1330#define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
Ben Hutchings512bb062013-12-04 19:48:07 +00001331/* enum: Insufficient PPS events to perform checks */
1332#define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
1333/* enum: PPS time event period not sufficiently close to 1s. */
1334#define MC_CMD_PTP_MANF_PPS_PERIOD 0xb
1335/* enum: PPS time event nS reading not sufficiently close to zero. */
1336#define MC_CMD_PTP_MANF_PPS_NS 0xc
1337/* enum: PTP peripheral registers incorrect */
1338#define MC_CMD_PTP_MANF_REGISTERS 0xd
1339/* enum: Failed to read time from PTP peripheral */
1340#define MC_CMD_PTP_MANF_CLOCK_READ 0xe
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001341/* Presence of external oscillator */
Ben Hutchings05a93202011-12-20 00:44:06 +00001342#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
1343
1344/* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
1345#define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001346/* Results of testing */
Ben Hutchings05a93202011-12-20 00:44:06 +00001347#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001348/* Number of packets received by FPGA */
Ben Hutchings05a93202011-12-20 00:44:06 +00001349#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001350/* Number of packets received by Siena filters */
Ben Hutchings05a93202011-12-20 00:44:06 +00001351#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
1352
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001353/* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
1354#define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
1355#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
1356#define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
1357#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
1358#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
1359#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
1360#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
1361
Ben Hutchings512bb062013-12-04 19:48:07 +00001362/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */
1363#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
1364/* Time format required/used by for this NIC. Applies to all PTP MCDI
1365 * operations that pass times between the host and firmware. If this operation
1366 * is not supported (older firmware) a format of seconds and nanoseconds should
1367 * be assumed.
1368 */
1369#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
1370/* enum: Times are in seconds and nanoseconds */
1371#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
1372/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
1373#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
1374/* enum: Major register has units of seconds, minor 2^-27s per tick */
1375#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
1376
1377/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */
1378#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 8
1379/* Time format required/used by for this NIC. Applies to all PTP MCDI
1380 * operations that pass times between the host and firmware. If this operation
1381 * is not supported (older firmware) a format of seconds and nanoseconds should
1382 * be assumed.
1383 */
1384#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
1385/* enum: Times are in seconds and nanoseconds */
1386#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
1387/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
1388#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
1389/* enum: Major register has units of seconds, minor 2^-27s per tick */
1390#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
1391/* Minimum acceptable value for a corrected synchronization timeset. When
1392 * comparing host and NIC clock times, the MC returns a set of samples that
1393 * contain the host start and end time, the MC time when the host start was
1394 * detected and the time the MC waited between reading the time and detecting
1395 * the host end. The corrected sync window is the difference between the host
1396 * end and start times minus the time that the MC waited for host end.
1397 */
1398#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
1399
1400/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */
1401#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16
1402/* Uncorrected error on transmit timestamps in NIC clock format */
1403#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
1404/* Uncorrected error on receive timestamps in NIC clock format */
1405#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
1406/* Uncorrected error on PPS output in NIC clock format */
1407#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8
1408/* Uncorrected error on PPS input in NIC clock format */
1409#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12
1410
1411/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */
1412#define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
1413/* Results of testing */
1414#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
1415/* Enum values, see field(s): */
1416/* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */
1417
Ben Hutchings05a93202011-12-20 00:44:06 +00001418
1419/***********************************/
1420/* MC_CMD_CSR_READ32
1421 * Read 32bit words from the indirect memory map.
1422 */
1423#define MC_CMD_CSR_READ32 0xc
1424
Shradha Shah75122ec2015-05-20 11:08:23 +01001425#define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1426
Ben Hutchings05a93202011-12-20 00:44:06 +00001427/* MC_CMD_CSR_READ32_IN msgrequest */
1428#define MC_CMD_CSR_READ32_IN_LEN 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001429/* Address */
Ben Hutchings05a93202011-12-20 00:44:06 +00001430#define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
1431#define MC_CMD_CSR_READ32_IN_STEP_OFST 4
1432#define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
1433
1434/* MC_CMD_CSR_READ32_OUT msgresponse */
1435#define MC_CMD_CSR_READ32_OUT_LENMIN 4
1436#define MC_CMD_CSR_READ32_OUT_LENMAX 252
1437#define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001438/* The last dword is the status, not a value read */
Ben Hutchings05a93202011-12-20 00:44:06 +00001439#define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
1440#define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
1441#define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
1442#define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
1443
1444
1445/***********************************/
1446/* MC_CMD_CSR_WRITE32
1447 * Write 32bit dwords to the indirect memory map.
1448 */
1449#define MC_CMD_CSR_WRITE32 0xd
1450
Shradha Shah75122ec2015-05-20 11:08:23 +01001451#define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1452
Ben Hutchings05a93202011-12-20 00:44:06 +00001453/* MC_CMD_CSR_WRITE32_IN msgrequest */
1454#define MC_CMD_CSR_WRITE32_IN_LENMIN 12
1455#define MC_CMD_CSR_WRITE32_IN_LENMAX 252
1456#define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001457/* Address */
Ben Hutchings05a93202011-12-20 00:44:06 +00001458#define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
1459#define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
1460#define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
1461#define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
1462#define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
1463#define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
1464
1465/* MC_CMD_CSR_WRITE32_OUT msgresponse */
1466#define MC_CMD_CSR_WRITE32_OUT_LEN 4
1467#define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
1468
1469
1470/***********************************/
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001471/* MC_CMD_HP
1472 * These commands are used for HP related features. They are grouped under one
1473 * MCDI command to avoid creating too many MCDI commands.
1474 */
1475#define MC_CMD_HP 0x54
1476
Shradha Shah75122ec2015-05-20 11:08:23 +01001477#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1478
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001479/* MC_CMD_HP_IN msgrequest */
1480#define MC_CMD_HP_IN_LEN 16
1481/* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
1482 * the specified address with the specified interval.When address is NULL,
1483 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
1484 * state / 2: (debug) Show temperature reported by one of the supported
1485 * sensors.
1486 */
1487#define MC_CMD_HP_IN_SUBCMD_OFST 0
1488/* enum: OCSD (Option Card Sensor Data) sub-command. */
1489#define MC_CMD_HP_IN_OCSD_SUBCMD 0x0
1490/* enum: Last known valid HP sub-command. */
1491#define MC_CMD_HP_IN_LAST_SUBCMD 0x0
1492/* The address to the array of sensor fields. (Or NULL to use a sub-command.)
1493 */
1494#define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
1495#define MC_CMD_HP_IN_OCSD_ADDR_LEN 8
1496#define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
1497#define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
1498/* The requested update interval, in seconds. (Or the sub-command if ADDR is
1499 * NULL.)
1500 */
1501#define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12
1502
1503/* MC_CMD_HP_OUT msgresponse */
1504#define MC_CMD_HP_OUT_LEN 4
1505#define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
1506/* enum: OCSD stopped for this card. */
1507#define MC_CMD_HP_OUT_OCSD_STOPPED 0x1
1508/* enum: OCSD was successfully started with the address provided. */
1509#define MC_CMD_HP_OUT_OCSD_STARTED 0x2
1510/* enum: OCSD was already started for this card. */
1511#define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
1512
1513
1514/***********************************/
Ben Hutchings05a93202011-12-20 00:44:06 +00001515/* MC_CMD_STACKINFO
1516 * Get stack information.
1517 */
1518#define MC_CMD_STACKINFO 0xf
1519
Shradha Shah75122ec2015-05-20 11:08:23 +01001520#define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1521
Ben Hutchings05a93202011-12-20 00:44:06 +00001522/* MC_CMD_STACKINFO_IN msgrequest */
1523#define MC_CMD_STACKINFO_IN_LEN 0
1524
1525/* MC_CMD_STACKINFO_OUT msgresponse */
1526#define MC_CMD_STACKINFO_OUT_LENMIN 12
1527#define MC_CMD_STACKINFO_OUT_LENMAX 252
1528#define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001529/* (thread ptr, stack size, free space) for each thread in system */
Ben Hutchings05a93202011-12-20 00:44:06 +00001530#define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
1531#define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
1532#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
1533#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
1534
1535
1536/***********************************/
1537/* MC_CMD_MDIO_READ
1538 * MDIO register read.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001539 */
1540#define MC_CMD_MDIO_READ 0x10
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001541
Shradha Shah75122ec2015-05-20 11:08:23 +01001542#define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1543
Ben Hutchings05a93202011-12-20 00:44:06 +00001544/* MC_CMD_MDIO_READ_IN msgrequest */
1545#define MC_CMD_MDIO_READ_IN_LEN 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001546/* Bus number; there are two MDIO buses: one for the internal PHY, and one for
1547 * external devices.
1548 */
Ben Hutchings05a93202011-12-20 00:44:06 +00001549#define MC_CMD_MDIO_READ_IN_BUS_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001550/* enum: Internal. */
1551#define MC_CMD_MDIO_BUS_INTERNAL 0x0
1552/* enum: External. */
1553#define MC_CMD_MDIO_BUS_EXTERNAL 0x1
1554/* Port address */
Ben Hutchings05a93202011-12-20 00:44:06 +00001555#define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001556/* Device Address or clause 22. */
Ben Hutchings05a93202011-12-20 00:44:06 +00001557#define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001558/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
1559 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
1560 */
1561#define MC_CMD_MDIO_CLAUSE22 0x20
1562/* Address */
Ben Hutchings05a93202011-12-20 00:44:06 +00001563#define MC_CMD_MDIO_READ_IN_ADDR_OFST 12
1564
1565/* MC_CMD_MDIO_READ_OUT msgresponse */
1566#define MC_CMD_MDIO_READ_OUT_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001567/* Value */
Ben Hutchings05a93202011-12-20 00:44:06 +00001568#define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001569/* Status the MDIO commands return the raw status bits from the MDIO block. A
1570 * "good" transaction should have the DONE bit set and all other bits clear.
1571 */
Ben Hutchings05a93202011-12-20 00:44:06 +00001572#define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001573/* enum: Good. */
1574#define MC_CMD_MDIO_STATUS_GOOD 0x8
Ben Hutchings05a93202011-12-20 00:44:06 +00001575
1576
1577/***********************************/
1578/* MC_CMD_MDIO_WRITE
1579 * MDIO register write.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001580 */
1581#define MC_CMD_MDIO_WRITE 0x11
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001582
Shradha Shah75122ec2015-05-20 11:08:23 +01001583#define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1584
Ben Hutchings05a93202011-12-20 00:44:06 +00001585/* MC_CMD_MDIO_WRITE_IN msgrequest */
1586#define MC_CMD_MDIO_WRITE_IN_LEN 20
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001587/* Bus number; there are two MDIO buses: one for the internal PHY, and one for
1588 * external devices.
1589 */
Ben Hutchings05a93202011-12-20 00:44:06 +00001590#define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001591/* enum: Internal. */
Ben Hutchings05a93202011-12-20 00:44:06 +00001592/* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001593/* enum: External. */
Ben Hutchings05a93202011-12-20 00:44:06 +00001594/* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001595/* Port address */
Ben Hutchings05a93202011-12-20 00:44:06 +00001596#define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001597/* Device Address or clause 22. */
Ben Hutchings05a93202011-12-20 00:44:06 +00001598#define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001599/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
1600 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
1601 */
Ben Hutchings05a93202011-12-20 00:44:06 +00001602/* MC_CMD_MDIO_CLAUSE22 0x20 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001603/* Address */
Ben Hutchings05a93202011-12-20 00:44:06 +00001604#define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001605/* Value */
Ben Hutchings05a93202011-12-20 00:44:06 +00001606#define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001607
Ben Hutchings05a93202011-12-20 00:44:06 +00001608/* MC_CMD_MDIO_WRITE_OUT msgresponse */
1609#define MC_CMD_MDIO_WRITE_OUT_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001610/* Status; the MDIO commands return the raw status bits from the MDIO block. A
1611 * "good" transaction should have the DONE bit set and all other bits clear.
1612 */
Ben Hutchings05a93202011-12-20 00:44:06 +00001613#define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001614/* enum: Good. */
Ben Hutchings05a93202011-12-20 00:44:06 +00001615/* MC_CMD_MDIO_STATUS_GOOD 0x8 */
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001616
1617
Ben Hutchings05a93202011-12-20 00:44:06 +00001618/***********************************/
1619/* MC_CMD_DBI_WRITE
1620 * Write DBI register(s).
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001621 */
1622#define MC_CMD_DBI_WRITE 0x12
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001623
Shradha Shah75122ec2015-05-20 11:08:23 +01001624#define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1625
Ben Hutchings05a93202011-12-20 00:44:06 +00001626/* MC_CMD_DBI_WRITE_IN msgrequest */
1627#define MC_CMD_DBI_WRITE_IN_LENMIN 12
1628#define MC_CMD_DBI_WRITE_IN_LENMAX 252
1629#define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001630/* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
1631 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.
1632 */
Ben Hutchings05a93202011-12-20 00:44:06 +00001633#define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
1634#define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
1635#define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
1636#define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001637
Ben Hutchings05a93202011-12-20 00:44:06 +00001638/* MC_CMD_DBI_WRITE_OUT msgresponse */
1639#define MC_CMD_DBI_WRITE_OUT_LEN 0
1640
1641/* MC_CMD_DBIWROP_TYPEDEF structuredef */
1642#define MC_CMD_DBIWROP_TYPEDEF_LEN 12
1643#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
1644#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
1645#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001646#define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
1647#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16
1648#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16
1649#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15
1650#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
1651#define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14
1652#define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
1653#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32
1654#define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32
Ben Hutchings05a93202011-12-20 00:44:06 +00001655#define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
1656#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
1657#define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32
1658
1659
1660/***********************************/
1661/* MC_CMD_PORT_READ32
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001662 * Read a 32-bit register from the indirect port register map. The port to
1663 * access is implied by the Shared memory channel used.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001664 */
1665#define MC_CMD_PORT_READ32 0x14
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001666
Ben Hutchings05a93202011-12-20 00:44:06 +00001667/* MC_CMD_PORT_READ32_IN msgrequest */
1668#define MC_CMD_PORT_READ32_IN_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001669/* Address */
Ben Hutchings05a93202011-12-20 00:44:06 +00001670#define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
1671
1672/* MC_CMD_PORT_READ32_OUT msgresponse */
1673#define MC_CMD_PORT_READ32_OUT_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001674/* Value */
Ben Hutchings05a93202011-12-20 00:44:06 +00001675#define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001676/* Status */
Ben Hutchings05a93202011-12-20 00:44:06 +00001677#define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
1678
1679
1680/***********************************/
1681/* MC_CMD_PORT_WRITE32
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001682 * Write a 32-bit register to the indirect port register map. The port to
1683 * access is implied by the Shared memory channel used.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001684 */
1685#define MC_CMD_PORT_WRITE32 0x15
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001686
Ben Hutchings05a93202011-12-20 00:44:06 +00001687/* MC_CMD_PORT_WRITE32_IN msgrequest */
1688#define MC_CMD_PORT_WRITE32_IN_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001689/* Address */
Ben Hutchings05a93202011-12-20 00:44:06 +00001690#define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001691/* Value */
Ben Hutchings05a93202011-12-20 00:44:06 +00001692#define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
1693
1694/* MC_CMD_PORT_WRITE32_OUT msgresponse */
1695#define MC_CMD_PORT_WRITE32_OUT_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001696/* Status */
Ben Hutchings05a93202011-12-20 00:44:06 +00001697#define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
1698
1699
1700/***********************************/
1701/* MC_CMD_PORT_READ128
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001702 * Read a 128-bit register from the indirect port register map. The port to
1703 * access is implied by the Shared memory channel used.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001704 */
1705#define MC_CMD_PORT_READ128 0x16
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001706
Ben Hutchings05a93202011-12-20 00:44:06 +00001707/* MC_CMD_PORT_READ128_IN msgrequest */
1708#define MC_CMD_PORT_READ128_IN_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001709/* Address */
Ben Hutchings05a93202011-12-20 00:44:06 +00001710#define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
1711
1712/* MC_CMD_PORT_READ128_OUT msgresponse */
1713#define MC_CMD_PORT_READ128_OUT_LEN 20
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001714/* Value */
Ben Hutchings05a93202011-12-20 00:44:06 +00001715#define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
1716#define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001717/* Status */
Ben Hutchings05a93202011-12-20 00:44:06 +00001718#define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
1719
1720
1721/***********************************/
1722/* MC_CMD_PORT_WRITE128
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001723 * Write a 128-bit register to the indirect port register map. The port to
1724 * access is implied by the Shared memory channel used.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001725 */
1726#define MC_CMD_PORT_WRITE128 0x17
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001727
Ben Hutchings05a93202011-12-20 00:44:06 +00001728/* MC_CMD_PORT_WRITE128_IN msgrequest */
1729#define MC_CMD_PORT_WRITE128_IN_LEN 20
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001730/* Address */
Ben Hutchings05a93202011-12-20 00:44:06 +00001731#define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001732/* Value */
Ben Hutchings05a93202011-12-20 00:44:06 +00001733#define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
1734#define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16
1735
1736/* MC_CMD_PORT_WRITE128_OUT msgresponse */
1737#define MC_CMD_PORT_WRITE128_OUT_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001738/* Status */
Ben Hutchings05a93202011-12-20 00:44:06 +00001739#define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
1740
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001741/* MC_CMD_CAPABILITIES structuredef */
1742#define MC_CMD_CAPABILITIES_LEN 4
1743/* Small buf table. */
1744#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
1745#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1
1746/* Turbo mode (for Maranello). */
1747#define MC_CMD_CAPABILITIES_TURBO_LBN 1
1748#define MC_CMD_CAPABILITIES_TURBO_WIDTH 1
1749/* Turbo mode active (for Maranello). */
1750#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2
1751#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1
1752/* PTP offload. */
1753#define MC_CMD_CAPABILITIES_PTP_LBN 3
1754#define MC_CMD_CAPABILITIES_PTP_WIDTH 1
1755/* AOE mode. */
1756#define MC_CMD_CAPABILITIES_AOE_LBN 4
1757#define MC_CMD_CAPABILITIES_AOE_WIDTH 1
1758/* AOE mode active. */
1759#define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5
1760#define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1
1761/* AOE mode active. */
1762#define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6
1763#define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1
1764#define MC_CMD_CAPABILITIES_RESERVED_LBN 7
1765#define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25
1766
Ben Hutchings05a93202011-12-20 00:44:06 +00001767
1768/***********************************/
1769/* MC_CMD_GET_BOARD_CFG
1770 * Returns the MC firmware configuration structure.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001771 */
1772#define MC_CMD_GET_BOARD_CFG 0x18
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001773
Shradha Shah75122ec2015-05-20 11:08:23 +01001774#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1775
Ben Hutchings05a93202011-12-20 00:44:06 +00001776/* MC_CMD_GET_BOARD_CFG_IN msgrequest */
1777#define MC_CMD_GET_BOARD_CFG_IN_LEN 0
1778
1779/* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
1780#define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
1781#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
1782#define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
1783#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
1784#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
1785#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001786/* See MC_CMD_CAPABILITIES */
Ben Hutchings05a93202011-12-20 00:44:06 +00001787#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001788/* See MC_CMD_CAPABILITIES */
Ben Hutchings05a93202011-12-20 00:44:06 +00001789#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
Ben Hutchings05a93202011-12-20 00:44:06 +00001790#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
1791#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
1792#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
1793#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
1794#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
1795#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
1796#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
1797#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001798/* This field contains a 16-bit value for each of the types of NVRAM area. The
1799 * values are defined in the firmware/mc/platform/.c file for a specific board
1800 * type, but otherwise have no meaning to the MC; they are used by the driver
1801 * to manage selection of appropriate firmware updates.
1802 */
Ben Hutchings05a93202011-12-20 00:44:06 +00001803#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
1804#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
1805#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
1806#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
1807
1808
1809/***********************************/
1810/* MC_CMD_DBI_READX
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001811 * Read DBI register(s) -- extended functionality
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001812 */
1813#define MC_CMD_DBI_READX 0x19
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001814
Shradha Shah75122ec2015-05-20 11:08:23 +01001815#define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1816
Ben Hutchings05a93202011-12-20 00:44:06 +00001817/* MC_CMD_DBI_READX_IN msgrequest */
1818#define MC_CMD_DBI_READX_IN_LENMIN 8
1819#define MC_CMD_DBI_READX_IN_LENMAX 248
1820#define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001821/* Each Read op consists of an address (offset 0), VF/CS2) */
Ben Hutchings05a93202011-12-20 00:44:06 +00001822#define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
1823#define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
1824#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
1825#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
1826#define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
1827#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
1828
1829/* MC_CMD_DBI_READX_OUT msgresponse */
1830#define MC_CMD_DBI_READX_OUT_LENMIN 4
1831#define MC_CMD_DBI_READX_OUT_LENMAX 252
1832#define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001833/* Value */
Ben Hutchings05a93202011-12-20 00:44:06 +00001834#define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
1835#define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
1836#define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
1837#define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
1838
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001839/* MC_CMD_DBIRDOP_TYPEDEF structuredef */
1840#define MC_CMD_DBIRDOP_TYPEDEF_LEN 8
1841#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
1842#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
1843#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32
1844#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
1845#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16
1846#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16
1847#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15
1848#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
1849#define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14
1850#define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
1851#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32
1852#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32
1853
Ben Hutchings05a93202011-12-20 00:44:06 +00001854
1855/***********************************/
1856/* MC_CMD_SET_RAND_SEED
1857 * Set the 16byte seed for the MC pseudo-random generator.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001858 */
1859#define MC_CMD_SET_RAND_SEED 0x1a
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001860
Shradha Shah75122ec2015-05-20 11:08:23 +01001861#define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1862
Ben Hutchings05a93202011-12-20 00:44:06 +00001863/* MC_CMD_SET_RAND_SEED_IN msgrequest */
1864#define MC_CMD_SET_RAND_SEED_IN_LEN 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001865/* Seed value. */
Ben Hutchings05a93202011-12-20 00:44:06 +00001866#define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
1867#define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16
1868
1869/* MC_CMD_SET_RAND_SEED_OUT msgresponse */
1870#define MC_CMD_SET_RAND_SEED_OUT_LEN 0
1871
1872
1873/***********************************/
1874/* MC_CMD_LTSSM_HIST
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001875 * Retrieve the history of the LTSSM, if the build supports it.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001876 */
1877#define MC_CMD_LTSSM_HIST 0x1b
1878
Ben Hutchings05a93202011-12-20 00:44:06 +00001879/* MC_CMD_LTSSM_HIST_IN msgrequest */
1880#define MC_CMD_LTSSM_HIST_IN_LEN 0
1881
1882/* MC_CMD_LTSSM_HIST_OUT msgresponse */
1883#define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
1884#define MC_CMD_LTSSM_HIST_OUT_LENMAX 252
1885#define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001886/* variable number of LTSSM values, as bytes. The history is read-to-clear. */
Ben Hutchings05a93202011-12-20 00:44:06 +00001887#define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
1888#define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
1889#define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
1890#define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
1891
1892
1893/***********************************/
1894/* MC_CMD_DRV_ATTACH
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001895 * Inform MCPU that this port is managed on the host (i.e. driver active). For
1896 * Huntington, also request the preferred datapath firmware to use if possible
1897 * (it may not be possible for this request to be fulfilled; the driver must
1898 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which
1899 * features are actually available). The FIRMWARE_ID field is ignored by older
1900 * platforms.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001901 */
1902#define MC_CMD_DRV_ATTACH 0x1c
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001903
Shradha Shah75122ec2015-05-20 11:08:23 +01001904#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1905
Ben Hutchings05a93202011-12-20 00:44:06 +00001906/* MC_CMD_DRV_ATTACH_IN msgrequest */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001907#define MC_CMD_DRV_ATTACH_IN_LEN 12
1908/* new state (0=detached, 1=attached) to set if UPDATE=1 */
Ben Hutchings05a93202011-12-20 00:44:06 +00001909#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001910/* 1 to set new state, or 0 to just report the existing state */
Ben Hutchings05a93202011-12-20 00:44:06 +00001911#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001912/* preferred datapath firmware (for Huntington; ignored for Siena) */
1913#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8
1914/* enum: Prefer to use full featured firmware */
1915#define MC_CMD_FW_FULL_FEATURED 0x0
1916/* enum: Prefer to use firmware with fewer features but lower latency */
1917#define MC_CMD_FW_LOW_LATENCY 0x1
Edward Cree267d9d72015-05-06 00:59:18 +01001918/* enum: Only this option is allowed for non-admin functions */
1919#define MC_CMD_FW_DONT_CARE 0xffffffff
Ben Hutchings05a93202011-12-20 00:44:06 +00001920
1921/* MC_CMD_DRV_ATTACH_OUT msgresponse */
1922#define MC_CMD_DRV_ATTACH_OUT_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001923/* previous or existing state (0=detached, 1=attached) */
Ben Hutchings05a93202011-12-20 00:44:06 +00001924#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
1925
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001926/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */
1927#define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8
1928/* previous or existing state (0=detached, 1=attached) */
1929#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
1930/* Flags associated with this function */
1931#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
1932/* enum: Labels the lowest-numbered function visible to the OS */
1933#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
1934/* enum: The function can control the link state of the physical port it is
1935 * bound to.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001936 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001937#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
1938/* enum: The function can perform privileged operations */
1939#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001940
Ben Hutchings05a93202011-12-20 00:44:06 +00001941
1942/***********************************/
1943/* MC_CMD_SHMUART
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001944 * Route UART output to circular buffer in shared memory instead.
1945 */
1946#define MC_CMD_SHMUART 0x1f
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001947
Ben Hutchings05a93202011-12-20 00:44:06 +00001948/* MC_CMD_SHMUART_IN msgrequest */
1949#define MC_CMD_SHMUART_IN_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001950/* ??? */
Ben Hutchings05a93202011-12-20 00:44:06 +00001951#define MC_CMD_SHMUART_IN_FLAG_OFST 0
1952
1953/* MC_CMD_SHMUART_OUT msgresponse */
1954#define MC_CMD_SHMUART_OUT_LEN 0
1955
1956
1957/***********************************/
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001958/* MC_CMD_PORT_RESET
1959 * Generic per-port reset. There is no equivalent for per-board reset. Locks
1960 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
1961 * use MC_CMD_ENTITY_RESET instead.
1962 */
1963#define MC_CMD_PORT_RESET 0x20
1964
Shradha Shah75122ec2015-05-20 11:08:23 +01001965#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1966
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001967/* MC_CMD_PORT_RESET_IN msgrequest */
1968#define MC_CMD_PORT_RESET_IN_LEN 0
1969
1970/* MC_CMD_PORT_RESET_OUT msgresponse */
1971#define MC_CMD_PORT_RESET_OUT_LEN 0
1972
1973
1974/***********************************/
Ben Hutchings05a93202011-12-20 00:44:06 +00001975/* MC_CMD_ENTITY_RESET
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001976 * Generic per-resource reset. There is no equivalent for per-board reset.
1977 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
1978 * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001979 */
Ben Hutchings05a93202011-12-20 00:44:06 +00001980#define MC_CMD_ENTITY_RESET 0x20
Shradha Shah75122ec2015-05-20 11:08:23 +01001981/* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001982
Ben Hutchings05a93202011-12-20 00:44:06 +00001983/* MC_CMD_ENTITY_RESET_IN msgrequest */
1984#define MC_CMD_ENTITY_RESET_IN_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01001985/* Optional flags field. Omitting this will perform a "legacy" reset action
1986 * (TBD).
1987 */
Ben Hutchings05a93202011-12-20 00:44:06 +00001988#define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
1989#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
1990#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
1991
1992/* MC_CMD_ENTITY_RESET_OUT msgresponse */
1993#define MC_CMD_ENTITY_RESET_OUT_LEN 0
1994
1995
1996/***********************************/
1997/* MC_CMD_PCIE_CREDITS
1998 * Read instantaneous and minimum flow control thresholds.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00001999 */
Ben Hutchings05a93202011-12-20 00:44:06 +00002000#define MC_CMD_PCIE_CREDITS 0x21
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002001
Ben Hutchings05a93202011-12-20 00:44:06 +00002002/* MC_CMD_PCIE_CREDITS_IN msgrequest */
2003#define MC_CMD_PCIE_CREDITS_IN_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002004/* poll period. 0 is disabled */
Ben Hutchings05a93202011-12-20 00:44:06 +00002005#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002006/* wipe statistics */
Ben Hutchings05a93202011-12-20 00:44:06 +00002007#define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
2008
2009/* MC_CMD_PCIE_CREDITS_OUT msgresponse */
2010#define MC_CMD_PCIE_CREDITS_OUT_LEN 16
2011#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
2012#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
2013#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
2014#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
2015#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
2016#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
2017#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
2018#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
2019#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
2020#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
2021#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
2022#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
2023#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
2024#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
2025#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
2026#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2
2027
2028
2029/***********************************/
2030/* MC_CMD_RXD_MONITOR
2031 * Get histogram of RX queue fill level.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002032 */
Ben Hutchings05a93202011-12-20 00:44:06 +00002033#define MC_CMD_RXD_MONITOR 0x22
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002034
Ben Hutchings05a93202011-12-20 00:44:06 +00002035/* MC_CMD_RXD_MONITOR_IN msgrequest */
2036#define MC_CMD_RXD_MONITOR_IN_LEN 12
2037#define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
2038#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
2039#define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
2040
2041/* MC_CMD_RXD_MONITOR_OUT msgresponse */
2042#define MC_CMD_RXD_MONITOR_OUT_LEN 80
2043#define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
2044#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
2045#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
2046#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
2047#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
2048#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
2049#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
2050#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
2051#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
2052#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
2053#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
2054#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
2055#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
2056#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
2057#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
2058#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
2059#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
2060#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
2061#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
2062#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
2063
2064
2065/***********************************/
2066/* MC_CMD_PUTS
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002067 * Copy the given ASCII string out onto UART and/or out of the network port.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002068 */
Ben Hutchings05a93202011-12-20 00:44:06 +00002069#define MC_CMD_PUTS 0x23
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002070
Shradha Shah75122ec2015-05-20 11:08:23 +01002071#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2072
Ben Hutchings05a93202011-12-20 00:44:06 +00002073/* MC_CMD_PUTS_IN msgrequest */
2074#define MC_CMD_PUTS_IN_LENMIN 13
Ben Hutchings576eda82012-09-19 02:46:37 +01002075#define MC_CMD_PUTS_IN_LENMAX 252
Ben Hutchings05a93202011-12-20 00:44:06 +00002076#define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
2077#define MC_CMD_PUTS_IN_DEST_OFST 0
2078#define MC_CMD_PUTS_IN_UART_LBN 0
2079#define MC_CMD_PUTS_IN_UART_WIDTH 1
2080#define MC_CMD_PUTS_IN_PORT_LBN 1
2081#define MC_CMD_PUTS_IN_PORT_WIDTH 1
2082#define MC_CMD_PUTS_IN_DHOST_OFST 4
2083#define MC_CMD_PUTS_IN_DHOST_LEN 6
2084#define MC_CMD_PUTS_IN_STRING_OFST 12
2085#define MC_CMD_PUTS_IN_STRING_LEN 1
2086#define MC_CMD_PUTS_IN_STRING_MINNUM 1
Ben Hutchings576eda82012-09-19 02:46:37 +01002087#define MC_CMD_PUTS_IN_STRING_MAXNUM 240
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002088
Ben Hutchings05a93202011-12-20 00:44:06 +00002089/* MC_CMD_PUTS_OUT msgresponse */
2090#define MC_CMD_PUTS_OUT_LEN 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002091
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002092
Ben Hutchings05a93202011-12-20 00:44:06 +00002093/***********************************/
2094/* MC_CMD_GET_PHY_CFG
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002095 * Report PHY configuration. This guarantees to succeed even if the PHY is in a
2096 * 'zombie' state. Locks required: None
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002097 */
2098#define MC_CMD_GET_PHY_CFG 0x24
2099
Shradha Shah75122ec2015-05-20 11:08:23 +01002100#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2101
Ben Hutchings05a93202011-12-20 00:44:06 +00002102/* MC_CMD_GET_PHY_CFG_IN msgrequest */
2103#define MC_CMD_GET_PHY_CFG_IN_LEN 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002104
Ben Hutchings05a93202011-12-20 00:44:06 +00002105/* MC_CMD_GET_PHY_CFG_OUT msgresponse */
2106#define MC_CMD_GET_PHY_CFG_OUT_LEN 72
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002107/* flags */
Ben Hutchings05a93202011-12-20 00:44:06 +00002108#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
2109#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
2110#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
2111#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
2112#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
2113#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
2114#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
2115#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
2116#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
2117#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
2118#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
2119#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
2120#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
2121#define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
2122#define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002123/* ?? */
Ben Hutchings05a93202011-12-20 00:44:06 +00002124#define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002125/* Bitmask of supported capabilities */
Ben Hutchings05a93202011-12-20 00:44:06 +00002126#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
2127#define MC_CMD_PHY_CAP_10HDX_LBN 1
2128#define MC_CMD_PHY_CAP_10HDX_WIDTH 1
2129#define MC_CMD_PHY_CAP_10FDX_LBN 2
2130#define MC_CMD_PHY_CAP_10FDX_WIDTH 1
2131#define MC_CMD_PHY_CAP_100HDX_LBN 3
2132#define MC_CMD_PHY_CAP_100HDX_WIDTH 1
2133#define MC_CMD_PHY_CAP_100FDX_LBN 4
2134#define MC_CMD_PHY_CAP_100FDX_WIDTH 1
2135#define MC_CMD_PHY_CAP_1000HDX_LBN 5
2136#define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
2137#define MC_CMD_PHY_CAP_1000FDX_LBN 6
2138#define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
2139#define MC_CMD_PHY_CAP_10000FDX_LBN 7
2140#define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
2141#define MC_CMD_PHY_CAP_PAUSE_LBN 8
2142#define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
2143#define MC_CMD_PHY_CAP_ASYM_LBN 9
2144#define MC_CMD_PHY_CAP_ASYM_WIDTH 1
2145#define MC_CMD_PHY_CAP_AN_LBN 10
2146#define MC_CMD_PHY_CAP_AN_WIDTH 1
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002147#define MC_CMD_PHY_CAP_40000FDX_LBN 11
2148#define MC_CMD_PHY_CAP_40000FDX_WIDTH 1
2149#define MC_CMD_PHY_CAP_DDM_LBN 12
2150#define MC_CMD_PHY_CAP_DDM_WIDTH 1
2151/* ?? */
Ben Hutchings05a93202011-12-20 00:44:06 +00002152#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002153/* ?? */
Ben Hutchings05a93202011-12-20 00:44:06 +00002154#define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002155/* ?? */
Ben Hutchings05a93202011-12-20 00:44:06 +00002156#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002157/* ?? */
Ben Hutchings05a93202011-12-20 00:44:06 +00002158#define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
2159#define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002160/* ?? */
Ben Hutchings05a93202011-12-20 00:44:06 +00002161#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002162/* enum: Xaui. */
2163#define MC_CMD_MEDIA_XAUI 0x1
2164/* enum: CX4. */
2165#define MC_CMD_MEDIA_CX4 0x2
2166/* enum: KX4. */
2167#define MC_CMD_MEDIA_KX4 0x3
2168/* enum: XFP Far. */
2169#define MC_CMD_MEDIA_XFP 0x4
2170/* enum: SFP+. */
2171#define MC_CMD_MEDIA_SFP_PLUS 0x5
2172/* enum: 10GBaseT. */
2173#define MC_CMD_MEDIA_BASE_T 0x6
Ben Hutchings512bb062013-12-04 19:48:07 +00002174/* enum: QSFP+. */
2175#define MC_CMD_MEDIA_QSFP_PLUS 0x7
Ben Hutchings05a93202011-12-20 00:44:06 +00002176#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002177/* enum: Native clause 22 */
2178#define MC_CMD_MMD_CLAUSE22 0x0
Ben Hutchings05a93202011-12-20 00:44:06 +00002179#define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
2180#define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
2181#define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
2182#define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
2183#define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
2184#define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
2185#define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002186/* enum: Clause22 proxied over clause45 by PHY. */
2187#define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
Ben Hutchings05a93202011-12-20 00:44:06 +00002188#define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
2189#define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
2190#define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
2191#define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002192
Ben Hutchings05a93202011-12-20 00:44:06 +00002193
2194/***********************************/
2195/* MC_CMD_START_BIST
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002196 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST
2197 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002198 */
2199#define MC_CMD_START_BIST 0x25
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002200
Shradha Shah75122ec2015-05-20 11:08:23 +01002201#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2202
Ben Hutchings05a93202011-12-20 00:44:06 +00002203/* MC_CMD_START_BIST_IN msgrequest */
2204#define MC_CMD_START_BIST_IN_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002205/* Type of test. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002206#define MC_CMD_START_BIST_IN_TYPE_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002207/* enum: Run the PHY's short cable BIST. */
2208#define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
2209/* enum: Run the PHY's long cable BIST. */
2210#define MC_CMD_PHY_BIST_CABLE_LONG 0x2
2211/* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */
2212#define MC_CMD_BPX_SERDES_BIST 0x3
2213/* enum: Run the MC loopback tests. */
2214#define MC_CMD_MC_LOOPBACK_BIST 0x4
2215/* enum: Run the PHY's standard BIST. */
2216#define MC_CMD_PHY_BIST 0x5
2217/* enum: Run MC RAM test. */
2218#define MC_CMD_MC_MEM_BIST 0x6
2219/* enum: Run Port RAM test. */
2220#define MC_CMD_PORT_MEM_BIST 0x7
2221/* enum: Run register test. */
2222#define MC_CMD_REG_BIST 0x8
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002223
Ben Hutchings05a93202011-12-20 00:44:06 +00002224/* MC_CMD_START_BIST_OUT msgresponse */
2225#define MC_CMD_START_BIST_OUT_LEN 0
2226
2227
2228/***********************************/
2229/* MC_CMD_POLL_BIST
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002230 * Poll for BIST completion. Returns a single status code, and optionally some
2231 * PHY specific bist output. The driver should only consume the BIST output
2232 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't
2233 * successfully parse the BIST output, it should still respect the pass/Fail in
2234 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
2235 * EACCES (if PHY_LOCK is not held).
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002236 */
2237#define MC_CMD_POLL_BIST 0x26
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002238
Shradha Shah75122ec2015-05-20 11:08:23 +01002239#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2240
Ben Hutchings05a93202011-12-20 00:44:06 +00002241/* MC_CMD_POLL_BIST_IN msgrequest */
2242#define MC_CMD_POLL_BIST_IN_LEN 0
2243
2244/* MC_CMD_POLL_BIST_OUT msgresponse */
2245#define MC_CMD_POLL_BIST_OUT_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002246/* result */
Ben Hutchings05a93202011-12-20 00:44:06 +00002247#define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002248/* enum: Running. */
2249#define MC_CMD_POLL_BIST_RUNNING 0x1
2250/* enum: Passed. */
2251#define MC_CMD_POLL_BIST_PASSED 0x2
2252/* enum: Failed. */
2253#define MC_CMD_POLL_BIST_FAILED 0x3
2254/* enum: Timed-out. */
2255#define MC_CMD_POLL_BIST_TIMEOUT 0x4
Ben Hutchings05a93202011-12-20 00:44:06 +00002256#define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
2257
2258/* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
2259#define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002260/* result */
Ben Hutchings05a93202011-12-20 00:44:06 +00002261/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
2262/* Enum values, see field(s): */
2263/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
2264#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
2265#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
2266#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
2267#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002268/* Status of each channel A */
Ben Hutchings05a93202011-12-20 00:44:06 +00002269#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002270/* enum: Ok. */
2271#define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
2272/* enum: Open. */
2273#define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
2274/* enum: Intra-pair short. */
2275#define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
2276/* enum: Inter-pair short. */
2277#define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
2278/* enum: Busy. */
2279#define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
2280/* Status of each channel B */
Ben Hutchings05a93202011-12-20 00:44:06 +00002281#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
2282/* Enum values, see field(s): */
2283/* CABLE_STATUS_A */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002284/* Status of each channel C */
Ben Hutchings05a93202011-12-20 00:44:06 +00002285#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
2286/* Enum values, see field(s): */
2287/* CABLE_STATUS_A */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002288/* Status of each channel D */
Ben Hutchings05a93202011-12-20 00:44:06 +00002289#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
2290/* Enum values, see field(s): */
2291/* CABLE_STATUS_A */
2292
2293/* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
2294#define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002295/* result */
Ben Hutchings05a93202011-12-20 00:44:06 +00002296/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
2297/* Enum values, see field(s): */
2298/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
2299#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002300/* enum: Complete. */
2301#define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
2302/* enum: Bus switch off I2C write. */
2303#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
2304/* enum: Bus switch off I2C no access IO exp. */
2305#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
2306/* enum: Bus switch off I2C no access module. */
2307#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
2308/* enum: IO exp I2C configure. */
2309#define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
2310/* enum: Bus switch I2C no cross talk. */
2311#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
2312/* enum: Module presence. */
2313#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
2314/* enum: Module ID I2C access. */
2315#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
2316/* enum: Module ID sane value. */
2317#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
2318
2319/* MC_CMD_POLL_BIST_OUT_MEM msgresponse */
2320#define MC_CMD_POLL_BIST_OUT_MEM_LEN 36
2321/* result */
2322/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
2323/* Enum values, see field(s): */
2324/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
2325#define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
2326/* enum: Test has completed. */
2327#define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
2328/* enum: RAM test - walk ones. */
2329#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
2330/* enum: RAM test - walk zeros. */
2331#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
2332/* enum: RAM test - walking inversions zeros/ones. */
2333#define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
2334/* enum: RAM test - walking inversions checkerboard. */
2335#define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
2336/* enum: Register test - set / clear individual bits. */
2337#define MC_CMD_POLL_BIST_MEM_REG 0x5
2338/* enum: ECC error detected. */
2339#define MC_CMD_POLL_BIST_MEM_ECC 0x6
2340/* Failure address, only valid if result is POLL_BIST_FAILED */
2341#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8
2342/* Bus or address space to which the failure address corresponds */
2343#define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12
2344/* enum: MC MIPS bus. */
2345#define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
2346/* enum: CSR IREG bus. */
2347#define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
2348/* enum: RX DPCPU bus. */
2349#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
2350/* enum: TX0 DPCPU bus. */
2351#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
2352/* enum: TX1 DPCPU bus. */
2353#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
2354/* enum: RX DICPU bus. */
2355#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
2356/* enum: TX DICPU bus. */
2357#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
2358/* Pattern written to RAM / register */
2359#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16
2360/* Actual value read from RAM / register */
2361#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20
2362/* ECC error mask */
2363#define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24
2364/* ECC parity error mask */
2365#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28
2366/* ECC fatal error mask */
2367#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32
Ben Hutchings05a93202011-12-20 00:44:06 +00002368
2369
2370/***********************************/
2371/* MC_CMD_FLUSH_RX_QUEUES
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002372 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ
2373 * flushes should be initiated via this MCDI operation, rather than via
2374 * directly writing FLUSH_CMD.
2375 *
2376 * The flush is completed (either done/fail) asynchronously (after this command
2377 * returns). The driver must still wait for flush done/failure events as usual.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002378 */
Ben Hutchings05a93202011-12-20 00:44:06 +00002379#define MC_CMD_FLUSH_RX_QUEUES 0x27
2380
2381/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
2382#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
2383#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
2384#define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
2385#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
2386#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
2387#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
2388#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
2389
2390/* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
2391#define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002392
2393
Ben Hutchings05a93202011-12-20 00:44:06 +00002394/***********************************/
2395/* MC_CMD_GET_LOOPBACK_MODES
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002396 * Returns a bitmask of loopback modes available at each speed.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002397 */
2398#define MC_CMD_GET_LOOPBACK_MODES 0x28
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002399
Shradha Shah75122ec2015-05-20 11:08:23 +01002400#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2401
Ben Hutchings05a93202011-12-20 00:44:06 +00002402/* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
2403#define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002404
Ben Hutchings05a93202011-12-20 00:44:06 +00002405/* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002406#define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40
2407/* Supported loopbacks. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002408#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
2409#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
2410#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
2411#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002412/* enum: None. */
2413#define MC_CMD_LOOPBACK_NONE 0x0
2414/* enum: Data. */
2415#define MC_CMD_LOOPBACK_DATA 0x1
2416/* enum: GMAC. */
2417#define MC_CMD_LOOPBACK_GMAC 0x2
2418/* enum: XGMII. */
2419#define MC_CMD_LOOPBACK_XGMII 0x3
2420/* enum: XGXS. */
2421#define MC_CMD_LOOPBACK_XGXS 0x4
2422/* enum: XAUI. */
2423#define MC_CMD_LOOPBACK_XAUI 0x5
2424/* enum: GMII. */
2425#define MC_CMD_LOOPBACK_GMII 0x6
2426/* enum: SGMII. */
2427#define MC_CMD_LOOPBACK_SGMII 0x7
2428/* enum: XGBR. */
2429#define MC_CMD_LOOPBACK_XGBR 0x8
2430/* enum: XFI. */
2431#define MC_CMD_LOOPBACK_XFI 0x9
2432/* enum: XAUI Far. */
2433#define MC_CMD_LOOPBACK_XAUI_FAR 0xa
2434/* enum: GMII Far. */
2435#define MC_CMD_LOOPBACK_GMII_FAR 0xb
2436/* enum: SGMII Far. */
2437#define MC_CMD_LOOPBACK_SGMII_FAR 0xc
2438/* enum: XFI Far. */
2439#define MC_CMD_LOOPBACK_XFI_FAR 0xd
2440/* enum: GPhy. */
2441#define MC_CMD_LOOPBACK_GPHY 0xe
2442/* enum: PhyXS. */
2443#define MC_CMD_LOOPBACK_PHYXS 0xf
2444/* enum: PCS. */
2445#define MC_CMD_LOOPBACK_PCS 0x10
2446/* enum: PMA-PMD. */
2447#define MC_CMD_LOOPBACK_PMAPMD 0x11
2448/* enum: Cross-Port. */
2449#define MC_CMD_LOOPBACK_XPORT 0x12
2450/* enum: XGMII-Wireside. */
2451#define MC_CMD_LOOPBACK_XGMII_WS 0x13
2452/* enum: XAUI Wireside. */
2453#define MC_CMD_LOOPBACK_XAUI_WS 0x14
2454/* enum: XAUI Wireside Far. */
2455#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
2456/* enum: XAUI Wireside near. */
2457#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
2458/* enum: GMII Wireside. */
2459#define MC_CMD_LOOPBACK_GMII_WS 0x17
2460/* enum: XFI Wireside. */
2461#define MC_CMD_LOOPBACK_XFI_WS 0x18
2462/* enum: XFI Wireside Far. */
2463#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
2464/* enum: PhyXS Wireside. */
2465#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
2466/* enum: PMA lanes MAC-Serdes. */
2467#define MC_CMD_LOOPBACK_PMA_INT 0x1b
2468/* enum: KR Serdes Parallel (Encoder). */
2469#define MC_CMD_LOOPBACK_SD_NEAR 0x1c
2470/* enum: KR Serdes Serial. */
2471#define MC_CMD_LOOPBACK_SD_FAR 0x1d
2472/* enum: PMA lanes MAC-Serdes Wireside. */
2473#define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
2474/* enum: KR Serdes Parallel Wireside (Full PCS). */
2475#define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
2476/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
2477#define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
2478/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
2479#define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
2480/* enum: KR Serdes Serial Wireside. */
2481#define MC_CMD_LOOPBACK_SD_FES_WS 0x22
Ben Hutchings512bb062013-12-04 19:48:07 +00002482/* enum: Near side of AOE Siena side port */
2483#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002484/* Supported loopbacks. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002485#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
2486#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
2487#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
2488#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
2489/* Enum values, see field(s): */
2490/* 100M */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002491/* Supported loopbacks. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002492#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
2493#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
2494#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
2495#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
2496/* Enum values, see field(s): */
2497/* 100M */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002498/* Supported loopbacks. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002499#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
2500#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
2501#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
2502#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
2503/* Enum values, see field(s): */
2504/* 100M */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002505/* Supported loopbacks. */
2506#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
2507#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
2508#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
2509#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
2510/* Enum values, see field(s): */
2511/* 100M */
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002512
Ben Hutchings05a93202011-12-20 00:44:06 +00002513
2514/***********************************/
2515/* MC_CMD_GET_LINK
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002516 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
2517 * ETIME.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002518 */
2519#define MC_CMD_GET_LINK 0x29
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002520
Shradha Shah75122ec2015-05-20 11:08:23 +01002521#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2522
Ben Hutchings05a93202011-12-20 00:44:06 +00002523/* MC_CMD_GET_LINK_IN msgrequest */
2524#define MC_CMD_GET_LINK_IN_LEN 0
2525
2526/* MC_CMD_GET_LINK_OUT msgresponse */
2527#define MC_CMD_GET_LINK_OUT_LEN 28
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002528/* near-side advertised capabilities */
Ben Hutchings05a93202011-12-20 00:44:06 +00002529#define MC_CMD_GET_LINK_OUT_CAP_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002530/* link-partner advertised capabilities */
Ben Hutchings05a93202011-12-20 00:44:06 +00002531#define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002532/* Autonegotiated speed in mbit/s. The link may still be down even if this
2533 * reads non-zero.
2534 */
Ben Hutchings05a93202011-12-20 00:44:06 +00002535#define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002536/* Current loopback setting. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002537#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
2538/* Enum values, see field(s): */
2539/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
2540#define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
2541#define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
2542#define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
2543#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
2544#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
2545#define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
2546#define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
2547#define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
2548#define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
Ben Hutchings512bb062013-12-04 19:48:07 +00002549#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
2550#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
2551#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
2552#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002553/* This returns the negotiated flow control value. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002554#define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002555/* enum: Flow control is off. */
2556#define MC_CMD_FCNTL_OFF 0x0
2557/* enum: Respond to flow control. */
2558#define MC_CMD_FCNTL_RESPOND 0x1
2559/* enum: Respond to and Issue flow control. */
2560#define MC_CMD_FCNTL_BIDIR 0x2
Ben Hutchings05a93202011-12-20 00:44:06 +00002561#define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
2562#define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
2563#define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
2564#define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
2565#define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
2566#define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
2567#define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
2568#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
2569#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
2570
2571
2572/***********************************/
2573/* MC_CMD_SET_LINK
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002574 * Write the unified MAC/PHY link configuration. Locks required: None. Return
2575 * code: 0, EINVAL, ETIME
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002576 */
2577#define MC_CMD_SET_LINK 0x2a
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002578
Shradha Shah75122ec2015-05-20 11:08:23 +01002579#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
2580
Ben Hutchings05a93202011-12-20 00:44:06 +00002581/* MC_CMD_SET_LINK_IN msgrequest */
2582#define MC_CMD_SET_LINK_IN_LEN 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002583/* ??? */
Ben Hutchings05a93202011-12-20 00:44:06 +00002584#define MC_CMD_SET_LINK_IN_CAP_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002585/* Flags */
Ben Hutchings05a93202011-12-20 00:44:06 +00002586#define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
2587#define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
2588#define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
2589#define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
2590#define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
2591#define MC_CMD_SET_LINK_IN_TXDIS_LBN 2
2592#define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002593/* Loopback mode. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002594#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
2595/* Enum values, see field(s): */
2596/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002597/* A loopback speed of "0" is supported, and means (choose any available
2598 * speed).
2599 */
Ben Hutchings05a93202011-12-20 00:44:06 +00002600#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
2601
2602/* MC_CMD_SET_LINK_OUT msgresponse */
2603#define MC_CMD_SET_LINK_OUT_LEN 0
2604
2605
2606/***********************************/
2607/* MC_CMD_SET_ID_LED
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002608 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002609 */
2610#define MC_CMD_SET_ID_LED 0x2b
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002611
Shradha Shah75122ec2015-05-20 11:08:23 +01002612#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
2613
Ben Hutchings05a93202011-12-20 00:44:06 +00002614/* MC_CMD_SET_ID_LED_IN msgrequest */
2615#define MC_CMD_SET_ID_LED_IN_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002616/* Set LED state. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002617#define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
2618#define MC_CMD_LED_OFF 0x0 /* enum */
2619#define MC_CMD_LED_ON 0x1 /* enum */
2620#define MC_CMD_LED_DEFAULT 0x2 /* enum */
2621
2622/* MC_CMD_SET_ID_LED_OUT msgresponse */
2623#define MC_CMD_SET_ID_LED_OUT_LEN 0
2624
2625
2626/***********************************/
2627/* MC_CMD_SET_MAC
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002628 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002629 */
2630#define MC_CMD_SET_MAC 0x2c
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002631
Shradha Shah75122ec2015-05-20 11:08:23 +01002632#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_LINK
2633
Ben Hutchings05a93202011-12-20 00:44:06 +00002634/* MC_CMD_SET_MAC_IN msgrequest */
2635#define MC_CMD_SET_MAC_IN_LEN 24
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002636/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
2637 * EtherII, VLAN, bug16011 padding).
2638 */
Ben Hutchings05a93202011-12-20 00:44:06 +00002639#define MC_CMD_SET_MAC_IN_MTU_OFST 0
2640#define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
2641#define MC_CMD_SET_MAC_IN_ADDR_OFST 8
2642#define MC_CMD_SET_MAC_IN_ADDR_LEN 8
2643#define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
2644#define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
2645#define MC_CMD_SET_MAC_IN_REJECT_OFST 16
2646#define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
2647#define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
2648#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
2649#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
2650#define MC_CMD_SET_MAC_IN_FCNTL_OFST 20
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002651/* enum: Flow control is off. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002652/* MC_CMD_FCNTL_OFF 0x0 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002653/* enum: Respond to flow control. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002654/* MC_CMD_FCNTL_RESPOND 0x1 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002655/* enum: Respond to and Issue flow control. */
Ben Hutchings05a93202011-12-20 00:44:06 +00002656/* MC_CMD_FCNTL_BIDIR 0x2 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002657/* enum: Auto neg flow control. */
2658#define MC_CMD_FCNTL_AUTO 0x3
Ben Hutchings05a93202011-12-20 00:44:06 +00002659
2660/* MC_CMD_SET_MAC_OUT msgresponse */
2661#define MC_CMD_SET_MAC_OUT_LEN 0
2662
2663
2664/***********************************/
2665/* MC_CMD_PHY_STATS
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002666 * Get generic PHY statistics. This call returns the statistics for a generic
2667 * PHY in a sparse array (indexed by the enumerate). Each value is represented
2668 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
2669 * statistics may be read from the message response. If DMA_ADDR != 0, then the
2670 * statistics are dmad to that (page-aligned location). Locks required: None.
2671 * Returns: 0, ETIME
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002672 */
2673#define MC_CMD_PHY_STATS 0x2d
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002674
Shradha Shah75122ec2015-05-20 11:08:23 +01002675#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
2676
Ben Hutchings05a93202011-12-20 00:44:06 +00002677/* MC_CMD_PHY_STATS_IN msgrequest */
2678#define MC_CMD_PHY_STATS_IN_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002679/* ??? */
Ben Hutchings05a93202011-12-20 00:44:06 +00002680#define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
2681#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
2682#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
2683#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002684
Ben Hutchings05a93202011-12-20 00:44:06 +00002685/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
2686#define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
2687
2688/* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
2689#define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
2690#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
2691#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
2692#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002693/* enum: OUI. */
2694#define MC_CMD_OUI 0x0
2695/* enum: PMA-PMD Link Up. */
2696#define MC_CMD_PMA_PMD_LINK_UP 0x1
2697/* enum: PMA-PMD RX Fault. */
2698#define MC_CMD_PMA_PMD_RX_FAULT 0x2
2699/* enum: PMA-PMD TX Fault. */
2700#define MC_CMD_PMA_PMD_TX_FAULT 0x3
2701/* enum: PMA-PMD Signal */
2702#define MC_CMD_PMA_PMD_SIGNAL 0x4
2703/* enum: PMA-PMD SNR A. */
2704#define MC_CMD_PMA_PMD_SNR_A 0x5
2705/* enum: PMA-PMD SNR B. */
2706#define MC_CMD_PMA_PMD_SNR_B 0x6
2707/* enum: PMA-PMD SNR C. */
2708#define MC_CMD_PMA_PMD_SNR_C 0x7
2709/* enum: PMA-PMD SNR D. */
2710#define MC_CMD_PMA_PMD_SNR_D 0x8
2711/* enum: PCS Link Up. */
2712#define MC_CMD_PCS_LINK_UP 0x9
2713/* enum: PCS RX Fault. */
2714#define MC_CMD_PCS_RX_FAULT 0xa
2715/* enum: PCS TX Fault. */
2716#define MC_CMD_PCS_TX_FAULT 0xb
2717/* enum: PCS BER. */
2718#define MC_CMD_PCS_BER 0xc
2719/* enum: PCS Block Errors. */
2720#define MC_CMD_PCS_BLOCK_ERRORS 0xd
2721/* enum: PhyXS Link Up. */
2722#define MC_CMD_PHYXS_LINK_UP 0xe
2723/* enum: PhyXS RX Fault. */
2724#define MC_CMD_PHYXS_RX_FAULT 0xf
2725/* enum: PhyXS TX Fault. */
2726#define MC_CMD_PHYXS_TX_FAULT 0x10
2727/* enum: PhyXS Align. */
2728#define MC_CMD_PHYXS_ALIGN 0x11
2729/* enum: PhyXS Sync. */
2730#define MC_CMD_PHYXS_SYNC 0x12
2731/* enum: AN link-up. */
2732#define MC_CMD_AN_LINK_UP 0x13
2733/* enum: AN Complete. */
2734#define MC_CMD_AN_COMPLETE 0x14
2735/* enum: AN 10GBaseT Status. */
2736#define MC_CMD_AN_10GBT_STATUS 0x15
2737/* enum: Clause 22 Link-Up. */
2738#define MC_CMD_CL22_LINK_UP 0x16
2739/* enum: (Last entry) */
2740#define MC_CMD_PHY_NSTATS 0x17
Ben Hutchings05a93202011-12-20 00:44:06 +00002741
2742
2743/***********************************/
2744/* MC_CMD_MAC_STATS
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002745 * Get generic MAC statistics. This call returns unified statistics maintained
2746 * by the MC as it switches between the GMAC and XMAC. The MC will write out
2747 * all supported stats. The driver should zero initialise the buffer to
2748 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
2749 * performed, and the statistics may be read from the message response. If
2750 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
2751 * Locks required: None. Returns: 0, ETIME
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002752 */
2753#define MC_CMD_MAC_STATS 0x2e
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002754
Shradha Shah75122ec2015-05-20 11:08:23 +01002755#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2756
Ben Hutchings05a93202011-12-20 00:44:06 +00002757/* MC_CMD_MAC_STATS_IN msgrequest */
Daniel Pieczkod7788192015-06-02 11:39:20 +01002758#define MC_CMD_MAC_STATS_IN_LEN 20
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002759/* ??? */
Ben Hutchings05a93202011-12-20 00:44:06 +00002760#define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
2761#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
2762#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
2763#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
2764#define MC_CMD_MAC_STATS_IN_CMD_OFST 8
2765#define MC_CMD_MAC_STATS_IN_DMA_LBN 0
2766#define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
2767#define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
2768#define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
2769#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
2770#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
2771#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
2772#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
2773#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
2774#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
2775#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
2776#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
2777#define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
2778#define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
2779#define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
Daniel Pieczkod7788192015-06-02 11:39:20 +01002780/* port id so vadapter stats can be provided */
2781#define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002782
Ben Hutchings05a93202011-12-20 00:44:06 +00002783/* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
2784#define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002785
Ben Hutchings05a93202011-12-20 00:44:06 +00002786/* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
2787#define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
2788#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
2789#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
2790#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
2791#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
2792#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
2793#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
2794#define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
2795#define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
2796#define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
2797#define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
2798#define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
2799#define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
2800#define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
2801#define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
2802#define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
2803#define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
2804#define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
2805#define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
2806#define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
2807#define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
2808#define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
2809#define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
2810#define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
2811#define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
2812#define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
2813#define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
2814#define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
2815#define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
2816#define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
2817#define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
2818#define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
2819#define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
2820#define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
2821#define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
2822#define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
2823#define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
2824#define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
2825#define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
2826#define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
2827#define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
2828#define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
2829#define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
2830#define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
2831#define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
2832#define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
2833#define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
2834#define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
2835#define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
2836#define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
2837#define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
2838#define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
2839#define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
2840#define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
2841#define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
2842#define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
2843#define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
2844#define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
2845#define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
2846#define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
2847#define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
2848#define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
2849#define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
2850#define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
2851#define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
2852#define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
Matthew Slattery2ca10a72013-09-10 19:06:27 +01002853/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
2854 * capability only.
2855 */
2856#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
2857/* enum: PM discard_bb_overflow counter. Valid for EF10 with
2858 * PM_AND_RXDP_COUNTERS capability only.
2859 */
2860#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
2861/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
2862 * capability only.
2863 */
2864#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
2865/* enum: PM discard_vfifo_full counter. Valid for EF10 with
2866 * PM_AND_RXDP_COUNTERS capability only.
2867 */
2868#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
2869/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
2870 * capability only.
2871 */
2872#define MC_CMD_MAC_PM_TRUNC_QBB 0x40
2873/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
2874 * capability only.
2875 */
2876#define MC_CMD_MAC_PM_DISCARD_QBB 0x41
2877/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
2878 * capability only.
2879 */
2880#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
2881/* enum: RXDP counter: Number of packets dropped due to the queue being
2882 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
2883 */
2884#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
2885/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
2886 * with PM_AND_RXDP_COUNTERS capability only.
2887 */
2888#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
2889/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
2890 * PM_AND_RXDP_COUNTERS capability only.
2891 */
2892#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
2893/* enum: RXDP counter: Number of times an emergency descriptor fetch was
2894 * performed. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
2895 */
Daniel Pieczkoe80ca0132015-06-02 11:38:34 +01002896#define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
Matthew Slattery2ca10a72013-09-10 19:06:27 +01002897/* enum: RXDP counter: Number of times the DPCPU waited for an existing
2898 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
2899 */
Daniel Pieczkoe80ca0132015-06-02 11:38:34 +01002900#define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
Daniel Pieczko3c36a2a2015-06-02 11:39:06 +01002901#define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
2902#define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
2903#define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
2904#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
2905#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
2906#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
2907#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
2908#define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
2909#define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
2910#define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
2911#define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
2912#define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
2913#define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
2914#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
2915#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
2916#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
2917#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
2918#define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
2919#define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
2920#define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
Matthew Slattery2ca10a72013-09-10 19:06:27 +01002921/* enum: Start of GMAC stats buffer space, for Siena only. */
2922#define MC_CMD_GMAC_DMABUF_START 0x40
2923/* enum: End of GMAC stats buffer space, for Siena only. */
2924#define MC_CMD_GMAC_DMABUF_END 0x5f
Ben Hutchings05a93202011-12-20 00:44:06 +00002925#define MC_CMD_MAC_GENERATION_END 0x60 /* enum */
2926#define MC_CMD_MAC_NSTATS 0x61 /* enum */
2927
2928
2929/***********************************/
2930/* MC_CMD_SRIOV
2931 * to be documented
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002932 */
Ben Hutchings05a93202011-12-20 00:44:06 +00002933#define MC_CMD_SRIOV 0x30
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002934
Ben Hutchings05a93202011-12-20 00:44:06 +00002935/* MC_CMD_SRIOV_IN msgrequest */
2936#define MC_CMD_SRIOV_IN_LEN 12
2937#define MC_CMD_SRIOV_IN_ENABLE_OFST 0
2938#define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
2939#define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
2940
2941/* MC_CMD_SRIOV_OUT msgresponse */
2942#define MC_CMD_SRIOV_OUT_LEN 8
2943#define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
2944#define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
2945
2946/* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
2947#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002948/* this is only used for the first record */
Ben Hutchings05a93202011-12-20 00:44:06 +00002949#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
2950#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
2951#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
2952#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
2953#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
2954#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
2955#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
2956#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
2957#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
2958#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
2959#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
2960#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
2961#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
2962#define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
2963#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
2964#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
2965#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
2966#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
2967#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
2968#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
2969#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
2970#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
2971#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
2972#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
2973#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32
2974
2975
2976/***********************************/
2977/* MC_CMD_MEMCPY
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01002978 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data
2979 * embedded directly in the command.
2980 *
2981 * A common pattern is for a client to use generation counts to signal a dma
2982 * update of a datastructure. To facilitate this, this MCDI operation can
2983 * contain multiple requests which are executed in strict order. Requests take
2984 * the form of duplicating the entire MCDI request continuously (including the
2985 * requests record, which is ignored in all but the first structure)
2986 *
2987 * The source data can either come from a DMA from the host, or it can be
2988 * embedded within the request directly, thereby eliminating a DMA read. To
2989 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
2990 * ADDR_LO=offset, and inserts the data at %offset from the start of the
2991 * payload. It's the callers responsibility to ensure that the embedded data
2992 * doesn't overlap the records.
2993 *
2994 * Returns: 0, EINVAL (invalid RID)
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00002995 */
Ben Hutchings05a93202011-12-20 00:44:06 +00002996#define MC_CMD_MEMCPY 0x31
2997
2998/* MC_CMD_MEMCPY_IN msgrequest */
2999#define MC_CMD_MEMCPY_IN_LENMIN 32
3000#define MC_CMD_MEMCPY_IN_LENMAX 224
3001#define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003002/* see MC_CMD_MEMCPY_RECORD_TYPEDEF */
Ben Hutchings05a93202011-12-20 00:44:06 +00003003#define MC_CMD_MEMCPY_IN_RECORD_OFST 0
3004#define MC_CMD_MEMCPY_IN_RECORD_LEN 32
3005#define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
3006#define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
3007
3008/* MC_CMD_MEMCPY_OUT msgresponse */
3009#define MC_CMD_MEMCPY_OUT_LEN 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003010
3011
Ben Hutchings05a93202011-12-20 00:44:06 +00003012/***********************************/
3013/* MC_CMD_WOL_FILTER_SET
3014 * Set a WoL filter.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003015 */
3016#define MC_CMD_WOL_FILTER_SET 0x32
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003017
Shradha Shah75122ec2015-05-20 11:08:23 +01003018#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
3019
Ben Hutchings05a93202011-12-20 00:44:06 +00003020/* MC_CMD_WOL_FILTER_SET_IN msgrequest */
3021#define MC_CMD_WOL_FILTER_SET_IN_LEN 192
3022#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
3023#define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
3024#define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003025/* A type value of 1 is unused. */
Ben Hutchings05a93202011-12-20 00:44:06 +00003026#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003027/* enum: Magic */
3028#define MC_CMD_WOL_TYPE_MAGIC 0x0
3029/* enum: MS Windows Magic */
3030#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
3031/* enum: IPv4 Syn */
3032#define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
3033/* enum: IPv6 Syn */
3034#define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
3035/* enum: Bitmap */
3036#define MC_CMD_WOL_TYPE_BITMAP 0x5
3037/* enum: Link */
3038#define MC_CMD_WOL_TYPE_LINK 0x6
3039/* enum: (Above this for future use) */
3040#define MC_CMD_WOL_TYPE_MAX 0x7
Ben Hutchings05a93202011-12-20 00:44:06 +00003041#define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
3042#define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
3043#define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003044
Ben Hutchings05a93202011-12-20 00:44:06 +00003045/* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
3046#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
3047/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
3048/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
3049#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
3050#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
3051#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
3052#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003053
Ben Hutchings05a93202011-12-20 00:44:06 +00003054/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
3055#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
3056/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
3057/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
3058#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
3059#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
3060#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
3061#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
3062#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
3063#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003064
Ben Hutchings05a93202011-12-20 00:44:06 +00003065/* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
3066#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
3067/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
3068/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
3069#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
3070#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
3071#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
3072#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
3073#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
3074#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
3075#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
3076#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003077
Ben Hutchings05a93202011-12-20 00:44:06 +00003078/* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
3079#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
3080/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
3081/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
3082#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
3083#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
3084#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
3085#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
3086#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
3087#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
3088#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
3089#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
3090#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
3091#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003092
Ben Hutchings05a93202011-12-20 00:44:06 +00003093/* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
3094#define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
3095/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
3096/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
3097#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
3098#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
3099#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
3100#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
3101#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
Ben Hutchings5297a982010-02-03 09:28:14 +00003102
Ben Hutchings05a93202011-12-20 00:44:06 +00003103/* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
3104#define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
3105#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003106
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003107
Ben Hutchings05a93202011-12-20 00:44:06 +00003108/***********************************/
3109/* MC_CMD_WOL_FILTER_REMOVE
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003110 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003111 */
3112#define MC_CMD_WOL_FILTER_REMOVE 0x33
Ben Hutchings05a93202011-12-20 00:44:06 +00003113
Shradha Shah75122ec2015-05-20 11:08:23 +01003114#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
3115
Ben Hutchings05a93202011-12-20 00:44:06 +00003116/* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
3117#define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
3118#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
3119
3120/* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
3121#define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003122
3123
Ben Hutchings05a93202011-12-20 00:44:06 +00003124/***********************************/
3125/* MC_CMD_WOL_FILTER_RESET
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003126 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
3127 * ENOSYS
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003128 */
3129#define MC_CMD_WOL_FILTER_RESET 0x34
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003130
Shradha Shah75122ec2015-05-20 11:08:23 +01003131#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
3132
Ben Hutchings05a93202011-12-20 00:44:06 +00003133/* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
3134#define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
3135#define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
3136#define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
3137#define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
3138
3139/* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
3140#define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
3141
3142
3143/***********************************/
3144/* MC_CMD_SET_MCAST_HASH
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003145 * Set the MCAST hash value without otherwise reconfiguring the MAC
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003146 */
3147#define MC_CMD_SET_MCAST_HASH 0x35
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003148
Ben Hutchings05a93202011-12-20 00:44:06 +00003149/* MC_CMD_SET_MCAST_HASH_IN msgrequest */
3150#define MC_CMD_SET_MCAST_HASH_IN_LEN 32
3151#define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
3152#define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
3153#define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
3154#define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16
3155
3156/* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
3157#define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
3158
3159
3160/***********************************/
3161/* MC_CMD_NVRAM_TYPES
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003162 * Return bitfield indicating available types of virtual NVRAM partitions.
3163 * Locks required: none. Returns: 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003164 */
3165#define MC_CMD_NVRAM_TYPES 0x36
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003166
Shradha Shah75122ec2015-05-20 11:08:23 +01003167#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3168
Ben Hutchings05a93202011-12-20 00:44:06 +00003169/* MC_CMD_NVRAM_TYPES_IN msgrequest */
3170#define MC_CMD_NVRAM_TYPES_IN_LEN 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003171
Ben Hutchings05a93202011-12-20 00:44:06 +00003172/* MC_CMD_NVRAM_TYPES_OUT msgresponse */
3173#define MC_CMD_NVRAM_TYPES_OUT_LEN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003174/* Bit mask of supported types. */
Ben Hutchings05a93202011-12-20 00:44:06 +00003175#define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003176/* enum: Disabled callisto. */
3177#define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
3178/* enum: MC firmware. */
3179#define MC_CMD_NVRAM_TYPE_MC_FW 0x1
3180/* enum: MC backup firmware. */
3181#define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
3182/* enum: Static configuration Port0. */
3183#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
3184/* enum: Static configuration Port1. */
3185#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
3186/* enum: Dynamic configuration Port0. */
3187#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
3188/* enum: Dynamic configuration Port1. */
3189#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
3190/* enum: Expansion Rom. */
3191#define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
3192/* enum: Expansion Rom Configuration Port0. */
3193#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
3194/* enum: Expansion Rom Configuration Port1. */
3195#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
3196/* enum: Phy Configuration Port0. */
3197#define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
3198/* enum: Phy Configuration Port1. */
3199#define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
3200/* enum: Log. */
3201#define MC_CMD_NVRAM_TYPE_LOG 0xc
3202/* enum: FPGA image. */
3203#define MC_CMD_NVRAM_TYPE_FPGA 0xd
3204/* enum: FPGA backup image */
3205#define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
3206/* enum: FC firmware. */
3207#define MC_CMD_NVRAM_TYPE_FC_FW 0xf
3208/* enum: FC backup firmware. */
3209#define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
3210/* enum: CPLD image. */
3211#define MC_CMD_NVRAM_TYPE_CPLD 0x11
3212/* enum: Licensing information. */
3213#define MC_CMD_NVRAM_TYPE_LICENSE 0x12
3214/* enum: FC Log. */
3215#define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
Ben Hutchings05a93202011-12-20 00:44:06 +00003216
3217
3218/***********************************/
3219/* MC_CMD_NVRAM_INFO
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003220 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
3221 * EINVAL (bad type).
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003222 */
3223#define MC_CMD_NVRAM_INFO 0x37
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003224
Shradha Shah75122ec2015-05-20 11:08:23 +01003225#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3226
Ben Hutchings05a93202011-12-20 00:44:06 +00003227/* MC_CMD_NVRAM_INFO_IN msgrequest */
3228#define MC_CMD_NVRAM_INFO_IN_LEN 4
3229#define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
3230/* Enum values, see field(s): */
3231/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3232
3233/* MC_CMD_NVRAM_INFO_OUT msgresponse */
3234#define MC_CMD_NVRAM_INFO_OUT_LEN 24
3235#define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
3236/* Enum values, see field(s): */
3237/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3238#define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
3239#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
3240#define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
3241#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
3242#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003243#define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
3244#define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
3245#define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7
3246#define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
Ben Hutchings05a93202011-12-20 00:44:06 +00003247#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
3248#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
3249
3250
3251/***********************************/
3252/* MC_CMD_NVRAM_UPDATE_START
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003253 * Start a group of update operations on a virtual NVRAM partition. Locks
3254 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
3255 * PHY_LOCK required and not held).
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003256 */
3257#define MC_CMD_NVRAM_UPDATE_START 0x38
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003258
Shradha Shah75122ec2015-05-20 11:08:23 +01003259#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3260
Ben Hutchings05a93202011-12-20 00:44:06 +00003261/* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */
3262#define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
3263#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
3264/* Enum values, see field(s): */
3265/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3266
3267/* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
3268#define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
3269
3270
3271/***********************************/
3272/* MC_CMD_NVRAM_READ
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003273 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if
3274 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
3275 * PHY_LOCK required and not held)
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003276 */
3277#define MC_CMD_NVRAM_READ 0x39
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003278
Shradha Shah75122ec2015-05-20 11:08:23 +01003279#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3280
Ben Hutchings05a93202011-12-20 00:44:06 +00003281/* MC_CMD_NVRAM_READ_IN msgrequest */
3282#define MC_CMD_NVRAM_READ_IN_LEN 12
3283#define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
3284/* Enum values, see field(s): */
3285/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3286#define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003287/* amount to read in bytes */
Ben Hutchings05a93202011-12-20 00:44:06 +00003288#define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
3289
3290/* MC_CMD_NVRAM_READ_OUT msgresponse */
3291#define MC_CMD_NVRAM_READ_OUT_LENMIN 1
Ben Hutchings576eda82012-09-19 02:46:37 +01003292#define MC_CMD_NVRAM_READ_OUT_LENMAX 252
Ben Hutchings05a93202011-12-20 00:44:06 +00003293#define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
3294#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
3295#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
3296#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
Ben Hutchings576eda82012-09-19 02:46:37 +01003297#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
Ben Hutchings05a93202011-12-20 00:44:06 +00003298
3299
3300/***********************************/
3301/* MC_CMD_NVRAM_WRITE
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003302 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if
3303 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
3304 * PHY_LOCK required and not held)
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003305 */
3306#define MC_CMD_NVRAM_WRITE 0x3a
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003307
Shradha Shah75122ec2015-05-20 11:08:23 +01003308#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3309
Ben Hutchings05a93202011-12-20 00:44:06 +00003310/* MC_CMD_NVRAM_WRITE_IN msgrequest */
3311#define MC_CMD_NVRAM_WRITE_IN_LENMIN 13
Ben Hutchings576eda82012-09-19 02:46:37 +01003312#define MC_CMD_NVRAM_WRITE_IN_LENMAX 252
Ben Hutchings05a93202011-12-20 00:44:06 +00003313#define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
3314#define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
3315/* Enum values, see field(s): */
3316/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3317#define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
3318#define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
3319#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
3320#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
3321#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
Ben Hutchings576eda82012-09-19 02:46:37 +01003322#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
Ben Hutchings05a93202011-12-20 00:44:06 +00003323
3324/* MC_CMD_NVRAM_WRITE_OUT msgresponse */
3325#define MC_CMD_NVRAM_WRITE_OUT_LEN 0
3326
3327
3328/***********************************/
3329/* MC_CMD_NVRAM_ERASE
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003330 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if
3331 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
3332 * PHY_LOCK required and not held)
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003333 */
3334#define MC_CMD_NVRAM_ERASE 0x3b
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003335
Shradha Shah75122ec2015-05-20 11:08:23 +01003336#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3337
Ben Hutchings05a93202011-12-20 00:44:06 +00003338/* MC_CMD_NVRAM_ERASE_IN msgrequest */
3339#define MC_CMD_NVRAM_ERASE_IN_LEN 12
3340#define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
3341/* Enum values, see field(s): */
3342/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3343#define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
3344#define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
3345
3346/* MC_CMD_NVRAM_ERASE_OUT msgresponse */
3347#define MC_CMD_NVRAM_ERASE_OUT_LEN 0
3348
3349
3350/***********************************/
3351/* MC_CMD_NVRAM_UPDATE_FINISH
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003352 * Finish a group of update operations on a virtual NVRAM partition. Locks
3353 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad
3354 * type/offset/length), EACCES (if PHY_LOCK required and not held)
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003355 */
3356#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003357
Shradha Shah75122ec2015-05-20 11:08:23 +01003358#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3359
Ben Hutchings05a93202011-12-20 00:44:06 +00003360/* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */
3361#define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
3362#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
3363/* Enum values, see field(s): */
3364/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3365#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
3366
3367/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */
3368#define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
3369
3370
3371/***********************************/
3372/* MC_CMD_REBOOT
Ben Hutchings5297a982010-02-03 09:28:14 +00003373 * Reboot the MC.
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003374 *
3375 * The AFTER_ASSERTION flag is intended to be used when the driver notices an
3376 * assertion failure (at which point it is expected to perform a complete tear
3377 * down and reinitialise), to allow both ports to reset the MC once in an
3378 * atomic fashion.
3379 *
3380 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
3381 * which means that they will automatically reboot out of the assertion
3382 * handler, so this is in practise an optional operation. It is still
3383 * recommended that drivers execute this to support custom firmwares with
3384 * REBOOT_ON_ASSERT=0.
3385 *
3386 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
3387 * DATALEN=0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003388 */
3389#define MC_CMD_REBOOT 0x3d
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003390
Shradha Shah75122ec2015-05-20 11:08:23 +01003391#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3392
Ben Hutchings05a93202011-12-20 00:44:06 +00003393/* MC_CMD_REBOOT_IN msgrequest */
3394#define MC_CMD_REBOOT_IN_LEN 4
3395#define MC_CMD_REBOOT_IN_FLAGS_OFST 0
3396#define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
3397
3398/* MC_CMD_REBOOT_OUT msgresponse */
3399#define MC_CMD_REBOOT_OUT_LEN 0
3400
3401
3402/***********************************/
3403/* MC_CMD_SCHEDINFO
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003404 * Request scheduler info. Locks required: NONE. Returns: An array of
3405 * (timeslice,maximum overrun), one for each thread, in ascending order of
3406 * thread address.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003407 */
3408#define MC_CMD_SCHEDINFO 0x3e
Ben Hutchings05a93202011-12-20 00:44:06 +00003409
3410/* MC_CMD_SCHEDINFO_IN msgrequest */
3411#define MC_CMD_SCHEDINFO_IN_LEN 0
3412
3413/* MC_CMD_SCHEDINFO_OUT msgresponse */
3414#define MC_CMD_SCHEDINFO_OUT_LENMIN 4
3415#define MC_CMD_SCHEDINFO_OUT_LENMAX 252
3416#define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
3417#define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
3418#define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
3419#define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
3420#define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003421
3422
Ben Hutchings05a93202011-12-20 00:44:06 +00003423/***********************************/
3424/* MC_CMD_REBOOT_MODE
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003425 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot
3426 * mode to the specified value. Returns the old mode.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003427 */
3428#define MC_CMD_REBOOT_MODE 0x3f
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003429
Shradha Shah75122ec2015-05-20 11:08:23 +01003430#define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3431
Ben Hutchings05a93202011-12-20 00:44:06 +00003432/* MC_CMD_REBOOT_MODE_IN msgrequest */
3433#define MC_CMD_REBOOT_MODE_IN_LEN 4
3434#define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003435/* enum: Normal. */
3436#define MC_CMD_REBOOT_MODE_NORMAL 0x0
3437/* enum: Power-on Reset. */
3438#define MC_CMD_REBOOT_MODE_POR 0x2
3439/* enum: Snapper. */
3440#define MC_CMD_REBOOT_MODE_SNAPPER 0x3
3441/* enum: snapper fake POR */
3442#define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
3443#define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7
3444#define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003445
Ben Hutchings05a93202011-12-20 00:44:06 +00003446/* MC_CMD_REBOOT_MODE_OUT msgresponse */
3447#define MC_CMD_REBOOT_MODE_OUT_LEN 4
3448#define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003449
3450
Ben Hutchings05a93202011-12-20 00:44:06 +00003451/***********************************/
3452/* MC_CMD_SENSOR_INFO
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003453 * Returns information about every available sensor.
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003454 *
3455 * Each sensor has a single (16bit) value, and a corresponding state. The
3456 * mapping between value and state is nominally determined by the MC, but may
3457 * be implemented using up to 2 ranges per sensor.
3458 *
3459 * This call returns a mask (32bit) of the sensors that are supported by this
3460 * platform, then an array of sensor information structures, in order of sensor
3461 * type (but without gaps for unimplemented sensors). Each structure defines
3462 * the ranges for the corresponding sensor. An unused range is indicated by
3463 * equal limit values. If one range is used, a value outside that range results
3464 * in STATE_FATAL. If two ranges are used, a value outside the second range
3465 * results in STATE_FATAL while a value outside the first and inside the second
3466 * range results in STATE_WARNING.
3467 *
3468 * Sensor masks and sensor information arrays are organised into pages. For
3469 * backward compatibility, older host software can only use sensors in page 0.
3470 * Bit 32 in the sensor mask was previously unused, and is no reserved for use
3471 * as the next page flag.
3472 *
3473 * If the request does not contain a PAGE value then firmware will only return
3474 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
3475 *
3476 * If the request contains a PAGE value then firmware responds with the sensor
3477 * mask and sensor information array for that page of sensors. In this case bit
3478 * 31 in the mask is set if another page exists.
3479 *
3480 * Locks required: None Returns: 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003481 */
3482#define MC_CMD_SENSOR_INFO 0x41
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003483
Shradha Shah75122ec2015-05-20 11:08:23 +01003484#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3485
Ben Hutchings05a93202011-12-20 00:44:06 +00003486/* MC_CMD_SENSOR_INFO_IN msgrequest */
3487#define MC_CMD_SENSOR_INFO_IN_LEN 0
3488
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003489/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */
3490#define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
3491/* Which page of sensors to report.
3492 *
3493 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
3494 *
3495 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
3496 */
3497#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
3498
Ben Hutchings05a93202011-12-20 00:44:06 +00003499/* MC_CMD_SENSOR_INFO_OUT msgresponse */
Ben Hutchings512bb062013-12-04 19:48:07 +00003500#define MC_CMD_SENSOR_INFO_OUT_LENMIN 4
Ben Hutchings05a93202011-12-20 00:44:06 +00003501#define MC_CMD_SENSOR_INFO_OUT_LENMAX 252
3502#define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
3503#define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003504/* enum: Controller temperature: degC */
3505#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
3506/* enum: Phy common temperature: degC */
3507#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
3508/* enum: Controller cooling: bool */
3509#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
3510/* enum: Phy 0 temperature: degC */
3511#define MC_CMD_SENSOR_PHY0_TEMP 0x3
3512/* enum: Phy 0 cooling: bool */
3513#define MC_CMD_SENSOR_PHY0_COOLING 0x4
3514/* enum: Phy 1 temperature: degC */
3515#define MC_CMD_SENSOR_PHY1_TEMP 0x5
3516/* enum: Phy 1 cooling: bool */
3517#define MC_CMD_SENSOR_PHY1_COOLING 0x6
3518/* enum: 1.0v power: mV */
3519#define MC_CMD_SENSOR_IN_1V0 0x7
3520/* enum: 1.2v power: mV */
3521#define MC_CMD_SENSOR_IN_1V2 0x8
3522/* enum: 1.8v power: mV */
3523#define MC_CMD_SENSOR_IN_1V8 0x9
3524/* enum: 2.5v power: mV */
3525#define MC_CMD_SENSOR_IN_2V5 0xa
3526/* enum: 3.3v power: mV */
3527#define MC_CMD_SENSOR_IN_3V3 0xb
3528/* enum: 12v power: mV */
3529#define MC_CMD_SENSOR_IN_12V0 0xc
3530/* enum: 1.2v analogue power: mV */
3531#define MC_CMD_SENSOR_IN_1V2A 0xd
3532/* enum: reference voltage: mV */
3533#define MC_CMD_SENSOR_IN_VREF 0xe
3534/* enum: AOE FPGA power: mV */
3535#define MC_CMD_SENSOR_OUT_VAOE 0xf
3536/* enum: AOE FPGA temperature: degC */
3537#define MC_CMD_SENSOR_AOE_TEMP 0x10
3538/* enum: AOE FPGA PSU temperature: degC */
3539#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
3540/* enum: AOE PSU temperature: degC */
3541#define MC_CMD_SENSOR_PSU_TEMP 0x12
3542/* enum: Fan 0 speed: RPM */
3543#define MC_CMD_SENSOR_FAN_0 0x13
3544/* enum: Fan 1 speed: RPM */
3545#define MC_CMD_SENSOR_FAN_1 0x14
3546/* enum: Fan 2 speed: RPM */
3547#define MC_CMD_SENSOR_FAN_2 0x15
3548/* enum: Fan 3 speed: RPM */
3549#define MC_CMD_SENSOR_FAN_3 0x16
3550/* enum: Fan 4 speed: RPM */
3551#define MC_CMD_SENSOR_FAN_4 0x17
3552/* enum: AOE FPGA input power: mV */
3553#define MC_CMD_SENSOR_IN_VAOE 0x18
3554/* enum: AOE FPGA current: mA */
3555#define MC_CMD_SENSOR_OUT_IAOE 0x19
3556/* enum: AOE FPGA input current: mA */
3557#define MC_CMD_SENSOR_IN_IAOE 0x1a
3558/* enum: NIC power consumption: W */
3559#define MC_CMD_SENSOR_NIC_POWER 0x1b
3560/* enum: 0.9v power voltage: mV */
3561#define MC_CMD_SENSOR_IN_0V9 0x1c
3562/* enum: 0.9v power current: mA */
3563#define MC_CMD_SENSOR_IN_I0V9 0x1d
3564/* enum: 1.2v power current: mA */
3565#define MC_CMD_SENSOR_IN_I1V2 0x1e
3566/* enum: Not a sensor: reserved for the next page flag */
3567#define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
3568/* enum: 0.9v power voltage (at ADC): mV */
3569#define MC_CMD_SENSOR_IN_0V9_ADC 0x20
3570/* enum: Controller temperature 2: degC */
3571#define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
3572/* enum: Voltage regulator internal temperature: degC */
3573#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
3574/* enum: 0.9V voltage regulator temperature: degC */
3575#define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
3576/* enum: 1.2V voltage regulator temperature: degC */
3577#define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
3578/* enum: controller internal temperature sensor voltage (internal ADC): mV */
3579#define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
3580/* enum: controller internal temperature (internal ADC): degC */
3581#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
3582/* enum: controller internal temperature sensor voltage (external ADC): mV */
3583#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
3584/* enum: controller internal temperature (external ADC): degC */
3585#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
3586/* enum: ambient temperature: degC */
3587#define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
3588/* enum: air flow: bool */
3589#define MC_CMD_SENSOR_AIRFLOW 0x2a
3590/* enum: voltage between VSS08D and VSS08D at CSR: mV */
3591#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
3592/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
3593#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
Ben Hutchings512bb062013-12-04 19:48:07 +00003594/* enum: Hotpoint temperature: degC */
3595#define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003596/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
Ben Hutchings05a93202011-12-20 00:44:06 +00003597#define MC_CMD_SENSOR_ENTRY_OFST 4
3598#define MC_CMD_SENSOR_ENTRY_LEN 8
3599#define MC_CMD_SENSOR_ENTRY_LO_OFST 4
3600#define MC_CMD_SENSOR_ENTRY_HI_OFST 8
Ben Hutchings512bb062013-12-04 19:48:07 +00003601#define MC_CMD_SENSOR_ENTRY_MINNUM 0
Ben Hutchings05a93202011-12-20 00:44:06 +00003602#define MC_CMD_SENSOR_ENTRY_MAXNUM 31
3603
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003604/* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */
Ben Hutchings512bb062013-12-04 19:48:07 +00003605#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003606#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
3607#define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
3608#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
3609/* Enum values, see field(s): */
3610/* MC_CMD_SENSOR_INFO_OUT */
3611#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31
3612#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
3613/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
3614/* MC_CMD_SENSOR_ENTRY_OFST 4 */
3615/* MC_CMD_SENSOR_ENTRY_LEN 8 */
3616/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
3617/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
Ben Hutchings512bb062013-12-04 19:48:07 +00003618/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003619/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
3620
Ben Hutchings05a93202011-12-20 00:44:06 +00003621/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
3622#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
3623#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
3624#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
3625#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
3626#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
3627#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
3628#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
3629#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
3630#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
3631#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
3632#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
3633#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
3634#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
3635#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
3636#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
3637#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
3638#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
3639
3640
3641/***********************************/
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003642/* MC_CMD_READ_SENSORS
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003643 * Returns the current reading from each sensor. DMAs an array of sensor
3644 * readings, in order of sensor type (but without gaps for unimplemented
3645 * sensors), into host memory. Each array element is a
3646 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.
3647 *
3648 * If the request does not contain the LENGTH field then only sensors 0 to 30
3649 * are reported, to avoid DMA buffer overflow in older host software. If the
3650 * sensor reading require more space than the LENGTH allows, then return
3651 * EINVAL.
3652 *
3653 * The MC will send a SENSOREVT event every time any sensor changes state. The
3654 * driver is responsible for ensuring that it doesn't miss any events. The
3655 * board will function normally if all sensors are in STATE_OK or
3656 * STATE_WARNING. Otherwise the board should not be expected to function.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003657 */
3658#define MC_CMD_READ_SENSORS 0x42
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003659
Shradha Shah75122ec2015-05-20 11:08:23 +01003660#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3661
Ben Hutchings05a93202011-12-20 00:44:06 +00003662/* MC_CMD_READ_SENSORS_IN msgrequest */
3663#define MC_CMD_READ_SENSORS_IN_LEN 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003664/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
Ben Hutchings05a93202011-12-20 00:44:06 +00003665#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
3666#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
3667#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
3668#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
3669
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003670/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
3671#define MC_CMD_READ_SENSORS_EXT_IN_LEN 12
3672/* DMA address of host buffer for sensor readings */
3673#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
3674#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
3675#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
3676#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
3677/* Size in bytes of host buffer. */
3678#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
3679
Ben Hutchings05a93202011-12-20 00:44:06 +00003680/* MC_CMD_READ_SENSORS_OUT msgresponse */
3681#define MC_CMD_READ_SENSORS_OUT_LEN 0
3682
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003683/* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */
3684#define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
3685
Ben Hutchings05a93202011-12-20 00:44:06 +00003686/* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003687#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
Ben Hutchings05a93202011-12-20 00:44:06 +00003688#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
3689#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
3690#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
3691#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
3692#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
3693#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003694/* enum: Ok. */
3695#define MC_CMD_SENSOR_STATE_OK 0x0
3696/* enum: Breached warning threshold. */
3697#define MC_CMD_SENSOR_STATE_WARNING 0x1
3698/* enum: Breached fatal threshold. */
3699#define MC_CMD_SENSOR_STATE_FATAL 0x2
3700/* enum: Fault with sensor. */
3701#define MC_CMD_SENSOR_STATE_BROKEN 0x3
3702/* enum: Sensor is working but does not currently have a reading. */
3703#define MC_CMD_SENSOR_STATE_NO_READING 0x4
Ben Hutchings05a93202011-12-20 00:44:06 +00003704#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
3705#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003706#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3
3707#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
3708/* Enum values, see field(s): */
3709/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
3710#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24
3711#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8
Ben Hutchings5297a982010-02-03 09:28:14 +00003712
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003713
Ben Hutchings05a93202011-12-20 00:44:06 +00003714/***********************************/
3715/* MC_CMD_GET_PHY_STATE
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003716 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot
3717 * (e.g. due to missing or corrupted firmware). Locks required: None. Return
3718 * code: 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003719 */
3720#define MC_CMD_GET_PHY_STATE 0x43
3721
Shradha Shah75122ec2015-05-20 11:08:23 +01003722#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3723
Ben Hutchings05a93202011-12-20 00:44:06 +00003724/* MC_CMD_GET_PHY_STATE_IN msgrequest */
3725#define MC_CMD_GET_PHY_STATE_IN_LEN 0
3726
3727/* MC_CMD_GET_PHY_STATE_OUT msgresponse */
3728#define MC_CMD_GET_PHY_STATE_OUT_LEN 4
3729#define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003730/* enum: Ok. */
3731#define MC_CMD_PHY_STATE_OK 0x1
3732/* enum: Faulty. */
3733#define MC_CMD_PHY_STATE_ZOMBIE 0x2
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003734
3735
Ben Hutchings05a93202011-12-20 00:44:06 +00003736/***********************************/
3737/* MC_CMD_SETUP_8021QBB
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003738 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
3739 * disable 802.Qbb for a given priority.
Ben Hutchings05a93202011-12-20 00:44:06 +00003740 */
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003741#define MC_CMD_SETUP_8021QBB 0x44
Ben Hutchings05a93202011-12-20 00:44:06 +00003742
3743/* MC_CMD_SETUP_8021QBB_IN msgrequest */
3744#define MC_CMD_SETUP_8021QBB_IN_LEN 32
3745#define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
3746#define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32
3747
3748/* MC_CMD_SETUP_8021QBB_OUT msgresponse */
3749#define MC_CMD_SETUP_8021QBB_OUT_LEN 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003750
3751
Ben Hutchings05a93202011-12-20 00:44:06 +00003752/***********************************/
3753/* MC_CMD_WOL_FILTER_GET
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003754 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003755 */
3756#define MC_CMD_WOL_FILTER_GET 0x45
Ben Hutchings05a93202011-12-20 00:44:06 +00003757
Shradha Shah75122ec2015-05-20 11:08:23 +01003758#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
3759
Ben Hutchings05a93202011-12-20 00:44:06 +00003760/* MC_CMD_WOL_FILTER_GET_IN msgrequest */
3761#define MC_CMD_WOL_FILTER_GET_IN_LEN 0
3762
3763/* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
3764#define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
3765#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003766
3767
Ben Hutchings05a93202011-12-20 00:44:06 +00003768/***********************************/
3769/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003770 * Add a protocol offload to NIC for lights-out state. Locks required: None.
3771 * Returns: 0, ENOSYS
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003772 */
3773#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
3774
Shradha Shah75122ec2015-05-20 11:08:23 +01003775#define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK
3776
Ben Hutchings05a93202011-12-20 00:44:06 +00003777/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
3778#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
3779#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
3780#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
3781#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
3782#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
3783#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
3784#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
3785#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
3786#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
3787#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003788
Ben Hutchings05a93202011-12-20 00:44:06 +00003789/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
3790#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
3791/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
3792#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
3793#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
3794#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003795
Ben Hutchings05a93202011-12-20 00:44:06 +00003796/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
3797#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
3798/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
3799#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
3800#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
3801#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
3802#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
3803#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
3804#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16
3805
3806/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
3807#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
3808#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003809
3810
Ben Hutchings05a93202011-12-20 00:44:06 +00003811/***********************************/
3812/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003813 * Remove a protocol offload from NIC for lights-out state. Locks required:
3814 * None. Returns: 0, ENOSYS
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003815 */
3816#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003817
Shradha Shah75122ec2015-05-20 11:08:23 +01003818#define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK
3819
Ben Hutchings05a93202011-12-20 00:44:06 +00003820/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
3821#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
3822#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
3823#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003824
Ben Hutchings05a93202011-12-20 00:44:06 +00003825/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
3826#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003827
3828
Ben Hutchings05a93202011-12-20 00:44:06 +00003829/***********************************/
3830/* MC_CMD_MAC_RESET_RESTORE
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003831 * Restore MAC after block reset. Locks required: None. Returns: 0.
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003832 */
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003833#define MC_CMD_MAC_RESET_RESTORE 0x48
Ben Hutchings05a93202011-12-20 00:44:06 +00003834
3835/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
3836#define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
3837
3838/* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
3839#define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00003840
Ben Hutchings5297a982010-02-03 09:28:14 +00003841
Ben Hutchings05a93202011-12-20 00:44:06 +00003842/***********************************/
3843/* MC_CMD_TESTASSERT
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003844 * Deliberately trigger an assert-detonation in the firmware for testing
3845 * purposes (i.e. to allow tests that the driver copes gracefully). Locks
3846 * required: None Returns: 0
Ben Hutchings5297a982010-02-03 09:28:14 +00003847 */
Ben Hutchings5297a982010-02-03 09:28:14 +00003848#define MC_CMD_TESTASSERT 0x49
Ben Hutchings5297a982010-02-03 09:28:14 +00003849
Shradha Shah75122ec2015-05-20 11:08:23 +01003850#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3851
Ben Hutchings05a93202011-12-20 00:44:06 +00003852/* MC_CMD_TESTASSERT_IN msgrequest */
3853#define MC_CMD_TESTASSERT_IN_LEN 0
3854
3855/* MC_CMD_TESTASSERT_OUT msgresponse */
3856#define MC_CMD_TESTASSERT_OUT_LEN 0
3857
3858
3859/***********************************/
3860/* MC_CMD_WORKAROUND
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003861 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't
3862 * understand the given workaround number - which should not be treated as a
3863 * hard error by client code. This op does not imply any semantics about each
3864 * workaround, that's between the driver and the mcfw on a per-workaround
3865 * basis. Locks required: None. Returns: 0, EINVAL .
Ben Hutchings5297a982010-02-03 09:28:14 +00003866 */
3867#define MC_CMD_WORKAROUND 0x4a
Ben Hutchings5297a982010-02-03 09:28:14 +00003868
Shradha Shah75122ec2015-05-20 11:08:23 +01003869#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3870
Ben Hutchings05a93202011-12-20 00:44:06 +00003871/* MC_CMD_WORKAROUND_IN msgrequest */
3872#define MC_CMD_WORKAROUND_IN_LEN 8
3873#define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003874/* enum: Bug 17230 work around. */
3875#define MC_CMD_WORKAROUND_BUG17230 0x1
3876/* enum: Bug 35388 work around (unsafe EVQ writes). */
3877#define MC_CMD_WORKAROUND_BUG35388 0x2
3878/* enum: Bug35017 workaround (A64 tables must be identity map) */
3879#define MC_CMD_WORKAROUND_BUG35017 0x3
Ben Hutchings05a93202011-12-20 00:44:06 +00003880#define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
3881
3882/* MC_CMD_WORKAROUND_OUT msgresponse */
3883#define MC_CMD_WORKAROUND_OUT_LEN 0
3884
3885
3886/***********************************/
3887/* MC_CMD_GET_PHY_MEDIA_INFO
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003888 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
3889 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG
3890 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the
3891 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1
3892 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
3893 * Anything else: currently undefined. Locks required: None. Return code: 0.
Ben Hutchings5297a982010-02-03 09:28:14 +00003894 */
3895#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
Ben Hutchings5297a982010-02-03 09:28:14 +00003896
Shradha Shah75122ec2015-05-20 11:08:23 +01003897#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3898
Ben Hutchings05a93202011-12-20 00:44:06 +00003899/* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
3900#define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
3901#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
3902
3903/* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
3904#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
Ben Hutchings576eda82012-09-19 02:46:37 +01003905#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
Ben Hutchings05a93202011-12-20 00:44:06 +00003906#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003907/* in bytes */
Ben Hutchings05a93202011-12-20 00:44:06 +00003908#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
3909#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
3910#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
3911#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
Ben Hutchings576eda82012-09-19 02:46:37 +01003912#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
Ben Hutchings05a93202011-12-20 00:44:06 +00003913
3914
3915/***********************************/
3916/* MC_CMD_NVRAM_TEST
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003917 * Test a particular NVRAM partition for valid contents (where "valid" depends
3918 * on the type of partition).
Ben Hutchings5297a982010-02-03 09:28:14 +00003919 */
3920#define MC_CMD_NVRAM_TEST 0x4c
Ben Hutchings5297a982010-02-03 09:28:14 +00003921
Shradha Shah75122ec2015-05-20 11:08:23 +01003922#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3923
Ben Hutchings05a93202011-12-20 00:44:06 +00003924/* MC_CMD_NVRAM_TEST_IN msgrequest */
3925#define MC_CMD_NVRAM_TEST_IN_LEN 4
3926#define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
3927/* Enum values, see field(s): */
3928/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3929
3930/* MC_CMD_NVRAM_TEST_OUT msgresponse */
3931#define MC_CMD_NVRAM_TEST_OUT_LEN 4
3932#define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003933/* enum: Passed. */
3934#define MC_CMD_NVRAM_TEST_PASS 0x0
3935/* enum: Failed. */
3936#define MC_CMD_NVRAM_TEST_FAIL 0x1
3937/* enum: Not supported. */
3938#define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
Ben Hutchings05a93202011-12-20 00:44:06 +00003939
3940
3941/***********************************/
3942/* MC_CMD_MRSFP_TWEAK
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003943 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.
3944 * I2C I/O expander bits are always read; if equaliser parameters are supplied,
3945 * they are configured first. Locks required: None. Return code: 0, EINVAL.
Ben Hutchings5297a982010-02-03 09:28:14 +00003946 */
3947#define MC_CMD_MRSFP_TWEAK 0x4d
Ben Hutchings5297a982010-02-03 09:28:14 +00003948
Ben Hutchings05a93202011-12-20 00:44:06 +00003949/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
3950#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003951/* 0-6 low->high de-emph. */
Ben Hutchings05a93202011-12-20 00:44:06 +00003952#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003953/* 0-8 low->high ref.V */
Ben Hutchings05a93202011-12-20 00:44:06 +00003954#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003955/* 0-8 0-8 low->high boost */
Ben Hutchings05a93202011-12-20 00:44:06 +00003956#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003957/* 0-8 low->high ref.V */
Ben Hutchings05a93202011-12-20 00:44:06 +00003958#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
Ben Hutchingsfbcfe8e2010-04-28 09:29:14 +00003959
Ben Hutchings05a93202011-12-20 00:44:06 +00003960/* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
3961#define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
3962
3963/* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
3964#define MC_CMD_MRSFP_TWEAK_OUT_LEN 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003965/* input bits */
Ben Hutchings05a93202011-12-20 00:44:06 +00003966#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003967/* output bits */
Ben Hutchings05a93202011-12-20 00:44:06 +00003968#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003969/* direction */
Ben Hutchings05a93202011-12-20 00:44:06 +00003970#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003971/* enum: Out. */
3972#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
3973/* enum: In. */
3974#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
Ben Hutchings05a93202011-12-20 00:44:06 +00003975
3976
3977/***********************************/
3978/* MC_CMD_SENSOR_SET_LIMS
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003979 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
3980 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out
3981 * of range.
Ben Hutchingsfbcfe8e2010-04-28 09:29:14 +00003982 */
3983#define MC_CMD_SENSOR_SET_LIMS 0x4e
Ben Hutchingsfbcfe8e2010-04-28 09:29:14 +00003984
Shradha Shah75122ec2015-05-20 11:08:23 +01003985#define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3986
Ben Hutchings05a93202011-12-20 00:44:06 +00003987/* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
3988#define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
3989#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
3990/* Enum values, see field(s): */
3991/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003992/* interpretation is is sensor-specific. */
Ben Hutchings05a93202011-12-20 00:44:06 +00003993#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003994/* interpretation is is sensor-specific. */
Ben Hutchings05a93202011-12-20 00:44:06 +00003995#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003996/* interpretation is is sensor-specific. */
Ben Hutchings05a93202011-12-20 00:44:06 +00003997#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01003998/* interpretation is is sensor-specific. */
Ben Hutchings05a93202011-12-20 00:44:06 +00003999#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
4000
4001/* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
4002#define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
4003
4004
4005/***********************************/
4006/* MC_CMD_GET_RESOURCE_LIMITS
4007 */
4008#define MC_CMD_GET_RESOURCE_LIMITS 0x4f
4009
4010/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
4011#define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
4012
4013/* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
4014#define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
4015#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
4016#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
4017#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
4018#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
4019
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004020
4021/***********************************/
4022/* MC_CMD_NVRAM_PARTITIONS
4023 * Reads the list of available virtual NVRAM partition types. Locks required:
4024 * none. Returns: 0, EINVAL (bad type).
4025 */
4026#define MC_CMD_NVRAM_PARTITIONS 0x51
4027
Shradha Shah75122ec2015-05-20 11:08:23 +01004028#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4029
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004030/* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */
4031#define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
4032
4033/* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */
4034#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
4035#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
4036#define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
4037/* total number of partitions */
4038#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
4039/* type ID code for each of NUM_PARTITIONS partitions */
4040#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
4041#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
4042#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
4043#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62
4044
4045
4046/***********************************/
4047/* MC_CMD_NVRAM_METADATA
4048 * Reads soft metadata for a virtual NVRAM partition type. Locks required:
4049 * none. Returns: 0, EINVAL (bad type).
4050 */
4051#define MC_CMD_NVRAM_METADATA 0x52
4052
Shradha Shah75122ec2015-05-20 11:08:23 +01004053#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4054
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004055/* MC_CMD_NVRAM_METADATA_IN msgrequest */
4056#define MC_CMD_NVRAM_METADATA_IN_LEN 4
4057/* Partition type ID code */
4058#define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
4059
4060/* MC_CMD_NVRAM_METADATA_OUT msgresponse */
4061#define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20
4062#define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
4063#define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
4064/* Partition type ID code */
4065#define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
4066#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
4067#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
4068#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
4069#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
4070#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
4071#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2
4072#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
4073/* Subtype ID code for content of this partition */
4074#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8
4075/* 1st component of W.X.Y.Z version number for content of this partition */
4076#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12
4077#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2
4078/* 2nd component of W.X.Y.Z version number for content of this partition */
4079#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14
4080#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2
4081/* 3rd component of W.X.Y.Z version number for content of this partition */
4082#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16
4083#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2
4084/* 4th component of W.X.Y.Z version number for content of this partition */
4085#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18
4086#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2
4087/* Zero-terminated string describing the content of this partition */
4088#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20
4089#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
4090#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
4091#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232
4092
4093
4094/***********************************/
4095/* MC_CMD_GET_MAC_ADDRESSES
4096 * Returns the base MAC, count and stride for the requestiong function
4097 */
4098#define MC_CMD_GET_MAC_ADDRESSES 0x55
4099
Shradha Shah75122ec2015-05-20 11:08:23 +01004100#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4101
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004102/* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */
4103#define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
4104
4105/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */
4106#define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16
4107/* Base MAC address */
4108#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
4109#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6
4110/* Padding */
4111#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6
4112#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2
4113/* Number of allocated MAC addresses */
4114#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8
4115/* Spacing of allocated MAC addresses */
4116#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12
4117
Ben Hutchings05a93202011-12-20 00:44:06 +00004118/* MC_CMD_RESOURCE_SPECIFIER enum */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004119/* enum: Any */
4120#define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
4121/* enum: None */
4122#define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe
4123
4124/* EVB_PORT_ID structuredef */
4125#define EVB_PORT_ID_LEN 4
4126#define EVB_PORT_ID_PORT_ID_OFST 0
4127/* enum: An invalid port handle. */
4128#define EVB_PORT_ID_NULL 0x0
4129/* enum: The port assigned to this function.. */
4130#define EVB_PORT_ID_ASSIGNED 0x1000000
4131/* enum: External network port 0 */
4132#define EVB_PORT_ID_MAC0 0x2000000
4133/* enum: External network port 1 */
4134#define EVB_PORT_ID_MAC1 0x2000001
4135/* enum: External network port 2 */
4136#define EVB_PORT_ID_MAC2 0x2000002
4137/* enum: External network port 3 */
4138#define EVB_PORT_ID_MAC3 0x2000003
4139#define EVB_PORT_ID_PORT_ID_LBN 0
4140#define EVB_PORT_ID_PORT_ID_WIDTH 32
4141
4142/* EVB_VLAN_TAG structuredef */
4143#define EVB_VLAN_TAG_LEN 2
4144/* The VLAN tag value */
4145#define EVB_VLAN_TAG_VLAN_ID_LBN 0
4146#define EVB_VLAN_TAG_VLAN_ID_WIDTH 12
4147#define EVB_VLAN_TAG_MODE_LBN 12
4148#define EVB_VLAN_TAG_MODE_WIDTH 4
4149/* enum: Insert the VLAN. */
4150#define EVB_VLAN_TAG_INSERT 0x0
4151/* enum: Replace the VLAN if already present. */
4152#define EVB_VLAN_TAG_REPLACE 0x1
4153
4154/* BUFTBL_ENTRY structuredef */
4155#define BUFTBL_ENTRY_LEN 12
4156/* the owner ID */
4157#define BUFTBL_ENTRY_OID_OFST 0
4158#define BUFTBL_ENTRY_OID_LEN 2
4159#define BUFTBL_ENTRY_OID_LBN 0
4160#define BUFTBL_ENTRY_OID_WIDTH 16
4161/* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */
4162#define BUFTBL_ENTRY_PGSZ_OFST 2
4163#define BUFTBL_ENTRY_PGSZ_LEN 2
4164#define BUFTBL_ENTRY_PGSZ_LBN 16
4165#define BUFTBL_ENTRY_PGSZ_WIDTH 16
4166/* the raw 64-bit address field from the SMC, not adjusted for page size */
4167#define BUFTBL_ENTRY_RAWADDR_OFST 4
4168#define BUFTBL_ENTRY_RAWADDR_LEN 8
4169#define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
4170#define BUFTBL_ENTRY_RAWADDR_HI_OFST 8
4171#define BUFTBL_ENTRY_RAWADDR_LBN 32
4172#define BUFTBL_ENTRY_RAWADDR_WIDTH 64
4173
4174/* NVRAM_PARTITION_TYPE structuredef */
4175#define NVRAM_PARTITION_TYPE_LEN 2
4176#define NVRAM_PARTITION_TYPE_ID_OFST 0
4177#define NVRAM_PARTITION_TYPE_ID_LEN 2
4178/* enum: Primary MC firmware partition */
4179#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
4180/* enum: Secondary MC firmware partition */
4181#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
4182/* enum: Expansion ROM partition */
4183#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
4184/* enum: Static configuration TLV partition */
4185#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
4186/* enum: Dynamic configuration TLV partition */
4187#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
4188/* enum: Expansion ROM configuration data for port 0 */
4189#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
4190/* enum: Expansion ROM configuration data for port 1 */
4191#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
4192/* enum: Expansion ROM configuration data for port 2 */
4193#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
4194/* enum: Expansion ROM configuration data for port 3 */
4195#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
4196/* enum: Non-volatile log output partition */
4197#define NVRAM_PARTITION_TYPE_LOG 0x700
4198/* enum: Device state dump output partition */
4199#define NVRAM_PARTITION_TYPE_DUMP 0x800
4200/* enum: Application license key storage partition */
4201#define NVRAM_PARTITION_TYPE_LICENSE 0x900
Matthew Slatterybedca862013-08-23 17:32:55 +01004202/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
4203#define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
4204/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
4205#define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004206/* enum: Start of reserved value range (firmware may use for any purpose) */
4207#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
4208/* enum: End of reserved value range (firmware may use for any purpose) */
4209#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
4210/* enum: Recovery partition map (provided if real map is missing or corrupt) */
4211#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
4212/* enum: Partition map (real map as stored in flash) */
4213#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
4214#define NVRAM_PARTITION_TYPE_ID_LBN 0
4215#define NVRAM_PARTITION_TYPE_ID_WIDTH 16
4216
Ben Hutchings512bb062013-12-04 19:48:07 +00004217/* LICENSED_APP_ID structuredef */
4218#define LICENSED_APP_ID_LEN 4
4219#define LICENSED_APP_ID_ID_OFST 0
4220/* enum: OpenOnload */
4221#define LICENSED_APP_ID_ONLOAD 0x1
4222/* enum: PTP timestamping */
4223#define LICENSED_APP_ID_PTP 0x2
4224/* enum: SolarCapture Pro */
4225#define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
4226#define LICENSED_APP_ID_ID_LBN 0
4227#define LICENSED_APP_ID_ID_WIDTH 32
4228
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004229
4230/***********************************/
Edward Cree267d9d72015-05-06 00:59:18 +01004231/* MC_CMD_GET_WORKAROUNDS
4232 * Read the list of all implemented and all currently enabled workarounds. The
4233 * enums here must correspond with those in MC_CMD_WORKAROUND.
4234 */
4235#define MC_CMD_GET_WORKAROUNDS 0x59
4236
4237/* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */
4238#define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8
4239/* Each workaround is represented by a single bit according to the enums below.
4240 */
4241#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
4242#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
4243/* enum: Bug 17230 work around. */
4244#define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
4245/* enum: Bug 35388 work around (unsafe EVQ writes). */
4246#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
4247/* enum: Bug35017 workaround (A64 tables must be identity map) */
4248#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
4249
4250
4251/***********************************/
Edward Cree4392dc62015-05-20 11:12:13 +01004252/* MC_CMD_LINK_STATE_MODE
4253 * Read/set link state mode of a VF
4254 */
4255#define MC_CMD_LINK_STATE_MODE 0x5c
4256
4257#define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4258
4259/* MC_CMD_LINK_STATE_MODE_IN msgrequest */
4260#define MC_CMD_LINK_STATE_MODE_IN_LEN 8
4261/* The target function to have its link state mode read or set, must be a VF
4262 * e.g. VF 1,3 = 0x00030001
4263 */
4264#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
4265#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
4266#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16
4267#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16
4268#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16
4269/* New link state mode to be set */
4270#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
4271#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
4272#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
4273#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
4274/* enum: Use this value to just read the existing setting without modifying it.
4275 */
4276#define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
4277
4278/* MC_CMD_LINK_STATE_MODE_OUT msgresponse */
4279#define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
4280#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
4281
4282
4283/***********************************/
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004284/* MC_CMD_READ_REGS
4285 * Get a dump of the MCPU registers
4286 */
4287#define MC_CMD_READ_REGS 0x50
4288
Shradha Shah75122ec2015-05-20 11:08:23 +01004289#define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4290
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004291/* MC_CMD_READ_REGS_IN msgrequest */
4292#define MC_CMD_READ_REGS_IN_LEN 0
4293
4294/* MC_CMD_READ_REGS_OUT msgresponse */
4295#define MC_CMD_READ_REGS_OUT_LEN 308
4296/* Whether the corresponding register entry contains a valid value */
4297#define MC_CMD_READ_REGS_OUT_MASK_OFST 0
4298#define MC_CMD_READ_REGS_OUT_MASK_LEN 16
4299/* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
4300 * fir, fp)
4301 */
4302#define MC_CMD_READ_REGS_OUT_REGS_OFST 16
4303#define MC_CMD_READ_REGS_OUT_REGS_LEN 4
4304#define MC_CMD_READ_REGS_OUT_REGS_NUM 73
4305
4306
4307/***********************************/
4308/* MC_CMD_INIT_EVQ
4309 * Set up an event queue according to the supplied parameters. The IN arguments
4310 * end with an address for each 4k of host memory required to back the EVQ.
4311 */
4312#define MC_CMD_INIT_EVQ 0x80
4313
Shradha Shah75122ec2015-05-20 11:08:23 +01004314#define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4315
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004316/* MC_CMD_INIT_EVQ_IN msgrequest */
4317#define MC_CMD_INIT_EVQ_IN_LENMIN 44
4318#define MC_CMD_INIT_EVQ_IN_LENMAX 548
4319#define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
4320/* Size, in entries */
4321#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
4322/* Desired instance. Must be set to a specific instance, which is a function
4323 * local queue index.
4324 */
4325#define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
4326/* The initial timer value. The load value is ignored if the timer mode is DIS.
4327 */
4328#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
4329/* The reload value is ignored in one-shot modes */
4330#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
4331/* tbd */
4332#define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
4333#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
4334#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
4335#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
4336#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
4337#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2
4338#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
4339#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3
4340#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
4341#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
4342#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
4343#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5
4344#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
4345#define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
4346/* enum: Disabled */
4347#define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
4348/* enum: Immediate */
4349#define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
4350/* enum: Triggered */
4351#define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
4352/* enum: Hold-off */
4353#define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
4354/* Target EVQ for wakeups if in wakeup mode. */
4355#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
4356/* Target interrupt if in interrupting mode (note union with target EVQ). Use
4357 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
4358 * purposes.
4359 */
4360#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
4361/* Event Counter Mode. */
4362#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28
4363/* enum: Disabled */
4364#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
4365/* enum: Disabled */
4366#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
4367/* enum: Disabled */
4368#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
4369/* enum: Disabled */
4370#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
4371/* Event queue packet count threshold. */
4372#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32
4373/* 64-bit address of 4k of 4k-aligned host memory buffer */
4374#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
4375#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
4376#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
4377#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
4378#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
4379#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
4380
4381/* MC_CMD_INIT_EVQ_OUT msgresponse */
4382#define MC_CMD_INIT_EVQ_OUT_LEN 4
4383/* Only valid if INTRFLAG was true */
4384#define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
4385
4386/* QUEUE_CRC_MODE structuredef */
4387#define QUEUE_CRC_MODE_LEN 1
4388#define QUEUE_CRC_MODE_MODE_LBN 0
4389#define QUEUE_CRC_MODE_MODE_WIDTH 4
4390/* enum: No CRC. */
4391#define QUEUE_CRC_MODE_NONE 0x0
4392/* enum: CRC Fiber channel over ethernet. */
4393#define QUEUE_CRC_MODE_FCOE 0x1
4394/* enum: CRC (digest) iSCSI header only. */
4395#define QUEUE_CRC_MODE_ISCSI_HDR 0x2
4396/* enum: CRC (digest) iSCSI header and payload. */
4397#define QUEUE_CRC_MODE_ISCSI 0x3
4398/* enum: CRC Fiber channel over IP over ethernet. */
4399#define QUEUE_CRC_MODE_FCOIPOE 0x4
4400/* enum: CRC MPA. */
4401#define QUEUE_CRC_MODE_MPA 0x5
4402#define QUEUE_CRC_MODE_SPARE_LBN 4
4403#define QUEUE_CRC_MODE_SPARE_WIDTH 4
4404
4405
4406/***********************************/
4407/* MC_CMD_INIT_RXQ
4408 * set up a receive queue according to the supplied parameters. The IN
4409 * arguments end with an address for each 4k of host memory required to back
4410 * the RXQ.
4411 */
4412#define MC_CMD_INIT_RXQ 0x81
4413
Shradha Shah75122ec2015-05-20 11:08:23 +01004414#define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4415
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004416/* MC_CMD_INIT_RXQ_IN msgrequest */
4417#define MC_CMD_INIT_RXQ_IN_LENMIN 36
4418#define MC_CMD_INIT_RXQ_IN_LENMAX 252
4419#define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
4420/* Size, in entries */
4421#define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
4422/* The EVQ to send events to. This is an index originally specified to INIT_EVQ
4423 */
4424#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
4425/* The value to put in the event data. Check hardware spec. for valid range. */
4426#define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
4427/* Desired instance. Must be set to a specific instance, which is a function
4428 * local queue index.
4429 */
4430#define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
4431/* There will be more flags here. */
4432#define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
4433#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
4434#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
4435#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
4436#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
4437#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2
4438#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
4439#define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
4440#define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
4441#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7
4442#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
4443#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8
4444#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
Ben Hutchings512bb062013-12-04 19:48:07 +00004445#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9
4446#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004447/* Owner ID to use if in buffer mode (zero if physical) */
4448#define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
4449/* The port ID associated with the v-adaptor which should contain this DMAQ. */
4450#define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24
4451/* 64-bit address of 4k of 4k-aligned host memory buffer */
4452#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
4453#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
4454#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
4455#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
4456#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
4457#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
4458
4459/* MC_CMD_INIT_RXQ_OUT msgresponse */
4460#define MC_CMD_INIT_RXQ_OUT_LEN 0
4461
4462
4463/***********************************/
4464/* MC_CMD_INIT_TXQ
4465 */
4466#define MC_CMD_INIT_TXQ 0x82
4467
Shradha Shah75122ec2015-05-20 11:08:23 +01004468#define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4469
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004470/* MC_CMD_INIT_TXQ_IN msgrequest */
4471#define MC_CMD_INIT_TXQ_IN_LENMIN 36
4472#define MC_CMD_INIT_TXQ_IN_LENMAX 252
4473#define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
4474/* Size, in entries */
4475#define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
4476/* The EVQ to send events to. This is an index originally specified to
4477 * INIT_EVQ.
4478 */
4479#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
4480/* The value to put in the event data. Check hardware spec. for valid range. */
4481#define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
4482/* Desired instance. Must be set to a specific instance, which is a function
4483 * local queue index.
4484 */
4485#define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
4486/* There will be more flags here. */
4487#define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
4488#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
4489#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
4490#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
4491#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
4492#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
4493#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
4494#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
4495#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
4496#define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
4497#define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
4498#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8
4499#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
4500#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9
4501#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
4502/* Owner ID to use if in buffer mode (zero if physical) */
4503#define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
4504/* The port ID associated with the v-adaptor which should contain this DMAQ. */
4505#define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24
4506/* 64-bit address of 4k of 4k-aligned host memory buffer */
4507#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
4508#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
4509#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
4510#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
4511#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
4512#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
4513
4514/* MC_CMD_INIT_TXQ_OUT msgresponse */
4515#define MC_CMD_INIT_TXQ_OUT_LEN 0
4516
4517
4518/***********************************/
4519/* MC_CMD_FINI_EVQ
4520 * Teardown an EVQ.
4521 *
4522 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first
4523 * or the operation will fail with EBUSY
4524 */
4525#define MC_CMD_FINI_EVQ 0x83
4526
Shradha Shah75122ec2015-05-20 11:08:23 +01004527#define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4528
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004529/* MC_CMD_FINI_EVQ_IN msgrequest */
4530#define MC_CMD_FINI_EVQ_IN_LEN 4
4531/* Instance of EVQ to destroy. Should be the same instance as that previously
4532 * passed to INIT_EVQ
4533 */
4534#define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
4535
4536/* MC_CMD_FINI_EVQ_OUT msgresponse */
4537#define MC_CMD_FINI_EVQ_OUT_LEN 0
4538
4539
4540/***********************************/
4541/* MC_CMD_FINI_RXQ
4542 * Teardown a RXQ.
4543 */
4544#define MC_CMD_FINI_RXQ 0x84
4545
Shradha Shah75122ec2015-05-20 11:08:23 +01004546#define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4547
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004548/* MC_CMD_FINI_RXQ_IN msgrequest */
4549#define MC_CMD_FINI_RXQ_IN_LEN 4
4550/* Instance of RXQ to destroy */
4551#define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
4552
4553/* MC_CMD_FINI_RXQ_OUT msgresponse */
4554#define MC_CMD_FINI_RXQ_OUT_LEN 0
4555
4556
4557/***********************************/
4558/* MC_CMD_FINI_TXQ
4559 * Teardown a TXQ.
4560 */
4561#define MC_CMD_FINI_TXQ 0x85
4562
Shradha Shah75122ec2015-05-20 11:08:23 +01004563#define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4564
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004565/* MC_CMD_FINI_TXQ_IN msgrequest */
4566#define MC_CMD_FINI_TXQ_IN_LEN 4
4567/* Instance of TXQ to destroy */
4568#define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
4569
4570/* MC_CMD_FINI_TXQ_OUT msgresponse */
4571#define MC_CMD_FINI_TXQ_OUT_LEN 0
4572
4573
4574/***********************************/
4575/* MC_CMD_DRIVER_EVENT
4576 * Generate an event on an EVQ belonging to the function issuing the command.
4577 */
4578#define MC_CMD_DRIVER_EVENT 0x86
4579
Shradha Shah75122ec2015-05-20 11:08:23 +01004580#define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4581
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004582/* MC_CMD_DRIVER_EVENT_IN msgrequest */
4583#define MC_CMD_DRIVER_EVENT_IN_LEN 12
4584/* Handle of target EVQ */
4585#define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
4586/* Bits 0 - 63 of event */
4587#define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
4588#define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
4589#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
4590#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
4591
4592/* MC_CMD_DRIVER_EVENT_OUT msgresponse */
4593#define MC_CMD_DRIVER_EVENT_OUT_LEN 0
4594
4595
4596/***********************************/
4597/* MC_CMD_PROXY_CMD
4598 * Execute an arbitrary MCDI command on behalf of a different function, subject
4599 * to security restrictions. The command to be proxied follows immediately
4600 * afterward in the host buffer (or on the UART). This command supercedes
4601 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
4602 */
4603#define MC_CMD_PROXY_CMD 0x5b
4604
Shradha Shah75122ec2015-05-20 11:08:23 +01004605#define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4606
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004607/* MC_CMD_PROXY_CMD_IN msgrequest */
4608#define MC_CMD_PROXY_CMD_IN_LEN 4
4609/* The handle of the target function. */
4610#define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
4611#define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
4612#define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16
4613#define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16
4614#define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16
4615#define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
4616
Ben Hutchings512bb062013-12-04 19:48:07 +00004617/* MC_CMD_PROXY_CMD_OUT msgresponse */
4618#define MC_CMD_PROXY_CMD_OUT_LEN 0
4619
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004620
4621/***********************************/
4622/* MC_CMD_ALLOC_BUFTBL_CHUNK
4623 * Allocate a set of buffer table entries using the specified owner ID. This
4624 * operation allocates the required buffer table entries (and fails if it
4625 * cannot do so). The buffer table entries will initially be zeroed.
4626 */
4627#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
4628
Shradha Shah75122ec2015-05-20 11:08:23 +01004629#define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
4630
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004631/* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */
4632#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8
4633/* Owner ID to use */
4634#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
4635/* Size of buffer table pages to use, in bytes (note that only a few values are
4636 * legal on any specific hardware).
4637 */
4638#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
4639
4640/* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */
4641#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12
4642#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
4643#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
4644/* Buffer table IDs for use in DMA descriptors. */
4645#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8
4646
4647
4648/***********************************/
4649/* MC_CMD_PROGRAM_BUFTBL_ENTRIES
4650 * Reprogram a set of buffer table entries in the specified chunk.
4651 */
4652#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
4653
Shradha Shah75122ec2015-05-20 11:08:23 +01004654#define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
4655
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004656/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */
4657#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20
Ben Hutchings512bb062013-12-04 19:48:07 +00004658#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004659#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
4660#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
4661/* ID */
4662#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
4663/* Num entries */
4664#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8
4665/* Buffer table entry address */
4666#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
4667#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
4668#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
4669#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
4670#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
Ben Hutchings512bb062013-12-04 19:48:07 +00004671#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004672
4673/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */
4674#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
4675
4676
4677/***********************************/
4678/* MC_CMD_FREE_BUFTBL_CHUNK
4679 */
4680#define MC_CMD_FREE_BUFTBL_CHUNK 0x89
4681
Shradha Shah75122ec2015-05-20 11:08:23 +01004682#define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
4683
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004684/* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */
4685#define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
4686#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
4687
4688/* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */
4689#define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
4690
4691
4692/***********************************/
4693/* MC_CMD_FILTER_OP
4694 * Multiplexed MCDI call for filter operations
4695 */
4696#define MC_CMD_FILTER_OP 0x8a
4697
Shradha Shah75122ec2015-05-20 11:08:23 +01004698#define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4699
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004700/* MC_CMD_FILTER_OP_IN msgrequest */
4701#define MC_CMD_FILTER_OP_IN_LEN 108
4702/* identifies the type of operation requested */
4703#define MC_CMD_FILTER_OP_IN_OP_OFST 0
4704/* enum: single-recipient filter insert */
4705#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
4706/* enum: single-recipient filter remove */
4707#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
4708/* enum: multi-recipient filter subscribe */
4709#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
4710/* enum: multi-recipient filter unsubscribe */
4711#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
4712/* enum: replace one recipient with another (warning - the filter handle may
4713 * change)
4714 */
4715#define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
4716/* filter handle (for remove / unsubscribe operations) */
4717#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
4718#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
4719#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
4720#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
4721/* The port ID associated with the v-adaptor which should contain this filter.
4722 */
4723#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
4724/* fields to include in match criteria */
4725#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16
4726#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
4727#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
4728#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
4729#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
4730#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
4731#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
4732#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
4733#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
4734#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
4735#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
4736#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
4737#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
4738#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
4739#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
4740#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
4741#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
4742#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
4743#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
4744#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
4745#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
4746#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
4747#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
4748#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
4749#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
4750#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
4751#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
4752#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
4753#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
4754/* receive destination */
4755#define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20
4756/* enum: drop packets */
4757#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
4758/* enum: receive to host */
4759#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
4760/* enum: receive to MC */
4761#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
4762/* enum: loop back to port 0 TX MAC */
4763#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
4764/* enum: loop back to port 1 TX MAC */
4765#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
4766/* receive queue handle (for multiple queue modes, this is the base queue) */
4767#define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24
4768/* receive mode */
4769#define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28
4770/* enum: receive to just the specified queue */
4771#define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
4772/* enum: receive to multiple queues using RSS context */
4773#define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
4774/* enum: receive to multiple queues using .1p mapping */
4775#define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
4776/* enum: install a filter entry that will never match; for test purposes only
4777 */
4778#define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
4779/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
4780 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
4781 * MC_CMD_DOT1P_MAPPING_ALLOC. Note that these handles should be considered
4782 * opaque to the host, although a value of 0xFFFFFFFF is guaranteed never to be
4783 * a valid handle.
4784 */
4785#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32
4786/* transmit domain (reserved; set to 0) */
4787#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36
4788/* transmit destination (either set the MAC and/or PM bits for explicit
4789 * control, or set this field to TX_DEST_DEFAULT for sensible default
4790 * behaviour)
4791 */
4792#define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40
4793/* enum: request default behaviour (based on filter type) */
4794#define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
4795#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
4796#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
4797#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
4798#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
4799/* source MAC address to match (as bytes in network order) */
4800#define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44
4801#define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
4802/* source port to match (as bytes in network order) */
4803#define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50
4804#define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
4805/* destination MAC address to match (as bytes in network order) */
4806#define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52
4807#define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
4808/* destination port to match (as bytes in network order) */
4809#define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58
4810#define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
4811/* Ethernet type to match (as bytes in network order) */
4812#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60
4813#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
4814/* Inner VLAN tag to match (as bytes in network order) */
4815#define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62
4816#define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
4817/* Outer VLAN tag to match (as bytes in network order) */
4818#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64
4819#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
4820/* IP protocol to match (in low byte; set high byte to 0) */
4821#define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66
4822#define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
4823/* Firmware defined register 0 to match (reserved; set to 0) */
4824#define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68
4825/* Firmware defined register 1 to match (reserved; set to 0) */
4826#define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72
4827/* source IP address to match (as bytes in network order; set last 12 bytes to
4828 * 0 for IPv4 address)
4829 */
4830#define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76
4831#define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
4832/* destination IP address to match (as bytes in network order; set last 12
4833 * bytes to 0 for IPv4 address)
4834 */
4835#define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92
4836#define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
4837
4838/* MC_CMD_FILTER_OP_OUT msgresponse */
4839#define MC_CMD_FILTER_OP_OUT_LEN 12
4840/* identifies the type of operation requested */
4841#define MC_CMD_FILTER_OP_OUT_OP_OFST 0
4842/* Enum values, see field(s): */
4843/* MC_CMD_FILTER_OP_IN/OP */
4844/* Returned filter handle (for insert / subscribe operations). Note that these
4845 * handles should be considered opaque to the host, although a value of
4846 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
4847 */
4848#define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
4849#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
4850#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
4851#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
4852
4853
4854/***********************************/
4855/* MC_CMD_GET_PARSER_DISP_INFO
4856 * Get information related to the parser-dispatcher subsystem
4857 */
4858#define MC_CMD_GET_PARSER_DISP_INFO 0xe4
4859
Shradha Shah75122ec2015-05-20 11:08:23 +01004860#define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4861
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004862/* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */
4863#define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
4864/* identifies the type of operation requested */
4865#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
4866/* enum: read the list of supported RX filter matches */
4867#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
4868
4869/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
4870#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
4871#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252
4872#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
4873/* identifies the type of operation requested */
4874#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
4875/* Enum values, see field(s): */
4876/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
4877/* number of supported match types */
4878#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
4879/* array of supported match types (valid MATCH_FIELDS values for
4880 * MC_CMD_FILTER_OP) sorted in decreasing priority order
4881 */
4882#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8
4883#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
4884#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
4885#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61
4886
4887
4888/***********************************/
4889/* MC_CMD_PARSER_DISP_RW
4890 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging
4891 */
4892#define MC_CMD_PARSER_DISP_RW 0xe5
4893
Shradha Shah75122ec2015-05-20 11:08:23 +01004894#define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4895
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004896/* MC_CMD_PARSER_DISP_RW_IN msgrequest */
4897#define MC_CMD_PARSER_DISP_RW_IN_LEN 32
4898/* identifies the target of the operation */
4899#define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0
4900/* enum: RX dispatcher CPU */
4901#define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
4902/* enum: TX dispatcher CPU */
4903#define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
4904/* enum: Lookup engine */
4905#define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
4906/* identifies the type of operation requested */
4907#define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4
4908/* enum: read a word of DICPU DMEM or a LUE entry */
4909#define MC_CMD_PARSER_DISP_RW_IN_READ 0x0
4910/* enum: write a word of DICPU DMEM or a LUE entry */
4911#define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
4912/* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */
4913#define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
4914/* data memory address or LUE index */
4915#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8
4916/* value to write (for DMEM writes) */
4917#define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12
4918/* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */
4919#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12
4920/* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */
4921#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16
4922/* value to write (for LUE writes) */
4923#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12
4924#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20
4925
4926/* MC_CMD_PARSER_DISP_RW_OUT msgresponse */
4927#define MC_CMD_PARSER_DISP_RW_OUT_LEN 52
4928/* value read (for DMEM reads) */
4929#define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0
4930/* value read (for LUE reads) */
4931#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0
4932#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20
4933/* up to 8 32-bit words of additional soft state from the LUE manager (the
4934 * exact content is firmware-dependent and intended only for debug use)
4935 */
4936#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20
4937#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32
4938
4939
4940/***********************************/
4941/* MC_CMD_GET_PF_COUNT
4942 * Get number of PFs on the device.
4943 */
4944#define MC_CMD_GET_PF_COUNT 0xb6
4945
Shradha Shah75122ec2015-05-20 11:08:23 +01004946#define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4947
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004948/* MC_CMD_GET_PF_COUNT_IN msgrequest */
4949#define MC_CMD_GET_PF_COUNT_IN_LEN 0
4950
4951/* MC_CMD_GET_PF_COUNT_OUT msgresponse */
4952#define MC_CMD_GET_PF_COUNT_OUT_LEN 1
4953/* Identifies the number of PFs on the device. */
4954#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
4955#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1
4956
4957
4958/***********************************/
4959/* MC_CMD_SET_PF_COUNT
4960 * Set number of PFs on the device.
4961 */
4962#define MC_CMD_SET_PF_COUNT 0xb7
4963
4964/* MC_CMD_SET_PF_COUNT_IN msgrequest */
4965#define MC_CMD_SET_PF_COUNT_IN_LEN 4
4966/* New number of PFs on the device. */
4967#define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
4968
4969/* MC_CMD_SET_PF_COUNT_OUT msgresponse */
4970#define MC_CMD_SET_PF_COUNT_OUT_LEN 0
4971
4972
4973/***********************************/
4974/* MC_CMD_GET_PORT_ASSIGNMENT
4975 * Get port assignment for current PCI function.
4976 */
4977#define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
4978
Shradha Shah75122ec2015-05-20 11:08:23 +01004979#define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4980
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004981/* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
4982#define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
4983
4984/* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
4985#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
4986/* Identifies the port assignment for this function. */
4987#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
4988
4989
4990/***********************************/
4991/* MC_CMD_SET_PORT_ASSIGNMENT
4992 * Set port assignment for current PCI function.
4993 */
4994#define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
4995
Shradha Shah75122ec2015-05-20 11:08:23 +01004996#define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
4997
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01004998/* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */
4999#define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
5000/* Identifies the port assignment for this function. */
5001#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
5002
5003/* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */
5004#define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
5005
5006
5007/***********************************/
5008/* MC_CMD_ALLOC_VIS
5009 * Allocate VIs for current PCI function.
5010 */
5011#define MC_CMD_ALLOC_VIS 0x8b
5012
Shradha Shah75122ec2015-05-20 11:08:23 +01005013#define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5014
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005015/* MC_CMD_ALLOC_VIS_IN msgrequest */
5016#define MC_CMD_ALLOC_VIS_IN_LEN 8
5017/* The minimum number of VIs that is acceptable */
5018#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
5019/* The maximum number of VIs that would be useful */
5020#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
5021
5022/* MC_CMD_ALLOC_VIS_OUT msgresponse */
5023#define MC_CMD_ALLOC_VIS_OUT_LEN 8
5024/* The number of VIs allocated on this function */
5025#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
5026/* The base absolute VI number allocated to this function. Required to
5027 * correctly interpret wakeup events.
5028 */
5029#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
5030
5031
5032/***********************************/
5033/* MC_CMD_FREE_VIS
5034 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,
5035 * but not freed.
5036 */
5037#define MC_CMD_FREE_VIS 0x8c
5038
Shradha Shah75122ec2015-05-20 11:08:23 +01005039#define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5040
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005041/* MC_CMD_FREE_VIS_IN msgrequest */
5042#define MC_CMD_FREE_VIS_IN_LEN 0
5043
5044/* MC_CMD_FREE_VIS_OUT msgresponse */
5045#define MC_CMD_FREE_VIS_OUT_LEN 0
5046
5047
5048/***********************************/
5049/* MC_CMD_GET_SRIOV_CFG
5050 * Get SRIOV config for this PF.
5051 */
5052#define MC_CMD_GET_SRIOV_CFG 0xba
5053
Shradha Shah75122ec2015-05-20 11:08:23 +01005054#define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5055
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005056/* MC_CMD_GET_SRIOV_CFG_IN msgrequest */
5057#define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
5058
5059/* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */
5060#define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20
5061/* Number of VFs currently enabled. */
5062#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
5063/* Max number of VFs before sriov stride and offset may need to be changed. */
5064#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
5065#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
5066#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
5067#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
5068/* RID offset of first VF from PF. */
5069#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12
5070/* RID offset of each subsequent VF from the previous. */
5071#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16
5072
5073
5074/***********************************/
5075/* MC_CMD_SET_SRIOV_CFG
5076 * Set SRIOV config for this PF.
5077 */
5078#define MC_CMD_SET_SRIOV_CFG 0xbb
5079
Shradha Shah75122ec2015-05-20 11:08:23 +01005080#define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5081
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005082/* MC_CMD_SET_SRIOV_CFG_IN msgrequest */
5083#define MC_CMD_SET_SRIOV_CFG_IN_LEN 20
5084/* Number of VFs currently enabled. */
5085#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
5086/* Max number of VFs before sriov stride and offset may need to be changed. */
5087#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
5088#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8
5089#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
5090#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
5091/* RID offset of first VF from PF, or 0 for no change, or
5092 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.
5093 */
5094#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12
5095/* RID offset of each subsequent VF from the previous, 0 for no change, or
5096 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.
5097 */
5098#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16
5099
5100/* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */
5101#define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
5102
5103
5104/***********************************/
5105/* MC_CMD_GET_VI_ALLOC_INFO
5106 * Get information about number of VI's and base VI number allocated to this
5107 * function.
5108 */
5109#define MC_CMD_GET_VI_ALLOC_INFO 0x8d
5110
Shradha Shah75122ec2015-05-20 11:08:23 +01005111#define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5112
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005113/* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */
5114#define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
5115
5116/* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */
5117#define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 8
5118/* The number of VIs allocated on this function */
5119#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
5120/* The base absolute VI number allocated to this function. Required to
5121 * correctly interpret wakeup events.
5122 */
5123#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
5124
5125
5126/***********************************/
5127/* MC_CMD_DUMP_VI_STATE
5128 * For CmdClient use. Dump pertinent information on a specific absolute VI.
5129 */
5130#define MC_CMD_DUMP_VI_STATE 0x8e
5131
Shradha Shah75122ec2015-05-20 11:08:23 +01005132#define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5133
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005134/* MC_CMD_DUMP_VI_STATE_IN msgrequest */
5135#define MC_CMD_DUMP_VI_STATE_IN_LEN 4
5136/* The VI number to query. */
5137#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
5138
5139/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */
5140#define MC_CMD_DUMP_VI_STATE_OUT_LEN 96
5141/* The PF part of the function owning this VI. */
5142#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
5143#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2
5144/* The VF part of the function owning this VI. */
5145#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2
5146#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2
5147/* Base of VIs allocated to this function. */
5148#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
5149#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2
5150/* Count of VIs allocated to the owner function. */
5151#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6
5152#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2
5153/* Base interrupt vector allocated to this function. */
5154#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8
5155#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2
5156/* Number of interrupt vectors allocated to this function. */
5157#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10
5158#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2
5159/* Raw evq ptr table data. */
5160#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12
5161#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8
5162#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12
5163#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16
5164/* Raw evq timer table data. */
5165#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20
5166#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8
5167#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20
5168#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24
5169/* Combined metadata field. */
5170#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
5171#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
5172#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16
5173#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16
5174#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8
5175#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24
5176#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8
5177/* TXDPCPU raw table data for queue. */
5178#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32
5179#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8
5180#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32
5181#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36
5182/* TXDPCPU raw table data for queue. */
5183#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40
5184#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8
5185#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40
5186#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44
5187/* TXDPCPU raw table data for queue. */
5188#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48
5189#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8
5190#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48
5191#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52
5192/* Combined metadata field. */
5193#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56
5194#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
5195#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
5196#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
5197#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
5198#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
5199#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16
5200#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8
5201#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24
5202#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8
5203#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32
5204#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8
5205#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40
5206#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24
5207/* RXDPCPU raw table data for queue. */
5208#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64
5209#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8
5210#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64
5211#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68
5212/* RXDPCPU raw table data for queue. */
5213#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72
5214#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8
5215#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72
5216#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76
5217/* Reserved, currently 0. */
5218#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80
5219#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8
5220#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80
5221#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84
5222/* Combined metadata field. */
5223#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88
5224#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
5225#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
5226#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
5227#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
5228#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
5229#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16
5230#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8
5231#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24
5232#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8
5233#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
5234#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
5235
5236
5237/***********************************/
5238/* MC_CMD_ALLOC_PIOBUF
5239 * Allocate a push I/O buffer for later use with a tx queue.
5240 */
5241#define MC_CMD_ALLOC_PIOBUF 0x8f
5242
Shradha Shah75122ec2015-05-20 11:08:23 +01005243#define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
5244
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005245/* MC_CMD_ALLOC_PIOBUF_IN msgrequest */
5246#define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
5247
5248/* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */
5249#define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
5250/* Handle for allocated push I/O buffer. */
5251#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
5252
5253
5254/***********************************/
5255/* MC_CMD_FREE_PIOBUF
5256 * Free a push I/O buffer.
5257 */
5258#define MC_CMD_FREE_PIOBUF 0x90
5259
Shradha Shah75122ec2015-05-20 11:08:23 +01005260#define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
5261
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005262/* MC_CMD_FREE_PIOBUF_IN msgrequest */
5263#define MC_CMD_FREE_PIOBUF_IN_LEN 4
5264/* Handle for allocated push I/O buffer. */
5265#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
5266
5267/* MC_CMD_FREE_PIOBUF_OUT msgresponse */
5268#define MC_CMD_FREE_PIOBUF_OUT_LEN 0
5269
5270
5271/***********************************/
5272/* MC_CMD_GET_VI_TLP_PROCESSING
5273 * Get TLP steering and ordering information for a VI.
5274 */
5275#define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
5276
Shradha Shah75122ec2015-05-20 11:08:23 +01005277#define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5278
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005279/* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */
5280#define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
5281/* VI number to get information for. */
5282#define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
5283
5284/* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */
5285#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4
5286/* Transaction processing steering hint 1 for use with the Rx Queue. */
5287#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0
5288#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1
5289/* Transaction processing steering hint 2 for use with the Ev Queue. */
5290#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1
5291#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1
5292/* Use Relaxed ordering model for TLPs on this VI. */
5293#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16
5294#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1
5295/* Use ID based ordering for TLPs on this VI. */
5296#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17
5297#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1
5298/* Set no snoop bit for TLPs on this VI. */
5299#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18
5300#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1
5301/* Enable TPH for TLPs on this VI. */
5302#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19
5303#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1
5304#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
5305
5306
5307/***********************************/
5308/* MC_CMD_SET_VI_TLP_PROCESSING
5309 * Set TLP steering and ordering information for a VI.
5310 */
5311#define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
5312
Shradha Shah75122ec2015-05-20 11:08:23 +01005313#define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5314
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005315/* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */
5316#define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8
5317/* VI number to set information for. */
5318#define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
5319/* Transaction processing steering hint 1 for use with the Rx Queue. */
5320#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4
5321#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1
5322/* Transaction processing steering hint 2 for use with the Ev Queue. */
5323#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5
5324#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1
5325/* Use Relaxed ordering model for TLPs on this VI. */
5326#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48
5327#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1
5328/* Use ID based ordering for TLPs on this VI. */
5329#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49
5330#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1
5331/* Set the no snoop bit for TLPs on this VI. */
5332#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50
5333#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1
5334/* Enable TPH for TLPs on this VI. */
5335#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51
5336#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1
5337#define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
5338
5339/* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */
5340#define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
5341
5342
5343/***********************************/
5344/* MC_CMD_GET_TLP_PROCESSING_GLOBALS
5345 * Get global PCIe steering and transaction processing configuration.
5346 */
5347#define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
5348
Shradha Shah75122ec2015-05-20 11:08:23 +01005349#define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5350
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005351/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */
5352#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4
5353#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
5354/* enum: MISC. */
5355#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
5356/* enum: IDO. */
5357#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
5358/* enum: RO. */
5359#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
5360/* enum: TPH Type. */
5361#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
5362
5363/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
5364#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8
5365#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0
5366/* Enum values, see field(s): */
5367/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
5368/* Amalgamated TLP info word. */
5369#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4
5370#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
5371#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
5372#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
5373#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31
5374#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
5375#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
5376#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1
5377#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1
5378#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2
5379#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1
5380#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3
5381#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
5382#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
5383#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28
5384#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
5385#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
5386#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1
5387#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1
5388#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2
5389#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
5390#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3
5391#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29
5392#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
5393#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
5394#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2
5395#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2
5396#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4
5397#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2
5398#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6
5399#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2
5400#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8
5401#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2
5402#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9
5403#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23
5404
5405
5406/***********************************/
5407/* MC_CMD_SET_TLP_PROCESSING_GLOBALS
5408 * Set global PCIe steering and transaction processing configuration.
5409 */
5410#define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
5411
Shradha Shah75122ec2015-05-20 11:08:23 +01005412#define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5413
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005414/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */
5415#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8
5416#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
5417/* Enum values, see field(s): */
5418/* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
5419/* Amalgamated TLP info word. */
5420#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4
5421#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0
5422#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1
5423#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0
5424#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1
5425#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1
5426#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1
5427#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2
5428#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1
5429#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3
5430#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1
5431#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0
5432#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1
5433#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1
5434#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1
5435#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2
5436#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1
5437#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0
5438#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
5439#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2
5440#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2
5441#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4
5442#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2
5443#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6
5444#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2
5445#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8
5446#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2
5447#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10
5448#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22
5449
5450/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
5451#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
5452
5453
5454/***********************************/
5455/* MC_CMD_SATELLITE_DOWNLOAD
5456 * Download a new set of images to the satellite CPUs from the host.
5457 */
5458#define MC_CMD_SATELLITE_DOWNLOAD 0x91
5459
Shradha Shah75122ec2015-05-20 11:08:23 +01005460#define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5461
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005462/* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs
5463 * are subtle, and so downloads must proceed in a number of phases.
5464 *
5465 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
5466 *
5467 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
5468 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should
5469 * be a checksum (a simple 32-bit sum) of the transferred data. An individual
5470 * download may be aborted using CHUNK_ID_ABORT.
5471 *
5472 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),
5473 * similar to PHASE_IMEMS.
5474 *
5475 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
5476 *
5477 * After any error (a requested abort is not considered to be an error) the
5478 * sequence must be restarted from PHASE_RESET.
5479 */
5480#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20
5481#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252
5482#define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
5483/* Download phase. (Note: the IDLE phase is used internally and is never valid
5484 * in a command from the host.)
5485 */
5486#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0
5487#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
5488#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
5489#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
5490#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
5491#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
5492/* Target for download. (These match the blob numbers defined in
5493 * mc_flash_layout.h.)
5494 */
5495#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4
5496/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5497#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
5498/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5499#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
5500/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5501#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
5502/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5503#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
5504/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5505#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
5506/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5507#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
5508/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5509#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
5510/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5511#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
5512/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5513#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
5514/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5515#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
5516/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5517#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
5518/* enum: Valid in phase 2 (PHASE_IMEMS) only */
5519#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
5520/* enum: Valid in phase 3 (PHASE_VECTORS) only */
5521#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
5522/* enum: Valid in phase 3 (PHASE_VECTORS) only */
5523#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
5524/* enum: Valid in phase 3 (PHASE_VECTORS) only */
5525#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
5526/* enum: Valid in phase 3 (PHASE_VECTORS) only */
5527#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
5528/* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
5529#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
5530/* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */
5531#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8
5532/* enum: Last chunk, containing checksum rather than data */
5533#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
5534/* enum: Abort download of this item */
5535#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
5536/* Length of this chunk in bytes */
5537#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12
5538/* Data for this chunk */
5539#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16
5540#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4
5541#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1
5542#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59
5543
5544/* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */
5545#define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8
5546/* Same as MC_CMD_ERR field, but included as 0 in success cases */
5547#define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0
5548/* Extra status information */
5549#define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4
5550/* enum: Code download OK, completed. */
5551#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
5552/* enum: Code download aborted as requested. */
5553#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
5554/* enum: Code download OK so far, send next chunk. */
5555#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
5556/* enum: Download phases out of sequence */
5557#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
5558/* enum: Bad target for this phase */
5559#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
5560/* enum: Chunk ID out of sequence */
5561#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
5562/* enum: Chunk length zero or too large */
5563#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
5564/* enum: Checksum was incorrect */
5565#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300
5566
5567
5568/***********************************/
5569/* MC_CMD_GET_CAPABILITIES
5570 * Get device capabilities.
5571 *
5572 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to
5573 * reference inherent device capabilities as opposed to current NVRAM config.
5574 */
5575#define MC_CMD_GET_CAPABILITIES 0xbe
5576
Shradha Shah75122ec2015-05-20 11:08:23 +01005577#define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005578/* MC_CMD_GET_CAPABILITIES_IN msgrequest */
5579#define MC_CMD_GET_CAPABILITIES_IN_LEN 0
5580
5581/* MC_CMD_GET_CAPABILITIES_OUT msgresponse */
5582#define MC_CMD_GET_CAPABILITIES_OUT_LEN 20
5583/* First word of flags. */
5584#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
5585#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19
5586#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
5587#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20
5588#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
5589#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21
5590#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
5591#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22
5592#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
5593#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23
5594#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
5595#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24
5596#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
5597#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25
5598#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
5599#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26
5600#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
Matthew Slattery2ca10a72013-09-10 19:06:27 +01005601#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27
5602#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
Daniel Pieczkod94619c2015-06-02 11:40:05 +01005603#define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30
5604#define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005605/* RxDPCPU firmware id. */
5606#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
5607#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2
5608/* enum: Standard RXDP firmware */
5609#define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
5610/* enum: Low latency RXDP firmware */
5611#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
5612/* enum: RXDP Test firmware image 1 */
5613#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
5614/* enum: RXDP Test firmware image 2 */
5615#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
5616/* enum: RXDP Test firmware image 3 */
5617#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
5618/* enum: RXDP Test firmware image 4 */
5619#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
5620/* enum: RXDP Test firmware image 5 */
5621#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
5622/* enum: RXDP Test firmware image 6 */
5623#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
5624/* enum: RXDP Test firmware image 7 */
5625#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
5626/* enum: RXDP Test firmware image 8 */
5627#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
5628/* TxDPCPU firmware id. */
5629#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6
5630#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2
5631/* enum: Standard TXDP firmware */
5632#define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
5633/* enum: Low latency TXDP firmware */
5634#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
5635/* enum: TXDP Test firmware image 1 */
5636#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
5637/* enum: TXDP Test firmware image 2 */
5638#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
5639#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8
5640#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2
5641#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
5642#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12
5643#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12
5644#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
5645#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */
5646#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */
5647#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 /* enum */
5648#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */
5649#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
5650#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10
5651#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2
5652#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
5653#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12
5654#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12
5655#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
5656#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */
5657#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */
5658#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 /* enum */
5659#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */
5660#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
5661/* Hardware capabilities of NIC */
5662#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12
5663/* Licensed capabilities */
5664#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16
5665
5666
5667/***********************************/
5668/* MC_CMD_V2_EXTN
5669 * Encapsulation for a v2 extended command
5670 */
5671#define MC_CMD_V2_EXTN 0x7f
5672
5673/* MC_CMD_V2_EXTN_IN msgrequest */
5674#define MC_CMD_V2_EXTN_IN_LEN 4
5675/* the extended command number */
5676#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
5677#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
5678#define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
5679#define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
5680/* the actual length of the encapsulated command (which is not in the v1
5681 * header)
5682 */
5683#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
5684#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
5685#define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
5686#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6
5687
5688
5689/***********************************/
5690/* MC_CMD_TCM_BUCKET_ALLOC
5691 * Allocate a pacer bucket (for qau rp or a snapper test)
5692 */
5693#define MC_CMD_TCM_BUCKET_ALLOC 0xb2
5694
Shradha Shah75122ec2015-05-20 11:08:23 +01005695#define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5696
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005697/* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */
5698#define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
5699
5700/* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */
5701#define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
5702/* the bucket id */
5703#define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
5704
5705
5706/***********************************/
5707/* MC_CMD_TCM_BUCKET_FREE
5708 * Free a pacer bucket
5709 */
5710#define MC_CMD_TCM_BUCKET_FREE 0xb3
5711
Shradha Shah75122ec2015-05-20 11:08:23 +01005712#define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5713
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005714/* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */
5715#define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
5716/* the bucket id */
5717#define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
5718
5719/* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */
5720#define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
5721
5722
5723/***********************************/
5724/* MC_CMD_TCM_BUCKET_INIT
5725 * Initialise pacer bucket with a given rate
5726 */
5727#define MC_CMD_TCM_BUCKET_INIT 0xb4
5728
Shradha Shah75122ec2015-05-20 11:08:23 +01005729#define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5730
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005731/* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */
5732#define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8
5733/* the bucket id */
5734#define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
5735/* the rate in mbps */
5736#define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
5737
5738/* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */
5739#define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
5740
5741
5742/***********************************/
5743/* MC_CMD_TCM_TXQ_INIT
5744 * Initialise txq in pacer with given options or set options
5745 */
5746#define MC_CMD_TCM_TXQ_INIT 0xb5
5747
Shradha Shah75122ec2015-05-20 11:08:23 +01005748#define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5749
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005750/* MC_CMD_TCM_TXQ_INIT_IN msgrequest */
5751#define MC_CMD_TCM_TXQ_INIT_IN_LEN 28
5752/* the txq id */
5753#define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
5754/* the static priority associated with the txq */
5755#define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
5756/* bitmask of the priority queues this txq is inserted into */
5757#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8
5758/* the reaction point (RP) bucket */
5759#define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12
5760/* an already reserved bucket (typically set to bucket associated with outer
5761 * vswitch)
5762 */
5763#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16
5764/* an already reserved bucket (typically set to bucket associated with inner
5765 * vswitch)
5766 */
5767#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20
5768/* the min bucket (typically for ETS/minimum bandwidth) */
5769#define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24
5770
5771/* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */
5772#define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
5773
5774
5775/***********************************/
5776/* MC_CMD_LINK_PIOBUF
5777 * Link a push I/O buffer to a TxQ
5778 */
5779#define MC_CMD_LINK_PIOBUF 0x92
5780
Shradha Shah75122ec2015-05-20 11:08:23 +01005781#define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
5782
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005783/* MC_CMD_LINK_PIOBUF_IN msgrequest */
5784#define MC_CMD_LINK_PIOBUF_IN_LEN 8
5785/* Handle for allocated push I/O buffer. */
5786#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
5787/* Function Local Instance (VI) number. */
5788#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
5789
5790/* MC_CMD_LINK_PIOBUF_OUT msgresponse */
5791#define MC_CMD_LINK_PIOBUF_OUT_LEN 0
5792
5793
5794/***********************************/
5795/* MC_CMD_UNLINK_PIOBUF
5796 * Unlink a push I/O buffer from a TxQ
5797 */
5798#define MC_CMD_UNLINK_PIOBUF 0x93
5799
Shradha Shah75122ec2015-05-20 11:08:23 +01005800#define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
5801
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005802/* MC_CMD_UNLINK_PIOBUF_IN msgrequest */
5803#define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
5804/* Function Local Instance (VI) number. */
5805#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
5806
5807/* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */
5808#define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
5809
5810
5811/***********************************/
5812/* MC_CMD_VSWITCH_ALLOC
5813 * allocate and initialise a v-switch.
5814 */
5815#define MC_CMD_VSWITCH_ALLOC 0x94
5816
Shradha Shah75122ec2015-05-20 11:08:23 +01005817#define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5818
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005819/* MC_CMD_VSWITCH_ALLOC_IN msgrequest */
5820#define MC_CMD_VSWITCH_ALLOC_IN_LEN 16
5821/* The port to connect to the v-switch's upstream port. */
5822#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
5823/* The type of v-switch to create. */
5824#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
5825/* enum: VLAN */
5826#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
5827/* enum: VEB */
5828#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
5829/* enum: VEPA */
5830#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
5831/* Flags controlling v-port creation */
5832#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8
5833#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
5834#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
5835/* The number of VLAN tags to support. */
5836#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
5837
5838/* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */
5839#define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
5840
5841
5842/***********************************/
5843/* MC_CMD_VSWITCH_FREE
5844 * de-allocate a v-switch.
5845 */
5846#define MC_CMD_VSWITCH_FREE 0x95
5847
Shradha Shah75122ec2015-05-20 11:08:23 +01005848#define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5849
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005850/* MC_CMD_VSWITCH_FREE_IN msgrequest */
5851#define MC_CMD_VSWITCH_FREE_IN_LEN 4
5852/* The port to which the v-switch is connected. */
5853#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
5854
5855/* MC_CMD_VSWITCH_FREE_OUT msgresponse */
5856#define MC_CMD_VSWITCH_FREE_OUT_LEN 0
5857
5858
5859/***********************************/
5860/* MC_CMD_VPORT_ALLOC
5861 * allocate a v-port.
5862 */
5863#define MC_CMD_VPORT_ALLOC 0x96
5864
Shradha Shah75122ec2015-05-20 11:08:23 +01005865#define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5866
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005867/* MC_CMD_VPORT_ALLOC_IN msgrequest */
5868#define MC_CMD_VPORT_ALLOC_IN_LEN 20
5869/* The port to which the v-switch is connected. */
5870#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
5871/* The type of the new v-port. */
5872#define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
5873/* enum: VLAN (obsolete) */
5874#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
5875/* enum: VEB (obsolete) */
5876#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
5877/* enum: VEPA (obsolete) */
5878#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
5879/* enum: A normal v-port receives packets which match a specified MAC and/or
5880 * VLAN.
5881 */
5882#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
5883/* enum: An expansion v-port packets traffic which don't match any other
5884 * v-port.
5885 */
5886#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
5887/* enum: An test v-port receives packets which match any filters installed by
5888 * its downstream components.
5889 */
5890#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
5891/* Flags controlling v-port creation */
5892#define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8
5893#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
5894#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
5895/* The number of VLAN tags to insert/remove. */
5896#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
5897/* The actual VLAN tags to insert/remove */
5898#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16
5899#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
5900#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16
5901#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16
5902#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16
5903
5904/* MC_CMD_VPORT_ALLOC_OUT msgresponse */
5905#define MC_CMD_VPORT_ALLOC_OUT_LEN 4
5906/* The handle of the new v-port */
5907#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
5908
5909
5910/***********************************/
5911/* MC_CMD_VPORT_FREE
5912 * de-allocate a v-port.
5913 */
5914#define MC_CMD_VPORT_FREE 0x97
5915
Shradha Shah75122ec2015-05-20 11:08:23 +01005916#define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5917
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005918/* MC_CMD_VPORT_FREE_IN msgrequest */
5919#define MC_CMD_VPORT_FREE_IN_LEN 4
5920/* The handle of the v-port */
5921#define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
5922
5923/* MC_CMD_VPORT_FREE_OUT msgresponse */
5924#define MC_CMD_VPORT_FREE_OUT_LEN 0
5925
5926
5927/***********************************/
5928/* MC_CMD_VADAPTOR_ALLOC
5929 * allocate a v-adaptor.
5930 */
5931#define MC_CMD_VADAPTOR_ALLOC 0x98
5932
Shradha Shah75122ec2015-05-20 11:08:23 +01005933#define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5934
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005935/* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */
Shradha Shahaf6a0742015-05-20 11:08:40 +01005936#define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005937/* The port to connect to the v-adaptor's port. */
5938#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
5939/* Flags controlling v-adaptor creation */
5940#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8
5941#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
5942#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
5943/* The number of VLAN tags to strip on receive */
5944#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12
Shradha Shahaf6a0742015-05-20 11:08:40 +01005945/* The number of VLAN tags to transparently insert/remove. */
5946#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16
5947/* The actual VLAN tags to insert/remove */
5948#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20
5949#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
5950#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16
5951#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16
5952#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16
5953/* The MAC address to assign to this v-adaptor */
5954#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24
5955#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6
5956/* enum: Derive the MAC address from the upstream port */
5957#define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005958
5959/* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */
5960#define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
5961
5962
5963/***********************************/
5964/* MC_CMD_VADAPTOR_FREE
5965 * de-allocate a v-adaptor.
5966 */
5967#define MC_CMD_VADAPTOR_FREE 0x99
5968
Shradha Shah75122ec2015-05-20 11:08:23 +01005969#define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5970
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01005971/* MC_CMD_VADAPTOR_FREE_IN msgrequest */
5972#define MC_CMD_VADAPTOR_FREE_IN_LEN 4
5973/* The port to which the v-adaptor is connected. */
5974#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
5975
5976/* MC_CMD_VADAPTOR_FREE_OUT msgresponse */
5977#define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
5978
5979
5980/***********************************/
Shradha Shah910c8782015-05-20 11:12:48 +01005981/* MC_CMD_VADAPTOR_SET_MAC
5982 * assign a new MAC address to a v-adaptor.
5983 */
5984#define MC_CMD_VADAPTOR_SET_MAC 0x5d
5985
5986#define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5987
5988/* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */
5989#define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10
5990/* The port to which the v-adaptor is connected. */
5991#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
5992/* The new MAC address to assign to this v-adaptor */
5993#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
5994#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6
5995
5996/* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */
5997#define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
5998
5999
6000/***********************************/
6001/* MC_CMD_VADAPTOR_GET_MAC
6002 * read the MAC address assigned to a v-adaptor.
6003 */
6004#define MC_CMD_VADAPTOR_GET_MAC 0x5e
6005
6006#define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6007
6008/* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */
6009#define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4
6010/* The port to which the v-adaptor is connected. */
6011#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
6012
6013/* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */
6014#define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6
6015/* The MAC address assigned to this v-adaptor */
6016#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0
6017#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6
6018
6019
6020/***********************************/
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006021/* MC_CMD_EVB_PORT_ASSIGN
6022 * assign a port to a PCI function.
6023 */
6024#define MC_CMD_EVB_PORT_ASSIGN 0x9a
6025
Shradha Shah75122ec2015-05-20 11:08:23 +01006026#define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6027
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006028/* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */
6029#define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8
6030/* The port to assign. */
6031#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
6032/* The target function to modify. */
6033#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
6034#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
6035#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16
6036#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16
6037#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16
6038
6039/* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */
6040#define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
6041
6042
6043/***********************************/
6044/* MC_CMD_RDWR_A64_REGIONS
6045 * Assign the 64 bit region addresses.
6046 */
6047#define MC_CMD_RDWR_A64_REGIONS 0x9b
6048
Shradha Shah75122ec2015-05-20 11:08:23 +01006049#define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6050
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006051/* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */
6052#define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17
6053#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
6054#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
6055#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8
6056#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12
6057/* Write enable bits 0-3, set to write, clear to read. */
6058#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128
6059#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
6060#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16
6061#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1
6062
6063/* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included
6064 * regardless of state of write bits in the request.
6065 */
6066#define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16
6067#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
6068#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
6069#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8
6070#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12
6071
6072
6073/***********************************/
6074/* MC_CMD_ONLOAD_STACK_ALLOC
6075 * Allocate an Onload stack ID.
6076 */
6077#define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
6078
Shradha Shah75122ec2015-05-20 11:08:23 +01006079#define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
6080
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006081/* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */
6082#define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
6083/* The handle of the owning upstream port */
6084#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
6085
6086/* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */
6087#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
6088/* The handle of the new Onload stack */
6089#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
6090
6091
6092/***********************************/
6093/* MC_CMD_ONLOAD_STACK_FREE
6094 * Free an Onload stack ID.
6095 */
6096#define MC_CMD_ONLOAD_STACK_FREE 0x9d
6097
Shradha Shah75122ec2015-05-20 11:08:23 +01006098#define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
6099
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006100/* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */
6101#define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
6102/* The handle of the Onload stack */
6103#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
6104
6105/* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */
6106#define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
6107
6108
6109/***********************************/
6110/* MC_CMD_RSS_CONTEXT_ALLOC
6111 * Allocate an RSS context.
6112 */
6113#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
6114
Shradha Shah75122ec2015-05-20 11:08:23 +01006115#define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6116
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006117/* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */
6118#define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12
6119/* The handle of the owning upstream port */
6120#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
6121/* The type of context to allocate */
6122#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
6123/* enum: Allocate a context for exclusive use. The key and indirection table
6124 * must be explicitly configured.
6125 */
6126#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
6127/* enum: Allocate a context for shared use; this will spread across a range of
6128 * queues, but the key and indirection table are pre-configured and may not be
6129 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
6130 */
6131#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
6132/* Number of queues spanned by this context, in the range 1-64; valid offsets
6133 * in the indirection table will be in the range 0 to NUM_QUEUES-1.
6134 */
6135#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8
6136
6137/* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */
6138#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
6139/* The handle of the new RSS context */
6140#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
6141
6142
6143/***********************************/
6144/* MC_CMD_RSS_CONTEXT_FREE
6145 * Free an RSS context.
6146 */
6147#define MC_CMD_RSS_CONTEXT_FREE 0x9f
6148
Shradha Shah75122ec2015-05-20 11:08:23 +01006149#define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6150
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006151/* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */
6152#define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
6153/* The handle of the RSS context */
6154#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
6155
6156/* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */
6157#define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
6158
6159
6160/***********************************/
6161/* MC_CMD_RSS_CONTEXT_SET_KEY
6162 * Set the Toeplitz hash key for an RSS context.
6163 */
6164#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
6165
Shradha Shah75122ec2015-05-20 11:08:23 +01006166#define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6167
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006168/* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */
6169#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44
6170/* The handle of the RSS context */
6171#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
6172/* The 40-byte Toeplitz hash key (TBD endianness issues?) */
6173#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
6174#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40
6175
6176/* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */
6177#define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
6178
6179
6180/***********************************/
6181/* MC_CMD_RSS_CONTEXT_GET_KEY
6182 * Get the Toeplitz hash key for an RSS context.
6183 */
6184#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
6185
Shradha Shah75122ec2015-05-20 11:08:23 +01006186#define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6187
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006188/* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */
6189#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
6190/* The handle of the RSS context */
6191#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
6192
6193/* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */
6194#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44
6195/* The 40-byte Toeplitz hash key (TBD endianness issues?) */
6196#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
6197#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40
6198
6199
6200/***********************************/
6201/* MC_CMD_RSS_CONTEXT_SET_TABLE
6202 * Set the indirection table for an RSS context.
6203 */
6204#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
6205
Shradha Shah75122ec2015-05-20 11:08:23 +01006206#define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6207
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006208/* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */
6209#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132
6210/* The handle of the RSS context */
6211#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
6212/* The 128-byte indirection table (1 byte per entry) */
6213#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
6214#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128
6215
6216/* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */
6217#define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
6218
6219
6220/***********************************/
6221/* MC_CMD_RSS_CONTEXT_GET_TABLE
6222 * Get the indirection table for an RSS context.
6223 */
6224#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
6225
Shradha Shah75122ec2015-05-20 11:08:23 +01006226#define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6227
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006228/* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */
6229#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
6230/* The handle of the RSS context */
6231#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
6232
6233/* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */
6234#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132
6235/* The 128-byte indirection table (1 byte per entry) */
6236#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
6237#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128
6238
6239
6240/***********************************/
6241/* MC_CMD_RSS_CONTEXT_SET_FLAGS
6242 * Set various control flags for an RSS context.
6243 */
6244#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
6245
Shradha Shah75122ec2015-05-20 11:08:23 +01006246#define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6247
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006248/* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */
6249#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8
6250/* The handle of the RSS context */
6251#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
6252/* Hash control flags */
6253#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
6254#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
6255#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
6256#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
6257#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
6258#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2
6259#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
6260#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3
6261#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
6262
6263/* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */
6264#define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
6265
6266
6267/***********************************/
6268/* MC_CMD_RSS_CONTEXT_GET_FLAGS
6269 * Get various control flags for an RSS context.
6270 */
6271#define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
6272
Shradha Shah75122ec2015-05-20 11:08:23 +01006273#define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6274
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006275/* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */
6276#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
6277/* The handle of the RSS context */
6278#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
6279
6280/* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */
6281#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8
6282/* Hash control flags */
6283#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
6284#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
6285#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
6286#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
6287#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
6288#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2
6289#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
6290#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3
6291#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
6292
6293
6294/***********************************/
6295/* MC_CMD_DOT1P_MAPPING_ALLOC
6296 * Allocate a .1p mapping.
6297 */
6298#define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
6299
Shradha Shah75122ec2015-05-20 11:08:23 +01006300#define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6301
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006302/* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */
6303#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8
6304/* The handle of the owning upstream port */
6305#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
6306/* Number of queues spanned by this mapping, in the range 1-64; valid fixed
6307 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
6308 * referenced RSS contexts must span no more than this number.
6309 */
6310#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4
6311
6312/* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */
6313#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4
6314/* The handle of the new .1p mapping */
6315#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0
6316
6317
6318/***********************************/
6319/* MC_CMD_DOT1P_MAPPING_FREE
6320 * Free a .1p mapping.
6321 */
6322#define MC_CMD_DOT1P_MAPPING_FREE 0xa5
6323
Shradha Shah75122ec2015-05-20 11:08:23 +01006324#define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6325
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006326/* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */
6327#define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4
6328/* The handle of the .1p mapping */
6329#define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0
6330
6331/* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */
6332#define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0
6333
6334
6335/***********************************/
6336/* MC_CMD_DOT1P_MAPPING_SET_TABLE
6337 * Set the mapping table for a .1p mapping.
6338 */
6339#define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
6340
Shradha Shah75122ec2015-05-20 11:08:23 +01006341#define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6342
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006343/* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */
6344#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36
6345/* The handle of the .1p mapping */
6346#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
6347/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
6348 * handle)
6349 */
6350#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4
6351#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32
6352
6353/* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */
6354#define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0
6355
6356
6357/***********************************/
6358/* MC_CMD_DOT1P_MAPPING_GET_TABLE
6359 * Get the mapping table for a .1p mapping.
6360 */
6361#define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
6362
Shradha Shah75122ec2015-05-20 11:08:23 +01006363#define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6364
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006365/* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */
6366#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4
6367/* The handle of the .1p mapping */
6368#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
6369
6370/* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */
6371#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36
6372/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
6373 * handle)
6374 */
6375#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4
6376#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32
6377
6378
6379/***********************************/
6380/* MC_CMD_GET_VECTOR_CFG
6381 * Get Interrupt Vector config for this PF.
6382 */
6383#define MC_CMD_GET_VECTOR_CFG 0xbf
6384
Shradha Shah75122ec2015-05-20 11:08:23 +01006385#define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6386
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006387/* MC_CMD_GET_VECTOR_CFG_IN msgrequest */
6388#define MC_CMD_GET_VECTOR_CFG_IN_LEN 0
6389
6390/* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */
6391#define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12
6392/* Base absolute interrupt vector number. */
6393#define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
6394/* Number of interrupt vectors allocate to this PF. */
6395#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
6396/* Number of interrupt vectors to allocate per VF. */
6397#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8
6398
6399
6400/***********************************/
6401/* MC_CMD_SET_VECTOR_CFG
6402 * Set Interrupt Vector config for this PF.
6403 */
6404#define MC_CMD_SET_VECTOR_CFG 0xc0
6405
Shradha Shah75122ec2015-05-20 11:08:23 +01006406#define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6407
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006408/* MC_CMD_SET_VECTOR_CFG_IN msgrequest */
6409#define MC_CMD_SET_VECTOR_CFG_IN_LEN 12
6410/* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to
6411 * let the system find a suitable base.
6412 */
6413#define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
6414/* Number of interrupt vectors allocate to this PF. */
6415#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
6416/* Number of interrupt vectors to allocate per VF. */
6417#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8
6418
6419/* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */
6420#define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
6421
6422
6423/***********************************/
6424/* MC_CMD_RMON_RX_CLASS_STATS
6425 * Retrieve rmon rx class statistics
6426 */
6427#define MC_CMD_RMON_RX_CLASS_STATS 0xc3
6428
6429/* MC_CMD_RMON_RX_CLASS_STATS_IN msgrequest */
6430#define MC_CMD_RMON_RX_CLASS_STATS_IN_LEN 4
6431/* flags */
6432#define MC_CMD_RMON_RX_CLASS_STATS_IN_FLAGS_OFST 0
6433#define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_LBN 0
6434#define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_WIDTH 8
6435#define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_LBN 8
6436#define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_WIDTH 1
6437
6438/* MC_CMD_RMON_RX_CLASS_STATS_OUT msgresponse */
6439#define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMIN 4
6440#define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMAX 252
6441#define MC_CMD_RMON_RX_CLASS_STATS_OUT_LEN(num) (0+4*(num))
6442/* Array of stats */
6443#define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_OFST 0
6444#define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_LEN 4
6445#define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MINNUM 1
6446#define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MAXNUM 63
6447
6448
6449/***********************************/
6450/* MC_CMD_RMON_TX_CLASS_STATS
6451 * Retrieve rmon tx class statistics
6452 */
6453#define MC_CMD_RMON_TX_CLASS_STATS 0xc4
6454
6455/* MC_CMD_RMON_TX_CLASS_STATS_IN msgrequest */
6456#define MC_CMD_RMON_TX_CLASS_STATS_IN_LEN 4
6457/* flags */
6458#define MC_CMD_RMON_TX_CLASS_STATS_IN_FLAGS_OFST 0
6459#define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_LBN 0
6460#define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_WIDTH 8
6461#define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_LBN 8
6462#define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_WIDTH 1
6463
6464/* MC_CMD_RMON_TX_CLASS_STATS_OUT msgresponse */
6465#define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMIN 4
6466#define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMAX 252
6467#define MC_CMD_RMON_TX_CLASS_STATS_OUT_LEN(num) (0+4*(num))
6468/* Array of stats */
6469#define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_OFST 0
6470#define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_LEN 4
6471#define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MINNUM 1
6472#define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MAXNUM 63
6473
6474
6475/***********************************/
6476/* MC_CMD_RMON_RX_SUPER_CLASS_STATS
6477 * Retrieve rmon rx super_class statistics
6478 */
6479#define MC_CMD_RMON_RX_SUPER_CLASS_STATS 0xc5
6480
6481/* MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN msgrequest */
6482#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_LEN 4
6483/* flags */
6484#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0
6485#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0
6486#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4
6487#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_LBN 4
6488#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_WIDTH 1
6489
6490/* MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT msgresponse */
6491#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMIN 4
6492#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMAX 252
6493#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num))
6494/* Array of stats */
6495#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0
6496#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4
6497#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1
6498#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63
6499
6500
6501/***********************************/
6502/* MC_CMD_RMON_TX_SUPER_CLASS_STATS
6503 * Retrieve rmon tx super_class statistics
6504 */
6505#define MC_CMD_RMON_TX_SUPER_CLASS_STATS 0xc6
6506
6507/* MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN msgrequest */
6508#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_LEN 4
6509/* flags */
6510#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0
6511#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0
6512#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4
6513#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_LBN 4
6514#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_WIDTH 1
6515
6516/* MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT msgresponse */
6517#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMIN 4
6518#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMAX 252
6519#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num))
6520/* Array of stats */
6521#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0
6522#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4
6523#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1
6524#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63
6525
6526
6527/***********************************/
6528/* MC_CMD_RMON_RX_ADD_QID_TO_CLASS
6529 * Add qid to class for statistics collection
6530 */
6531#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS 0xc7
6532
6533/* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN msgrequest */
6534#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_LEN 12
6535/* class */
6536#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0
6537/* qid */
6538#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_QID_OFST 4
6539/* flags */
6540#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8
6541#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0
6542#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4
6543#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4
6544#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4
6545#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_LBN 8
6546#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14
6547
6548/* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT msgresponse */
6549#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT_LEN 0
6550
6551
6552/***********************************/
6553/* MC_CMD_RMON_TX_ADD_QID_TO_CLASS
6554 * Add qid to class for statistics collection
6555 */
6556#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS 0xc8
6557
6558/* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN msgrequest */
6559#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_LEN 12
6560/* class */
6561#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0
6562/* qid */
6563#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_QID_OFST 4
6564/* flags */
6565#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8
6566#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0
6567#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4
6568#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4
6569#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4
6570#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_LBN 8
6571#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14
6572
6573/* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT msgresponse */
6574#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT_LEN 0
6575
6576
6577/***********************************/
6578/* MC_CMD_RMON_MC_ADD_QID_TO_CLASS
6579 * Add qid to class for statistics collection
6580 */
6581#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS 0xc9
6582
6583/* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN msgrequest */
6584#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_LEN 12
6585/* class */
6586#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_CLASS_OFST 0
6587/* qid */
6588#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_QID_OFST 4
6589/* flags */
6590#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8
6591#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0
6592#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4
6593#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4
6594#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4
6595#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_LBN 8
6596#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14
6597
6598/* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT msgresponse */
6599#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT_LEN 0
6600
6601
6602/***********************************/
6603/* MC_CMD_RMON_ALLOC_CLASS
6604 * Allocate an rmon class
6605 */
6606#define MC_CMD_RMON_ALLOC_CLASS 0xca
6607
6608/* MC_CMD_RMON_ALLOC_CLASS_IN msgrequest */
6609#define MC_CMD_RMON_ALLOC_CLASS_IN_LEN 0
6610
6611/* MC_CMD_RMON_ALLOC_CLASS_OUT msgresponse */
6612#define MC_CMD_RMON_ALLOC_CLASS_OUT_LEN 4
6613/* class */
6614#define MC_CMD_RMON_ALLOC_CLASS_OUT_CLASS_OFST 0
6615
6616
6617/***********************************/
6618/* MC_CMD_RMON_DEALLOC_CLASS
6619 * Deallocate an rmon class
6620 */
6621#define MC_CMD_RMON_DEALLOC_CLASS 0xcb
6622
6623/* MC_CMD_RMON_DEALLOC_CLASS_IN msgrequest */
6624#define MC_CMD_RMON_DEALLOC_CLASS_IN_LEN 4
6625/* class */
6626#define MC_CMD_RMON_DEALLOC_CLASS_IN_CLASS_OFST 0
6627
6628/* MC_CMD_RMON_DEALLOC_CLASS_OUT msgresponse */
6629#define MC_CMD_RMON_DEALLOC_CLASS_OUT_LEN 0
6630
6631
6632/***********************************/
6633/* MC_CMD_RMON_ALLOC_SUPER_CLASS
6634 * Allocate an rmon super_class
6635 */
6636#define MC_CMD_RMON_ALLOC_SUPER_CLASS 0xcc
6637
6638/* MC_CMD_RMON_ALLOC_SUPER_CLASS_IN msgrequest */
6639#define MC_CMD_RMON_ALLOC_SUPER_CLASS_IN_LEN 0
6640
6641/* MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT msgresponse */
6642#define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_LEN 4
6643/* super_class */
6644#define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_SUPER_CLASS_OFST 0
6645
6646
6647/***********************************/
6648/* MC_CMD_RMON_DEALLOC_SUPER_CLASS
6649 * Deallocate an rmon tx super_class
6650 */
6651#define MC_CMD_RMON_DEALLOC_SUPER_CLASS 0xcd
6652
6653/* MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN msgrequest */
6654#define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_LEN 4
6655/* super_class */
6656#define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_SUPER_CLASS_OFST 0
6657
6658/* MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT msgresponse */
6659#define MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT_LEN 0
6660
6661
6662/***********************************/
6663/* MC_CMD_RMON_RX_UP_CONV_STATS
6664 * Retrieve up converter statistics
6665 */
6666#define MC_CMD_RMON_RX_UP_CONV_STATS 0xce
6667
6668/* MC_CMD_RMON_RX_UP_CONV_STATS_IN msgrequest */
6669#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_LEN 4
6670/* flags */
6671#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_FLAGS_OFST 0
6672#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_LBN 0
6673#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_WIDTH 2
6674#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_LBN 2
6675#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_WIDTH 1
6676
6677/* MC_CMD_RMON_RX_UP_CONV_STATS_OUT msgresponse */
6678#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMIN 4
6679#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMAX 252
6680#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LEN(num) (0+4*(num))
6681/* Array of stats */
6682#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_OFST 0
6683#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_LEN 4
6684#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MINNUM 1
6685#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MAXNUM 63
6686
6687
6688/***********************************/
6689/* MC_CMD_RMON_RX_IPI_STATS
6690 * Retrieve rx ipi stats
6691 */
6692#define MC_CMD_RMON_RX_IPI_STATS 0xcf
6693
6694/* MC_CMD_RMON_RX_IPI_STATS_IN msgrequest */
6695#define MC_CMD_RMON_RX_IPI_STATS_IN_LEN 4
6696/* flags */
6697#define MC_CMD_RMON_RX_IPI_STATS_IN_FLAGS_OFST 0
6698#define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_LBN 0
6699#define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_WIDTH 5
6700#define MC_CMD_RMON_RX_IPI_STATS_IN_RST_LBN 5
6701#define MC_CMD_RMON_RX_IPI_STATS_IN_RST_WIDTH 1
6702
6703/* MC_CMD_RMON_RX_IPI_STATS_OUT msgresponse */
6704#define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMIN 4
6705#define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMAX 252
6706#define MC_CMD_RMON_RX_IPI_STATS_OUT_LEN(num) (0+4*(num))
6707/* Array of stats */
6708#define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_OFST 0
6709#define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_LEN 4
6710#define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MINNUM 1
6711#define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MAXNUM 63
6712
6713
6714/***********************************/
6715/* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS
6716 * Retrieve rx ipsec cntxt_ptr indexed stats
6717 */
6718#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS 0xd0
6719
6720/* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */
6721#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4
6722/* flags */
6723#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0
6724#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0
6725#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9
6726#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9
6727#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1
6728
6729/* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */
6730#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4
6731#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252
6732#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num))
6733/* Array of stats */
6734#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0
6735#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4
6736#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1
6737#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63
6738
6739
6740/***********************************/
6741/* MC_CMD_RMON_RX_IPSEC_PORT_STATS
6742 * Retrieve rx ipsec port indexed stats
6743 */
6744#define MC_CMD_RMON_RX_IPSEC_PORT_STATS 0xd1
6745
6746/* MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN msgrequest */
6747#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_LEN 4
6748/* flags */
6749#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0
6750#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_LBN 0
6751#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2
6752#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_LBN 2
6753#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_WIDTH 1
6754
6755/* MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT msgresponse */
6756#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMIN 4
6757#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMAX 252
6758#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num))
6759/* Array of stats */
6760#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0
6761#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4
6762#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1
6763#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63
6764
6765
6766/***********************************/
6767/* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS
6768 * Retrieve tx ipsec overflow
6769 */
6770#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS 0xd2
6771
6772/* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN msgrequest */
6773#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_LEN 4
6774/* flags */
6775#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0
6776#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0
6777#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2
6778#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_LBN 2
6779#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1
6780
6781/* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT msgresponse */
6782#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMIN 4
6783#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMAX 252
6784#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num))
6785/* Array of stats */
6786#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0
6787#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4
6788#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1
6789#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63
6790
6791
6792/***********************************/
6793/* MC_CMD_VPORT_ADD_MAC_ADDRESS
6794 * Add a MAC address to a v-port
6795 */
6796#define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
6797
Shradha Shah75122ec2015-05-20 11:08:23 +01006798#define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6799
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006800/* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */
6801#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10
6802/* The handle of the v-port */
6803#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
6804/* MAC address to add */
6805#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
6806#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6
6807
6808/* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */
6809#define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
6810
6811
6812/***********************************/
6813/* MC_CMD_VPORT_DEL_MAC_ADDRESS
6814 * Delete a MAC address from a v-port
6815 */
6816#define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
6817
Shradha Shah75122ec2015-05-20 11:08:23 +01006818#define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6819
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006820/* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */
6821#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10
6822/* The handle of the v-port */
6823#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
6824/* MAC address to add */
6825#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
6826#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6
6827
6828/* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */
6829#define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
6830
6831
6832/***********************************/
6833/* MC_CMD_VPORT_GET_MAC_ADDRESSES
6834 * Delete a MAC address from a v-port
6835 */
6836#define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
6837
Shradha Shah75122ec2015-05-20 11:08:23 +01006838#define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6839
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006840/* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */
6841#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
6842/* The handle of the v-port */
6843#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
6844
6845/* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */
6846#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
6847#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250
6848#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
6849/* The number of MAC addresses returned */
6850#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
6851/* Array of MAC addresses */
6852#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
6853#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6
6854#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
6855#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41
6856
6857
6858/***********************************/
6859/* MC_CMD_DUMP_BUFTBL_ENTRIES
6860 * Dump buffer table entries, mainly for command client debug use. Dumps
6861 * absolute entries, and does not use chunk handles. All entries must be in
6862 * range, and used for q page mapping, Although the latter restriction may be
6863 * lifted in future.
6864 */
6865#define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
6866
Shradha Shah75122ec2015-05-20 11:08:23 +01006867#define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6868
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006869/* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */
6870#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8
6871/* Index of the first buffer table entry. */
6872#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0
6873/* Number of buffer table entries to dump. */
6874#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4
6875
6876/* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */
6877#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12
6878#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252
6879#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
Joe Perchesdbedd442015-03-06 20:49:12 -08006880/* Raw buffer table entries, laid out as BUFTBL_ENTRY. */
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006881#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
6882#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12
6883#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1
6884#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21
6885
6886
6887/***********************************/
6888/* MC_CMD_SET_RXDP_CONFIG
6889 * Set global RXDP configuration settings
6890 */
6891#define MC_CMD_SET_RXDP_CONFIG 0xc1
6892
Shradha Shah75122ec2015-05-20 11:08:23 +01006893#define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6894
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006895/* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */
6896#define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4
6897#define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0
6898#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0
6899#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1
6900
6901/* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */
6902#define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0
6903
6904
6905/***********************************/
6906/* MC_CMD_GET_RXDP_CONFIG
6907 * Get global RXDP configuration settings
6908 */
6909#define MC_CMD_GET_RXDP_CONFIG 0xc2
6910
Shradha Shah75122ec2015-05-20 11:08:23 +01006911#define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6912
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01006913/* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */
6914#define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0
6915
6916/* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */
6917#define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4
6918#define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0
6919#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0
6920#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1
6921
6922
6923/***********************************/
6924/* MC_CMD_RMON_RX_CLASS_DROPS_STATS
6925 * Retrieve rx class drop stats
6926 */
6927#define MC_CMD_RMON_RX_CLASS_DROPS_STATS 0xd3
6928
6929/* MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN msgrequest */
6930#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_LEN 4
6931/* flags */
6932#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_FLAGS_OFST 0
6933#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_LBN 0
6934#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_WIDTH 8
6935#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_LBN 8
6936#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_WIDTH 1
6937
6938/* MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT msgresponse */
6939#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMIN 4
6940#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMAX 252
6941#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num))
6942/* Array of stats */
6943#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0
6944#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4
6945#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1
6946#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63
6947
6948
6949/***********************************/
6950/* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS
6951 * Retrieve rx super class drop stats
6952 */
6953#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS 0xd4
6954
6955/* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN msgrequest */
6956#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_LEN 4
6957/* flags */
6958#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_FLAGS_OFST 0
6959#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_LBN 0
6960#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_WIDTH 4
6961#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_LBN 4
6962#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_WIDTH 1
6963
6964/* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT msgresponse */
6965#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMIN 4
6966#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMAX 252
6967#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num))
6968/* Array of stats */
6969#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0
6970#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4
6971#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1
6972#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63
6973
6974
6975/***********************************/
6976/* MC_CMD_RMON_RX_ERRORS_STATS
6977 * Retrieve rxdp errors
6978 */
6979#define MC_CMD_RMON_RX_ERRORS_STATS 0xd5
6980
6981/* MC_CMD_RMON_RX_ERRORS_STATS_IN msgrequest */
6982#define MC_CMD_RMON_RX_ERRORS_STATS_IN_LEN 4
6983/* flags */
6984#define MC_CMD_RMON_RX_ERRORS_STATS_IN_FLAGS_OFST 0
6985#define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_LBN 0
6986#define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_WIDTH 11
6987#define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_LBN 11
6988#define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_WIDTH 1
6989
6990/* MC_CMD_RMON_RX_ERRORS_STATS_OUT msgresponse */
6991#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMIN 4
6992#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMAX 252
6993#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LEN(num) (0+4*(num))
6994/* Array of stats */
6995#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_OFST 0
6996#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_LEN 4
6997#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MINNUM 1
6998#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63
6999
7000
7001/***********************************/
7002/* MC_CMD_RMON_RX_OVERFLOW_STATS
7003 * Retrieve rxdp overflow
7004 */
7005#define MC_CMD_RMON_RX_OVERFLOW_STATS 0xd6
7006
7007/* MC_CMD_RMON_RX_OVERFLOW_STATS_IN msgrequest */
7008#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_LEN 4
7009/* flags */
7010#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_FLAGS_OFST 0
7011#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_LBN 0
7012#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_WIDTH 8
7013#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_LBN 8
7014#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_WIDTH 1
7015
7016/* MC_CMD_RMON_RX_OVERFLOW_STATS_OUT msgresponse */
7017#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMIN 4
7018#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMAX 252
7019#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num))
7020/* Array of stats */
7021#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_OFST 0
7022#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_LEN 4
7023#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1
7024#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63
7025
7026
7027/***********************************/
7028/* MC_CMD_RMON_TX_IPI_STATS
7029 * Retrieve tx ipi stats
7030 */
7031#define MC_CMD_RMON_TX_IPI_STATS 0xd7
7032
7033/* MC_CMD_RMON_TX_IPI_STATS_IN msgrequest */
7034#define MC_CMD_RMON_TX_IPI_STATS_IN_LEN 4
7035/* flags */
7036#define MC_CMD_RMON_TX_IPI_STATS_IN_FLAGS_OFST 0
7037#define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_LBN 0
7038#define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_WIDTH 5
7039#define MC_CMD_RMON_TX_IPI_STATS_IN_RST_LBN 5
7040#define MC_CMD_RMON_TX_IPI_STATS_IN_RST_WIDTH 1
7041
7042/* MC_CMD_RMON_TX_IPI_STATS_OUT msgresponse */
7043#define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMIN 4
7044#define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMAX 252
7045#define MC_CMD_RMON_TX_IPI_STATS_OUT_LEN(num) (0+4*(num))
7046/* Array of stats */
7047#define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_OFST 0
7048#define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_LEN 4
7049#define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MINNUM 1
7050#define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MAXNUM 63
7051
7052
7053/***********************************/
7054/* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS
7055 * Retrieve tx ipsec counters by cntxt_ptr
7056 */
7057#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS 0xd8
7058
7059/* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */
7060#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4
7061/* flags */
7062#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0
7063#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0
7064#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9
7065#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9
7066#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1
7067
7068/* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */
7069#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4
7070#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252
7071#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num))
7072/* Array of stats */
7073#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0
7074#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4
7075#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1
7076#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63
7077
7078
7079/***********************************/
7080/* MC_CMD_RMON_TX_IPSEC_PORT_STATS
7081 * Retrieve tx ipsec counters by port
7082 */
7083#define MC_CMD_RMON_TX_IPSEC_PORT_STATS 0xd9
7084
7085/* MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN msgrequest */
7086#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_LEN 4
7087/* flags */
7088#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0
7089#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_LBN 0
7090#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2
7091#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_LBN 2
7092#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_WIDTH 1
7093
7094/* MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT msgresponse */
7095#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMIN 4
7096#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMAX 252
7097#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num))
7098/* Array of stats */
7099#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0
7100#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4
7101#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1
7102#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63
7103
7104
7105/***********************************/
7106/* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS
7107 * Retrieve tx ipsec overflow
7108 */
7109#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS 0xda
7110
7111/* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN msgrequest */
7112#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_LEN 4
7113/* flags */
7114#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0
7115#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0
7116#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2
7117#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_LBN 2
7118#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1
7119
7120/* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT msgresponse */
7121#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMIN 4
7122#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMAX 252
7123#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num))
7124/* Array of stats */
7125#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0
7126#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4
7127#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1
7128#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63
7129
7130
7131/***********************************/
7132/* MC_CMD_RMON_TX_NOWHERE_STATS
7133 * Retrieve tx nowhere stats
7134 */
7135#define MC_CMD_RMON_TX_NOWHERE_STATS 0xdb
7136
7137/* MC_CMD_RMON_TX_NOWHERE_STATS_IN msgrequest */
7138#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_LEN 4
7139/* flags */
7140#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_FLAGS_OFST 0
7141#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_LBN 0
7142#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_WIDTH 8
7143#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_LBN 8
7144#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_WIDTH 1
7145
7146/* MC_CMD_RMON_TX_NOWHERE_STATS_OUT msgresponse */
7147#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMIN 4
7148#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMAX 252
7149#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LEN(num) (0+4*(num))
7150/* Array of stats */
7151#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_OFST 0
7152#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_LEN 4
7153#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MINNUM 1
7154#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MAXNUM 63
7155
7156
7157/***********************************/
7158/* MC_CMD_RMON_TX_NOWHERE_QBB_STATS
7159 * Retrieve tx nowhere qbb stats
7160 */
7161#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS 0xdc
7162
7163/* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN msgrequest */
7164#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_LEN 4
7165/* flags */
7166#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_FLAGS_OFST 0
7167#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_LBN 0
7168#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_WIDTH 3
7169#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_LBN 3
7170#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_WIDTH 1
7171
7172/* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT msgresponse */
7173#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMIN 4
7174#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMAX 252
7175#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LEN(num) (0+4*(num))
7176/* Array of stats */
7177#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_OFST 0
7178#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_LEN 4
7179#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MINNUM 1
7180#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MAXNUM 63
7181
7182
7183/***********************************/
7184/* MC_CMD_RMON_TX_ERRORS_STATS
7185 * Retrieve rxdp errors
7186 */
7187#define MC_CMD_RMON_TX_ERRORS_STATS 0xdd
7188
7189/* MC_CMD_RMON_TX_ERRORS_STATS_IN msgrequest */
7190#define MC_CMD_RMON_TX_ERRORS_STATS_IN_LEN 4
7191/* flags */
7192#define MC_CMD_RMON_TX_ERRORS_STATS_IN_FLAGS_OFST 0
7193#define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_LBN 0
7194#define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_WIDTH 11
7195#define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_LBN 11
7196#define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_WIDTH 1
7197
7198/* MC_CMD_RMON_TX_ERRORS_STATS_OUT msgresponse */
7199#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMIN 4
7200#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMAX 252
7201#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LEN(num) (0+4*(num))
7202/* Array of stats */
7203#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_OFST 0
7204#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_LEN 4
7205#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MINNUM 1
7206#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63
7207
7208
7209/***********************************/
7210/* MC_CMD_RMON_TX_OVERFLOW_STATS
7211 * Retrieve rxdp overflow
7212 */
7213#define MC_CMD_RMON_TX_OVERFLOW_STATS 0xde
7214
7215/* MC_CMD_RMON_TX_OVERFLOW_STATS_IN msgrequest */
7216#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_LEN 4
7217/* flags */
7218#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_FLAGS_OFST 0
7219#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_LBN 0
7220#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_WIDTH 8
7221#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_LBN 8
7222#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_WIDTH 1
7223
7224/* MC_CMD_RMON_TX_OVERFLOW_STATS_OUT msgresponse */
7225#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMIN 4
7226#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMAX 252
7227#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num))
7228/* Array of stats */
7229#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_OFST 0
7230#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_LEN 4
7231#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1
7232#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63
7233
7234
7235/***********************************/
7236/* MC_CMD_RMON_COLLECT_CLASS_STATS
7237 * Explicitly collect class stats at the specified evb port
7238 */
7239#define MC_CMD_RMON_COLLECT_CLASS_STATS 0xdf
7240
7241/* MC_CMD_RMON_COLLECT_CLASS_STATS_IN msgrequest */
7242#define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_LEN 4
7243/* The port id associated with the vport/pport at which to collect class stats
7244 */
7245#define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_PORT_ID_OFST 0
7246
7247/* MC_CMD_RMON_COLLECT_CLASS_STATS_OUT msgresponse */
7248#define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_LEN 4
7249/* class */
7250#define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_CLASS_OFST 0
7251
7252
7253/***********************************/
7254/* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS
7255 * Explicitly collect class stats at the specified evb port
7256 */
7257#define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS 0xe0
7258
7259/* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN msgrequest */
7260#define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_LEN 4
7261/* The port id associated with the vport/pport at which to collect class stats
7262 */
7263#define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_PORT_ID_OFST 0
7264
7265/* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT msgresponse */
7266#define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_LEN 4
7267/* super_class */
7268#define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_SUPER_CLASS_OFST 0
7269
7270
7271/***********************************/
7272/* MC_CMD_GET_CLOCK
7273 * Return the system and PDCPU clock frequencies.
7274 */
7275#define MC_CMD_GET_CLOCK 0xac
7276
Shradha Shah75122ec2015-05-20 11:08:23 +01007277#define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7278
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007279/* MC_CMD_GET_CLOCK_IN msgrequest */
7280#define MC_CMD_GET_CLOCK_IN_LEN 0
7281
7282/* MC_CMD_GET_CLOCK_OUT msgresponse */
7283#define MC_CMD_GET_CLOCK_OUT_LEN 8
7284/* System frequency, MHz */
7285#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
7286/* DPCPU frequency, MHz */
7287#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
7288
7289
7290/***********************************/
7291/* MC_CMD_SET_CLOCK
7292 * Control the system and DPCPU clock frequencies. Changes are lost reboot.
7293 */
7294#define MC_CMD_SET_CLOCK 0xad
7295
Shradha Shah75122ec2015-05-20 11:08:23 +01007296#define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7297
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007298/* MC_CMD_SET_CLOCK_IN msgrequest */
7299#define MC_CMD_SET_CLOCK_IN_LEN 12
7300/* Requested system frequency in MHz; 0 leaves unchanged. */
7301#define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0
7302/* Requested inter-core frequency in MHz; 0 leaves unchanged. */
7303#define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4
7304/* Request DPCPU frequency in MHz; 0 leaves unchanged. */
7305#define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8
7306
7307/* MC_CMD_SET_CLOCK_OUT msgresponse */
7308#define MC_CMD_SET_CLOCK_OUT_LEN 12
7309/* Resulting system frequency in MHz */
7310#define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0
7311/* Resulting inter-core frequency in MHz */
7312#define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4
7313/* Resulting DPCPU frequency in MHz */
7314#define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8
7315
7316
7317/***********************************/
7318/* MC_CMD_DPCPU_RPC
7319 * Send an arbitrary DPCPU message.
7320 */
7321#define MC_CMD_DPCPU_RPC 0xae
7322
Shradha Shah75122ec2015-05-20 11:08:23 +01007323#define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7324
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007325/* MC_CMD_DPCPU_RPC_IN msgrequest */
7326#define MC_CMD_DPCPU_RPC_IN_LEN 36
7327#define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0
7328/* enum: RxDPCPU */
7329#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x0
7330/* enum: TxDPCPU0 */
7331#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
7332/* enum: TxDPCPU1 */
7333#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
7334/* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be
7335 * initialised to zero
7336 */
7337#define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4
7338#define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32
7339#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8
7340#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8
7341#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
7342#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
7343#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
7344#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
7345#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
7346#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
7347#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
7348#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
7349#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
7350#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16
7351#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16
7352#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16
7353#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16
7354#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48
7355#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16
7356#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16
7357#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240
7358#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16
7359#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16
7360#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
7361#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
7362#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
7363#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
7364#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
7365#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48
7366#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16
7367#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64
7368#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16
7369#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80
7370#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16
7371#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16
7372#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16
7373#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
7374#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
7375#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
7376#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64
7377#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16
7378#define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12
7379#define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24
7380/* Register data to write. Only valid in write/write-read. */
7381#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16
7382/* Register address. */
7383#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20
7384
7385/* MC_CMD_DPCPU_RPC_OUT msgresponse */
7386#define MC_CMD_DPCPU_RPC_OUT_LEN 36
7387#define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0
7388/* DATA */
7389#define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4
7390#define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32
7391#define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32
7392#define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16
7393#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48
7394#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16
7395#define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12
7396#define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24
7397#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12
7398#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16
7399#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20
7400#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24
7401
7402
7403/***********************************/
7404/* MC_CMD_TRIGGER_INTERRUPT
7405 * Trigger an interrupt by prodding the BIU.
7406 */
7407#define MC_CMD_TRIGGER_INTERRUPT 0xe3
7408
Shradha Shah75122ec2015-05-20 11:08:23 +01007409#define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7410
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007411/* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */
7412#define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
7413/* Interrupt level relative to base for function. */
7414#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
7415
7416/* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */
7417#define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
7418
7419
7420/***********************************/
Ben Hutchings512bb062013-12-04 19:48:07 +00007421/* MC_CMD_CAP_BLK_READ
7422 * Read multiple 64bit words from capture block memory
7423 */
7424#define MC_CMD_CAP_BLK_READ 0xe7
7425
Shradha Shah75122ec2015-05-20 11:08:23 +01007426#define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7427
Ben Hutchings512bb062013-12-04 19:48:07 +00007428/* MC_CMD_CAP_BLK_READ_IN msgrequest */
7429#define MC_CMD_CAP_BLK_READ_IN_LEN 12
7430#define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0
7431#define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4
7432#define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8
7433
7434/* MC_CMD_CAP_BLK_READ_OUT msgresponse */
7435#define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8
7436#define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248
7437#define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))
7438#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
7439#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8
7440#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
7441#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
7442#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
7443#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31
7444
7445
7446/***********************************/
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007447/* MC_CMD_DUMP_DO
7448 * Take a dump of the DUT state
7449 */
7450#define MC_CMD_DUMP_DO 0xe8
7451
Shradha Shah75122ec2015-05-20 11:08:23 +01007452#define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7453
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007454/* MC_CMD_DUMP_DO_IN msgrequest */
7455#define MC_CMD_DUMP_DO_IN_LEN 52
7456#define MC_CMD_DUMP_DO_IN_PADDING_OFST 0
7457#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
7458#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
7459#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
7460#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
7461#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
7462#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
7463#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
7464#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
7465#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
7466#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
7467#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
7468#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
7469#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
7470#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
7471#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
7472#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
7473#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
7474#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
Ben Hutchings512bb062013-12-04 19:48:07 +00007475/* enum: The uart port this command was received over (if using a uart
7476 * transport)
7477 */
7478#define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007479#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
7480#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28
7481#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
7482#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
7483#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
7484/* Enum values, see field(s): */
7485/* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
7486#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
7487#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
7488#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
7489#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
7490#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
7491#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
7492#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
7493#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
7494#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
7495
7496/* MC_CMD_DUMP_DO_OUT msgresponse */
7497#define MC_CMD_DUMP_DO_OUT_LEN 4
7498#define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
7499
7500
7501/***********************************/
7502/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED
7503 * Configure unsolicited dumps
7504 */
7505#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
7506
Shradha Shah75122ec2015-05-20 11:08:23 +01007507#define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7508
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007509/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */
7510#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52
7511#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
7512#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
7513/* Enum values, see field(s): */
7514/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */
7515#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
7516/* Enum values, see field(s): */
7517/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
7518#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
7519#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
7520#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
7521#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
7522#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
7523#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
7524#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
7525#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
7526#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
7527#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28
7528/* Enum values, see field(s): */
7529/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */
7530#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
7531/* Enum values, see field(s): */
7532/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
7533#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
7534#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
7535#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
7536#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
7537#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
7538#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
7539#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
7540#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
7541#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
7542
7543
7544/***********************************/
7545/* MC_CMD_SET_PSU
7546 * Adjusts power supply parameters. This is a warranty-voiding operation.
7547 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if
7548 * the parameter is out of range.
7549 */
7550#define MC_CMD_SET_PSU 0xea
7551
Shradha Shah75122ec2015-05-20 11:08:23 +01007552#define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7553
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007554/* MC_CMD_SET_PSU_IN msgrequest */
7555#define MC_CMD_SET_PSU_IN_LEN 12
7556#define MC_CMD_SET_PSU_IN_PARAM_OFST 0
7557#define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
7558#define MC_CMD_SET_PSU_IN_RAIL_OFST 4
7559#define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
7560#define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
7561/* desired value, eg voltage in mV */
7562#define MC_CMD_SET_PSU_IN_VALUE_OFST 8
7563
7564/* MC_CMD_SET_PSU_OUT msgresponse */
7565#define MC_CMD_SET_PSU_OUT_LEN 0
7566
7567
7568/***********************************/
7569/* MC_CMD_GET_FUNCTION_INFO
7570 * Get function information. PF and VF number.
7571 */
7572#define MC_CMD_GET_FUNCTION_INFO 0xec
7573
Shradha Shah75122ec2015-05-20 11:08:23 +01007574#define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7575
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007576/* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */
7577#define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
7578
7579/* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */
7580#define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8
7581#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
7582#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
7583
7584
7585/***********************************/
7586/* MC_CMD_ENABLE_OFFLINE_BIST
7587 * Enters offline BIST mode. All queues are torn down, chip enters quiescent
7588 * mode, calling function gets exclusive MCDI ownership. The only way out is
7589 * reboot.
7590 */
7591#define MC_CMD_ENABLE_OFFLINE_BIST 0xed
7592
Shradha Shah75122ec2015-05-20 11:08:23 +01007593#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7594
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007595/* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */
7596#define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
7597
7598/* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */
7599#define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
7600
7601
7602/***********************************/
Ben Hutchings512bb062013-12-04 19:48:07 +00007603/* MC_CMD_UART_SEND_DATA
7604 * Send checksummed[sic] block of data over the uart. Response is a placeholder
7605 * should we wish to make this reliable; currently requests are fire-and-
7606 * forget.
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007607 */
Ben Hutchings512bb062013-12-04 19:48:07 +00007608#define MC_CMD_UART_SEND_DATA 0xee
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007609
Shradha Shah75122ec2015-05-20 11:08:23 +01007610#define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7611
Ben Hutchings512bb062013-12-04 19:48:07 +00007612/* MC_CMD_UART_SEND_DATA_OUT msgrequest */
7613#define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16
7614#define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252
7615#define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))
7616/* CRC32 over OFFSET, LENGTH, RESERVED, DATA */
7617#define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0
7618/* Offset at which to write the data */
7619#define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4
7620/* Length of data */
7621#define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8
7622/* Reserved for future use */
7623#define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12
7624#define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16
7625#define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1
7626#define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0
7627#define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007628
Ben Hutchings512bb062013-12-04 19:48:07 +00007629/* MC_CMD_UART_SEND_DATA_IN msgresponse */
7630#define MC_CMD_UART_SEND_DATA_IN_LEN 0
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007631
7632
7633/***********************************/
Ben Hutchings512bb062013-12-04 19:48:07 +00007634/* MC_CMD_UART_RECV_DATA
7635 * Request checksummed[sic] block of data over the uart. Only a placeholder,
7636 * subject to change and not currently implemented.
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007637 */
Ben Hutchings512bb062013-12-04 19:48:07 +00007638#define MC_CMD_UART_RECV_DATA 0xef
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007639
Shradha Shah75122ec2015-05-20 11:08:23 +01007640#define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7641
Ben Hutchings512bb062013-12-04 19:48:07 +00007642/* MC_CMD_UART_RECV_DATA_OUT msgrequest */
7643#define MC_CMD_UART_RECV_DATA_OUT_LEN 16
7644/* CRC32 over OFFSET, LENGTH, RESERVED */
7645#define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0
7646/* Offset from which to read the data */
7647#define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4
7648/* Length of data */
7649#define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8
7650/* Reserved for future use */
7651#define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007652
Ben Hutchings512bb062013-12-04 19:48:07 +00007653/* MC_CMD_UART_RECV_DATA_IN msgresponse */
7654#define MC_CMD_UART_RECV_DATA_IN_LENMIN 16
7655#define MC_CMD_UART_RECV_DATA_IN_LENMAX 252
7656#define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))
7657/* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */
7658#define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0
7659/* Offset at which to write the data */
7660#define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4
7661/* Length of data */
7662#define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8
7663/* Reserved for future use */
7664#define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12
7665#define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16
7666#define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1
7667#define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0
7668#define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007669
7670
7671/***********************************/
7672/* MC_CMD_READ_FUSES
7673 * Read data programmed into the device One-Time-Programmable (OTP) Fuses
7674 */
7675#define MC_CMD_READ_FUSES 0xf0
7676
Shradha Shah75122ec2015-05-20 11:08:23 +01007677#define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7678
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007679/* MC_CMD_READ_FUSES_IN msgrequest */
7680#define MC_CMD_READ_FUSES_IN_LEN 8
7681/* Offset in OTP to read */
7682#define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
7683/* Length of data to read in bytes */
7684#define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
7685
7686/* MC_CMD_READ_FUSES_OUT msgresponse */
7687#define MC_CMD_READ_FUSES_OUT_LENMIN 4
7688#define MC_CMD_READ_FUSES_OUT_LENMAX 252
7689#define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
7690/* Length of returned OTP data in bytes */
7691#define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
7692/* Returned data */
7693#define MC_CMD_READ_FUSES_OUT_DATA_OFST 4
7694#define MC_CMD_READ_FUSES_OUT_DATA_LEN 1
7695#define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
7696#define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248
7697
7698
7699/***********************************/
7700/* MC_CMD_KR_TUNE
7701 * Get or set KR Serdes RXEQ and TX Driver settings
7702 */
7703#define MC_CMD_KR_TUNE 0xf1
7704
Shradha Shah75122ec2015-05-20 11:08:23 +01007705#define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7706
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007707/* MC_CMD_KR_TUNE_IN msgrequest */
7708#define MC_CMD_KR_TUNE_IN_LENMIN 4
7709#define MC_CMD_KR_TUNE_IN_LENMAX 252
7710#define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
7711/* Requested operation */
7712#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
7713#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
7714/* enum: Get current RXEQ settings */
7715#define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
7716/* enum: Override RXEQ settings */
7717#define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
7718/* enum: Get current TX Driver settings */
7719#define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
7720/* enum: Override TX Driver settings */
7721#define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
7722/* enum: Force KR Serdes reset / recalibration */
7723#define MC_CMD_KR_TUNE_IN_RECAL 0x4
Ben Hutchings512bb062013-12-04 19:48:07 +00007724/* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid
7725 * signal.
7726 */
7727#define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
7728/* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The
7729 * caller should call this command repeatedly after starting eye plot, until no
7730 * more data is returned.
7731 */
7732#define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007733/* Align the arguments to 32 bits */
7734#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
7735#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3
7736/* Arguments specific to the operation */
7737#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
7738#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
7739#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
7740#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62
7741
7742/* MC_CMD_KR_TUNE_OUT msgresponse */
7743#define MC_CMD_KR_TUNE_OUT_LEN 0
7744
7745/* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */
7746#define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
7747/* Requested operation */
7748#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
7749#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1
7750/* Align the arguments to 32 bits */
7751#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
7752#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
7753
7754/* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */
7755#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
7756#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252
7757#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
7758/* RXEQ Parameter */
7759#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
7760#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
7761#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
7762#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
7763#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
7764#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
7765/* enum: Attenuation (0-15) */
7766#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
7767/* enum: CTLE Boost (0-15) */
7768#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
7769/* enum: Edge DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
7770#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
7771/* enum: Edge DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
7772#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
7773/* enum: Edge DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
7774#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
7775/* enum: Edge DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
7776#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
7777/* enum: Edge DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
7778#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
7779#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
7780#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3
7781#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
7782#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
7783#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
7784#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
7785#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
7786#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11
7787#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
7788#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
7789#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
7790#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16
7791#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
7792#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
7793#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
7794
7795/* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */
7796#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8
7797#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252
7798#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
7799/* Requested operation */
7800#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
7801#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
7802/* Align the arguments to 32 bits */
7803#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
7804#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
7805/* RXEQ Parameter */
7806#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
7807#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
7808#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
7809#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
7810#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
7811#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
7812/* Enum values, see field(s): */
7813/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */
7814#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
7815#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3
7816/* Enum values, see field(s): */
7817/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */
7818#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11
7819#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
7820#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12
7821#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
7822#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
7823#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
7824#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
7825#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
7826
7827/* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */
7828#define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
7829
Ben Hutchings512bb062013-12-04 19:48:07 +00007830/* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */
7831#define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4
7832/* Requested operation */
7833#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0
7834#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1
7835/* Align the arguments to 32 bits */
7836#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
7837#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
7838
7839/* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */
7840#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
7841#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252
7842#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
7843/* TXEQ Parameter */
7844#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
7845#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
7846#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
7847#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
7848#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
7849#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
7850/* enum: TX Amplitude */
7851#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
7852/* enum: De-Emphasis Tap1 Magnitude (0-7) */
7853#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
7854/* enum: De-Emphasis Tap1 Fine */
7855#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
7856/* enum: De-Emphasis Tap2 Magnitude (0-6) */
7857#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
7858/* enum: De-Emphasis Tap2 Fine */
7859#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
7860/* enum: Pre-Emphasis Magnitude */
7861#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
7862/* enum: Pre-Emphasis Fine */
7863#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
7864/* enum: TX Slew Rate Coarse control */
7865#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
7866/* enum: TX Slew Rate Fine control */
7867#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
7868#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
7869#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3
7870#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
7871#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
7872#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
7873#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
7874#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
7875#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11
7876#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5
7877#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16
7878#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
7879#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24
7880#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8
7881
7882/* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */
7883#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8
7884#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252
7885#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
7886/* Requested operation */
7887#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
7888#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1
7889/* Align the arguments to 32 bits */
7890#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
7891#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
7892/* TXEQ Parameter */
7893#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4
7894#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
7895#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1
7896#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62
7897#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
7898#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8
7899/* Enum values, see field(s): */
7900/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */
7901#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8
7902#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3
7903/* Enum values, see field(s): */
7904/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */
7905#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11
7906#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5
7907#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16
7908#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
7909#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24
7910#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8
7911
7912/* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */
7913#define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0
7914
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007915/* MC_CMD_KR_TUNE_RECAL_IN msgrequest */
7916#define MC_CMD_KR_TUNE_RECAL_IN_LEN 4
7917/* Requested operation */
7918#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
7919#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1
7920/* Align the arguments to 32 bits */
7921#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1
7922#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3
7923
7924/* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */
7925#define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
7926
Ben Hutchings512bb062013-12-04 19:48:07 +00007927/* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */
7928#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8
7929/* Requested operation */
7930#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
7931#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
7932/* Align the arguments to 32 bits */
7933#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
7934#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
7935#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
7936
7937/* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */
7938#define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0
7939
7940/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */
7941#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4
7942/* Requested operation */
7943#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
7944#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
7945/* Align the arguments to 32 bits */
7946#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
7947#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
7948
7949/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */
7950#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
7951#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
7952#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
7953#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
7954#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
7955#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
7956#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
7957
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007958
7959/***********************************/
7960/* MC_CMD_PCIE_TUNE
7961 * Get or set PCIE Serdes RXEQ and TX Driver settings
7962 */
7963#define MC_CMD_PCIE_TUNE 0xf2
7964
Shradha Shah75122ec2015-05-20 11:08:23 +01007965#define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7966
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007967/* MC_CMD_PCIE_TUNE_IN msgrequest */
7968#define MC_CMD_PCIE_TUNE_IN_LENMIN 4
7969#define MC_CMD_PCIE_TUNE_IN_LENMAX 252
7970#define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
7971/* Requested operation */
7972#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
7973#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
7974/* enum: Get current RXEQ settings */
7975#define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
7976/* enum: Override RXEQ settings */
7977#define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
7978/* enum: Get current TX Driver settings */
7979#define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
7980/* enum: Override TX Driver settings */
7981#define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
Ben Hutchings512bb062013-12-04 19:48:07 +00007982/* enum: Start PCIe Serdes Eye diagram plot on a given lane. */
7983#define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5
7984/* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The
7985 * caller should call this command repeatedly after starting eye plot, until no
7986 * more data is returned.
7987 */
7988#define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01007989/* Align the arguments to 32 bits */
7990#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1
7991#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3
7992/* Arguments specific to the operation */
7993#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4
7994#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4
7995#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0
7996#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62
7997
7998/* MC_CMD_PCIE_TUNE_OUT msgresponse */
7999#define MC_CMD_PCIE_TUNE_OUT_LEN 0
8000
8001/* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */
8002#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4
8003/* Requested operation */
8004#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
8005#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
8006/* Align the arguments to 32 bits */
8007#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
8008#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
8009
8010/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */
8011#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4
8012#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252
8013#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
8014/* RXEQ Parameter */
8015#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
8016#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
8017#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
8018#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
8019#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
8020#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
8021/* enum: Attenuation (0-15) */
8022#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
8023/* enum: CTLE Boost (0-15) */
8024#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
8025/* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
8026#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
8027/* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
8028#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
8029/* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
8030#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
8031/* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
8032#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
8033/* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
8034#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
8035#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
8036#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 4
8037#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
8038#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
8039#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
8040#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
8041#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
8042#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
8043#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
8044#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
8045#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x8 /* enum */
8046#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
8047#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 12
8048#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
8049#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
8050
8051/* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */
8052#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4
8053/* Requested operation */
8054#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
8055#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
8056/* Align the arguments to 32 bits */
8057#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
8058#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
8059
8060/* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */
8061#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4
8062#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252
8063#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
8064/* RXEQ Parameter */
8065#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
8066#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
8067#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
8068#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
8069#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
8070#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
8071/* enum: TxMargin (PIPE) */
8072#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
8073/* enum: TxSwing (PIPE) */
8074#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
8075/* enum: De-emphasis coefficient C(-1) (PIPE) */
8076#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
8077/* enum: De-emphasis coefficient C(0) (PIPE) */
8078#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
8079/* enum: De-emphasis coefficient C(+1) (PIPE) */
8080#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
8081#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
8082#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
8083/* Enum values, see field(s): */
8084/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
8085#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12
8086#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12
8087#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24
8088#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
8089
Ben Hutchings512bb062013-12-04 19:48:07 +00008090/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */
8091#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8
8092/* Requested operation */
8093#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
8094#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
8095/* Align the arguments to 32 bits */
8096#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
8097#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
8098#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
8099
8100/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */
8101#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0
8102
8103/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */
8104#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4
8105/* Requested operation */
8106#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
8107#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
8108/* Align the arguments to 32 bits */
8109#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
8110#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3
8111
8112/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */
8113#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
8114#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
8115#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
8116#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
8117#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
8118#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
8119#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
8120
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01008121
8122/***********************************/
8123/* MC_CMD_LICENSING
8124 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
8125 */
8126#define MC_CMD_LICENSING 0xf3
8127
Shradha Shah75122ec2015-05-20 11:08:23 +01008128#define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8129
Ben Hutchingsf2b0bef2013-08-20 20:35:50 +01008130/* MC_CMD_LICENSING_IN msgrequest */
8131#define MC_CMD_LICENSING_IN_LEN 4
8132/* identifies the type of operation requested */
8133#define MC_CMD_LICENSING_IN_OP_OFST 0
8134/* enum: re-read and apply licenses after a license key partition update; note
8135 * that this operation returns a zero-length response
8136 */
8137#define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
8138/* enum: report counts of installed licenses */
8139#define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
8140
8141/* MC_CMD_LICENSING_OUT msgresponse */
8142#define MC_CMD_LICENSING_OUT_LEN 28
8143/* count of application keys which are valid */
8144#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
8145/* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with
8146 * MC_CMD_FC_OP_LICENSE)
8147 */
8148#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
8149/* count of application keys which are invalid due to being blacklisted */
8150#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8
8151/* count of application keys which are invalid due to being unverifiable */
8152#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12
8153/* count of application keys which are invalid due to being for the wrong node
8154 */
8155#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16
8156/* licensing state (for diagnostics; the exact meaning of the bits in this
8157 * field are private to the firmware)
8158 */
8159#define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20
8160/* licensing subsystem self-test report (for manftest) */
8161#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24
8162/* enum: licensing subsystem self-test failed */
8163#define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
8164/* enum: licensing subsystem self-test passed */
8165#define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
8166
8167
8168/***********************************/
8169/* MC_CMD_MC2MC_PROXY
8170 * Execute an arbitrary MCDI command on the slave MC of a dual-core device.
8171 * This will fail on a single-core system.
8172 */
8173#define MC_CMD_MC2MC_PROXY 0xf4
Ben Hutchings05a93202011-12-20 00:44:06 +00008174
Shradha Shah75122ec2015-05-20 11:08:23 +01008175#define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8176
Ben Hutchings512bb062013-12-04 19:48:07 +00008177/* MC_CMD_MC2MC_PROXY_IN msgrequest */
8178#define MC_CMD_MC2MC_PROXY_IN_LEN 0
8179
8180/* MC_CMD_MC2MC_PROXY_OUT msgresponse */
8181#define MC_CMD_MC2MC_PROXY_OUT_LEN 0
8182
8183
8184/***********************************/
8185/* MC_CMD_GET_LICENSED_APP_STATE
8186 * Query the state of an individual licensed application. (Note that the actual
8187 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation
8188 * or a reboot of the MC.)
8189 */
8190#define MC_CMD_GET_LICENSED_APP_STATE 0xf5
8191
Shradha Shah75122ec2015-05-20 11:08:23 +01008192#define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8193
Ben Hutchings512bb062013-12-04 19:48:07 +00008194/* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */
8195#define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
8196/* application ID to query (LICENSED_APP_ID_xxx) */
8197#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
8198
8199/* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */
8200#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
8201/* state of this application */
8202#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
8203/* enum: no (or invalid) license is present for the application */
8204#define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
8205/* enum: a valid license is present for the application */
8206#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
8207
8208
8209/***********************************/
8210/* MC_CMD_LICENSED_APP_OP
8211 * Perform an action for an individual licensed application.
8212 */
8213#define MC_CMD_LICENSED_APP_OP 0xf6
8214
Shradha Shah75122ec2015-05-20 11:08:23 +01008215#define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8216
Ben Hutchings512bb062013-12-04 19:48:07 +00008217/* MC_CMD_LICENSED_APP_OP_IN msgrequest */
8218#define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8
8219#define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252
8220#define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
8221/* application ID */
8222#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
8223/* the type of operation requested */
8224#define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
8225/* enum: validate application */
8226#define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
8227/* arguments specific to this particular operation */
8228#define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8
8229#define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
8230#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
8231#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61
8232
8233/* MC_CMD_LICENSED_APP_OP_OUT msgresponse */
8234#define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
8235#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252
8236#define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
8237/* result specific to this particular operation */
8238#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
8239#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
8240#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
8241#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63
8242
8243/* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */
8244#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72
8245/* application ID */
8246#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0
8247/* the type of operation requested */
8248#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4
8249/* validation challenge */
8250#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8
8251#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64
8252
8253/* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */
8254#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68
8255/* feature expiry (time_t) */
8256#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0
8257/* validation response */
8258#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4
8259#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64
8260
8261
8262/***********************************/
8263/* MC_CMD_SET_PORT_SNIFF_CONFIG
8264 * Configure port sniffing for the physical port associated with the calling
8265 * function. Only a privileged function may change the port sniffing
8266 * configuration. A copy of all traffic delivered to the host (non-promiscuous
8267 * mode) or all traffic arriving at the port (promiscuous mode) may be
8268 * delivered to a specific queue, or a set of queues with RSS.
8269 */
8270#define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
8271
Shradha Shah75122ec2015-05-20 11:08:23 +01008272#define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8273
Ben Hutchings512bb062013-12-04 19:48:07 +00008274/* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */
8275#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16
8276/* configuration flags */
8277#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
8278#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
8279#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
8280#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1
8281#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1
8282/* receive queue handle (for RSS mode, this is the base queue) */
8283#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
8284/* receive mode */
8285#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
8286/* enum: receive to just the specified queue */
8287#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
8288/* enum: receive to multiple queues using RSS context */
8289#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
8290/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
8291 * that these handles should be considered opaque to the host, although a value
8292 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
8293 */
8294#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12
8295
8296/* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */
8297#define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0
8298
8299
8300/***********************************/
8301/* MC_CMD_GET_PORT_SNIFF_CONFIG
8302 * Obtain the current port sniffing configuration for the physical port
8303 * associated with the calling function. Only a privileged function may read
8304 * the configuration.
8305 */
8306#define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
8307
Shradha Shah75122ec2015-05-20 11:08:23 +01008308#define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8309
Ben Hutchings512bb062013-12-04 19:48:07 +00008310/* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */
8311#define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0
8312
8313/* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */
8314#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16
8315/* configuration flags */
8316#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
8317#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
8318#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
8319#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1
8320#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1
8321/* receiving queue handle (for RSS mode, this is the base queue) */
8322#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
8323/* receive mode */
8324#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
8325/* enum: receiving to just the specified queue */
8326#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
8327/* enum: receiving to multiple queues using RSS context */
8328#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
8329/* RSS context (for RX_MODE_RSS) */
8330#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
8331
Ben Hutchings5297a982010-02-03 09:28:14 +00008332
Steve Hodgsonf0d37f42009-11-29 15:15:07 +00008333#endif /* MCDI_PCOL_H */