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gerrit-public.fairphone.software / kernel / msm-5.4 / ab049fbf5ea87fc92441fc5211c315d04a312cca / . / drivers / net / wireless / rtlwifi / rtl8192de / phy.c
blob: 97fb6ca39d73ea3cb245312a88092e1bb318eb6d [file] [log] [blame]
Chaoming Li7274a8c2011-06-10 15:10:25 -0500[diff] [blame]1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "rf.h"
37#include "dm.h"
38#include "table.h"
39#include "sw.h"
40#include "hw.h"
41
42#define MAX_RF_IMR_INDEX 12
43#define MAX_RF_IMR_INDEX_NORMAL 13
44#define RF_REG_NUM_FOR_C_CUT_5G 6
45#define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7
46#define RF_REG_NUM_FOR_C_CUT_2G 5
47#define RF_CHNL_NUM_5G 19
48#define RF_CHNL_NUM_5G_40M 17
49#define TARGET_CHNL_NUM_5G 221
50#define TARGET_CHNL_NUM_2G 14
51#define CV_CURVE_CNT 64
52
53static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
54 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
55};
56
57static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
58 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
59};
60
61static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
62 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
63};
64
65static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
66 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
67};
68
69static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
70 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
71 BIT(10) | BIT(9),
72 BIT(18) | BIT(17) | BIT(16) | BIT(1),
73 BIT(2) | BIT(1),
74 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
75};
76
77static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
78 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
79 112, 116, 120, 124, 128, 132, 136, 140
80};
81
82static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
83 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
84 118, 122, 126, 130, 134, 138
85};
86static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
87 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
88 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
89 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
90 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
91 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
92};
93
94static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
95 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
96 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
97 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
98};
99
100static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
101
102static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
103 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
104 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
105 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
106};
107
108/* [mode][patha+b][reg] */
109static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
110 {
111 /* channel 1-14. */
112 {
113 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
114 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
115 },
116 /* path 36-64 */
117 {
118 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
119 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
120 0x32c9a
121 },
122 /* 100 -165 */
123 {
124 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
125 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
126 }
127 }
128};
129
130static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
131
132static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
133
134static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
135 25141, 25116, 25091, 25066, 25041,
136 25016, 24991, 24966, 24941, 24917,
137 24892, 24867, 24843, 24818, 24794,
138 24770, 24765, 24721, 24697, 24672,
139 24648, 24624, 24600, 24576, 24552,
140 24528, 24504, 24480, 24457, 24433,
141 24409, 24385, 24362, 24338, 24315,
142 24291, 24268, 24245, 24221, 24198,
143 24175, 24151, 24128, 24105, 24082,
144 24059, 24036, 24013, 23990, 23967,
145 23945, 23922, 23899, 23876, 23854,
146 23831, 23809, 23786, 23764, 23741,
147 23719, 23697, 23674, 23652, 23630,
148 23608, 23586, 23564, 23541, 23519,
149 23498, 23476, 23454, 23432, 23410,
150 23388, 23367, 23345, 23323, 23302,
151 23280, 23259, 23237, 23216, 23194,
152 23173, 23152, 23130, 23109, 23088,
153 23067, 23046, 23025, 23003, 22982,
154 22962, 22941, 22920, 22899, 22878,
155 22857, 22837, 22816, 22795, 22775,
156 22754, 22733, 22713, 22692, 22672,
157 22652, 22631, 22611, 22591, 22570,
158 22550, 22530, 22510, 22490, 22469,
159 22449, 22429, 22409, 22390, 22370,
160 22350, 22336, 22310, 22290, 22271,
161 22251, 22231, 22212, 22192, 22173,
162 22153, 22134, 22114, 22095, 22075,
163 22056, 22037, 22017, 21998, 21979,
164 21960, 21941, 21921, 21902, 21883,
165 21864, 21845, 21826, 21807, 21789,
166 21770, 21751, 21732, 21713, 21695,
167 21676, 21657, 21639, 21620, 21602,
168 21583, 21565, 21546, 21528, 21509,
169 21491, 21473, 21454, 21436, 21418,
170 21400, 21381, 21363, 21345, 21327,
171 21309, 21291, 21273, 21255, 21237,
172 21219, 21201, 21183, 21166, 21148,
173 21130, 21112, 21095, 21077, 21059,
174 21042, 21024, 21007, 20989, 20972,
175 25679, 25653, 25627, 25601, 25575,
176 25549, 25523, 25497, 25471, 25446,
177 25420, 25394, 25369, 25343, 25318,
178 25292, 25267, 25242, 25216, 25191,
179 25166
180};
181
182/* channel 1~14 */
183static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
184 26084, 26030, 25976, 25923, 25869, 25816, 25764,
185 25711, 25658, 25606, 25554, 25502, 25451, 25328
186};
187
188static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
189{
190 u32 i;
191
192 for (i = 0; i <= 31; i++) {
193 if (((bitmask >> i) & 0x1) == 1)
194 break;
195 }
196
197 return i;
198}
199
200u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
201{
202 struct rtl_priv *rtlpriv = rtl_priv(hw);
203 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
204 u32 returnvalue, originalvalue, bitshift;
205 u8 dbi_direct;
206
207 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
208 "bitmask(%#x)\n", regaddr, bitmask));
209 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
210 /* mac1 use phy0 read radio_b. */
211 /* mac0 use phy1 read radio_b. */
212 if (rtlhal->during_mac1init_radioa)
213 dbi_direct = BIT(3);
214 else if (rtlhal->during_mac0init_radiob)
215 dbi_direct = BIT(3) | BIT(2);
216 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
217 dbi_direct);
218 } else {
219 originalvalue = rtl_read_dword(rtlpriv, regaddr);
220 }
221 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
222 returnvalue = (originalvalue & bitmask) >> bitshift;
223 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
224 "Addr[0x%x]=0x%x\n", bitmask, regaddr, originalvalue));
225 return returnvalue;
226}
227
228void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
229 u32 regaddr, u32 bitmask, u32 data)
230{
231 struct rtl_priv *rtlpriv = rtl_priv(hw);
232 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
233 u8 dbi_direct = 0;
234 u32 originalvalue, bitshift;
235
236 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
237 " data(%#x)\n", regaddr, bitmask, data));
238 if (rtlhal->during_mac1init_radioa)
239 dbi_direct = BIT(3);
240 else if (rtlhal->during_mac0init_radiob)
241 /* mac0 use phy1 write radio_b. */
242 dbi_direct = BIT(3) | BIT(2);
243 if (bitmask != BMASKDWORD) {
244 if (rtlhal->during_mac1init_radioa ||
245 rtlhal->during_mac0init_radiob)
246 originalvalue = rtl92de_read_dword_dbi(hw,
247 (u16) regaddr,
248 dbi_direct);
249 else
250 originalvalue = rtl_read_dword(rtlpriv, regaddr);
251 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
252 data = ((originalvalue & (~bitmask)) | (data << bitshift));
253 }
254 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
255 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
256 else
257 rtl_write_dword(rtlpriv, regaddr, data);
258 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
259 " data(%#x)\n", regaddr, bitmask, data));
260}
261
262static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
263 enum radio_path rfpath, u32 offset)
264{
265
266 struct rtl_priv *rtlpriv = rtl_priv(hw);
267 struct rtl_phy *rtlphy = &(rtlpriv->phy);
268 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
269 u32 newoffset;
270 u32 tmplong, tmplong2;
271 u8 rfpi_enable = 0;
272 u32 retvalue;
273
274 newoffset = offset;
275 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD);
276 if (rfpath == RF90_PATH_A)
277 tmplong2 = tmplong;
278 else
279 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD);
280 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
281 (newoffset << 23) | BLSSIREADEDGE;
282 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
283 tmplong & (~BLSSIREADEDGE));
284 udelay(10);
285 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD, tmplong2);
286 udelay(50);
287 udelay(50);
288 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
289 tmplong | BLSSIREADEDGE);
290 udelay(10);
291 if (rfpath == RF90_PATH_A)
292 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
293 BIT(8));
294 else if (rfpath == RF90_PATH_B)
295 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
296 BIT(8));
297 if (rfpi_enable)
298 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
299 BLSSIREADBACKDATA);
300 else
301 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
302 BLSSIREADBACKDATA);
303 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x] = 0x%x\n",
304 rfpath, pphyreg->rflssi_readback, retvalue));
305 return retvalue;
306}
307
308static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
309 enum radio_path rfpath,
310 u32 offset, u32 data)
311{
312 u32 data_and_addr;
313 u32 newoffset;
314 struct rtl_priv *rtlpriv = rtl_priv(hw);
315 struct rtl_phy *rtlphy = &(rtlpriv->phy);
316 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
317
318 newoffset = offset;
319 /* T65 RF */
320 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
321 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, BMASKDWORD, data_and_addr);
322 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
323 rfpath, pphyreg->rf3wire_offset, data_and_addr));
324}
325
326u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
327 enum radio_path rfpath, u32 regaddr, u32 bitmask)
328{
329 struct rtl_priv *rtlpriv = rtl_priv(hw);
330 u32 original_value, readback_value, bitshift;
331 unsigned long flags;
332
333 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
334 "rfpath(%#x), bitmask(%#x)\n",
335 regaddr, rfpath, bitmask));
336 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
337 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
338 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
339 readback_value = (original_value & bitmask) >> bitshift;
340 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
341 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), "
342 "bitmask(%#x), original_value(%#x)\n",
343 regaddr, rfpath, bitmask, original_value));
344 return readback_value;
345}
346
347void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
348 u32 regaddr, u32 bitmask, u32 data)
349{
350 struct rtl_priv *rtlpriv = rtl_priv(hw);
351 struct rtl_phy *rtlphy = &(rtlpriv->phy);
352 u32 original_value, bitshift;
353 unsigned long flags;
354
355 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
356 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
357 regaddr, bitmask, data, rfpath));
358 if (bitmask == 0)
359 return;
360 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
361 if (rtlphy->rf_mode != RF_OP_BY_FW) {
362 if (bitmask != BRFREGOFFSETMASK) {
363 original_value = _rtl92d_phy_rf_serial_read(hw,
364 rfpath, regaddr);
365 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
366 data = ((original_value & (~bitmask)) |
367 (data << bitshift));
368 }
369 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
370 }
371 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
372 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
373 "bitmask(%#x), data(%#x), rfpath(%#x)\n",
374 regaddr, bitmask, data, rfpath));
375}
376
377bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
378{
379 struct rtl_priv *rtlpriv = rtl_priv(hw);
380 u32 i;
381 u32 arraylength;
382 u32 *ptrarray;
383
384 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
385 arraylength = MAC_2T_ARRAYLENGTH;
386 ptrarray = rtl8192de_mac_2tarray;
387 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Img:Rtl819XMAC_Array\n"));
388 for (i = 0; i < arraylength; i = i + 2)
389 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
390 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
391 /* improve 2-stream TX EVM */
392 /* rtl_write_byte(rtlpriv, 0x14,0x71); */
393 /* AMPDU aggregation number 9 */
394 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
395 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
396 } else {
397 /* 92D need to test to decide the num. */
398 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
399 }
400 return true;
401}
402
403static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
404{
405 struct rtl_priv *rtlpriv = rtl_priv(hw);
406 struct rtl_phy *rtlphy = &(rtlpriv->phy);
407
408 /* RF Interface Sowrtware Control */
409 /* 16 LSBs if read 32-bit from 0x870 */
410 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
411 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
412 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
413 /* 16 LSBs if read 32-bit from 0x874 */
414 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
415 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
416
417 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
418 /* RF Interface Readback Value */
419 /* 16 LSBs if read 32-bit from 0x8E0 */
420 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
421 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
422 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
423 /* 16 LSBs if read 32-bit from 0x8E4 */
424 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
425 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
426 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
427
428 /* RF Interface Output (and Enable) */
429 /* 16 LSBs if read 32-bit from 0x860 */
430 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
431 /* 16 LSBs if read 32-bit from 0x864 */
432 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
433
434 /* RF Interface (Output and) Enable */
435 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
436 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
437 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
438 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
439
440 /* Addr of LSSI. Wirte RF register by driver */
441 /* LSSI Parameter */
442 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
443 RFPGA0_XA_LSSIPARAMETER;
444 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
445 RFPGA0_XB_LSSIPARAMETER;
446
447 /* RF parameter */
448 /* BB Band Select */
449 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
450 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
451 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
452 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
453
454 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
455 /* Tx gain stage */
456 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
457 /* Tx gain stage */
458 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
459 /* Tx gain stage */
460 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
461 /* Tx gain stage */
462 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
463
464 /* Tranceiver A~D HSSI Parameter-1 */
465 /* wire control parameter1 */
466 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
467 /* wire control parameter1 */
468 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
469
470 /* Tranceiver A~D HSSI Parameter-2 */
471 /* wire control parameter2 */
472 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
473 /* wire control parameter2 */
474 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
475
476 /* RF switch Control */
477 /* TR/Ant switch control */
478 rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
479 RFPGA0_XAB_SWITCHCONTROL;
480 rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
481 RFPGA0_XAB_SWITCHCONTROL;
482 rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
483 RFPGA0_XCD_SWITCHCONTROL;
484 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
485 RFPGA0_XCD_SWITCHCONTROL;
486
487 /* AGC control 1 */
488 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
489 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
490 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
491 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
492
493 /* AGC control 2 */
494 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
495 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
496 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
497 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
498
499 /* RX AFE control 1 */
500 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
501 ROFDM0_XARXIQIMBALANCE;
502 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
503 ROFDM0_XBRXIQIMBALANCE;
504 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
505 ROFDM0_XCRXIQIMBALANCE;
506 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
507 ROFDM0_XDRXIQIMBALANCE;
508
509 /*RX AFE control 1 */
510 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
511 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
512 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
513 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
514
515 /* Tx AFE control 1 */
516 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
517 ROFDM0_XATxIQIMBALANCE;
518 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
519 ROFDM0_XBTxIQIMBALANCE;
520 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
521 ROFDM0_XCTxIQIMBALANCE;
522 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
523 ROFDM0_XDTxIQIMBALANCE;
524
525 /* Tx AFE control 2 */
526 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;
527 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;
528 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;
529 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;
530
531 /* Tranceiver LSSI Readback SI mode */
532 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
533 RFPGA0_XA_LSSIREADBACK;
534 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
535 RFPGA0_XB_LSSIREADBACK;
536 rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
537 RFPGA0_XC_LSSIREADBACK;
538 rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
539 RFPGA0_XD_LSSIREADBACK;
540
541 /* Tranceiver LSSI Readback PI mode */
542 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
543 TRANSCEIVERA_HSPI_READBACK;
544 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
545 TRANSCEIVERB_HSPI_READBACK;
546}
547
548static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
549 u8 configtype)
550{
551 int i;
552 u32 *phy_regarray_table;
553 u32 *agctab_array_table = NULL;
554 u32 *agctab_5garray_table;
555 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
556 struct rtl_priv *rtlpriv = rtl_priv(hw);
557 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
558
559 /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
560 if (rtlhal->interfaceindex == 0) {
561 agctab_arraylen = AGCTAB_ARRAYLENGTH;
562 agctab_array_table = rtl8192de_agctab_array;
563 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
564 (" ===> phy:MAC0, Rtl819XAGCTAB_Array\n"));
565 } else {
566 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
567 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
568 agctab_array_table = rtl8192de_agctab_2garray;
569 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
570 (" ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"));
571 } else {
572 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
573 agctab_5garray_table = rtl8192de_agctab_5garray;
574 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
575 (" ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"));
576
577 }
578 }
579 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
580 phy_regarray_table = rtl8192de_phy_reg_2tarray;
581 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
582 (" ===> phy:Rtl819XPHY_REG_Array_PG\n"));
583 if (configtype == BASEBAND_CONFIG_PHY_REG) {
584 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
585 if (phy_regarray_table[i] == 0xfe)
586 mdelay(50);
587 else if (phy_regarray_table[i] == 0xfd)
588 mdelay(5);
589 else if (phy_regarray_table[i] == 0xfc)
590 mdelay(1);
591 else if (phy_regarray_table[i] == 0xfb)
592 udelay(50);
593 else if (phy_regarray_table[i] == 0xfa)
594 udelay(5);
595 else if (phy_regarray_table[i] == 0xf9)
596 udelay(1);
597 rtl_set_bbreg(hw, phy_regarray_table[i], BMASKDWORD,
598 phy_regarray_table[i + 1]);
599 udelay(1);
600 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
601 ("The phy_regarray_table[0] is %x"
602 " Rtl819XPHY_REGArray[1] is %x\n",
603 phy_regarray_table[i],
604 phy_regarray_table[i + 1]));
605 }
606 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
607 if (rtlhal->interfaceindex == 0) {
608 for (i = 0; i < agctab_arraylen; i = i + 2) {
609 rtl_set_bbreg(hw, agctab_array_table[i],
610 BMASKDWORD,
611 agctab_array_table[i + 1]);
612 /* Add 1us delay between BB/RF register
613 * setting. */
614 udelay(1);
615 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
616 ("The Rtl819XAGCTAB_Array_"
617 "Table[0] is %ul "
618 "Rtl819XPHY_REGArray[1] is %ul\n",
619 agctab_array_table[i],
620 agctab_array_table[i + 1]));
621 }
622 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
623 ("Normal Chip, MAC0, load "
624 "Rtl819XAGCTAB_Array\n"));
625 } else {
626 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
627 for (i = 0; i < agctab_arraylen; i = i + 2) {
628 rtl_set_bbreg(hw, agctab_array_table[i],
629 BMASKDWORD,
630 agctab_array_table[i + 1]);
631 /* Add 1us delay between BB/RF register
632 * setting. */
633 udelay(1);
634 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
635 ("The Rtl819XAGCTAB_Array_"
636 "Table[0] is %ul Rtl819XPHY_"
637 "REGArray[1] is %ul\n",
638 agctab_array_table[i],
639 agctab_array_table[i + 1]));
640 }
641 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
642 ("Load Rtl819XAGCTAB_2GArray\n"));
643 } else {
644 for (i = 0; i < agctab_5garraylen; i = i + 2) {
645 rtl_set_bbreg(hw,
646 agctab_5garray_table[i],
647 BMASKDWORD,
648 agctab_5garray_table[i + 1]);
649 /* Add 1us delay between BB/RF registeri
650 * setting. */
651 udelay(1);
652 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
653 ("The Rtl819XAGCTAB_5GArray_"
654 "Table[0] is %ul Rtl819XPHY_"
655 "REGArray[1] is %ul\n",
656 agctab_5garray_table[i],
657 agctab_5garray_table[i + 1]));
658 }
659 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
660 ("Load Rtl819XAGCTAB_5GArray\n"));
661 }
662 }
663 }
664 return true;
665}
666
667static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
668 u32 regaddr, u32 bitmask,
669 u32 data)
670{
671 struct rtl_priv *rtlpriv = rtl_priv(hw);
672 struct rtl_phy *rtlphy = &(rtlpriv->phy);
673
674 if (regaddr == RTXAGC_A_RATE18_06) {
675 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
676 data;
677 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
678 ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%ulx\n",
679 rtlphy->pwrgroup_cnt,
680 rtlphy->mcs_txpwrlevel_origoffset
681 [rtlphy->pwrgroup_cnt][0]));
682 }
683 if (regaddr == RTXAGC_A_RATE54_24) {
684 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
685 data;
686 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
687 ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%ulx\n",
688 rtlphy->pwrgroup_cnt,
689 rtlphy->mcs_txpwrlevel_origoffset
690 [rtlphy->pwrgroup_cnt][1]));
691 }
692 if (regaddr == RTXAGC_A_CCK1_MCS32) {
693 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
694 data;
695 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
696 ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%ulx\n",
697 rtlphy->pwrgroup_cnt,
698 rtlphy->mcs_txpwrlevel_origoffset
699 [rtlphy->pwrgroup_cnt][6]));
700 }
701 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
702 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
703 data;
704 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
705 ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%ulx\n",
706 rtlphy->pwrgroup_cnt,
707 rtlphy->mcs_txpwrlevel_origoffset
708 [rtlphy->pwrgroup_cnt][7]));
709 }
710 if (regaddr == RTXAGC_A_MCS03_MCS00) {
711 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
712 data;
713 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
714 ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%ulx\n",
715 rtlphy->pwrgroup_cnt,
716 rtlphy->mcs_txpwrlevel_origoffset
717 [rtlphy->pwrgroup_cnt][2]));
718 }
719 if (regaddr == RTXAGC_A_MCS07_MCS04) {
720 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
721 data;
722 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
723 ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%ulx\n",
724 rtlphy->pwrgroup_cnt,
725 rtlphy->mcs_txpwrlevel_origoffset
726 [rtlphy->pwrgroup_cnt][3]));
727 }
728 if (regaddr == RTXAGC_A_MCS11_MCS08) {
729 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
730 data;
731 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
732 ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%ulx\n",
733 rtlphy->pwrgroup_cnt,
734 rtlphy->mcs_txpwrlevel_origoffset
735 [rtlphy->pwrgroup_cnt][4]));
736 }
737 if (regaddr == RTXAGC_A_MCS15_MCS12) {
738 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
739 data;
740 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
741 ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%ulx\n",
742 rtlphy->pwrgroup_cnt,
743 rtlphy->mcs_txpwrlevel_origoffset
744 [rtlphy->pwrgroup_cnt][5]));
745 }
746 if (regaddr == RTXAGC_B_RATE18_06) {
747 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
748 data;
749 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
750 ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%ulx\n",
751 rtlphy->pwrgroup_cnt,
752 rtlphy->mcs_txpwrlevel_origoffset
753 [rtlphy->pwrgroup_cnt][8]));
754 }
755 if (regaddr == RTXAGC_B_RATE54_24) {
756 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
757 data;
758 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
759 ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%ulx\n",
760 rtlphy->pwrgroup_cnt,
761 rtlphy->mcs_txpwrlevel_origoffset
762 [rtlphy->pwrgroup_cnt][9]));
763 }
764 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
765 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
766 data;
767 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
768 ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%ulx\n",
769 rtlphy->pwrgroup_cnt,
770 rtlphy->mcs_txpwrlevel_origoffset
771 [rtlphy->pwrgroup_cnt][14]));
772 }
773 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
774 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
775 data;
776 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
777 ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%ulx\n",
778 rtlphy->pwrgroup_cnt,
779 rtlphy->mcs_txpwrlevel_origoffset
780 [rtlphy->pwrgroup_cnt][15]));
781 }
782 if (regaddr == RTXAGC_B_MCS03_MCS00) {
783 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
784 data;
785 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
786 ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%ulx\n",
787 rtlphy->pwrgroup_cnt,
788 rtlphy->mcs_txpwrlevel_origoffset
789 [rtlphy->pwrgroup_cnt][10]));
790 }
791 if (regaddr == RTXAGC_B_MCS07_MCS04) {
792 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
793 data;
794 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
795 ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%ulx\n",
796 rtlphy->pwrgroup_cnt,
797 rtlphy->mcs_txpwrlevel_origoffset
798 [rtlphy->pwrgroup_cnt][11]));
799 }
800 if (regaddr == RTXAGC_B_MCS11_MCS08) {
801 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
802 data;
803 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
804 ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%ulx\n",
805 rtlphy->pwrgroup_cnt,
806 rtlphy->mcs_txpwrlevel_origoffset
807 [rtlphy->pwrgroup_cnt][12]));
808 }
809 if (regaddr == RTXAGC_B_MCS15_MCS12) {
810 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
811 data;
812 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
813 ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%ulx\n",
814 rtlphy->pwrgroup_cnt,
815 rtlphy->mcs_txpwrlevel_origoffset
816 [rtlphy->pwrgroup_cnt][13]));
817 rtlphy->pwrgroup_cnt++;
818 }
819}
820
821static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
822 u8 configtype)
823{
824 struct rtl_priv *rtlpriv = rtl_priv(hw);
825 int i;
826 u32 *phy_regarray_table_pg;
827 u16 phy_regarray_pg_len;
828
829 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
830 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
831 if (configtype == BASEBAND_CONFIG_PHY_REG) {
832 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
833 if (phy_regarray_table_pg[i] == 0xfe)
834 mdelay(50);
835 else if (phy_regarray_table_pg[i] == 0xfd)
836 mdelay(5);
837 else if (phy_regarray_table_pg[i] == 0xfc)
838 mdelay(1);
839 else if (phy_regarray_table_pg[i] == 0xfb)
840 udelay(50);
841 else if (phy_regarray_table_pg[i] == 0xfa)
842 udelay(5);
843 else if (phy_regarray_table_pg[i] == 0xf9)
844 udelay(1);
845 _rtl92d_store_pwrindex_diffrate_offset(hw,
846 phy_regarray_table_pg[i],
847 phy_regarray_table_pg[i + 1],
848 phy_regarray_table_pg[i + 2]);
849 }
850 } else {
851 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
852 ("configtype != BaseBand_Config_PHY_REG\n"));
853 }
854 return true;
855}
856
857static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
858{
859 struct rtl_priv *rtlpriv = rtl_priv(hw);
860 struct rtl_phy *rtlphy = &(rtlpriv->phy);
861 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
862 bool rtstatus = true;
863
864 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n"));
865 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
866 BASEBAND_CONFIG_PHY_REG);
867 if (rtstatus != true) {
868 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
869 return false;
870 }
871
872 /* if (rtlphy->rf_type == RF_1T2R) {
873 * _rtl92c_phy_bb_config_1t(hw);
874 * RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n"));
875 *} */
876
877 if (rtlefuse->autoload_failflag == false) {
878 rtlphy->pwrgroup_cnt = 0;
879 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
880 BASEBAND_CONFIG_PHY_REG);
881 }
882 if (rtstatus != true) {
883 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
884 return false;
885 }
886 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
887 BASEBAND_CONFIG_AGC_TAB);
888 if (rtstatus != true) {
889 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
890 return false;
891 }
892 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
893 RFPGA0_XA_HSSIPARAMETER2, 0x200));
894
895 return true;
896}
897
898bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
899{
900 struct rtl_priv *rtlpriv = rtl_priv(hw);
901 u16 regval;
902 u32 regvaldw;
903 u8 value;
904
905 _rtl92d_phy_init_bb_rf_register_definition(hw);
906 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
907 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
908 regval | BIT(13) | BIT(0) | BIT(1));
909 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
910 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
911 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
912 value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
913 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
914 RF_SDMRSTB);
915 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
916 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
917 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
918 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
919 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
920 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
921 }
922
923 return _rtl92d_phy_bb_config(hw);
924}
925
926bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
927{
928 return rtl92d_phy_rf6052_config(hw);
929}
930
931bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
932 enum rf_content content,
933 enum radio_path rfpath)
934{
935 int i, j;
936 u32 *radioa_array_table;
937 u32 *radiob_array_table;
938 u16 radioa_arraylen, radiob_arraylen;
939 struct rtl_priv *rtlpriv = rtl_priv(hw);
940
941 radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
942 radioa_array_table = rtl8192de_radioa_2tarray;
943 radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
944 radiob_array_table = rtl8192de_radiob_2tarray;
945 if (rtlpriv->efuse.internal_pa_5g[0]) {
946 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
947 radioa_array_table = rtl8192de_radioa_2t_int_paarray;
948 }
949 if (rtlpriv->efuse.internal_pa_5g[1]) {
950 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
951 radiob_array_table = rtl8192de_radiob_2t_int_paarray;
952 }
953 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
954 ("PHY_ConfigRFWithHeaderFile() "
955 "Radio_A:Rtl819XRadioA_1TArray\n"));
956 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
957 ("PHY_ConfigRFWithHeaderFile() "
958 "Radio_B:Rtl819XRadioB_1TArray\n"));
959 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
960
961 /* this only happens when DMDP, mac0 start on 2.4G,
962 * mac1 start on 5G, mac 0 has to set phy0&phy1
963 * pathA or mac1 has to set phy0&phy1 pathA */
964 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
965 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
966 (" ===> althougth Path A, we load radiob.txt\n"));
967 radioa_arraylen = radiob_arraylen;
968 radioa_array_table = radiob_array_table;
969 }
970 switch (rfpath) {
971 case RF90_PATH_A:
972 for (i = 0; i < radioa_arraylen; i = i + 2) {
973 if (radioa_array_table[i] == 0xfe) {
974 mdelay(50);
975 } else if (radioa_array_table[i] == 0xfd) {
976 /* delay_ms(5); */
977 for (j = 0; j < 100; j++)
978 udelay(MAX_STALL_TIME);
979 } else if (radioa_array_table[i] == 0xfc) {
980 /* delay_ms(1); */
981 for (j = 0; j < 20; j++)
982 udelay(MAX_STALL_TIME);
983
984 } else if (radioa_array_table[i] == 0xfb) {
985 udelay(50);
986 } else if (radioa_array_table[i] == 0xfa) {
987 udelay(5);
988 } else if (radioa_array_table[i] == 0xf9) {
989 udelay(1);
990 } else {
991 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
992 BRFREGOFFSETMASK,
993 radioa_array_table[i + 1]);
994 /* Add 1us delay between BB/RF register set. */
995 udelay(1);
996 }
997 }
998 break;
999 case RF90_PATH_B:
1000 for (i = 0; i < radiob_arraylen; i = i + 2) {
1001 if (radiob_array_table[i] == 0xfe) {
1002 /* Delay specific ms. Only RF configuration
1003 * requires delay. */
1004 mdelay(50);
1005 } else if (radiob_array_table[i] == 0xfd) {
1006 /* delay_ms(5); */
1007 for (j = 0; j < 100; j++)
1008 udelay(MAX_STALL_TIME);
1009 } else if (radiob_array_table[i] == 0xfc) {
1010 /* delay_ms(1); */
1011 for (j = 0; j < 20; j++)
1012 udelay(MAX_STALL_TIME);
1013 } else if (radiob_array_table[i] == 0xfb) {
1014 udelay(50);
1015 } else if (radiob_array_table[i] == 0xfa) {
1016 udelay(5);
1017 } else if (radiob_array_table[i] == 0xf9) {
1018 udelay(1);
1019 } else {
1020 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
1021 BRFREGOFFSETMASK,
1022 radiob_array_table[i + 1]);
1023 /* Add 1us delay between BB/RF register set. */
1024 udelay(1);
1025 }
1026 }
1027 break;
1028 case RF90_PATH_C:
1029 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1030 ("switch case not process\n"));
1031 break;
1032 case RF90_PATH_D:
1033 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1034 ("switch case not process\n"));
1035 break;
1036 }
1037 return true;
1038}
1039
1040void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1041{
1042 struct rtl_priv *rtlpriv = rtl_priv(hw);
1043 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1044
1045 rtlphy->default_initialgain[0] =
1046 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, BMASKBYTE0);
1047 rtlphy->default_initialgain[1] =
1048 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, BMASKBYTE0);
1049 rtlphy->default_initialgain[2] =
1050 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, BMASKBYTE0);
1051 rtlphy->default_initialgain[3] =
1052 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, BMASKBYTE0);
1053 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1054 ("Default initial gain (c50=0x%x, "
1055 "c58=0x%x, c60=0x%x, c68=0x%x\n",
1056 rtlphy->default_initialgain[0],
1057 rtlphy->default_initialgain[1],
1058 rtlphy->default_initialgain[2],
1059 rtlphy->default_initialgain[3]));
1060 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
1061 BMASKBYTE0);
1062 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1063 BMASKDWORD);
1064 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1065 ("Default framesync (0x%x) = 0x%x\n",
1066 ROFDM0_RXDETECTOR3, rtlphy->framesync));
1067}
1068
1069static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1070 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1071{
1072 struct rtl_priv *rtlpriv = rtl_priv(hw);
1073 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1074 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1075 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1076 u8 index = (channel - 1);
1077
1078 /* 1. CCK */
1079 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1080 /* RF-A */
1081 cckpowerlevel[RF90_PATH_A] =
1082 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
1083 /* RF-B */
1084 cckpowerlevel[RF90_PATH_B] =
1085 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
1086 } else {
1087 cckpowerlevel[RF90_PATH_A] = 0;
1088 cckpowerlevel[RF90_PATH_B] = 0;
1089 }
1090 /* 2. OFDM for 1S or 2S */
1091 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1092 /* Read HT 40 OFDM TX power */
1093 ofdmpowerlevel[RF90_PATH_A] =
1094 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
1095 ofdmpowerlevel[RF90_PATH_B] =
1096 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
1097 } else if (rtlphy->rf_type == RF_2T2R) {
1098 /* Read HT 40 OFDM TX power */
1099 ofdmpowerlevel[RF90_PATH_A] =
1100 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
1101 ofdmpowerlevel[RF90_PATH_B] =
1102 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
1103 }
1104}
1105
1106static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
1107 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1108{
1109 struct rtl_priv *rtlpriv = rtl_priv(hw);
1110 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1111
1112 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1113 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1114}
1115
1116static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
1117{
1118 u8 channel_5g[59] = {
1119 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1120 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1121 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1122 114, 116, 118, 120, 122, 124, 126, 128,
1123 130, 132, 134, 136, 138, 140, 149, 151,
1124 153, 155, 157, 159, 161, 163, 165
1125 };
1126 u8 place = chnl;
1127
1128 if (chnl > 14) {
1129 for (place = 14; place < sizeof(channel_5g); place++) {
1130 if (channel_5g[place] == chnl) {
1131 place++;
1132 break;
1133 }
1134 }
1135 }
1136 return place;
1137}
1138
1139void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1140{
1141 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1142 struct rtl_priv *rtlpriv = rtl_priv(hw);
1143 u8 cckpowerlevel[2], ofdmpowerlevel[2];
1144
1145 if (rtlefuse->txpwr_fromeprom == false)
1146 return;
1147 channel = _rtl92c_phy_get_rightchnlplace(channel);
1148 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
1149 &ofdmpowerlevel[0]);
1150 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1151 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
1152 &ofdmpowerlevel[0]);
1153 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1154 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
1155 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
1156}
1157
1158void rtl92d_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1159{
1160 struct rtl_priv *rtlpriv = rtl_priv(hw);
1161 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1162 enum io_type iotype;
1163
1164 if (!is_hal_stop(rtlhal)) {
1165 switch (operation) {
1166 case SCAN_OPT_BACKUP:
1167 rtlhal->current_bandtypebackup =
1168 rtlhal->current_bandtype;
1169 iotype = IO_CMD_PAUSE_DM_BY_SCAN;
1170 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1171 (u8 *)&iotype);
1172 break;
1173 case SCAN_OPT_RESTORE:
1174 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1175 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1176 (u8 *)&iotype);
1177 break;
1178 default:
1179 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1180 ("Unknown Scan Backup operation.\n"));
1181 break;
1182 }
1183 }
1184}
1185
1186void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
1187 enum nl80211_channel_type ch_type)
1188{
1189 struct rtl_priv *rtlpriv = rtl_priv(hw);
1190 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1192 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1193 unsigned long flag = 0;
1194 u8 reg_prsr_rsc;
1195 u8 reg_bw_opmode;
1196
1197 if (rtlphy->set_bwmode_inprogress)
1198 return;
1199 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
1200 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1201 ("FALSE driver sleep or unload\n"));
1202 return;
1203 }
1204 rtlphy->set_bwmode_inprogress = true;
1205 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1206 ("Switch to %s bandwidth\n",
1207 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1208 "20MHz" : "40MHz"));
1209 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1210 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1211 switch (rtlphy->current_chan_bw) {
1212 case HT_CHANNEL_WIDTH_20:
1213 reg_bw_opmode |= BW_OPMODE_20MHZ;
1214 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1215 break;
1216 case HT_CHANNEL_WIDTH_20_40:
1217 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1218 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1219
1220 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1221 (mac->cur_40_prime_sc << 5);
1222 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1223 break;
1224 default:
1225 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1226 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1227 break;
1228 }
1229 switch (rtlphy->current_chan_bw) {
1230 case HT_CHANNEL_WIDTH_20:
1231 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1232 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1233 /* SET BIT10 BIT11 for receive cck */
1234 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1235 BIT(11), 3);
1236 break;
1237 case HT_CHANNEL_WIDTH_20_40:
1238 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1239 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1240 /* Set Control channel to upper or lower.
1241 * These settings are required only for 40MHz */
1242 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1243 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1244 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
1245 (mac->cur_40_prime_sc >> 1));
1246 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1247 }
1248 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1249 /* SET BIT10 BIT11 for receive cck */
1250 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1251 BIT(11), 0);
1252 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1253 (mac->cur_40_prime_sc ==
1254 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1255 break;
1256 default:
1257 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1258 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1259 break;
1260
1261 }
1262 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1263 rtlphy->set_bwmode_inprogress = false;
1264 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
1265}
1266
1267static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1268{
1269 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1270 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1271 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x00);
1272 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1273}
1274
1275static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1276{
1277 struct rtl_priv *rtlpriv = rtl_priv(hw);
1278 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1279 u8 i, value8;
1280
1281 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("==>\n"));
1282 rtlhal->bandset = band;
1283 rtlhal->current_bandtype = band;
1284 if (IS_92D_SINGLEPHY(rtlhal->version))
1285 rtlhal->bandset = BAND_ON_BOTH;
1286 /* stop RX/Tx */
1287 _rtl92d_phy_stop_trx_before_changeband(hw);
1288 /* reconfig BB/RF according to wireless mode */
1289 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1290 /* BB & RF Config */
1291 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, ("====>2.4G\n"));
1292 if (rtlhal->interfaceindex == 1)
1293 _rtl92d_phy_config_bb_with_headerfile(hw,
1294 BASEBAND_CONFIG_AGC_TAB);
1295 } else {
1296 /* 5G band */
1297 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, ("====>5G\n"));
1298 if (rtlhal->interfaceindex == 1)
1299 _rtl92d_phy_config_bb_with_headerfile(hw,
1300 BASEBAND_CONFIG_AGC_TAB);
1301 }
1302 rtl92d_update_bbrf_configuration(hw);
1303 if (rtlhal->current_bandtype == BAND_ON_2_4G)
1304 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1305 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1306
1307 /* 20M BW. */
1308 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1309 rtlhal->reloadtxpowerindex = true;
1310 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1311 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1312 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1313 0 ? REG_MAC0 : REG_MAC1));
1314 value8 |= BIT(1);
1315 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1316 0 ? REG_MAC0 : REG_MAC1), value8);
1317 } else {
1318 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1319 0 ? REG_MAC0 : REG_MAC1));
1320 value8 &= (~BIT(1));
1321 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1322 0 ? REG_MAC0 : REG_MAC1), value8);
1323 }
1324 for (i = 0; i < 20; i++)
1325 udelay(MAX_STALL_TIME);
1326 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("<==Switch Band OK.\n"));
1327}
1328
1329static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1330 u8 channel, u8 rfpath)
1331{
1332 struct rtl_priv *rtlpriv = rtl_priv(hw);
1333 u32 imr_num = MAX_RF_IMR_INDEX;
1334 u32 rfmask = BRFREGOFFSETMASK;
1335 u8 group, i;
1336 unsigned long flag = 0;
1337
1338 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>path %d\n", rfpath));
1339 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1340 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>5G\n"));
1341 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1342 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1343 /* fc area 0xd2c */
1344 if (channel > 99)
1345 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1346 BIT(14), 2);
1347 else
1348 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1349 BIT(14), 1);
1350 /* leave 0 for channel1-14. */
1351 group = channel <= 64 ? 1 : 2;
1352 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1353 for (i = 0; i < imr_num; i++)
1354 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1355 rf_reg_for_5g_swchnl_normal[i], rfmask,
1356 rf_imr_param_normal[0][group][i]);
1357 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1358 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1359 } else {
1360 /* G band. */
1361 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1362 ("Load RF IMR parameters for G band. IMR already "
1363 "setting %d\n",
1364 rtlpriv->rtlhal.load_imrandiqk_setting_for2g));
1365 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>2.4G\n"));
1366 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1367 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1368 ("Load RF IMR parameters "
1369 "for G band. %d\n", rfpath));
1370 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1371 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1372 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1373 0x00f00000, 0xf);
1374 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1375 for (i = 0; i < imr_num; i++) {
1376 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1377 rf_reg_for_5g_swchnl_normal[i],
1378 BRFREGOFFSETMASK,
1379 rf_imr_param_normal[0][0][i]);
1380 }
1381 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1382 0x00f00000, 0);
1383 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1384 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1385 }
1386 }
1387 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
1388}
1389
1390static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1391 u8 rfpath, u32 *pu4_regval)
1392{
1393 struct rtl_priv *rtlpriv = rtl_priv(hw);
1394 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1395 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1396
1397 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("====>\n"));
1398 /*----Store original RFENV control type----*/
1399 switch (rfpath) {
1400 case RF90_PATH_A:
1401 case RF90_PATH_C:
1402 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1403 break;
1404 case RF90_PATH_B:
1405 case RF90_PATH_D:
1406 *pu4_regval =
1407 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1408 break;
1409 }
1410 /*----Set RF_ENV enable----*/
1411 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1412 udelay(1);
1413 /*----Set RF_ENV output high----*/
1414 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1415 udelay(1);
1416 /* Set bit number of Address and Data for RF register */
1417 /* Set 1 to 4 bits for 8255 */
1418 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1419 udelay(1);
1420 /*Set 0 to 12 bits for 8255 */
1421 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1422 udelay(1);
1423 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<====\n"));
1424}
1425
1426static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1427 u32 *pu4_regval)
1428{
1429 struct rtl_priv *rtlpriv = rtl_priv(hw);
1430 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1431 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1432
1433 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("=====>\n"));
1434 /*----Restore RFENV control type----*/ ;
1435 switch (rfpath) {
1436 case RF90_PATH_A:
1437 case RF90_PATH_C:
1438 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1439 break;
1440 case RF90_PATH_B:
1441 case RF90_PATH_D:
1442 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1443 *pu4_regval);
1444 break;
1445 }
1446 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<=====\n"));
1447}
1448
1449static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1450{
1451 struct rtl_priv *rtlpriv = rtl_priv(hw);
1452 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1453 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1454 u8 path = rtlhal->current_bandtype ==
1455 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1456 u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1457 bool need_pwr_down = false, internal_pa = false;
1458 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1459
1460 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>\n"));
1461 /* config path A for 5G */
1462 if (rtlhal->current_bandtype == BAND_ON_5G) {
1463 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>5G\n"));
1464 u4tmp = curveindex_5g[channel - 1];
1465 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ver 1 set RF-A, 5G, "
1466 "0x28 = 0x%x !!\n", u4tmp));
1467 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1468 if (channel == rf_chnl_5g[i] && channel <= 140)
1469 index = 0;
1470 }
1471 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1472 if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1473 index = 1;
1474 }
1475 if (channel == 149 || channel == 155 || channel == 161)
1476 index = 2;
1477 else if (channel == 151 || channel == 153 || channel == 163
1478 || channel == 165)
1479 index = 3;
1480 else if (channel == 157 || channel == 159)
1481 index = 4;
1482
1483 if (rtlhal->macphymode == DUALMAC_DUALPHY
1484 && rtlhal->interfaceindex == 1) {
1485 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1486 rtlhal->during_mac1init_radioa = true;
1487 /* asume no this case */
1488 if (need_pwr_down)
1489 _rtl92d_phy_enable_rf_env(hw, path,
1490 &u4regvalue);
1491 }
1492 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1493 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1494 rtl_set_rfreg(hw, (enum radio_path)path,
1495 rf_reg_for_c_cut_5g[i],
1496 BRFREGOFFSETMASK, 0xE439D);
1497 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1498 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1499 0x7FF) | (u4tmp << 11);
1500 if (channel == 36)
1501 u4tmp2 &= ~(BIT(7) | BIT(6));
1502 rtl_set_rfreg(hw, (enum radio_path)path,
1503 rf_reg_for_c_cut_5g[i],
1504 BRFREGOFFSETMASK, u4tmp2);
1505 } else {
1506 rtl_set_rfreg(hw, (enum radio_path)path,
1507 rf_reg_for_c_cut_5g[i],
1508 BRFREGOFFSETMASK,
1509 rf_reg_pram_c_5g[index][i]);
1510 }
1511 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1512 ("offset 0x%x value 0x%x "
1513 "path %d index %d readback 0x%x\n",
1514 rf_reg_for_c_cut_5g[i],
1515 rf_reg_pram_c_5g[index][i], path,
1516 index, rtl_get_rfreg(hw, (enum radio_path)path,
1517 rf_reg_for_c_cut_5g[i], BRFREGOFFSETMASK)));
1518 }
1519 if (need_pwr_down)
1520 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1521 if (rtlhal->during_mac1init_radioa)
1522 rtl92d_phy_powerdown_anotherphy(hw, false);
1523 if (channel < 149)
1524 value = 0x07;
1525 else if (channel >= 149)
1526 value = 0x02;
1527 if (channel >= 36 && channel <= 64)
1528 index = 0;
1529 else if (channel >= 100 && channel <= 140)
1530 index = 1;
1531 else
1532 index = 2;
1533 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1534 rfpath++) {
1535 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1536 rtlhal->interfaceindex == 1) /* MAC 1 5G */
1537 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1538 else
1539 internal_pa =
1540 rtlpriv->efuse.internal_pa_5g[rfpath];
1541 if (internal_pa) {
1542 for (i = 0;
1543 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1544 i++) {
1545 rtl_set_rfreg(hw, rfpath,
1546 rf_for_c_cut_5g_internal_pa[i],
1547 BRFREGOFFSETMASK,
1548 rf_pram_c_5g_int_pa[index][i]);
1549 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1550 ("offset 0x%x value 0x%x "
1551 "path %d index %d\n",
1552 rf_for_c_cut_5g_internal_pa[i],
1553 rf_pram_c_5g_int_pa[index][i],
1554 rfpath, index));
1555 }
1556 } else {
1557 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1558 mask, value);
1559 }
1560 }
1561 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1562 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>2.4G\n"));
1563 u4tmp = curveindex_2g[channel - 1];
1564 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ver 3 set RF-B, 2G, "
1565 "0x28 = 0x%x !!\n", u4tmp));
1566 if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1567 || channel == 10 || channel == 11 || channel == 12)
1568 index = 0;
1569 else if (channel == 3 || channel == 13 || channel == 14)
1570 index = 1;
1571 else if (channel >= 5 && channel <= 8)
1572 index = 2;
1573 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1574 path = RF90_PATH_A;
1575 if (rtlhal->interfaceindex == 0) {
1576 need_pwr_down =
1577 rtl92d_phy_enable_anotherphy(hw, true);
1578 rtlhal->during_mac0init_radiob = true;
1579
1580 if (need_pwr_down)
1581 _rtl92d_phy_enable_rf_env(hw, path,
1582 &u4regvalue);
1583 }
1584 }
1585 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1586 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1587 rtl_set_rfreg(hw, (enum radio_path)path,
1588 rf_reg_for_c_cut_2g[i],
1589 BRFREGOFFSETMASK,
1590 (rf_reg_param_for_c_cut_2g[index][i] |
1591 BIT(17)));
1592 else
1593 rtl_set_rfreg(hw, (enum radio_path)path,
1594 rf_reg_for_c_cut_2g[i],
1595 BRFREGOFFSETMASK,
1596 rf_reg_param_for_c_cut_2g
1597 [index][i]);
1598 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1599 ("offset 0x%x value 0x%x mak 0x%x path %d "
1600 "index %d readback 0x%x\n",
1601 rf_reg_for_c_cut_2g[i],
1602 rf_reg_param_for_c_cut_2g[index][i],
1603 rf_reg_mask_for_c_cut_2g[i], path, index,
1604 rtl_get_rfreg(hw, (enum radio_path)path,
1605 rf_reg_for_c_cut_2g[i],
1606 BRFREGOFFSETMASK)));
1607 }
1608 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1609 ("cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1610 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)));
1611
1612 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1613 BRFREGOFFSETMASK,
1614 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1615 if (need_pwr_down)
1616 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1617 if (rtlhal->during_mac0init_radiob)
1618 rtl92d_phy_powerdown_anotherphy(hw, true);
1619 }
1620 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
1621}
1622
1623u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1624{
1625 u8 channel_all[59] = {
1626 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1627 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1628 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1629 114, 116, 118, 120, 122, 124, 126, 128, 130,
1630 132, 134, 136, 138, 140, 149, 151, 153, 155,
1631 157, 159, 161, 163, 165
1632 };
1633 u8 place = chnl;
1634
1635 if (chnl > 14) {
1636 for (place = 14; place < sizeof(channel_all); place++) {
1637 if (channel_all[place] == chnl)
1638 return place - 13;
1639 }
1640 }
1641
1642 return 0;
1643}
1644
1645#define MAX_TOLERANCE 5
1646#define IQK_DELAY_TIME 1 /* ms */
1647#define MAX_TOLERANCE_92D 3
1648
1649/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1650static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1651{
1652 struct rtl_priv *rtlpriv = rtl_priv(hw);
1653 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1654 u32 regeac, rege94, rege9c, regea4;
1655 u8 result = 0;
1656
1657 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK!\n"));
1658 /* path-A IQK setting */
1659 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1660 if (rtlhal->interfaceindex == 0) {
1661 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c1f);
1662 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c1f);
1663 } else {
1664 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c22);
1665 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c22);
1666 }
1667 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140102);
1668 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x28160206);
1669 /* path-B IQK setting */
1670 if (configpathb) {
1671 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x10008c22);
1672 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x10008c22);
1673 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140102);
1674 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x28160206);
1675 }
1676 /* LO calibration setting */
1677 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1678 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1679 /* One shot, path A LOK & IQK */
1680 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
1681 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1682 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1683 /* delay x ms */
1684 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1685 ("Delay %d ms for One shot, path A LOK & IQK.\n",
1686 IQK_DELAY_TIME));
1687 udelay(IQK_DELAY_TIME * 1000);
1688 /* Check failed */
1689 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1690 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1691 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1692 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe94 = 0x%x\n", rege94));
1693 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1694 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe9c = 0x%x\n", rege9c));
1695 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1696 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regea4));
1697 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1698 (((rege9c & 0x03FF0000) >> 16) != 0x42))
1699 result |= 0x01;
1700 else /* if Tx not OK, ignore Rx */
1701 return result;
1702 /* if Tx is OK, check whether Rx is OK */
1703 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1704 (((regeac & 0x03FF0000) >> 16) != 0x36))
1705 result |= 0x02;
1706 else
1707 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
1708 return result;
1709}
1710
1711/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1712static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1713 bool configpathb)
1714{
1715 struct rtl_priv *rtlpriv = rtl_priv(hw);
1716 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1717 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1718 u32 regeac, rege94, rege9c, regea4;
1719 u8 result = 0;
1720 u8 i;
1721 u8 retrycount = 2;
1722 u32 TxOKBit = BIT(28), RxOKBit = BIT(27);
1723
1724 if (rtlhal->interfaceindex == 1) { /* PHY1 */
1725 TxOKBit = BIT(31);
1726 RxOKBit = BIT(30);
1727 }
1728 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK!\n"));
1729 /* path-A IQK setting */
1730 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1731 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1732 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1733 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140307);
1734 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68160960);
1735 /* path-B IQK setting */
1736 if (configpathb) {
1737 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1738 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1739 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82110000);
1740 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68110000);
1741 }
1742 /* LO calibration setting */
1743 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1744 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1745 /* path-A PA on */
1746 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x07000f60);
1747 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD, 0x66e60e30);
1748 for (i = 0; i < retrycount; i++) {
1749 /* One shot, path A LOK & IQK */
1750 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1751 ("One shot, path A LOK & IQK!\n"));
1752 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1753 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1754 /* delay x ms */
1755 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1756 ("Delay %d ms for One shot, path A LOK & IQK.\n",
1757 IQK_DELAY_TIME));
1758 udelay(IQK_DELAY_TIME * 1000 * 10);
1759 /* Check failed */
1760 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1761 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1762 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1763 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe94 = 0x%x\n", rege94));
1764 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1765 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe9c = 0x%x\n", rege9c));
1766 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1767 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regea4));
1768 if (!(regeac & TxOKBit) &&
1769 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1770 result |= 0x01;
1771 } else { /* if Tx not OK, ignore Rx */
1772 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1773 ("Path A Tx IQK fail!!\n"));
1774 continue;
1775 }
1776
1777 /* if Tx is OK, check whether Rx is OK */
1778 if (!(regeac & RxOKBit) &&
1779 (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1780 result |= 0x02;
1781 break;
1782 } else {
1783 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1784 ("Path A Rx IQK fail!!\n"));
1785 }
1786 }
1787 /* path A PA off */
1788 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1789 rtlphy->iqk_bb_backup[0]);
1790 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD,
1791 rtlphy->iqk_bb_backup[1]);
1792 return result;
1793}
1794
1795/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1796static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1797{
1798 struct rtl_priv *rtlpriv = rtl_priv(hw);
1799 u32 regeac, regeb4, regebc, regec4, regecc;
1800 u8 result = 0;
1801
1802 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQK!\n"));
1803 /* One shot, path B LOK & IQK */
1804 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
1805 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000002);
1806 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000000);
1807 /* delay x ms */
1808 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1809 ("Delay %d ms for One shot, path B LOK & IQK.\n",
1810 IQK_DELAY_TIME));
1811 udelay(IQK_DELAY_TIME * 1000);
1812 /* Check failed */
1813 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1814 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1815 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1816 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regeb4));
1817 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1818 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xebc = 0x%x\n", regebc));
1819 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1820 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regec4));
1821 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1822 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xecc = 0x%x\n", regecc));
1823 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1824 (((regebc & 0x03FF0000) >> 16) != 0x42))
1825 result |= 0x01;
1826 else
1827 return result;
1828 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1829 (((regecc & 0x03FF0000) >> 16) != 0x36))
1830 result |= 0x02;
1831 else
1832 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n"));
1833 return result;
1834}
1835
1836/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1837static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1838{
1839 struct rtl_priv *rtlpriv = rtl_priv(hw);
1840 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1841 u32 regeac, regeb4, regebc, regec4, regecc;
1842 u8 result = 0;
1843 u8 i;
1844 u8 retrycount = 2;
1845
1846 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQK!\n"));
1847 /* path-A IQK setting */
1848 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1849 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1850 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1851 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82110000);
1852 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68110000);
1853
1854 /* path-B IQK setting */
1855 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1856 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1857 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140307);
1858 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68160960);
1859
1860 /* LO calibration setting */
1861 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1862 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1863
1864 /* path-B PA on */
1865 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x0f600700);
1866 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD, 0x061f0d30);
1867
1868 for (i = 0; i < retrycount; i++) {
1869 /* One shot, path B LOK & IQK */
1870 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1871 ("One shot, path A LOK & IQK!\n"));
1872 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xfa000000);
1873 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1874
1875 /* delay x ms */
1876 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1877 ("Delay %d ms for One shot, path B LOK & IQK.\n", 10));
1878 udelay(IQK_DELAY_TIME * 1000 * 10);
1879
1880 /* Check failed */
1881 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1882 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1883 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1884 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regeb4));
1885 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1886 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xebc = 0x%x\n", regebc));
1887 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1888 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regec4));
1889 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1890 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xecc = 0x%x\n", regecc));
1891 if (!(regeac & BIT(31)) &&
1892 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1893 result |= 0x01;
1894 else
1895 continue;
1896 if (!(regeac & BIT(30)) &&
1897 (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1898 result |= 0x02;
1899 break;
1900 } else {
1901 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1902 ("Path B Rx IQK fail!!\n"));
1903 }
1904 }
1905
1906 /* path B PA off */
1907 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1908 rtlphy->iqk_bb_backup[0]);
1909 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD,
1910 rtlphy->iqk_bb_backup[2]);
1911 return result;
1912}
1913
1914static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1915 u32 *adda_reg, u32 *adda_backup,
1916 u32 regnum)
1917{
1918 struct rtl_priv *rtlpriv = rtl_priv(hw);
1919 u32 i;
1920
1921 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
1922 for (i = 0; i < regnum; i++)
1923 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], BMASKDWORD);
1924}
1925
1926static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1927 u32 *macreg, u32 *macbackup)
1928{
1929 struct rtl_priv *rtlpriv = rtl_priv(hw);
1930 u32 i;
1931
1932 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Save MAC parameters.\n"));
1933 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1934 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1935 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1936}
1937
1938static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1939 u32 *adda_reg, u32 *adda_backup,
1940 u32 regnum)
1941{
1942 struct rtl_priv *rtlpriv = rtl_priv(hw);
1943 u32 i;
1944
1945 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1946 ("Reload ADDA power saving parameters !\n"));
1947 for (i = 0; i < regnum; i++)
1948 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, adda_backup[i]);
1949}
1950
1951static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1952 u32 *macreg, u32 *macbackup)
1953{
1954 struct rtl_priv *rtlpriv = rtl_priv(hw);
1955 u32 i;
1956
1957 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Reload MAC parameters !\n"));
1958 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1959 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1960 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1961}
1962
1963static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1964 u32 *adda_reg, bool patha_on, bool is2t)
1965{
1966 struct rtl_priv *rtlpriv = rtl_priv(hw);
1967 u32 pathon;
1968 u32 i;
1969
1970 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ADDA ON.\n"));
1971 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1972 if (patha_on)
1973 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1974 0x04db25a4 : 0x0b1b25a4;
1975 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1976 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, pathon);
1977}
1978
1979static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1980 u32 *macreg, u32 *macbackup)
1981{
1982 struct rtl_priv *rtlpriv = rtl_priv(hw);
1983 u32 i;
1984
1985 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("MAC settings for Calibration.\n"));
1986 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1987
1988 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1989 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1990 (~BIT(3))));
1991 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1992}
1993
1994static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1995{
1996 struct rtl_priv *rtlpriv = rtl_priv(hw);
1997 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A standby mode!\n"));
1998
1999 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x0);
2000 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 0x00010000);
2001 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2002}
2003
2004static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
2005{
2006 struct rtl_priv *rtlpriv = rtl_priv(hw);
2007 u32 mode;
2008
2009 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2010 ("BB Switch to %s mode!\n", (pi_mode ? "PI" : "SI")));
2011 mode = pi_mode ? 0x01000100 : 0x01000000;
2012 rtl_set_bbreg(hw, 0x820, BMASKDWORD, mode);
2013 rtl_set_bbreg(hw, 0x828, BMASKDWORD, mode);
2014}
2015
2016static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2017 u8 t, bool is2t)
2018{
2019 struct rtl_priv *rtlpriv = rtl_priv(hw);
2020 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2021 u32 i;
2022 u8 patha_ok, pathb_ok;
2023 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
2024 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
2025 0xe78, 0xe7c, 0xe80, 0xe84,
2026 0xe88, 0xe8c, 0xed0, 0xed4,
2027 0xed8, 0xedc, 0xee0, 0xeec
2028 };
2029 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2030 0x522, 0x550, 0x551, 0x040
2031 };
2032 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2033 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
2034 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
2035 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
2036 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
2037 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
2038 };
2039 const u32 retrycount = 2;
2040 u32 bbvalue;
2041
2042 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK for 2.4G :Start!!!\n"));
2043 if (t == 0) {
2044 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
2045 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("==>0x%08x\n", bbvalue));
2046 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQ Calibration for %s\n",
2047 (is2t ? "2T2R" : "1T1R")));
2048
2049 /* Save ADDA parameters, turn Path A ADDA on */
2050 _rtl92d_phy_save_adda_registers(hw, adda_reg,
2051 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
2052 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
2053 rtlphy->iqk_mac_backup);
2054 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2055 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
2056 }
2057 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
2058 if (t == 0)
2059 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2060 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2061
2062 /* Switch BB to PI mode to do IQ Calibration. */
2063 if (!rtlphy->rfpi_enable)
2064 _rtl92d_phy_pimode_switch(hw, true);
2065
2066 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2067 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
2068 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
2069 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22204000);
2070 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2071 if (is2t) {
2072 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD,
2073 0x00010000);
2074 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, BMASKDWORD,
2075 0x00010000);
2076 }
2077 /* MAC settings */
2078 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2079 rtlphy->iqk_mac_backup);
2080 /* Page B init */
2081 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
2082 if (is2t)
2083 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2084 /* IQ calibration setting */
2085 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK setting!\n"));
2086 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2087 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x01007c00);
2088 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
2089 for (i = 0; i < retrycount; i++) {
2090 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
2091 if (patha_ok == 0x03) {
2092 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2093 ("Path A IQK Success!!\n"));
2094 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2095 0x3FF0000) >> 16;
2096 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2097 0x3FF0000) >> 16;
2098 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
2099 0x3FF0000) >> 16;
2100 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
2101 0x3FF0000) >> 16;
2102 break;
2103 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
2104 /* Tx IQK OK */
2105 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2106 ("Path A IQK Only Tx Success!!\n"));
2107
2108 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2109 0x3FF0000) >> 16;
2110 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2111 0x3FF0000) >> 16;
2112 }
2113 }
2114 if (0x00 == patha_ok)
2115 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK failed!!\n"));
2116 if (is2t) {
2117 _rtl92d_phy_patha_standby(hw);
2118 /* Turn Path B ADDA on */
2119 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2120 for (i = 0; i < retrycount; i++) {
2121 pathb_ok = _rtl92d_phy_pathb_iqk(hw);
2122 if (pathb_ok == 0x03) {
2123 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2124 ("Path B IQK Success!!\n"));
2125 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
2126 BMASKDWORD) & 0x3FF0000) >> 16;
2127 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
2128 BMASKDWORD) & 0x3FF0000) >> 16;
2129 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
2130 BMASKDWORD) & 0x3FF0000) >> 16;
2131 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
2132 BMASKDWORD) & 0x3FF0000) >> 16;
2133 break;
2134 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
2135 /* Tx IQK OK */
2136 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2137 ("Path B Only Tx IQK Success!!\n"));
2138 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
2139 BMASKDWORD) & 0x3FF0000) >> 16;
2140 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
2141 BMASKDWORD) & 0x3FF0000) >> 16;
2142 }
2143 }
2144 if (0x00 == pathb_ok)
2145 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2146 ("Path B IQK failed!!\n"));
2147 }
2148
2149 /* Back to BB mode, load original value */
2150 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2151 ("IQK:Back to BB mode, load original value!\n"));
2152
2153 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2154 if (t != 0) {
2155 /* Switch back BB to SI mode after finish IQ Calibration. */
2156 if (!rtlphy->rfpi_enable)
2157 _rtl92d_phy_pimode_switch(hw, false);
2158 /* Reload ADDA power saving parameters */
2159 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2160 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
2161 /* Reload MAC parameters */
2162 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2163 rtlphy->iqk_mac_backup);
2164 if (is2t)
2165 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2166 rtlphy->iqk_bb_backup,
2167 IQK_BB_REG_NUM);
2168 else
2169 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2170 rtlphy->iqk_bb_backup,
2171 IQK_BB_REG_NUM - 1);
2172 /* load 0xe30 IQC default value */
2173 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x01008c00);
2174 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x01008c00);
2175 }
2176 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("<==\n"));
2177}
2178
2179static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2180 long result[][8], u8 t)
2181{
2182 struct rtl_priv *rtlpriv = rtl_priv(hw);
2183 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2184 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2185 u8 patha_ok, pathb_ok;
2186 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
2187 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
2188 0xe78, 0xe7c, 0xe80, 0xe84,
2189 0xe88, 0xe8c, 0xed0, 0xed4,
2190 0xed8, 0xedc, 0xee0, 0xeec
2191 };
2192 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2193 0x522, 0x550, 0x551, 0x040
2194 };
2195 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2196 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
2197 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
2198 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
2199 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
2200 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
2201 };
2202 u32 bbvalue;
2203 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2204
2205 /* Note: IQ calibration must be performed after loading
2206 * PHY_REG.txt , and radio_a, radio_b.txt */
2207
2208 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK for 5G NORMAL:Start!!!\n"));
2209 udelay(IQK_DELAY_TIME * 1000 * 20);
2210 if (t == 0) {
2211 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
2212 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("==>0x%08x\n", bbvalue));
2213 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQ Calibration for %s\n",
2214 (is2t ? "2T2R" : "1T1R")));
2215 /* Save ADDA parameters, turn Path A ADDA on */
2216 _rtl92d_phy_save_adda_registers(hw, adda_reg,
2217 rtlphy->adda_backup,
2218 IQK_ADDA_REG_NUM);
2219 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
2220 rtlphy->iqk_mac_backup);
2221 if (is2t)
2222 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2223 rtlphy->iqk_bb_backup,
2224 IQK_BB_REG_NUM);
2225 else
2226 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2227 rtlphy->iqk_bb_backup,
2228 IQK_BB_REG_NUM - 1);
2229 }
2230 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
2231 /* MAC settings */
2232 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2233 rtlphy->iqk_mac_backup);
2234 if (t == 0)
2235 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2236 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2237 /* Switch BB to PI mode to do IQ Calibration. */
2238 if (!rtlphy->rfpi_enable)
2239 _rtl92d_phy_pimode_switch(hw, true);
2240 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2241 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
2242 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
2243 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22208000);
2244 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2245
2246 /* Page B init */
2247 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
2248 if (is2t)
2249 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2250 /* IQ calibration setting */
2251 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK setting!\n"));
2252 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2253 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x10007c00);
2254 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
2255 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2256 if (patha_ok == 0x03) {
2257 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK Success!!\n"));
2258 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2259 0x3FF0000) >> 16;
2260 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2261 0x3FF0000) >> 16;
2262 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
2263 0x3FF0000) >> 16;
2264 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
2265 0x3FF0000) >> 16;
2266 } else if (patha_ok == 0x01) { /* Tx IQK OK */
2267 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2268 ("Path A IQK Only Tx Success!!\n"));
2269
2270 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2271 0x3FF0000) >> 16;
2272 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2273 0x3FF0000) >> 16;
2274 } else {
2275 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK Fail!!\n"));
2276 }
2277 if (is2t) {
2278 /* _rtl92d_phy_patha_standby(hw); */
2279 /* Turn Path B ADDA on */
2280 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2281 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2282 if (pathb_ok == 0x03) {
2283 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2284 ("Path B IQK Success!!\n"));
2285 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2286 0x3FF0000) >> 16;
2287 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2288 0x3FF0000) >> 16;
2289 result[t][6] = (rtl_get_bbreg(hw, 0xec4, BMASKDWORD) &
2290 0x3FF0000) >> 16;
2291 result[t][7] = (rtl_get_bbreg(hw, 0xecc, BMASKDWORD) &
2292 0x3FF0000) >> 16;
2293 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2294 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2295 ("Path B Only Tx IQK Success!!\n"));
2296 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2297 0x3FF0000) >> 16;
2298 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2299 0x3FF0000) >> 16;
2300 } else {
2301 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2302 ("Path B IQK failed!!\n"));
2303 }
2304 }
2305
2306 /* Back to BB mode, load original value */
2307 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2308 ("IQK:Back to BB mode, load original value!\n"));
2309 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2310 if (t != 0) {
2311 if (is2t)
2312 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2313 rtlphy->iqk_bb_backup,
2314 IQK_BB_REG_NUM);
2315 else
2316 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2317 rtlphy->iqk_bb_backup,
2318 IQK_BB_REG_NUM - 1);
2319 /* Reload MAC parameters */
2320 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2321 rtlphy->iqk_mac_backup);
2322 /* Switch back BB to SI mode after finish IQ Calibration. */
2323 if (!rtlphy->rfpi_enable)
2324 _rtl92d_phy_pimode_switch(hw, false);
2325 /* Reload ADDA power saving parameters */
2326 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2327 rtlphy->adda_backup,
2328 IQK_ADDA_REG_NUM);
2329 }
2330 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("<==\n"));
2331}
2332
2333static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2334 long result[][8], u8 c1, u8 c2)
2335{
2336 struct rtl_priv *rtlpriv = rtl_priv(hw);
2337 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2338 u32 i, j, diff, sim_bitmap, bound;
2339 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
2340 bool bresult = true;
2341 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2342
2343 if (is2t)
2344 bound = 8;
2345 else
2346 bound = 4;
2347 sim_bitmap = 0;
2348 for (i = 0; i < bound; i++) {
2349 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2350 result[c2][i]) : (result[c2][i] - result[c1][i]);
2351 if (diff > MAX_TOLERANCE_92D) {
2352 if ((i == 2 || i == 6) && !sim_bitmap) {
2353 if (result[c1][i] + result[c1][i + 1] == 0)
2354 final_candidate[(i / 4)] = c2;
2355 else if (result[c2][i] + result[c2][i + 1] == 0)
2356 final_candidate[(i / 4)] = c1;
2357 else
2358 sim_bitmap = sim_bitmap | (1 << i);
2359 } else {
2360 sim_bitmap = sim_bitmap | (1 << i);
2361 }
2362 }
2363 }
2364 if (sim_bitmap == 0) {
2365 for (i = 0; i < (bound / 4); i++) {
2366 if (final_candidate[i] != 0xFF) {
2367 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2368 result[3][j] =
2369 result[final_candidate[i]][j];
2370 bresult = false;
2371 }
2372 }
2373 return bresult;
2374 }
2375 if (!(sim_bitmap & 0x0F)) { /* path A OK */
2376 for (i = 0; i < 4; i++)
2377 result[3][i] = result[c1][i];
2378 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2379 for (i = 0; i < 2; i++)
2380 result[3][i] = result[c1][i];
2381 }
2382 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2383 for (i = 4; i < 8; i++)
2384 result[3][i] = result[c1][i];
2385 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2386 for (i = 4; i < 6; i++)
2387 result[3][i] = result[c1][i];
2388 }
2389 return false;
2390}
2391
2392static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2393 bool iqk_ok, long result[][8],
2394 u8 final_candidate, bool txonly)
2395{
2396 struct rtl_priv *rtlpriv = rtl_priv(hw);
2397 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2398 u32 oldval_0, val_x, tx0_a, reg;
2399 long val_y, tx0_c;
2400 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2401 rtlhal->macphymode == DUALMAC_DUALPHY;
2402
2403 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2404 ("Path A IQ Calibration %s !\n",
2405 (iqk_ok) ? "Success" : "Failed"));
2406 if (final_candidate == 0xFF) {
2407 return;
2408 } else if (iqk_ok) {
2409 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2410 BMASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
2411 val_x = result[final_candidate][0];
2412 if ((val_x & 0x00000200) != 0)
2413 val_x = val_x | 0xFFFFFC00;
2414 tx0_a = (val_x * oldval_0) >> 8;
2415 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("X = 0x%x, tx0_a = 0x%x,"
2416 " oldval_0 0x%x\n", val_x, tx0_a, oldval_0));
2417 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2418 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2419 ((val_x * oldval_0 >> 7) & 0x1));
2420 val_y = result[final_candidate][1];
2421 if ((val_y & 0x00000200) != 0)
2422 val_y = val_y | 0xFFFFFC00;
2423 /* path B IQK result + 3 */
2424 if (rtlhal->interfaceindex == 1 &&
2425 rtlhal->current_bandtype == BAND_ON_5G)
2426 val_y += 3;
2427 tx0_c = (val_y * oldval_0) >> 8;
2428 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Y = 0x%lx, tx0_c = 0x%lx\n",
2429 val_y, tx0_c));
2430 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2431 ((tx0_c & 0x3C0) >> 6));
2432 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
2433 (tx0_c & 0x3F));
2434 if (is2t)
2435 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2436 ((val_y * oldval_0 >> 7) & 0x1));
2437 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xC80 = 0x%x\n",
2438 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2439 BMASKDWORD)));
2440 if (txonly) {
2441 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("only Tx OK\n"));
2442 return;
2443 }
2444 reg = result[final_candidate][2];
2445 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2446 reg = result[final_candidate][3] & 0x3F;
2447 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2448 reg = (result[final_candidate][3] >> 6) & 0xF;
2449 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2450 }
2451}
2452
2453static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2454 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2455{
2456 struct rtl_priv *rtlpriv = rtl_priv(hw);
2457 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2458 u32 oldval_1, val_x, tx1_a, reg;
2459 long val_y, tx1_c;
2460
2461 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",
2462 (iqk_ok) ? "Success" : "Failed"));
2463 if (final_candidate == 0xFF) {
2464 return;
2465 } else if (iqk_ok) {
2466 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2467 BMASKDWORD) >> 22) & 0x3FF;
2468 val_x = result[final_candidate][4];
2469 if ((val_x & 0x00000200) != 0)
2470 val_x = val_x | 0xFFFFFC00;
2471 tx1_a = (val_x * oldval_1) >> 8;
2472 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("X = 0x%x, tx1_a = 0x%x\n",
2473 val_x, tx1_a));
2474 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2475 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2476 ((val_x * oldval_1 >> 7) & 0x1));
2477 val_y = result[final_candidate][5];
2478 if ((val_y & 0x00000200) != 0)
2479 val_y = val_y | 0xFFFFFC00;
2480 if (rtlhal->current_bandtype == BAND_ON_5G)
2481 val_y += 3;
2482 tx1_c = (val_y * oldval_1) >> 8;
2483 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Y = 0x%lx, tx1_c = 0x%lx\n",
2484 val_y, tx1_c));
2485 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2486 ((tx1_c & 0x3C0) >> 6));
2487 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
2488 (tx1_c & 0x3F));
2489 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2490 ((val_y * oldval_1 >> 7) & 0x1));
2491 if (txonly)
2492 return;
2493 reg = result[final_candidate][6];
2494 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2495 reg = result[final_candidate][7] & 0x3F;
2496 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2497 reg = (result[final_candidate][7] >> 6) & 0xF;
2498 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2499 }
2500}
2501
2502void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2503{
2504 struct rtl_priv *rtlpriv = rtl_priv(hw);
2505 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2506 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2507 long result[4][8];
2508 u8 i, final_candidate, indexforchannel;
2509 bool patha_ok, pathb_ok;
2510 long rege94, rege9c, regea4, regeac, regeb4;
2511 long regebc, regec4, regecc, regtmp = 0;
2512 bool is12simular, is13simular, is23simular;
2513 unsigned long flag = 0;
2514
2515 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2516 ("IQK:Start!!!channel %d\n", rtlphy->current_channel));
2517 for (i = 0; i < 8; i++) {
2518 result[0][i] = 0;
2519 result[1][i] = 0;
2520 result[2][i] = 0;
2521 result[3][i] = 0;
2522 }
2523 final_candidate = 0xff;
2524 patha_ok = false;
2525 pathb_ok = false;
2526 is12simular = false;
2527 is23simular = false;
2528 is13simular = false;
2529 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2530 ("IQK !!!currentband %d\n", rtlhal->current_bandtype));
2531 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2532 for (i = 0; i < 3; i++) {
2533 if (rtlhal->current_bandtype == BAND_ON_5G) {
2534 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2535 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2536 if (IS_92D_SINGLEPHY(rtlhal->version))
2537 _rtl92d_phy_iq_calibrate(hw, result, i, true);
2538 else
2539 _rtl92d_phy_iq_calibrate(hw, result, i, false);
2540 }
2541 if (i == 1) {
2542 is12simular = _rtl92d_phy_simularity_compare(hw, result,
2543 0, 1);
2544 if (is12simular) {
2545 final_candidate = 0;
2546 break;
2547 }
2548 }
2549 if (i == 2) {
2550 is13simular = _rtl92d_phy_simularity_compare(hw, result,
2551 0, 2);
2552 if (is13simular) {
2553 final_candidate = 0;
2554 break;
2555 }
2556 is23simular = _rtl92d_phy_simularity_compare(hw, result,
2557 1, 2);
2558 if (is23simular) {
2559 final_candidate = 1;
2560 } else {
2561 for (i = 0; i < 8; i++)
2562 regtmp += result[3][i];
2563
2564 if (regtmp != 0)
2565 final_candidate = 3;
2566 else
2567 final_candidate = 0xFF;
2568 }
2569 }
2570 }
2571 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2572 for (i = 0; i < 4; i++) {
2573 rege94 = result[i][0];
2574 rege9c = result[i][1];
2575 regea4 = result[i][2];
2576 regeac = result[i][3];
2577 regeb4 = result[i][4];
2578 regebc = result[i][5];
2579 regec4 = result[i][6];
2580 regecc = result[i][7];
2581 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2582 ("IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx "
2583 "regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n ",
2584 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2585 regecc));
2586 }
2587 if (final_candidate != 0xff) {
2588 rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2589 rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2590 regea4 = result[final_candidate][2];
2591 regeac = result[final_candidate][3];
2592 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2593 rtlphy->reg_ebc = regebc = result[final_candidate][5];
2594 regec4 = result[final_candidate][6];
2595 regecc = result[final_candidate][7];
2596 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2597 ("IQK: final_candidate is %x\n", final_candidate));
2598 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2599 ("IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx "
2600 "regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n ",
2601 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2602 regecc));
2603 patha_ok = pathb_ok = true;
2604 } else {
2605 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2606 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */
2607 }
2608 if ((rege94 != 0) /*&&(regea4 != 0) */)
2609 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2610 final_candidate, (regea4 == 0));
2611 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2612 if ((regeb4 != 0) /*&&(regec4 != 0) */)
2613 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2614 final_candidate, (regec4 == 0));
2615 }
2616 if (final_candidate != 0xFF) {
2617 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2618 rtlphy->current_channel);
2619
2620 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2621 rtlphy->iqk_matrix_regsetting[indexforchannel].
2622 value[0][i] = result[final_candidate][i];
2623 rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done =
2624 true;
2625
2626 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2627 ("\nIQK OK indexforchannel %d.\n", indexforchannel));
2628 }
2629}
2630
2631void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2632{
2633 struct rtl_priv *rtlpriv = rtl_priv(hw);
2634 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2635 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2636 u8 indexforchannel;
2637
2638 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("channel %d\n", channel));
2639 /*------Do IQK for normal chip and test chip 5G band------- */
2640 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2641 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
2642 ("indexforchannel %d done %d\n", indexforchannel,
2643 rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done));
2644 if (0 && !rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done &&
2645 rtlphy->need_iqk) {
2646 /* Re Do IQK. */
2647 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2648 ("Do IQK Matrix reg for channel:%d....\n", channel));
2649 rtl92d_phy_iq_calibrate(hw);
2650 } else {
2651 /* Just load the value. */
2652 /* 2G band just load once. */
2653 if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2654 indexforchannel == 0) || indexforchannel > 0) {
2655 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
2656 ("Just Read IQK Matrix reg for channel:%d"
2657 "....\n", channel));
2658 if ((rtlphy->iqk_matrix_regsetting[indexforchannel].
2659 value[0] != NULL)
2660 /*&&(regea4 != 0) */)
2661 _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2662 rtlphy->iqk_matrix_regsetting[
2663 indexforchannel].value, 0,
2664 (rtlphy->iqk_matrix_regsetting[
2665 indexforchannel].value[0][2] == 0));
2666 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2667 if ((rtlphy->iqk_matrix_regsetting[
2668 indexforchannel].value[0][4] != 0)
2669 /*&&(regec4 != 0) */)
2670 _rtl92d_phy_pathb_fill_iqk_matrix(hw,
2671 true,
2672 rtlphy->iqk_matrix_regsetting[
2673 indexforchannel].value, 0,
2674 (rtlphy->iqk_matrix_regsetting[
2675 indexforchannel].value[0][6]
2676 == 0));
2677 }
2678 }
2679 }
2680 rtlphy->need_iqk = false;
2681 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
2682}
2683
2684static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2685{
2686 u32 ret;
2687
2688 if (val1 >= val2)
2689 ret = val1 - val2;
2690 else
2691 ret = val2 - val1;
2692 return ret;
2693}
2694
2695static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2696{
2697
2698 int i;
2699 u8 channel_5g[45] = {
2700 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
2701 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
2702 114, 116, 118, 120, 122, 124, 126, 128, 130, 132,
2703 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
2704 161, 163, 165
2705 };
2706
2707 for (i = 0; i < sizeof(channel_5g); i++)
2708 if (channel == channel_5g[i])
2709 return true;
2710 return false;
2711}
2712
2713static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2714 u32 *targetchnl, u32 * curvecount_val,
2715 bool is5g, u32 *curveindex)
2716{
2717 struct rtl_priv *rtlpriv = rtl_priv(hw);
2718 u32 smallest_abs_val = 0xffffffff, u4tmp;
2719 u8 i, j;
2720 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2721
2722 for (i = 0; i < chnl_num; i++) {
2723 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2724 continue;
2725 curveindex[i] = 0;
2726 for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2727 u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2728 curvecount_val[j]);
2729
2730 if (u4tmp < smallest_abs_val) {
2731 curveindex[i] = j;
2732 smallest_abs_val = u4tmp;
2733 }
2734 }
2735 smallest_abs_val = 0xffffffff;
2736 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("curveindex[%d] = %x\n", i,
2737 curveindex[i]));
2738 }
2739}
2740
2741static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2742 u8 channel)
2743{
2744 struct rtl_priv *rtlpriv = rtl_priv(hw);
2745 u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2746 BAND_ON_5G ? RF90_PATH_A :
2747 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2748 RF90_PATH_B : RF90_PATH_A;
2749 u32 u4tmp = 0, u4regvalue = 0;
2750 bool bneed_powerdown_radio = false;
2751
2752 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("path %d\n", erfpath));
2753 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("band type = %d\n",
2754 rtlpriv->rtlhal.current_bandtype));
2755 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("channel = %d\n", channel));
2756 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2757 u4tmp = curveindex_5g[channel-1];
2758 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2759 ("ver 1 set RF-A, 5G, 0x28 = 0x%ulx !!\n", u4tmp));
2760 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2761 rtlpriv->rtlhal.interfaceindex == 1) {
2762 bneed_powerdown_radio =
2763 rtl92d_phy_enable_anotherphy(hw, false);
2764 rtlpriv->rtlhal.during_mac1init_radioa = true;
2765 /* asume no this case */
2766 if (bneed_powerdown_radio)
2767 _rtl92d_phy_enable_rf_env(hw, erfpath,
2768 &u4regvalue);
2769 }
2770 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2771 if (bneed_powerdown_radio)
2772 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2773 if (rtlpriv->rtlhal.during_mac1init_radioa)
2774 rtl92d_phy_powerdown_anotherphy(hw, false);
2775 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2776 u4tmp = curveindex_2g[channel-1];
2777 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2778 ("ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n", u4tmp));
2779 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2780 rtlpriv->rtlhal.interfaceindex == 0) {
2781 bneed_powerdown_radio =
2782 rtl92d_phy_enable_anotherphy(hw, true);
2783 rtlpriv->rtlhal.during_mac0init_radiob = true;
2784 if (bneed_powerdown_radio)
2785 _rtl92d_phy_enable_rf_env(hw, erfpath,
2786 &u4regvalue);
2787 }
2788 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2789 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2790 ("ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n",
2791 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)));
2792 if (bneed_powerdown_radio)
2793 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2794 if (rtlpriv->rtlhal.during_mac0init_radiob)
2795 rtl92d_phy_powerdown_anotherphy(hw, true);
2796 }
2797 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
2798}
2799
2800static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2801{
2802 struct rtl_priv *rtlpriv = rtl_priv(hw);
2803 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2804 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2805 u8 tmpreg, index, rf_mode[2];
2806 u8 path = is2t ? 2 : 1;
2807 u8 i;
2808 u32 u4tmp, offset;
2809 u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2810 u16 timeout = 800, timecount = 0;
2811
2812 /* Check continuous TX and Packet TX */
2813 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2814 /* if Deal with contisuous TX case, disable all continuous TX */
2815 /* if Deal with Packet TX case, block all queues */
2816 if ((tmpreg & 0x70) != 0)
2817 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2818 else
2819 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2820 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2821 for (index = 0; index < path; index++) {
2822 /* 1. Read original RF mode */
2823 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2824 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2825 /* 2. Set RF mode = standby mode */
2826 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2827 BRFREGOFFSETMASK, 0x010000);
2828 if (rtlpci->init_ready) {
2829 /* switch CV-curve control by LC-calibration */
2830 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2831 BIT(17), 0x0);
2832 /* 4. Set LC calibration begin */
2833 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2834 0x08000, 0x01);
2835 }
2836 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2837 BRFREGOFFSETMASK);
2838 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2839 mdelay(50);
2840 timecount += 50;
2841 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2842 RF_SYN_G6, BRFREGOFFSETMASK);
2843 }
2844 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2845 ("PHY_LCK finish delay for %d ms=2\n", timecount));
2846 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, BRFREGOFFSETMASK);
2847 if (index == 0 && rtlhal->interfaceindex == 0) {
2848 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2849 ("path-A / 5G LCK\n"));
2850 } else {
2851 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2852 ("path-B / 2.4G LCK\n"));
2853 }
2854 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2);
2855 /* Set LC calibration off */
2856 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2857 0x08000, 0x0);
2858 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("set RF 0x18[15] = 0\n"));
2859 /* save Curve-counting number */
2860 for (i = 0; i < CV_CURVE_CNT; i++) {
2861 u32 readval = 0, readval2 = 0;
2862 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2863 0x7f, i);
2864
2865 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2866 BRFREGOFFSETMASK, 0x0);
2867 readval = rtl_get_rfreg(hw, (enum radio_path)index,
2868 0x4F, BRFREGOFFSETMASK);
2869 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2870 /* reg 0x4f [4:0] */
2871 /* reg 0x50 [19:10] */
2872 readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2873 0x50, 0xffc00);
2874 curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2875 readval2);
2876 }
2877 if (index == 0 && rtlhal->interfaceindex == 0)
2878 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2879 curvecount_val,
2880 true, curveindex_5g);
2881 else
2882 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2883 curvecount_val,
2884 false, curveindex_2g);
2885 /* switch CV-curve control mode */
2886 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2887 BIT(17), 0x1);
2888 }
2889
2890 /* Restore original situation */
2891 for (index = 0; index < path; index++) {
2892 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2893 rtl_write_byte(rtlpriv, offset, 0x50);
2894 rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2895 }
2896 if ((tmpreg & 0x70) != 0)
2897 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2898 else /*Deal with Packet TX case */
2899 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2900 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2901 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2902}
2903
2904static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2905{
2906 struct rtl_priv *rtlpriv = rtl_priv(hw);
2907
2908 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("cosa PHY_LCK ver=2\n"));
2909 _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2910}
2911
2912void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2913{
2914 struct rtl_priv *rtlpriv = rtl_priv(hw);
2915 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2916 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2917 u32 timeout = 2000, timecount = 0;
2918
2919 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2920 udelay(50);
2921 timecount += 50;
2922 }
2923
2924 rtlphy->lck_inprogress = true;
2925 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2926 ("LCK:Start!!! currentband %x delay %d ms\n",
2927 rtlhal->current_bandtype, timecount));
2928 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2929 _rtl92d_phy_lc_calibrate(hw, true);
2930 } else {
2931 /* For 1T1R */
2932 _rtl92d_phy_lc_calibrate(hw, false);
2933 }
2934 rtlphy->lck_inprogress = false;
2935 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LCK:Finish!!!\n"));
2936}
2937
2938void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2939{
2940 return;
2941}
2942
2943static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2944 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2945 u32 para1, u32 para2, u32 msdelay)
2946{
2947 struct swchnlcmd *pcmd;
2948
2949 if (cmdtable == NULL) {
2950 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
2951 return false;
2952 }
2953 if (cmdtableidx >= cmdtablesz)
2954 return false;
2955
2956 pcmd = cmdtable + cmdtableidx;
2957 pcmd->cmdid = cmdid;
2958 pcmd->para1 = para1;
2959 pcmd->para2 = para2;
2960 pcmd->msdelay = msdelay;
2961 return true;
2962}
2963
2964void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2965{
2966 struct rtl_priv *rtlpriv = rtl_priv(hw);
2967 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2968 u8 i;
2969
2970 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2971 ("settings regs %d default regs %d\n",
2972 (int)(sizeof(rtlphy->iqk_matrix_regsetting) /
2973 sizeof(struct iqk_matrix_regs)),
2974 IQK_MATRIX_REG_NUM));
2975 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2976 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2977 rtlphy->iqk_matrix_regsetting[i].value[0][0] = 0x100;
2978 rtlphy->iqk_matrix_regsetting[i].value[0][2] = 0x100;
2979 rtlphy->iqk_matrix_regsetting[i].value[0][4] = 0x100;
2980 rtlphy->iqk_matrix_regsetting[i].value[0][6] = 0x100;
2981 rtlphy->iqk_matrix_regsetting[i].value[0][1] = 0x0;
2982 rtlphy->iqk_matrix_regsetting[i].value[0][3] = 0x0;
2983 rtlphy->iqk_matrix_regsetting[i].value[0][5] = 0x0;
2984 rtlphy->iqk_matrix_regsetting[i].value[0][7] = 0x0;
2985 rtlphy->iqk_matrix_regsetting[i].iqk_done = false;
2986 }
2987}
2988
2989static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2990 u8 channel, u8 *stage, u8 *step,
2991 u32 *delay)
2992{
2993 struct rtl_priv *rtlpriv = rtl_priv(hw);
2994 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2995 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2996 u32 precommoncmdcnt;
2997 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2998 u32 postcommoncmdcnt;
2999 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
3000 u32 rfdependcmdcnt;
3001 struct swchnlcmd *currentcmd = NULL;
3002 u8 rfpath;
3003 u8 num_total_rfpath = rtlphy->num_total_rfpath;
3004
3005 precommoncmdcnt = 0;
3006 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
3007 MAX_PRECMD_CNT,
3008 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
3009 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
3010 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
3011 postcommoncmdcnt = 0;
3012 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
3013 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
3014 rfdependcmdcnt = 0;
3015 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
3016 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
3017 RF_CHNLBW, channel, 0);
3018 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
3019 MAX_RFDEPENDCMD_CNT, CMDID_END,
3020 0, 0, 0);
3021
3022 do {
3023 switch (*stage) {
3024 case 0:
3025 currentcmd = &precommoncmd[*step];
3026 break;
3027 case 1:
3028 currentcmd = &rfdependcmd[*step];
3029 break;
3030 case 2:
3031 currentcmd = &postcommoncmd[*step];
3032 break;
3033 }
3034 if (currentcmd->cmdid == CMDID_END) {
3035 if ((*stage) == 2) {
3036 return true;
3037 } else {
3038 (*stage)++;
3039 (*step) = 0;
3040 continue;
3041 }
3042 }
3043 switch (currentcmd->cmdid) {
3044 case CMDID_SET_TXPOWEROWER_LEVEL:
3045 rtl92d_phy_set_txpower_level(hw, channel);
3046 break;
3047 case CMDID_WRITEPORT_ULONG:
3048 rtl_write_dword(rtlpriv, currentcmd->para1,
3049 currentcmd->para2);
3050 break;
3051 case CMDID_WRITEPORT_USHORT:
3052 rtl_write_word(rtlpriv, currentcmd->para1,
3053 (u16)currentcmd->para2);
3054 break;
3055 case CMDID_WRITEPORT_UCHAR:
3056 rtl_write_byte(rtlpriv, currentcmd->para1,
3057 (u8)currentcmd->para2);
3058 break;
3059 case CMDID_RF_WRITEREG:
3060 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
3061 rtlphy->rfreg_chnlval[rfpath] =
3062 ((rtlphy->rfreg_chnlval[rfpath] &
3063 0xffffff00) | currentcmd->para2);
3064 if (rtlpriv->rtlhal.current_bandtype ==
3065 BAND_ON_5G) {
3066 if (currentcmd->para2 > 99)
3067 rtlphy->rfreg_chnlval[rfpath] =
3068 rtlphy->rfreg_chnlval
3069 [rfpath] | (BIT(18));
3070 else
3071 rtlphy->rfreg_chnlval[rfpath] =
3072 rtlphy->rfreg_chnlval
3073 [rfpath] & (~BIT(18));
3074 rtlphy->rfreg_chnlval[rfpath] |=
3075 (BIT(16) | BIT(8));
3076 } else {
3077 rtlphy->rfreg_chnlval[rfpath] &=
3078 ~(BIT(8) | BIT(16) | BIT(18));
3079 }
3080 rtl_set_rfreg(hw, (enum radio_path)rfpath,
3081 currentcmd->para1,
3082 BRFREGOFFSETMASK,
3083 rtlphy->rfreg_chnlval[rfpath]);
3084 _rtl92d_phy_reload_imr_setting(hw, channel,
3085 rfpath);
3086 }
3087 _rtl92d_phy_switch_rf_setting(hw, channel);
3088 /* do IQK when all parameters are ready */
3089 rtl92d_phy_reload_iqk_setting(hw, channel);
3090 break;
3091 default:
3092 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3093 ("switch case not process\n"));
3094 break;
3095 }
3096 break;
3097 } while (true);
3098 (*delay) = currentcmd->msdelay;
3099 (*step)++;
3100 return false;
3101}
3102
3103u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
3104{
3105 struct rtl_priv *rtlpriv = rtl_priv(hw);
3106 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3107 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3108 u32 delay;
3109 u32 timeout = 1000, timecount = 0;
3110 u8 channel = rtlphy->current_channel;
3111 u32 ret_value;
3112
3113 if (rtlphy->sw_chnl_inprogress)
3114 return 0;
3115 if (rtlphy->set_bwmode_inprogress)
3116 return 0;
3117
3118 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
3119 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
3120 ("sw_chnl_inprogress false driver sleep or unload\n"));
3121 return 0;
3122 }
3123 while (rtlphy->lck_inprogress && timecount < timeout) {
3124 mdelay(50);
3125 timecount += 50;
3126 }
3127 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
3128 rtlhal->bandset == BAND_ON_BOTH) {
3129 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3130 BMASKDWORD);
3131 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
3132 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
3133 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
3134 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
3135 }
3136 switch (rtlhal->current_bandtype) {
3137 case BAND_ON_5G:
3138 /* Get first channel error when change between
3139 * 5G and 2.4G band. */
3140 if (channel <= 14)
3141 return 0;
3142 RT_ASSERT((channel > 14), ("5G but channel<=14"));
3143 break;
3144 case BAND_ON_2_4G:
3145 /* Get first channel error when change between
3146 * 5G and 2.4G band. */
3147 if (channel > 14)
3148 return 0;
3149 RT_ASSERT((channel <= 14), ("2G but channel>14"));
3150 break;
3151 default:
3152 RT_ASSERT(false,
3153 ("Invalid WirelessMode(%#x)!!\n",
3154 rtlpriv->mac80211.mode));
3155 break;
3156 }
3157 rtlphy->sw_chnl_inprogress = true;
3158 if (channel == 0)
3159 channel = 1;
3160 rtlphy->sw_chnl_stage = 0;
3161 rtlphy->sw_chnl_step = 0;
3162 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
3163 ("switch to channel%d\n", rtlphy->current_channel));
3164
3165 do {
3166 if (!rtlphy->sw_chnl_inprogress)
3167 break;
3168 if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
3169 rtlphy->current_channel,
3170 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
3171 if (delay > 0)
3172 mdelay(delay);
3173 else
3174 continue;
3175 } else {
3176 rtlphy->sw_chnl_inprogress = false;
3177 }
3178 break;
3179 } while (true);
3180 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
3181 rtlphy->sw_chnl_inprogress = false;
3182 return 1;
3183}
3184
3185static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
3186{
3187 struct rtl_priv *rtlpriv = rtl_priv(hw);
3188 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3189
3190 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3191 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
3192 rtlphy->current_io_type, rtlphy->set_io_inprogress));
3193 switch (rtlphy->current_io_type) {
3194 case IO_CMD_RESUME_DM_BY_SCAN:
Larry Fingerab049fb2011-06-28 18:55:50 -0500[diff] [blame^]3195 de_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
Chaoming Li7274a8c2011-06-10 15:10:25 -0500[diff] [blame]3196 rtl92d_dm_write_dig(hw);
3197 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
3198 break;
3199 case IO_CMD_PAUSE_DM_BY_SCAN:
Larry Fingerab049fb2011-06-28 18:55:50 -0500[diff] [blame^]3200 rtlphy->initgain_backup.xaagccore1 = de_digtable.cur_igvalue;
3201 de_digtable.cur_igvalue = 0x17;
Chaoming Li7274a8c2011-06-10 15:10:25 -0500[diff] [blame]3202 rtl92d_dm_write_dig(hw);
3203 break;
3204 default:
3205 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3206 ("switch case not process\n"));
3207 break;
3208 }
3209 rtlphy->set_io_inprogress = false;
3210 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3211 ("<---(%#x)\n", rtlphy->current_io_type));
3212}
3213
3214bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
3215{
3216 struct rtl_priv *rtlpriv = rtl_priv(hw);
3217 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3218 bool postprocessing = false;
3219
3220 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3221 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
3222 iotype, rtlphy->set_io_inprogress));
3223 do {
3224 switch (iotype) {
3225 case IO_CMD_RESUME_DM_BY_SCAN:
3226 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3227 ("[IO CMD] Resume DM after scan.\n"));
3228 postprocessing = true;
3229 break;
3230 case IO_CMD_PAUSE_DM_BY_SCAN:
3231 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3232 ("[IO CMD] Pause DM before scan.\n"));
3233 postprocessing = true;
3234 break;
3235 default:
3236 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3237 ("switch case not process\n"));
3238 break;
3239 }
3240 } while (false);
3241 if (postprocessing && !rtlphy->set_io_inprogress) {
3242 rtlphy->set_io_inprogress = true;
3243 rtlphy->current_io_type = iotype;
3244 } else {
3245 return false;
3246 }
3247 rtl92d_phy_set_io(hw);
3248 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype));
3249 return true;
3250}
3251
3252static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
3253{
3254 struct rtl_priv *rtlpriv = rtl_priv(hw);
3255
3256 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */
3257 /* b. SPS_CTRL 0x11[7:0] = 0x2b */
3258 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3259 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3260 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
3261 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3262 /* RF_ON_EXCEP(d~g): */
3263 /* d. APSD_CTRL 0x600[7:0] = 0x00 */
3264 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3265 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */
3266 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/
3267 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3268 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3269 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */
3270 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3271}
3272
3273static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3274{
3275 struct rtl_priv *rtlpriv = rtl_priv(hw);
3276 u32 u4btmp;
3277 u8 delay = 5;
3278
3279 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
3280 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3281 /* b. RF path 0 offset 0x00 = 0x00 disable RF */
3282 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3283 /* c. APSD_CTRL 0x600[7:0] = 0x40 */
3284 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3285 /* d. APSD_CTRL 0x600[7:0] = 0x00
3286 * APSD_CTRL 0x600[7:0] = 0x00
3287 * RF path 0 offset 0x00 = 0x00
3288 * APSD_CTRL 0x600[7:0] = 0x40
3289 * */
3290 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3291 while (u4btmp != 0 && delay > 0) {
3292 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3293 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3294 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3295 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3296 delay--;
3297 }
3298 if (delay == 0) {
3299 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3300 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3301
3302 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3303 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3304 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3305 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3306 ("Fail !!! Switch RF timeout.\n"));
3307 return;
3308 }
3309 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3310 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3311 /* f. SPS_CTRL 0x11[7:0] = 0x22 */
3312 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3313 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3314 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */
3315}
3316
3317bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3318 enum rf_pwrstate rfpwr_state)
3319{
3320
3321 bool bresult = true;
3322 struct rtl_priv *rtlpriv = rtl_priv(hw);
3323 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3324 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3325 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3326 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3327 u8 i, queue_id;
3328 struct rtl8192_tx_ring *ring = NULL;
3329
3330 if (rfpwr_state == ppsc->rfpwr_state)
3331 return false;
3332 switch (rfpwr_state) {
3333 case ERFON:
3334 if ((ppsc->rfpwr_state == ERFOFF) &&
3335 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3336 bool rtstatus;
3337 u32 InitializeCount = 0;
3338 do {
3339 InitializeCount++;
3340 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3341 ("IPS Set eRf nic enable\n"));
3342 rtstatus = rtl_ps_enable_nic(hw);
3343 } while ((rtstatus != true) &&
3344 (InitializeCount < 10));
3345
3346 RT_CLEAR_PS_LEVEL(ppsc,
3347 RT_RF_OFF_LEVL_HALT_NIC);
3348 } else {
3349 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3350 ("awake, sleeped:%d ms state_"
3351 "inap:%x\n",
3352 jiffies_to_msecs(jiffies -
3353 ppsc->last_sleep_jiffies),
3354 rtlpriv->psc.state_inap));
3355 ppsc->last_awake_jiffies = jiffies;
3356 _rtl92d_phy_set_rfon(hw);
3357 }
3358
3359 if (mac->link_state == MAC80211_LINKED)
3360 rtlpriv->cfg->ops->led_control(hw,
3361 LED_CTL_LINK);
3362 else
3363 rtlpriv->cfg->ops->led_control(hw,
3364 LED_CTL_NO_LINK);
3365 break;
3366 case ERFOFF:
3367 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3368 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3369 ("IPS Set eRf nic disable\n"));
3370 rtl_ps_disable_nic(hw);
3371 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3372 } else {
3373 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3374 rtlpriv->cfg->ops->led_control(hw,
3375 LED_CTL_NO_LINK);
3376 else
3377 rtlpriv->cfg->ops->led_control(hw,
3378 LED_CTL_POWER_OFF);
3379 }
3380 break;
3381 case ERFSLEEP:
3382 if (ppsc->rfpwr_state == ERFOFF)
3383 break;
3384
3385 for (queue_id = 0, i = 0;
3386 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3387 ring = &pcipriv->dev.tx_ring[queue_id];
3388 if (skb_queue_len(&ring->queue) == 0 ||
3389 queue_id == BEACON_QUEUE) {
3390 queue_id++;
3391 continue;
3392 } else if (rtlpci->pdev->current_state != PCI_D0) {
3393 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3394 ("eRf Off/Sleep: %d times TcbBusyQueu"
3395 "e[%d] !=0 but lower power state!\n",
3396 (i + 1), queue_id));
3397 break;
3398 } else {
3399 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3400 ("eRf Off/Sleep: %d times TcbBusyQueu"
3401 "e[%d] =%d "
3402 "before doze!\n", (i + 1), queue_id,
3403 skb_queue_len(&ring->queue)));
3404 udelay(10);
3405 i++;
3406 }
3407
3408 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3409 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3410 ("\nERFOFF: %d times TcbBusyQueue[%d] "
3411 "= %d !\n",
3412 MAX_DOZE_WAITING_TIMES_9x, queue_id,
3413 skb_queue_len(&ring->queue)));
3414 break;
3415 }
3416 }
3417 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3418 ("Set rfsleep awaked:%d ms\n",
3419 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies)));
3420 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, ("sleep awaked:%d ms "
3421 "state_inap:%x\n", jiffies_to_msecs(jiffies -
3422 ppsc->last_awake_jiffies), rtlpriv->psc.state_inap));
3423 ppsc->last_sleep_jiffies = jiffies;
3424 _rtl92d_phy_set_rfsleep(hw);
3425 break;
3426 default:
3427 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3428 ("switch case not process\n"));
3429 bresult = false;
3430 break;
3431 }
3432 if (bresult)
3433 ppsc->rfpwr_state = rfpwr_state;
3434 return bresult;
3435}
3436
3437void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3438{
3439 struct rtl_priv *rtlpriv = rtl_priv(hw);
3440 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3441 u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3442
3443 switch (rtlhal->macphymode) {
3444 case DUALMAC_DUALPHY:
3445 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3446 ("MacPhyMode: DUALMAC_DUALPHY\n"));
3447 rtl_write_byte(rtlpriv, offset, 0xF3);
3448 break;
3449 case SINGLEMAC_SINGLEPHY:
3450 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3451 ("MacPhyMode: SINGLEMAC_SINGLEPHY\n"));
3452 rtl_write_byte(rtlpriv, offset, 0xF4);
3453 break;
3454 case DUALMAC_SINGLEPHY:
3455 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3456 ("MacPhyMode: DUALMAC_SINGLEPHY\n"));
3457 rtl_write_byte(rtlpriv, offset, 0xF1);
3458 break;
3459 }
3460}
3461
3462void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3463{
3464 struct rtl_priv *rtlpriv = rtl_priv(hw);
3465 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3466 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3467
3468 switch (rtlhal->macphymode) {
3469 case DUALMAC_SINGLEPHY:
3470 rtlphy->rf_type = RF_2T2R;
3471 rtlhal->version |= CHIP_92D_SINGLEPHY;
3472 rtlhal->bandset = BAND_ON_BOTH;
3473 rtlhal->current_bandtype = BAND_ON_2_4G;
3474 break;
3475
3476 case SINGLEMAC_SINGLEPHY:
3477 rtlphy->rf_type = RF_2T2R;
3478 rtlhal->version |= CHIP_92D_SINGLEPHY;
3479 rtlhal->bandset = BAND_ON_BOTH;
3480 rtlhal->current_bandtype = BAND_ON_2_4G;
3481 break;
3482
3483 case DUALMAC_DUALPHY:
3484 rtlphy->rf_type = RF_1T1R;
3485 rtlhal->version &= (~CHIP_92D_SINGLEPHY);
3486 /* Now we let MAC0 run on 5G band. */
3487 if (rtlhal->interfaceindex == 0) {
3488 rtlhal->bandset = BAND_ON_5G;
3489 rtlhal->current_bandtype = BAND_ON_5G;
3490 } else {
3491 rtlhal->bandset = BAND_ON_2_4G;
3492 rtlhal->current_bandtype = BAND_ON_2_4G;
3493 }
3494 break;
3495 default:
3496 break;
3497 }
3498}
3499
3500u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3501{
3502 u8 group;
3503 u8 channel_info[59] = {
3504 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
3505 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56,
3506 58, 60, 62, 64, 100, 102, 104, 106, 108,
3507 110, 112, 114, 116, 118, 120, 122, 124,
3508 126, 128, 130, 132, 134, 136, 138, 140,
3509 149, 151, 153, 155, 157, 159, 161, 163,
3510 165
3511 };
3512
3513 if (channel_info[chnl] <= 3)
3514 group = 0;
3515 else if (channel_info[chnl] <= 9)
3516 group = 1;
3517 else if (channel_info[chnl] <= 14)
3518 group = 2;
3519 else if (channel_info[chnl] <= 44)
3520 group = 3;
3521 else if (channel_info[chnl] <= 54)
3522 group = 4;
3523 else if (channel_info[chnl] <= 64)
3524 group = 5;
3525 else if (channel_info[chnl] <= 112)
3526 group = 6;
3527 else if (channel_info[chnl] <= 126)
3528 group = 7;
3529 else if (channel_info[chnl] <= 140)
3530 group = 8;
3531 else if (channel_info[chnl] <= 153)
3532 group = 9;
3533 else if (channel_info[chnl] <= 159)
3534 group = 10;
3535 else
3536 group = 11;
3537 return group;
3538}
3539
3540void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3541{
3542 struct rtl_priv *rtlpriv = rtl_priv(hw);
3543 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3544 unsigned long flags;
3545 u8 value8;
3546 u16 i;
3547 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3548
3549 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3550 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3551 value8 = rtl_read_byte(rtlpriv, mac_reg);
3552 value8 |= BIT(1);
3553 rtl_write_byte(rtlpriv, mac_reg, value8);
3554 } else {
3555 value8 = rtl_read_byte(rtlpriv, mac_reg);
3556 value8 &= (~BIT(1));
3557 rtl_write_byte(rtlpriv, mac_reg, value8);
3558 }
3559
3560 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3561 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3562 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3563 } else {
3564 spin_lock_irqsave(&globalmutex_power, flags);
3565 if (rtlhal->interfaceindex == 0) {
3566 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3567 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3568 } else {
3569 value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3570 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3571 }
3572 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3573 spin_unlock_irqrestore(&globalmutex_power, flags);
3574 for (i = 0; i < 200; i++) {
3575 if ((value8 & BIT(7)) == 0) {
3576 break;
3577 } else {
3578 udelay(500);
3579 spin_lock_irqsave(&globalmutex_power, flags);
3580 value8 = rtl_read_byte(rtlpriv,
3581 REG_POWER_OFF_IN_PROCESS);
3582 spin_unlock_irqrestore(&globalmutex_power,
3583 flags);
3584 }
3585 }
3586 if (i == 200)
3587 RT_ASSERT(false, ("Another mac power off over time\n"));
3588 }
3589}
3590
3591void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3592{
3593 struct rtl_priv *rtlpriv = rtl_priv(hw);
3594
3595 switch (rtlpriv->rtlhal.macphymode) {
3596 case DUALMAC_DUALPHY:
3597 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3598 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3599 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3600 break;
3601 case DUALMAC_SINGLEPHY:
3602 rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3603 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3604 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3605 break;
3606 case SINGLEMAC_SINGLEPHY:
3607 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3608 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3609 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3610 break;
3611 default:
3612 break;
3613 }
3614}
3615
3616void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3617{
3618 struct rtl_priv *rtlpriv = rtl_priv(hw);
3619 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3620 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3621 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3622 u8 rfpath, i;
3623
3624 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("==>\n"));
3625 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3626 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3627 /* r_select_5G for path_A/B,0x878 */
3628 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3629 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3630 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3631 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3632 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3633 }
3634 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3635 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3636 /* fc_area 0xd2c */
3637 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3638 /* 5G LAN ON */
3639 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3640 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3641 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3642 0x40000100);
3643 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3644 0x40000100);
3645 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3646 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3647 BIT(10) | BIT(6) | BIT(5),
3648 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3649 (rtlefuse->eeprom_c9 & BIT(1)) |
3650 ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3651 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3652 BIT(10) | BIT(6) | BIT(5),
3653 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3654 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3655 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3656 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3657 } else {
3658 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3659 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3660 BIT(6) | BIT(5),
3661 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3662 (rtlefuse->eeprom_c9 & BIT(1)) |
3663 ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3664 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3665 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3666 ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3667 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3668 BIT(10) | BIT(6) | BIT(5),
3669 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3670 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3671 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3672 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3673 BIT(10) | BIT(6) | BIT(5),
3674 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3675 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3676 ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3677 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3678 BIT(31) | BIT(15), 0);
3679 }
3680 /* 1.5V_LDO */
3681 } else {
3682 /* r_select_5G for path_A/B */
3683 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3684 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3685 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3686 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3687 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3688 }
3689 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3690 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3691 /* fc_area */
3692 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3693 /* 5G LAN ON */
3694 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3695 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3696 if (rtlefuse->internal_pa_5g[0])
3697 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3698 0x2d4000b5);
3699 else
3700 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3701 0x20000080);
3702 if (rtlefuse->internal_pa_5g[1])
3703 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3704 0x2d4000b5);
3705 else
3706 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3707 0x20000080);
3708 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3709 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3710 BIT(10) | BIT(6) | BIT(5),
3711 (rtlefuse->eeprom_cc & BIT(5)));
3712 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3713 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3714 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3715 (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3716 } else {
3717 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3718 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3719 BIT(6) | BIT(5),
3720 (rtlefuse->eeprom_cc & BIT(5)) |
3721 ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3722 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3723 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3724 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3725 ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3726 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3727 BIT(31) | BIT(15),
3728 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3729 ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3730 }
3731 }
3732 /* update IQK related settings */
3733 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, BMASKDWORD, 0x40000100);
3734 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, BMASKDWORD, 0x40000100);
3735 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3736 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3737 BIT(26) | BIT(24), 0x00);
3738 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00);
3739 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3740 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3741
3742 /* Update RF */
3743 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3744 rfpath++) {
3745 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3746 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3747 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3748 BIT(18), 0);
3749 /* RF0x0b[16:14] =3b'111 */
3750 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3751 0x1c000, 0x07);
3752 } else {
3753 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3754 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3755 BIT(16) | BIT(18),
3756 (BIT(16) | BIT(8)) >> 8);
3757 }
3758 }
3759 /* Update for all band. */
3760 /* DMDP */
3761 if (rtlphy->rf_type == RF_1T1R) {
3762 /* Use antenna 0,0xc04,0xd04 */
3763 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x11);
3764 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3765
3766 /* enable ad/da clock1 for dual-phy reg0x888 */
3767 if (rtlhal->interfaceindex == 0) {
3768 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3769 BIT(13), 0x3);
3770 } else {
3771 rtl92d_phy_enable_anotherphy(hw, false);
3772 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3773 ("MAC1 use DBI to update 0x888"));
3774 /* 0x888 */
3775 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3776 rtl92de_read_dword_dbi(hw,
3777 RFPGA0_ADDALLOCKEN,
3778 BIT(3)) | BIT(12) | BIT(13),
3779 BIT(3));
3780 rtl92d_phy_powerdown_anotherphy(hw, false);
3781 }
3782 } else {
3783 /* Single PHY */
3784 /* Use antenna 0 & 1,0xc04,0xd04 */
3785 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x33);
3786 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3787 /* disable ad/da clock1,0x888 */
3788 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3789 }
3790 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3791 rfpath++) {
3792 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3793 RF_CHNLBW, BRFREGOFFSETMASK);
3794 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3795 BRFREGOFFSETMASK);
3796 }
3797 for (i = 0; i < 2; i++)
3798 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("RF 0x18 = 0x%x\n",
3799 rtlphy->rfreg_chnlval[i]));
3800 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("<==\n"));
3801
3802}
3803
3804bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3805{
3806 struct rtl_priv *rtlpriv = rtl_priv(hw);
3807 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3808 u8 u1btmp;
3809 unsigned long flags;
3810
3811 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3812 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3813 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3814 return true;
3815 }
3816 spin_lock_irqsave(&globalmutex_power, flags);
3817 if (rtlhal->interfaceindex == 0) {
3818 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3819 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3820 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3821 u1btmp &= MAC1_ON;
3822 } else {
3823 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3824 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3825 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3826 u1btmp &= MAC0_ON;
3827 }
3828 if (u1btmp) {
3829 spin_unlock_irqrestore(&globalmutex_power, flags);
3830 return false;
3831 }
3832 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3833 u1btmp |= BIT(7);
3834 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3835 spin_unlock_irqrestore(&globalmutex_power, flags);
3836 return true;
3837}