Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 IBM Corp. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation; either version |
| 7 | * 2 of the License, or (at your option) any later version. |
| 8 | */ |
| 9 | |
| 10 | #include <linux/spinlock.h> |
| 11 | #include <linux/sched.h> |
Ingo Molnar | e601757 | 2017-02-01 16:36:40 +0100 | [diff] [blame] | 12 | #include <linux/sched/clock.h> |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 13 | #include <linux/slab.h> |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 14 | #include <linux/mutex.h> |
| 15 | #include <linux/mm.h> |
| 16 | #include <linux/uaccess.h> |
Michael Neuling | 2bc79ff | 2016-04-22 14:57:49 +1000 | [diff] [blame] | 17 | #include <linux/delay.h> |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 18 | #include <asm/synch.h> |
Michael Neuling | ec249dd | 2015-05-27 16:07:16 +1000 | [diff] [blame] | 19 | #include <misc/cxl-base.h> |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 20 | |
| 21 | #include "cxl.h" |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 22 | #include "trace.h" |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 23 | |
Ian Munsie | 5e7823c | 2016-07-01 02:50:40 +1000 | [diff] [blame] | 24 | static int afu_control(struct cxl_afu *afu, u64 command, u64 clear, |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 25 | u64 result, u64 mask, bool enabled) |
| 26 | { |
Ian Munsie | 5e7823c | 2016-07-01 02:50:40 +1000 | [diff] [blame] | 27 | u64 AFU_Cntl; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 28 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 29 | int rc = 0; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 30 | |
| 31 | spin_lock(&afu->afu_cntl_lock); |
| 32 | pr_devel("AFU command starting: %llx\n", command); |
| 33 | |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 34 | trace_cxl_afu_ctrl(afu, command); |
| 35 | |
Ian Munsie | 5e7823c | 2016-07-01 02:50:40 +1000 | [diff] [blame] | 36 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
| 37 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 38 | |
| 39 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
| 40 | while ((AFU_Cntl & mask) != result) { |
| 41 | if (time_after_eq(jiffies, timeout)) { |
| 42 | dev_warn(&afu->dev, "WARNING: AFU control timed out!\n"); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 43 | rc = -EBUSY; |
| 44 | goto out; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 45 | } |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 46 | |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 47 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 48 | afu->enabled = enabled; |
| 49 | rc = -EIO; |
| 50 | goto out; |
| 51 | } |
| 52 | |
Rasmus Villemoes | de36953 | 2015-06-11 13:27:52 +0200 | [diff] [blame] | 53 | pr_devel_ratelimited("AFU control... (0x%016llx)\n", |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 54 | AFU_Cntl | command); |
| 55 | cpu_relax(); |
| 56 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
Andrew Donnellan | 3382a62 | 2016-11-22 21:13:27 +1100 | [diff] [blame] | 57 | } |
Ian Munsie | 2a4f667 | 2016-06-30 04:51:26 +1000 | [diff] [blame] | 58 | |
| 59 | if (AFU_Cntl & CXL_AFU_Cntl_An_RA) { |
| 60 | /* |
| 61 | * Workaround for a bug in the XSL used in the Mellanox CX4 |
| 62 | * that fails to clear the RA bit after an AFU reset, |
| 63 | * preventing subsequent AFU resets from working. |
| 64 | */ |
| 65 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA); |
| 66 | } |
| 67 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 68 | pr_devel("AFU command complete: %llx\n", command); |
| 69 | afu->enabled = enabled; |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 70 | out: |
| 71 | trace_cxl_afu_ctrl_done(afu, command, rc); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 72 | spin_unlock(&afu->afu_cntl_lock); |
| 73 | |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 74 | return rc; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | static int afu_enable(struct cxl_afu *afu) |
| 78 | { |
| 79 | pr_devel("AFU enable request\n"); |
| 80 | |
Ian Munsie | 5e7823c | 2016-07-01 02:50:40 +1000 | [diff] [blame] | 81 | return afu_control(afu, CXL_AFU_Cntl_An_E, 0, |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 82 | CXL_AFU_Cntl_An_ES_Enabled, |
| 83 | CXL_AFU_Cntl_An_ES_MASK, true); |
| 84 | } |
| 85 | |
| 86 | int cxl_afu_disable(struct cxl_afu *afu) |
| 87 | { |
| 88 | pr_devel("AFU disable request\n"); |
| 89 | |
Ian Munsie | 5e7823c | 2016-07-01 02:50:40 +1000 | [diff] [blame] | 90 | return afu_control(afu, 0, CXL_AFU_Cntl_An_E, |
| 91 | CXL_AFU_Cntl_An_ES_Disabled, |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 92 | CXL_AFU_Cntl_An_ES_MASK, false); |
| 93 | } |
| 94 | |
| 95 | /* This will disable as well as reset */ |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 96 | static int native_afu_reset(struct cxl_afu *afu) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 97 | { |
| 98 | pr_devel("AFU reset request\n"); |
| 99 | |
Ian Munsie | 5e7823c | 2016-07-01 02:50:40 +1000 | [diff] [blame] | 100 | return afu_control(afu, CXL_AFU_Cntl_An_RA, 0, |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 101 | CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled, |
| 102 | CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK, |
| 103 | false); |
| 104 | } |
| 105 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 106 | static int native_afu_check_and_enable(struct cxl_afu *afu) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 107 | { |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 108 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 109 | WARN(1, "Refusing to enable afu while link down!\n"); |
| 110 | return -EIO; |
| 111 | } |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 112 | if (afu->enabled) |
| 113 | return 0; |
| 114 | return afu_enable(afu); |
| 115 | } |
| 116 | |
| 117 | int cxl_psl_purge(struct cxl_afu *afu) |
| 118 | { |
| 119 | u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); |
| 120 | u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
| 121 | u64 dsisr, dar; |
| 122 | u64 start, end; |
| 123 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 124 | int rc = 0; |
| 125 | |
| 126 | trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 127 | |
| 128 | pr_devel("PSL purge request\n"); |
| 129 | |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 130 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 131 | dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n"); |
| 132 | rc = -EIO; |
| 133 | goto out; |
| 134 | } |
| 135 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 136 | if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { |
| 137 | WARN(1, "psl_purge request while AFU not disabled!\n"); |
| 138 | cxl_afu_disable(afu); |
| 139 | } |
| 140 | |
| 141 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, |
| 142 | PSL_CNTL | CXL_PSL_SCNTL_An_Pc); |
| 143 | start = local_clock(); |
| 144 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); |
| 145 | while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK) |
| 146 | == CXL_PSL_SCNTL_An_Ps_Pending) { |
| 147 | if (time_after_eq(jiffies, timeout)) { |
| 148 | dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n"); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 149 | rc = -EBUSY; |
| 150 | goto out; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 151 | } |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 152 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 153 | rc = -EIO; |
| 154 | goto out; |
| 155 | } |
| 156 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 157 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
Christophe Lombard | abd1d99 | 2017-04-07 16:11:58 +0200 | [diff] [blame^] | 158 | pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", |
| 159 | PSL_CNTL, dsisr); |
| 160 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 161 | if (dsisr & CXL_PSL_DSISR_TRANS) { |
| 162 | dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); |
Christophe Lombard | abd1d99 | 2017-04-07 16:11:58 +0200 | [diff] [blame^] | 163 | dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", |
| 164 | dsisr, dar); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 165 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); |
| 166 | } else if (dsisr) { |
Christophe Lombard | abd1d99 | 2017-04-07 16:11:58 +0200 | [diff] [blame^] | 167 | dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", |
| 168 | dsisr); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 169 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); |
| 170 | } else { |
| 171 | cpu_relax(); |
| 172 | } |
| 173 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); |
Andrew Donnellan | 3382a62 | 2016-11-22 21:13:27 +1100 | [diff] [blame] | 174 | } |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 175 | end = local_clock(); |
| 176 | pr_devel("PSL purged in %lld ns\n", end - start); |
| 177 | |
| 178 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, |
| 179 | PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 180 | out: |
| 181 | trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc); |
| 182 | return rc; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 183 | } |
| 184 | |
| 185 | static int spa_max_procs(int spa_size) |
| 186 | { |
| 187 | /* |
| 188 | * From the CAIA: |
| 189 | * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255 |
| 190 | * Most of that junk is really just an overly-complicated way of saying |
| 191 | * the last 256 bytes are __aligned(128), so it's really: |
| 192 | * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255 |
| 193 | * and |
| 194 | * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1 |
| 195 | * so |
| 196 | * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256 |
| 197 | * Ignore the alignment (which is safe in this case as long as we are |
| 198 | * careful with our rounding) and solve for n: |
| 199 | */ |
| 200 | return ((spa_size / 8) - 96) / 17; |
| 201 | } |
| 202 | |
Daniel Axtens | 05155772 | 2015-08-14 17:41:19 +1000 | [diff] [blame] | 203 | int cxl_alloc_spa(struct cxl_afu *afu) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 204 | { |
Ian Munsie | 895a798 | 2016-05-04 14:46:30 +1000 | [diff] [blame] | 205 | unsigned spa_size; |
| 206 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 207 | /* Work out how many pages to allocate */ |
Ian Munsie | 2224b67 | 2016-06-29 22:16:26 +1000 | [diff] [blame] | 208 | afu->native->spa_order = -1; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 209 | do { |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 210 | afu->native->spa_order++; |
Ian Munsie | 895a798 | 2016-05-04 14:46:30 +1000 | [diff] [blame] | 211 | spa_size = (1 << afu->native->spa_order) * PAGE_SIZE; |
| 212 | |
| 213 | if (spa_size > 0x100000) { |
| 214 | dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n", |
| 215 | afu->native->spa_max_procs, afu->native->spa_size); |
| 216 | afu->num_procs = afu->native->spa_max_procs; |
| 217 | break; |
| 218 | } |
| 219 | |
| 220 | afu->native->spa_size = spa_size; |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 221 | afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size); |
| 222 | } while (afu->native->spa_max_procs < afu->num_procs); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 223 | |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 224 | if (!(afu->native->spa = (struct cxl_process_element *) |
| 225 | __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) { |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 226 | pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n"); |
| 227 | return -ENOMEM; |
| 228 | } |
| 229 | pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n", |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 230 | 1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 231 | |
Daniel Axtens | 05155772 | 2015-08-14 17:41:19 +1000 | [diff] [blame] | 232 | return 0; |
| 233 | } |
| 234 | |
| 235 | static void attach_spa(struct cxl_afu *afu) |
| 236 | { |
| 237 | u64 spap; |
| 238 | |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 239 | afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa + |
| 240 | ((afu->native->spa_max_procs + 3) * 128)); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 241 | |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 242 | spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr; |
| 243 | spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 244 | spap |= CXL_PSL_SPAP_V; |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 245 | pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", |
| 246 | afu->native->spa, afu->native->spa_max_procs, |
| 247 | afu->native->sw_command_status, spap); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 248 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 249 | } |
| 250 | |
Daniel Axtens | 05155772 | 2015-08-14 17:41:19 +1000 | [diff] [blame] | 251 | static inline void detach_spa(struct cxl_afu *afu) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 252 | { |
Ian Munsie | db7933f | 2014-12-08 19:18:00 +1100 | [diff] [blame] | 253 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); |
Daniel Axtens | 05155772 | 2015-08-14 17:41:19 +1000 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | void cxl_release_spa(struct cxl_afu *afu) |
| 257 | { |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 258 | if (afu->native->spa) { |
| 259 | free_pages((unsigned long) afu->native->spa, |
| 260 | afu->native->spa_order); |
| 261 | afu->native->spa = NULL; |
Daniel Axtens | 05155772 | 2015-08-14 17:41:19 +1000 | [diff] [blame] | 262 | } |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 263 | } |
| 264 | |
Christophe Lombard | 64663f3 | 2017-04-07 16:11:57 +0200 | [diff] [blame] | 265 | int cxl_invalidate_all_psl8(struct cxl *adapter) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 266 | { |
| 267 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
| 268 | |
| 269 | pr_devel("CXL adapter wide TLBIA & SLBIA\n"); |
| 270 | |
| 271 | cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A); |
| 272 | |
| 273 | cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL); |
| 274 | while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) { |
| 275 | if (time_after_eq(jiffies, timeout)) { |
| 276 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n"); |
| 277 | return -EBUSY; |
| 278 | } |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 279 | if (!cxl_ops->link_ok(adapter, NULL)) |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 280 | return -EIO; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 281 | cpu_relax(); |
| 282 | } |
| 283 | |
| 284 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL); |
| 285 | while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) { |
| 286 | if (time_after_eq(jiffies, timeout)) { |
| 287 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n"); |
| 288 | return -EBUSY; |
| 289 | } |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 290 | if (!cxl_ops->link_ok(adapter, NULL)) |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 291 | return -EIO; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 292 | cpu_relax(); |
| 293 | } |
| 294 | return 0; |
| 295 | } |
| 296 | |
Frederic Barrat | aaa2245 | 2016-10-03 21:36:02 +0200 | [diff] [blame] | 297 | int cxl_data_cache_flush(struct cxl *adapter) |
| 298 | { |
| 299 | u64 reg; |
| 300 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
| 301 | |
| 302 | pr_devel("Flushing data cache\n"); |
| 303 | |
| 304 | reg = cxl_p1_read(adapter, CXL_PSL_Control); |
| 305 | reg |= CXL_PSL_Control_Fr; |
| 306 | cxl_p1_write(adapter, CXL_PSL_Control, reg); |
| 307 | |
| 308 | reg = cxl_p1_read(adapter, CXL_PSL_Control); |
| 309 | while ((reg & CXL_PSL_Control_Fs_MASK) != CXL_PSL_Control_Fs_Complete) { |
| 310 | if (time_after_eq(jiffies, timeout)) { |
| 311 | dev_warn(&adapter->dev, "WARNING: cache flush timed out!\n"); |
| 312 | return -EBUSY; |
| 313 | } |
| 314 | |
| 315 | if (!cxl_ops->link_ok(adapter, NULL)) { |
| 316 | dev_warn(&adapter->dev, "WARNING: link down when flushing cache\n"); |
| 317 | return -EIO; |
| 318 | } |
| 319 | cpu_relax(); |
| 320 | reg = cxl_p1_read(adapter, CXL_PSL_Control); |
| 321 | } |
| 322 | |
| 323 | reg &= ~CXL_PSL_Control_Fr; |
| 324 | cxl_p1_write(adapter, CXL_PSL_Control, reg); |
| 325 | return 0; |
| 326 | } |
| 327 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 328 | static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1) |
| 329 | { |
| 330 | int rc; |
| 331 | |
| 332 | /* 1. Disable SSTP by writing 0 to SSTP1[V] */ |
| 333 | cxl_p2n_write(afu, CXL_SSTP1_An, 0); |
| 334 | |
| 335 | /* 2. Invalidate all SLB entries */ |
| 336 | if ((rc = cxl_afu_slbia(afu))) |
| 337 | return rc; |
| 338 | |
| 339 | /* 3. Set SSTP0_An */ |
| 340 | cxl_p2n_write(afu, CXL_SSTP0_An, sstp0); |
| 341 | |
| 342 | /* 4. Set SSTP1_An */ |
| 343 | cxl_p2n_write(afu, CXL_SSTP1_An, sstp1); |
| 344 | |
| 345 | return 0; |
| 346 | } |
| 347 | |
| 348 | /* Using per slice version may improve performance here. (ie. SLBIA_An) */ |
| 349 | static void slb_invalid(struct cxl_context *ctx) |
| 350 | { |
| 351 | struct cxl *adapter = ctx->afu->adapter; |
| 352 | u64 slbia; |
| 353 | |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 354 | WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex)); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 355 | |
| 356 | cxl_p1_write(adapter, CXL_PSL_LBISEL, |
| 357 | ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) | |
| 358 | be32_to_cpu(ctx->elem->lpid)); |
| 359 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID); |
| 360 | |
| 361 | while (1) { |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 362 | if (!cxl_ops->link_ok(adapter, NULL)) |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 363 | break; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 364 | slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA); |
| 365 | if (!(slbia & CXL_TLB_SLB_P)) |
| 366 | break; |
| 367 | cpu_relax(); |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | static int do_process_element_cmd(struct cxl_context *ctx, |
| 372 | u64 cmd, u64 pe_state) |
| 373 | { |
| 374 | u64 state; |
Ian Munsie | a98e6e9 | 2014-12-08 19:17:56 +1100 | [diff] [blame] | 375 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 376 | int rc = 0; |
| 377 | |
| 378 | trace_cxl_llcmd(ctx, cmd); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 379 | |
| 380 | WARN_ON(!ctx->afu->enabled); |
| 381 | |
| 382 | ctx->elem->software_state = cpu_to_be32(pe_state); |
| 383 | smp_wmb(); |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 384 | *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 385 | smp_mb(); |
| 386 | cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); |
| 387 | while (1) { |
Ian Munsie | a98e6e9 | 2014-12-08 19:17:56 +1100 | [diff] [blame] | 388 | if (time_after_eq(jiffies, timeout)) { |
| 389 | dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 390 | rc = -EBUSY; |
| 391 | goto out; |
Ian Munsie | a98e6e9 | 2014-12-08 19:17:56 +1100 | [diff] [blame] | 392 | } |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 393 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 394 | dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n"); |
| 395 | rc = -EIO; |
| 396 | goto out; |
| 397 | } |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 398 | state = be64_to_cpup(ctx->afu->native->sw_command_status); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 399 | if (state == ~0ULL) { |
| 400 | pr_err("cxl: Error adding process element to AFU\n"); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 401 | rc = -1; |
| 402 | goto out; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 403 | } |
| 404 | if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) == |
| 405 | (cmd | (cmd >> 16) | ctx->pe)) |
| 406 | break; |
| 407 | /* |
| 408 | * The command won't finish in the PSL if there are |
| 409 | * outstanding DSIs. Hence we need to yield here in |
| 410 | * case there are outstanding DSIs that we need to |
| 411 | * service. Tuning possiblity: we could wait for a |
| 412 | * while before sched |
| 413 | */ |
| 414 | schedule(); |
| 415 | |
| 416 | } |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 417 | out: |
| 418 | trace_cxl_llcmd_done(ctx, cmd, rc); |
| 419 | return rc; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 420 | } |
| 421 | |
| 422 | static int add_process_element(struct cxl_context *ctx) |
| 423 | { |
| 424 | int rc = 0; |
| 425 | |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 426 | mutex_lock(&ctx->afu->native->spa_mutex); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 427 | pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe); |
| 428 | if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V))) |
| 429 | ctx->pe_inserted = true; |
| 430 | pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe); |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 431 | mutex_unlock(&ctx->afu->native->spa_mutex); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 432 | return rc; |
| 433 | } |
| 434 | |
| 435 | static int terminate_process_element(struct cxl_context *ctx) |
| 436 | { |
| 437 | int rc = 0; |
| 438 | |
| 439 | /* fast path terminate if it's already invalid */ |
| 440 | if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V))) |
| 441 | return rc; |
| 442 | |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 443 | mutex_lock(&ctx->afu->native->spa_mutex); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 444 | pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe); |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 445 | /* We could be asked to terminate when the hw is down. That |
| 446 | * should always succeed: it's not running if the hw has gone |
| 447 | * away and is being reset. |
| 448 | */ |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 449 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 450 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE, |
| 451 | CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 452 | ctx->elem->software_state = 0; /* Remove Valid bit */ |
| 453 | pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe); |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 454 | mutex_unlock(&ctx->afu->native->spa_mutex); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 455 | return rc; |
| 456 | } |
| 457 | |
| 458 | static int remove_process_element(struct cxl_context *ctx) |
| 459 | { |
| 460 | int rc = 0; |
| 461 | |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 462 | mutex_lock(&ctx->afu->native->spa_mutex); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 463 | pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe); |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 464 | |
| 465 | /* We could be asked to remove when the hw is down. Again, if |
| 466 | * the hw is down, the PE is gone, so we succeed. |
| 467 | */ |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 468 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 469 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0); |
| 470 | |
| 471 | if (!rc) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 472 | ctx->pe_inserted = false; |
Christophe Lombard | abd1d99 | 2017-04-07 16:11:58 +0200 | [diff] [blame^] | 473 | if (cxl_is_power8()) |
| 474 | slb_invalid(ctx); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 475 | pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe); |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 476 | mutex_unlock(&ctx->afu->native->spa_mutex); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 477 | |
| 478 | return rc; |
| 479 | } |
| 480 | |
Michael Neuling | 1a1a94b | 2015-05-27 16:07:10 +1000 | [diff] [blame] | 481 | void cxl_assign_psn_space(struct cxl_context *ctx) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 482 | { |
| 483 | if (!ctx->afu->pp_size || ctx->master) { |
| 484 | ctx->psn_phys = ctx->afu->psn_phys; |
| 485 | ctx->psn_size = ctx->afu->adapter->ps_size; |
| 486 | } else { |
| 487 | ctx->psn_phys = ctx->afu->psn_phys + |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 488 | (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 489 | ctx->psn_size = ctx->afu->pp_size; |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | static int activate_afu_directed(struct cxl_afu *afu) |
| 494 | { |
| 495 | int rc; |
| 496 | |
| 497 | dev_info(&afu->dev, "Activating AFU directed mode\n"); |
| 498 | |
Christophe Lombard | 4108efb | 2015-10-07 16:07:40 +1100 | [diff] [blame] | 499 | afu->num_procs = afu->max_procs_virtualised; |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 500 | if (afu->native->spa == NULL) { |
Daniel Axtens | 05155772 | 2015-08-14 17:41:19 +1000 | [diff] [blame] | 501 | if (cxl_alloc_spa(afu)) |
| 502 | return -ENOMEM; |
| 503 | } |
| 504 | attach_spa(afu); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 505 | |
| 506 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU); |
Christophe Lombard | abd1d99 | 2017-04-07 16:11:58 +0200 | [diff] [blame^] | 507 | if (cxl_is_power8()) |
| 508 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 509 | cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); |
| 510 | |
| 511 | afu->current_mode = CXL_MODE_DIRECTED; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 512 | |
| 513 | if ((rc = cxl_chardev_m_afu_add(afu))) |
| 514 | return rc; |
| 515 | |
| 516 | if ((rc = cxl_sysfs_afu_m_add(afu))) |
| 517 | goto err; |
| 518 | |
| 519 | if ((rc = cxl_chardev_s_afu_add(afu))) |
| 520 | goto err1; |
| 521 | |
| 522 | return 0; |
| 523 | err1: |
| 524 | cxl_sysfs_afu_m_remove(afu); |
| 525 | err: |
| 526 | cxl_chardev_afu_remove(afu); |
| 527 | return rc; |
| 528 | } |
| 529 | |
| 530 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 531 | #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE) |
| 532 | #else |
| 533 | #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE)) |
| 534 | #endif |
| 535 | |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 536 | static u64 calculate_sr(struct cxl_context *ctx) |
| 537 | { |
| 538 | u64 sr = 0; |
| 539 | |
Frederic Barrat | e606e03 | 2015-12-07 14:34:40 +0100 | [diff] [blame] | 540 | set_endian(sr); |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 541 | if (ctx->master) |
| 542 | sr |= CXL_PSL_SR_An_MP; |
| 543 | if (mfspr(SPRN_LPCR) & LPCR_TC) |
| 544 | sr |= CXL_PSL_SR_An_TC; |
| 545 | if (ctx->kernel) { |
Ian Munsie | 7a0d85d | 2016-05-06 17:46:36 +1000 | [diff] [blame] | 546 | if (!ctx->real_mode) |
| 547 | sr |= CXL_PSL_SR_An_R; |
| 548 | sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV; |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 549 | } else { |
| 550 | sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 551 | sr &= ~(CXL_PSL_SR_An_HV); |
| 552 | if (!test_tsk_thread_flag(current, TIF_32BIT)) |
| 553 | sr |= CXL_PSL_SR_An_SF; |
| 554 | } |
| 555 | return sr; |
| 556 | } |
| 557 | |
Ian Munsie | 292841b | 2016-05-24 02:14:05 +1000 | [diff] [blame] | 558 | static void update_ivtes_directed(struct cxl_context *ctx) |
| 559 | { |
| 560 | bool need_update = (ctx->status == STARTED); |
| 561 | int r; |
| 562 | |
| 563 | if (need_update) { |
| 564 | WARN_ON(terminate_process_element(ctx)); |
| 565 | WARN_ON(remove_process_element(ctx)); |
| 566 | } |
| 567 | |
| 568 | for (r = 0; r < CXL_IRQ_RANGES; r++) { |
| 569 | ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); |
| 570 | ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); |
| 571 | } |
| 572 | |
| 573 | /* |
| 574 | * Theoretically we could use the update llcmd, instead of a |
| 575 | * terminate/remove/add (or if an atomic update was required we could |
| 576 | * do a suspend/update/resume), however it seems there might be issues |
| 577 | * with the update llcmd on some cards (including those using an XSL on |
| 578 | * an ASIC) so for now it's safest to go with the commands that are |
| 579 | * known to work. In the future if we come across a situation where the |
| 580 | * card may be performing transactions using the same PE while we are |
| 581 | * doing this update we might need to revisit this. |
| 582 | */ |
| 583 | if (need_update) |
| 584 | WARN_ON(add_process_element(ctx)); |
| 585 | } |
| 586 | |
Christophe Lombard | 64663f3 | 2017-04-07 16:11:57 +0200 | [diff] [blame] | 587 | int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 588 | { |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 589 | u32 pid; |
Ian Munsie | 292841b | 2016-05-24 02:14:05 +1000 | [diff] [blame] | 590 | int result; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 591 | |
Michael Neuling | 1a1a94b | 2015-05-27 16:07:10 +1000 | [diff] [blame] | 592 | cxl_assign_psn_space(ctx); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 593 | |
| 594 | ctx->elem->ctxtime = 0; /* disable */ |
| 595 | ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); |
| 596 | ctx->elem->haurp = 0; /* disable */ |
| 597 | ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1)); |
| 598 | |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 599 | pid = current->pid; |
| 600 | if (ctx->kernel) |
| 601 | pid = 0; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 602 | ctx->elem->common.tid = 0; |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 603 | ctx->elem->common.pid = cpu_to_be32(pid); |
| 604 | |
| 605 | ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 606 | |
| 607 | ctx->elem->common.csrp = 0; /* disable */ |
| 608 | ctx->elem->common.aurp0 = 0; /* disable */ |
| 609 | ctx->elem->common.aurp1 = 0; /* disable */ |
| 610 | |
| 611 | cxl_prefault(ctx, wed); |
| 612 | |
| 613 | ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0); |
| 614 | ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1); |
| 615 | |
Ian Munsie | 3c206fa | 2016-05-04 14:52:58 +1000 | [diff] [blame] | 616 | /* |
| 617 | * Ensure we have the multiplexed PSL interrupt set up to take faults |
| 618 | * for kernel contexts that may not have allocated any AFU IRQs at all: |
| 619 | */ |
| 620 | if (ctx->irqs.range[0] == 0) { |
| 621 | ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq; |
| 622 | ctx->irqs.range[0] = 1; |
| 623 | } |
| 624 | |
Ian Munsie | 292841b | 2016-05-24 02:14:05 +1000 | [diff] [blame] | 625 | update_ivtes_directed(ctx); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 626 | |
| 627 | ctx->elem->common.amr = cpu_to_be64(amr); |
| 628 | ctx->elem->common.wed = cpu_to_be64(wed); |
| 629 | |
| 630 | /* first guy needs to enable */ |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 631 | if ((result = cxl_ops->afu_check_and_enable(ctx->afu))) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 632 | return result; |
| 633 | |
Daniel Axtens | 368857c | 2015-07-29 14:07:22 +1000 | [diff] [blame] | 634 | return add_process_element(ctx); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 635 | } |
| 636 | |
| 637 | static int deactivate_afu_directed(struct cxl_afu *afu) |
| 638 | { |
| 639 | dev_info(&afu->dev, "Deactivating AFU directed mode\n"); |
| 640 | |
| 641 | afu->current_mode = 0; |
| 642 | afu->num_procs = 0; |
| 643 | |
| 644 | cxl_sysfs_afu_m_remove(afu); |
| 645 | cxl_chardev_afu_remove(afu); |
| 646 | |
Ian Munsie | 5e7823c | 2016-07-01 02:50:40 +1000 | [diff] [blame] | 647 | /* |
| 648 | * The CAIA section 2.2.1 indicates that the procedure for starting and |
| 649 | * stopping an AFU in AFU directed mode is AFU specific, which is not |
| 650 | * ideal since this code is generic and with one exception has no |
| 651 | * knowledge of the AFU. This is in contrast to the procedure for |
| 652 | * disabling a dedicated process AFU, which is documented to just |
| 653 | * require a reset. The architecture does indicate that both an AFU |
| 654 | * reset and an AFU disable should result in the AFU being disabled and |
| 655 | * we do both followed by a PSL purge for safety. |
| 656 | * |
| 657 | * Notably we used to have some issues with the disable sequence on PSL |
| 658 | * cards, which is why we ended up using this heavy weight procedure in |
| 659 | * the first place, however a bug was discovered that had rendered the |
| 660 | * disable operation ineffective, so it is conceivable that was the |
| 661 | * sole explanation for those difficulties. Careful regression testing |
| 662 | * is recommended if anyone attempts to remove or reorder these |
| 663 | * operations. |
| 664 | * |
| 665 | * The XSL on the Mellanox CX4 behaves a little differently from the |
| 666 | * PSL based cards and will time out an AFU reset if the AFU is still |
| 667 | * enabled. That card is special in that we do have a means to identify |
| 668 | * it from this code, so in that case we skip the reset and just use a |
| 669 | * disable/purge to avoid the timeout and corresponding noise in the |
| 670 | * kernel log. |
| 671 | */ |
| 672 | if (afu->adapter->native->sl_ops->needs_reset_before_disable) |
| 673 | cxl_ops->afu_reset(afu); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 674 | cxl_afu_disable(afu); |
| 675 | cxl_psl_purge(afu); |
| 676 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 677 | return 0; |
| 678 | } |
| 679 | |
Christophe Lombard | 64663f3 | 2017-04-07 16:11:57 +0200 | [diff] [blame] | 680 | int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 681 | { |
| 682 | dev_info(&afu->dev, "Activating dedicated process mode\n"); |
| 683 | |
| 684 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); |
| 685 | |
| 686 | cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */ |
| 687 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */ |
| 688 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); |
| 689 | cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID)); |
| 690 | cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */ |
| 691 | cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1)); |
| 692 | |
| 693 | cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */ |
| 694 | cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */ |
| 695 | cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */ |
| 696 | |
| 697 | afu->current_mode = CXL_MODE_DEDICATED; |
| 698 | afu->num_procs = 1; |
| 699 | |
| 700 | return cxl_chardev_d_afu_add(afu); |
| 701 | } |
| 702 | |
Christophe Lombard | 64663f3 | 2017-04-07 16:11:57 +0200 | [diff] [blame] | 703 | void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx) |
Ian Munsie | 292841b | 2016-05-24 02:14:05 +1000 | [diff] [blame] | 704 | { |
| 705 | struct cxl_afu *afu = ctx->afu; |
| 706 | |
| 707 | cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, |
| 708 | (((u64)ctx->irqs.offset[0] & 0xffff) << 48) | |
| 709 | (((u64)ctx->irqs.offset[1] & 0xffff) << 32) | |
| 710 | (((u64)ctx->irqs.offset[2] & 0xffff) << 16) | |
| 711 | ((u64)ctx->irqs.offset[3] & 0xffff)); |
| 712 | cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64) |
| 713 | (((u64)ctx->irqs.range[0] & 0xffff) << 48) | |
| 714 | (((u64)ctx->irqs.range[1] & 0xffff) << 32) | |
| 715 | (((u64)ctx->irqs.range[2] & 0xffff) << 16) | |
| 716 | ((u64)ctx->irqs.range[3] & 0xffff)); |
| 717 | } |
| 718 | |
Christophe Lombard | 64663f3 | 2017-04-07 16:11:57 +0200 | [diff] [blame] | 719 | int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 720 | { |
| 721 | struct cxl_afu *afu = ctx->afu; |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 722 | u64 pid; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 723 | int rc; |
| 724 | |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 725 | pid = (u64)current->pid << 32; |
| 726 | if (ctx->kernel) |
| 727 | pid = 0; |
| 728 | cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid); |
| 729 | |
| 730 | cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx)); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 731 | |
| 732 | if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1))) |
| 733 | return rc; |
| 734 | |
| 735 | cxl_prefault(ctx, wed); |
| 736 | |
Christophe Lombard | bdd2e71 | 2017-04-07 16:11:56 +0200 | [diff] [blame] | 737 | if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes) |
| 738 | afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 739 | |
| 740 | cxl_p2n_write(afu, CXL_PSL_AMR_An, amr); |
| 741 | |
| 742 | /* master only context for dedicated */ |
Michael Neuling | 1a1a94b | 2015-05-27 16:07:10 +1000 | [diff] [blame] | 743 | cxl_assign_psn_space(ctx); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 744 | |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 745 | if ((rc = cxl_ops->afu_reset(afu))) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 746 | return rc; |
| 747 | |
| 748 | cxl_p2n_write(afu, CXL_PSL_WED_An, wed); |
| 749 | |
| 750 | return afu_enable(afu); |
| 751 | } |
| 752 | |
| 753 | static int deactivate_dedicated_process(struct cxl_afu *afu) |
| 754 | { |
| 755 | dev_info(&afu->dev, "Deactivating dedicated process mode\n"); |
| 756 | |
| 757 | afu->current_mode = 0; |
| 758 | afu->num_procs = 0; |
| 759 | |
| 760 | cxl_chardev_afu_remove(afu); |
| 761 | |
| 762 | return 0; |
| 763 | } |
| 764 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 765 | static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 766 | { |
| 767 | if (mode == CXL_MODE_DIRECTED) |
| 768 | return deactivate_afu_directed(afu); |
| 769 | if (mode == CXL_MODE_DEDICATED) |
| 770 | return deactivate_dedicated_process(afu); |
| 771 | return 0; |
| 772 | } |
| 773 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 774 | static int native_afu_activate_mode(struct cxl_afu *afu, int mode) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 775 | { |
| 776 | if (!mode) |
| 777 | return 0; |
| 778 | if (!(mode & afu->modes_supported)) |
| 779 | return -EINVAL; |
| 780 | |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 781 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 782 | WARN(1, "Device link is down, refusing to activate!\n"); |
| 783 | return -EIO; |
| 784 | } |
| 785 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 786 | if (mode == CXL_MODE_DIRECTED) |
| 787 | return activate_afu_directed(afu); |
Christophe Lombard | bdd2e71 | 2017-04-07 16:11:56 +0200 | [diff] [blame] | 788 | if ((mode == CXL_MODE_DEDICATED) && |
| 789 | (afu->adapter->native->sl_ops->activate_dedicated_process)) |
| 790 | return afu->adapter->native->sl_ops->activate_dedicated_process(afu); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 791 | |
| 792 | return -EINVAL; |
| 793 | } |
| 794 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 795 | static int native_attach_process(struct cxl_context *ctx, bool kernel, |
| 796 | u64 wed, u64 amr) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 797 | { |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 798 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 799 | WARN(1, "Device link is down, refusing to attach process!\n"); |
| 800 | return -EIO; |
| 801 | } |
| 802 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 803 | ctx->kernel = kernel; |
Christophe Lombard | bdd2e71 | 2017-04-07 16:11:56 +0200 | [diff] [blame] | 804 | if ((ctx->afu->current_mode == CXL_MODE_DIRECTED) && |
| 805 | (ctx->afu->adapter->native->sl_ops->attach_afu_directed)) |
| 806 | return ctx->afu->adapter->native->sl_ops->attach_afu_directed(ctx, wed, amr); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 807 | |
Christophe Lombard | bdd2e71 | 2017-04-07 16:11:56 +0200 | [diff] [blame] | 808 | if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) && |
| 809 | (ctx->afu->adapter->native->sl_ops->attach_dedicated_process)) |
| 810 | return ctx->afu->adapter->native->sl_ops->attach_dedicated_process(ctx, wed, amr); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 811 | |
| 812 | return -EINVAL; |
| 813 | } |
| 814 | |
| 815 | static inline int detach_process_native_dedicated(struct cxl_context *ctx) |
| 816 | { |
Ian Munsie | 5e7823c | 2016-07-01 02:50:40 +1000 | [diff] [blame] | 817 | /* |
| 818 | * The CAIA section 2.1.1 indicates that we need to do an AFU reset to |
| 819 | * stop the AFU in dedicated mode (we therefore do not make that |
| 820 | * optional like we do in the afu directed path). It does not indicate |
| 821 | * that we need to do an explicit disable (which should occur |
| 822 | * implicitly as part of the reset) or purge, but we do these as well |
| 823 | * to be on the safe side. |
| 824 | * |
| 825 | * Notably we used to have some issues with the disable sequence |
| 826 | * (before the sequence was spelled out in the architecture) which is |
| 827 | * why we were so heavy weight in the first place, however a bug was |
| 828 | * discovered that had rendered the disable operation ineffective, so |
| 829 | * it is conceivable that was the sole explanation for those |
| 830 | * difficulties. Point is, we should be careful and do some regression |
| 831 | * testing if we ever attempt to remove any part of this procedure. |
| 832 | */ |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 833 | cxl_ops->afu_reset(ctx->afu); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 834 | cxl_afu_disable(ctx->afu); |
| 835 | cxl_psl_purge(ctx->afu); |
| 836 | return 0; |
| 837 | } |
| 838 | |
Ian Munsie | 292841b | 2016-05-24 02:14:05 +1000 | [diff] [blame] | 839 | static void native_update_ivtes(struct cxl_context *ctx) |
| 840 | { |
| 841 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) |
| 842 | return update_ivtes_directed(ctx); |
Christophe Lombard | bdd2e71 | 2017-04-07 16:11:56 +0200 | [diff] [blame] | 843 | if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) && |
| 844 | (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)) |
| 845 | return ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx); |
Ian Munsie | 292841b | 2016-05-24 02:14:05 +1000 | [diff] [blame] | 846 | WARN(1, "native_update_ivtes: Bad mode\n"); |
| 847 | } |
| 848 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 849 | static inline int detach_process_native_afu_directed(struct cxl_context *ctx) |
| 850 | { |
| 851 | if (!ctx->pe_inserted) |
| 852 | return 0; |
| 853 | if (terminate_process_element(ctx)) |
| 854 | return -1; |
| 855 | if (remove_process_element(ctx)) |
| 856 | return -1; |
| 857 | |
| 858 | return 0; |
| 859 | } |
| 860 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 861 | static int native_detach_process(struct cxl_context *ctx) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 862 | { |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 863 | trace_cxl_detach(ctx); |
| 864 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 865 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) |
| 866 | return detach_process_native_dedicated(ctx); |
| 867 | |
| 868 | return detach_process_native_afu_directed(ctx); |
| 869 | } |
| 870 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 871 | static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 872 | { |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 873 | /* If the adapter has gone away, we can't get any meaningful |
| 874 | * information. |
| 875 | */ |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 876 | if (!cxl_ops->link_ok(afu->adapter, afu)) |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 877 | return -EIO; |
| 878 | |
Ian Munsie | bc78b05 | 2014-11-14 17:37:50 +1100 | [diff] [blame] | 879 | info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
| 880 | info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); |
Christophe Lombard | abd1d99 | 2017-04-07 16:11:58 +0200 | [diff] [blame^] | 881 | if (cxl_is_power8()) |
| 882 | info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An); |
Ian Munsie | bc78b05 | 2014-11-14 17:37:50 +1100 | [diff] [blame] | 883 | info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
| 884 | info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); |
Christophe Lombard | 444c4ba | 2016-03-04 12:26:34 +0100 | [diff] [blame] | 885 | info->proc_handle = 0; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 886 | |
| 887 | return 0; |
| 888 | } |
| 889 | |
Christophe Lombard | 64663f3 | 2017-04-07 16:11:57 +0200 | [diff] [blame] | 890 | void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 891 | { |
| 892 | u64 fir1, fir2, fir_slice, serr, afu_debug; |
| 893 | |
| 894 | fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1); |
| 895 | fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2); |
| 896 | fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An); |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 897 | afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An); |
| 898 | |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 899 | dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1); |
| 900 | dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2); |
Frederic Barrat | 6d38261 | 2016-05-24 03:39:18 +1000 | [diff] [blame] | 901 | if (ctx->afu->adapter->native->sl_ops->register_serr_irq) { |
| 902 | serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An); |
Philippe Bergheaud | 6e0c50f | 2016-07-05 13:08:06 +0200 | [diff] [blame] | 903 | cxl_afu_decode_psl_serr(ctx->afu, serr); |
Frederic Barrat | 6d38261 | 2016-05-24 03:39:18 +1000 | [diff] [blame] | 904 | } |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 905 | dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); |
| 906 | dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); |
Frederic Barrat | 6d38261 | 2016-05-24 03:39:18 +1000 | [diff] [blame] | 907 | } |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 908 | |
Frederic Barrat | 6d38261 | 2016-05-24 03:39:18 +1000 | [diff] [blame] | 909 | static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx, |
| 910 | u64 dsisr, u64 errstat) |
| 911 | { |
| 912 | |
| 913 | dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat); |
| 914 | |
| 915 | if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers) |
| 916 | ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx); |
| 917 | |
| 918 | if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) { |
| 919 | dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n"); |
| 920 | ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter); |
| 921 | } |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 922 | |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 923 | return cxl_ops->ack_irq(ctx, 0, errstat); |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 924 | } |
| 925 | |
Christophe Lombard | bdd2e71 | 2017-04-07 16:11:56 +0200 | [diff] [blame] | 926 | irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 927 | { |
| 928 | if (irq_info->dsisr & CXL_PSL_DSISR_TRANS) |
| 929 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); |
| 930 | else |
| 931 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); |
| 932 | |
| 933 | return IRQ_HANDLED; |
| 934 | } |
| 935 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 936 | static irqreturn_t native_irq_multiplexed(int irq, void *data) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 937 | { |
| 938 | struct cxl_afu *afu = data; |
| 939 | struct cxl_context *ctx; |
| 940 | struct cxl_irq_info irq_info; |
Vaibhav Jain | abf051b | 2016-11-16 19:39:33 +0530 | [diff] [blame] | 941 | u64 phreg = cxl_p2n_read(afu, CXL_PSL_PEHandle_An); |
Christophe Lombard | bdd2e71 | 2017-04-07 16:11:56 +0200 | [diff] [blame] | 942 | int ph, ret = IRQ_HANDLED, res; |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 943 | |
Vaibhav Jain | abf051b | 2016-11-16 19:39:33 +0530 | [diff] [blame] | 944 | /* check if eeh kicked in while the interrupt was in flight */ |
| 945 | if (unlikely(phreg == ~0ULL)) { |
| 946 | dev_warn(&afu->dev, |
| 947 | "Ignoring slice interrupt(%d) due to fenced card", |
| 948 | irq); |
| 949 | return IRQ_HANDLED; |
| 950 | } |
| 951 | /* Mask the pe-handle from register value */ |
| 952 | ph = phreg & 0xffff; |
Christophe Lombard | bdd2e71 | 2017-04-07 16:11:56 +0200 | [diff] [blame] | 953 | if ((res = native_get_irq_info(afu, &irq_info))) { |
| 954 | WARN(1, "Unable to get CXL IRQ Info: %i\n", res); |
| 955 | if (afu->adapter->native->sl_ops->fail_irq) |
| 956 | return afu->adapter->native->sl_ops->fail_irq(afu, &irq_info); |
| 957 | return ret; |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 958 | } |
| 959 | |
| 960 | rcu_read_lock(); |
| 961 | ctx = idr_find(&afu->contexts_idr, ph); |
| 962 | if (ctx) { |
Christophe Lombard | bdd2e71 | 2017-04-07 16:11:56 +0200 | [diff] [blame] | 963 | if (afu->adapter->native->sl_ops->handle_interrupt) |
| 964 | ret = afu->adapter->native->sl_ops->handle_interrupt(irq, ctx, &irq_info); |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 965 | rcu_read_unlock(); |
| 966 | return ret; |
| 967 | } |
| 968 | rcu_read_unlock(); |
| 969 | |
| 970 | WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR" |
| 971 | " %016llx\n(Possible AFU HW issue - was a term/remove acked" |
| 972 | " with outstanding transactions?)\n", ph, irq_info.dsisr, |
| 973 | irq_info.dar); |
Christophe Lombard | bdd2e71 | 2017-04-07 16:11:56 +0200 | [diff] [blame] | 974 | if (afu->adapter->native->sl_ops->fail_irq) |
| 975 | ret = afu->adapter->native->sl_ops->fail_irq(afu, &irq_info); |
| 976 | return ret; |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 977 | } |
| 978 | |
Andrew Donnellan | 6fd40f1 | 2016-07-22 19:01:36 +1000 | [diff] [blame] | 979 | static void native_irq_wait(struct cxl_context *ctx) |
Michael Neuling | 2bc79ff | 2016-04-22 14:57:49 +1000 | [diff] [blame] | 980 | { |
| 981 | u64 dsisr; |
| 982 | int timeout = 1000; |
| 983 | int ph; |
| 984 | |
| 985 | /* |
| 986 | * Wait until no further interrupts are presented by the PSL |
| 987 | * for this context. |
| 988 | */ |
| 989 | while (timeout--) { |
| 990 | ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff; |
| 991 | if (ph != ctx->pe) |
| 992 | return; |
| 993 | dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An); |
Christophe Lombard | abd1d99 | 2017-04-07 16:11:58 +0200 | [diff] [blame^] | 994 | if (cxl_is_psl8(ctx->afu) && |
| 995 | ((dsisr & CXL_PSL_DSISR_PENDING) == 0)) |
Michael Neuling | 2bc79ff | 2016-04-22 14:57:49 +1000 | [diff] [blame] | 996 | return; |
| 997 | /* |
| 998 | * We are waiting for the workqueue to process our |
| 999 | * irq, so need to let that run here. |
| 1000 | */ |
| 1001 | msleep(1); |
| 1002 | } |
| 1003 | |
| 1004 | dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i" |
| 1005 | " DSISR %016llx!\n", ph, dsisr); |
| 1006 | return; |
| 1007 | } |
| 1008 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1009 | static irqreturn_t native_slice_irq_err(int irq, void *data) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1010 | { |
| 1011 | struct cxl_afu *afu = data; |
Christophe Lombard | abd1d99 | 2017-04-07 16:11:58 +0200 | [diff] [blame^] | 1012 | u64 errstat, serr, afu_error, dsisr; |
| 1013 | u64 fir_slice, afu_debug; |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1014 | |
Frederic Barrat | 6d38261 | 2016-05-24 03:39:18 +1000 | [diff] [blame] | 1015 | /* |
| 1016 | * slice err interrupt is only used with full PSL (no XSL) |
| 1017 | */ |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1018 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1019 | errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); |
Philippe Bergheaud | 6e0c50f | 2016-07-05 13:08:06 +0200 | [diff] [blame] | 1020 | afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
| 1021 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
| 1022 | cxl_afu_decode_psl_serr(afu, serr); |
Christophe Lombard | abd1d99 | 2017-04-07 16:11:58 +0200 | [diff] [blame^] | 1023 | |
| 1024 | if (cxl_is_power8()) { |
| 1025 | fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An); |
| 1026 | afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An); |
| 1027 | dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); |
| 1028 | dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); |
| 1029 | } |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1030 | dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat); |
Philippe Bergheaud | 6e0c50f | 2016-07-05 13:08:06 +0200 | [diff] [blame] | 1031 | dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error); |
| 1032 | dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr); |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1033 | |
| 1034 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); |
| 1035 | |
| 1036 | return IRQ_HANDLED; |
| 1037 | } |
| 1038 | |
Frederic Barrat | 6d38261 | 2016-05-24 03:39:18 +1000 | [diff] [blame] | 1039 | void cxl_native_err_irq_dump_regs(struct cxl *adapter) |
| 1040 | { |
| 1041 | u64 fir1, fir2; |
| 1042 | |
| 1043 | fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1); |
| 1044 | fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2); |
| 1045 | |
| 1046 | dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2); |
| 1047 | } |
| 1048 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1049 | static irqreturn_t native_irq_err(int irq, void *data) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1050 | { |
| 1051 | struct cxl *adapter = data; |
Frederic Barrat | 6d38261 | 2016-05-24 03:39:18 +1000 | [diff] [blame] | 1052 | u64 err_ivte; |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1053 | |
| 1054 | WARN(1, "CXL ERROR interrupt %i\n", irq); |
| 1055 | |
| 1056 | err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE); |
| 1057 | dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte); |
| 1058 | |
Frederic Barrat | 6d38261 | 2016-05-24 03:39:18 +1000 | [diff] [blame] | 1059 | if (adapter->native->sl_ops->debugfs_stop_trace) { |
| 1060 | dev_crit(&adapter->dev, "STOPPING CXL TRACE\n"); |
| 1061 | adapter->native->sl_ops->debugfs_stop_trace(adapter); |
| 1062 | } |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1063 | |
Frederic Barrat | 6d38261 | 2016-05-24 03:39:18 +1000 | [diff] [blame] | 1064 | if (adapter->native->sl_ops->err_irq_dump_registers) |
| 1065 | adapter->native->sl_ops->err_irq_dump_registers(adapter); |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1066 | |
| 1067 | return IRQ_HANDLED; |
| 1068 | } |
| 1069 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1070 | int cxl_native_register_psl_err_irq(struct cxl *adapter) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1071 | { |
| 1072 | int rc; |
| 1073 | |
| 1074 | adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", |
| 1075 | dev_name(&adapter->dev)); |
| 1076 | if (!adapter->irq_name) |
| 1077 | return -ENOMEM; |
| 1078 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1079 | if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter, |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 1080 | &adapter->native->err_hwirq, |
| 1081 | &adapter->native->err_virq, |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1082 | adapter->irq_name))) { |
| 1083 | kfree(adapter->irq_name); |
| 1084 | adapter->irq_name = NULL; |
| 1085 | return rc; |
| 1086 | } |
| 1087 | |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 1088 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff); |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1089 | |
| 1090 | return 0; |
| 1091 | } |
| 1092 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1093 | void cxl_native_release_psl_err_irq(struct cxl *adapter) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1094 | { |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 1095 | if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq)) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1096 | return; |
| 1097 | |
| 1098 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000); |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 1099 | cxl_unmap_irq(adapter->native->err_virq, adapter); |
| 1100 | cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq); |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1101 | kfree(adapter->irq_name); |
| 1102 | } |
| 1103 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1104 | int cxl_native_register_serr_irq(struct cxl_afu *afu) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1105 | { |
| 1106 | u64 serr; |
| 1107 | int rc; |
| 1108 | |
| 1109 | afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", |
| 1110 | dev_name(&afu->dev)); |
| 1111 | if (!afu->err_irq_name) |
| 1112 | return -ENOMEM; |
| 1113 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1114 | if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu, |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1115 | &afu->serr_hwirq, |
| 1116 | &afu->serr_virq, afu->err_irq_name))) { |
| 1117 | kfree(afu->err_irq_name); |
| 1118 | afu->err_irq_name = NULL; |
| 1119 | return rc; |
| 1120 | } |
| 1121 | |
| 1122 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); |
Christophe Lombard | abd1d99 | 2017-04-07 16:11:58 +0200 | [diff] [blame^] | 1123 | if (cxl_is_power8()) |
| 1124 | serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff); |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1125 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); |
| 1126 | |
| 1127 | return 0; |
| 1128 | } |
| 1129 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1130 | void cxl_native_release_serr_irq(struct cxl_afu *afu) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1131 | { |
| 1132 | if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq)) |
| 1133 | return; |
| 1134 | |
| 1135 | cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000); |
| 1136 | cxl_unmap_irq(afu->serr_virq, afu); |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1137 | cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq); |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1138 | kfree(afu->err_irq_name); |
| 1139 | } |
| 1140 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1141 | int cxl_native_register_psl_irq(struct cxl_afu *afu) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1142 | { |
| 1143 | int rc; |
| 1144 | |
| 1145 | afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s", |
| 1146 | dev_name(&afu->dev)); |
| 1147 | if (!afu->psl_irq_name) |
| 1148 | return -ENOMEM; |
| 1149 | |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 1150 | if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed, |
| 1151 | afu, &afu->native->psl_hwirq, &afu->native->psl_virq, |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1152 | afu->psl_irq_name))) { |
| 1153 | kfree(afu->psl_irq_name); |
| 1154 | afu->psl_irq_name = NULL; |
| 1155 | } |
| 1156 | return rc; |
| 1157 | } |
| 1158 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1159 | void cxl_native_release_psl_irq(struct cxl_afu *afu) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1160 | { |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 1161 | if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq)) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1162 | return; |
| 1163 | |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 1164 | cxl_unmap_irq(afu->native->psl_virq, afu); |
| 1165 | cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq); |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1166 | kfree(afu->psl_irq_name); |
| 1167 | } |
| 1168 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 1169 | static void recover_psl_err(struct cxl_afu *afu, u64 errstat) |
| 1170 | { |
| 1171 | u64 dsisr; |
| 1172 | |
Rasmus Villemoes | de36953 | 2015-06-11 13:27:52 +0200 | [diff] [blame] | 1173 | pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 1174 | |
| 1175 | /* Clear PSL_DSISR[PE] */ |
| 1176 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
| 1177 | cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); |
| 1178 | |
| 1179 | /* Write 1s to clear error status bits */ |
| 1180 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat); |
| 1181 | } |
| 1182 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1183 | static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 1184 | { |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 1185 | trace_cxl_psl_irq_ack(ctx, tfc); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 1186 | if (tfc) |
| 1187 | cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc); |
| 1188 | if (psl_reset_mask) |
| 1189 | recover_psl_err(ctx->afu, psl_reset_mask); |
| 1190 | |
| 1191 | return 0; |
| 1192 | } |
| 1193 | |
| 1194 | int cxl_check_error(struct cxl_afu *afu) |
| 1195 | { |
| 1196 | return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL); |
| 1197 | } |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1198 | |
Christophe Lombard | 4752876 | 2016-03-04 12:26:37 +0100 | [diff] [blame] | 1199 | static bool native_support_attributes(const char *attr_name, |
| 1200 | enum cxl_attrs type) |
| 1201 | { |
| 1202 | return true; |
| 1203 | } |
| 1204 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1205 | static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1206 | { |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 1207 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1208 | return -EIO; |
| 1209 | if (unlikely(off >= afu->crs_len)) |
| 1210 | return -ERANGE; |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 1211 | *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset + |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1212 | (cr * afu->crs_len) + off); |
| 1213 | return 0; |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1214 | } |
| 1215 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1216 | static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1217 | { |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 1218 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1219 | return -EIO; |
| 1220 | if (unlikely(off >= afu->crs_len)) |
| 1221 | return -ERANGE; |
Christophe Lombard | cbffa3a | 2016-03-04 12:26:35 +0100 | [diff] [blame] | 1222 | *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset + |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1223 | (cr * afu->crs_len) + off); |
| 1224 | return 0; |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1225 | } |
| 1226 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1227 | static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1228 | { |
| 1229 | u64 aligned_off = off & ~0x3L; |
| 1230 | u32 val; |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1231 | int rc; |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1232 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1233 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1234 | if (!rc) |
| 1235 | *out = (val >> ((off & 0x3) * 8)) & 0xffff; |
| 1236 | return rc; |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1237 | } |
| 1238 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1239 | static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out) |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1240 | { |
| 1241 | u64 aligned_off = off & ~0x3L; |
| 1242 | u32 val; |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1243 | int rc; |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1244 | |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1245 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1246 | if (!rc) |
| 1247 | *out = (val >> ((off & 0x3) * 8)) & 0xff; |
| 1248 | return rc; |
Frederic Barrat | d56d301 | 2016-03-04 12:26:26 +0100 | [diff] [blame] | 1249 | } |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1250 | |
Frederic Barrat | d601ea9 | 2016-03-04 12:26:40 +0100 | [diff] [blame] | 1251 | static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in) |
| 1252 | { |
Christophe Lombard | 0d400f7 | 2016-03-04 12:26:41 +0100 | [diff] [blame] | 1253 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
Frederic Barrat | d601ea9 | 2016-03-04 12:26:40 +0100 | [diff] [blame] | 1254 | return -EIO; |
| 1255 | if (unlikely(off >= afu->crs_len)) |
| 1256 | return -ERANGE; |
| 1257 | out_le32(afu->native->afu_desc_mmio + afu->crs_offset + |
| 1258 | (cr * afu->crs_len) + off, in); |
| 1259 | return 0; |
| 1260 | } |
| 1261 | |
| 1262 | static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in) |
| 1263 | { |
| 1264 | u64 aligned_off = off & ~0x3L; |
| 1265 | u32 val32, mask, shift; |
| 1266 | int rc; |
| 1267 | |
| 1268 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); |
| 1269 | if (rc) |
| 1270 | return rc; |
| 1271 | shift = (off & 0x3) * 8; |
| 1272 | WARN_ON(shift == 24); |
| 1273 | mask = 0xffff << shift; |
| 1274 | val32 = (val32 & ~mask) | (in << shift); |
| 1275 | |
| 1276 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); |
| 1277 | return rc; |
| 1278 | } |
| 1279 | |
| 1280 | static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in) |
| 1281 | { |
| 1282 | u64 aligned_off = off & ~0x3L; |
| 1283 | u32 val32, mask, shift; |
| 1284 | int rc; |
| 1285 | |
| 1286 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); |
| 1287 | if (rc) |
| 1288 | return rc; |
| 1289 | shift = (off & 0x3) * 8; |
| 1290 | mask = 0xff << shift; |
| 1291 | val32 = (val32 & ~mask) | (in << shift); |
| 1292 | |
| 1293 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); |
| 1294 | return rc; |
| 1295 | } |
| 1296 | |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1297 | const struct cxl_backend_ops cxl_native_ops = { |
| 1298 | .module = THIS_MODULE, |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1299 | .adapter_reset = cxl_pci_reset, |
| 1300 | .alloc_one_irq = cxl_pci_alloc_one_irq, |
| 1301 | .release_one_irq = cxl_pci_release_one_irq, |
| 1302 | .alloc_irq_ranges = cxl_pci_alloc_irq_ranges, |
| 1303 | .release_irq_ranges = cxl_pci_release_irq_ranges, |
| 1304 | .setup_irq = cxl_pci_setup_irq, |
| 1305 | .handle_psl_slice_error = native_handle_psl_slice_error, |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1306 | .psl_interrupt = NULL, |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1307 | .ack_irq = native_ack_irq, |
Michael Neuling | 2bc79ff | 2016-04-22 14:57:49 +1000 | [diff] [blame] | 1308 | .irq_wait = native_irq_wait, |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1309 | .attach_process = native_attach_process, |
| 1310 | .detach_process = native_detach_process, |
Ian Munsie | 292841b | 2016-05-24 02:14:05 +1000 | [diff] [blame] | 1311 | .update_ivtes = native_update_ivtes, |
Christophe Lombard | 4752876 | 2016-03-04 12:26:37 +0100 | [diff] [blame] | 1312 | .support_attributes = native_support_attributes, |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1313 | .link_ok = cxl_adapter_link_ok, |
Frederic Barrat | 2b04cf3 | 2016-03-04 12:26:29 +0100 | [diff] [blame] | 1314 | .release_afu = cxl_pci_release_afu, |
| 1315 | .afu_read_err_buffer = cxl_pci_afu_read_err_buffer, |
| 1316 | .afu_check_and_enable = native_afu_check_and_enable, |
| 1317 | .afu_activate_mode = native_afu_activate_mode, |
| 1318 | .afu_deactivate_mode = native_afu_deactivate_mode, |
| 1319 | .afu_reset = native_afu_reset, |
| 1320 | .afu_cr_read8 = native_afu_cr_read8, |
| 1321 | .afu_cr_read16 = native_afu_cr_read16, |
| 1322 | .afu_cr_read32 = native_afu_cr_read32, |
| 1323 | .afu_cr_read64 = native_afu_cr_read64, |
Frederic Barrat | d601ea9 | 2016-03-04 12:26:40 +0100 | [diff] [blame] | 1324 | .afu_cr_write8 = native_afu_cr_write8, |
| 1325 | .afu_cr_write16 = native_afu_cr_write16, |
| 1326 | .afu_cr_write32 = native_afu_cr_write32, |
| 1327 | .read_adapter_vpd = cxl_pci_read_adapter_vpd, |
Frederic Barrat | 5be587b | 2016-03-04 12:26:28 +0100 | [diff] [blame] | 1328 | }; |