blob: 32e82cc92ea57de64b5d8152308c8e80ca062381 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
eric miaob1d907f2008-01-28 23:00:02 +00002/*
3 * Static Memory Controller
4 */
5
6#include <linux/module.h>
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/io.h>
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020010#include <linux/syscore_ops.h>
eric miaob1d907f2008-01-28 23:00:02 +000011
Russell King05678a92008-11-28 16:04:54 +000012#include <mach/hardware.h>
Marek Vasutad68bb92010-11-03 16:29:35 +010013#include <mach/smemc.h>
eric miaob1d907f2008-01-28 23:00:02 +000014
15#ifdef CONFIG_PM
eric miaob1d907f2008-01-28 23:00:02 +000016static unsigned long msc[2];
17static unsigned long sxcnfg, memclkcfg;
18static unsigned long csadrcfg[4];
19
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020020static int pxa3xx_smemc_suspend(void)
eric miaob1d907f2008-01-28 23:00:02 +000021{
Marek Vasutad68bb92010-11-03 16:29:35 +010022 msc[0] = __raw_readl(MSC0);
23 msc[1] = __raw_readl(MSC1);
24 sxcnfg = __raw_readl(SXCNFG);
25 memclkcfg = __raw_readl(MEMCLKCFG);
26 csadrcfg[0] = __raw_readl(CSADRCFG0);
27 csadrcfg[1] = __raw_readl(CSADRCFG1);
28 csadrcfg[2] = __raw_readl(CSADRCFG2);
29 csadrcfg[3] = __raw_readl(CSADRCFG3);
eric miaob1d907f2008-01-28 23:00:02 +000030
31 return 0;
32}
33
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020034static void pxa3xx_smemc_resume(void)
eric miaob1d907f2008-01-28 23:00:02 +000035{
Marek Vasutad68bb92010-11-03 16:29:35 +010036 __raw_writel(msc[0], MSC0);
37 __raw_writel(msc[1], MSC1);
38 __raw_writel(sxcnfg, SXCNFG);
39 __raw_writel(memclkcfg, MEMCLKCFG);
40 __raw_writel(csadrcfg[0], CSADRCFG0);
41 __raw_writel(csadrcfg[1], CSADRCFG1);
42 __raw_writel(csadrcfg[2], CSADRCFG2);
43 __raw_writel(csadrcfg[3], CSADRCFG3);
Igor Grinbergd107a202013-01-13 13:49:47 +020044 /* CSMSADRCFG wakes up in its default state (0), so we need to set it */
45 __raw_writel(0x2, CSMSADRCFG);
eric miaob1d907f2008-01-28 23:00:02 +000046}
47
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020048static struct syscore_ops smemc_syscore_ops = {
eric miaob1d907f2008-01-28 23:00:02 +000049 .suspend = pxa3xx_smemc_suspend,
50 .resume = pxa3xx_smemc_resume,
51};
52
eric miaob1d907f2008-01-28 23:00:02 +000053static int __init smemc_init(void)
54{
Igor Grinbergd107a202013-01-13 13:49:47 +020055 if (cpu_is_pxa3xx()) {
56 /*
57 * The only documentation we have on the
58 * Chip Select Configuration Register (CSMSADRCFG) is that
59 * it must be programmed to 0x2.
60 * Moreover, in the bit definitions, the second bit
61 * (CSMSADRCFG[1]) is called "SETALWAYS".
62 * Other bits are reserved in this register.
63 */
64 __raw_writel(0x2, CSMSADRCFG);
65
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020066 register_syscore_ops(&smemc_syscore_ops);
Igor Grinbergd107a202013-01-13 13:49:47 +020067 }
eric miaob1d907f2008-01-28 23:00:02 +000068
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020069 return 0;
eric miaob1d907f2008-01-28 23:00:02 +000070}
71subsys_initcall(smemc_init);
72#endif