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gerrit-public.fairphone.software / kernel / msm-5.4 / ad3793fc3945173f64d82d05d3ecde41f6c0435c / . / arch / m32r / lib / ashxdi3.S
blob: cd1acca539119604869514f5d30b6f32b1dc1549 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2/*
3 * linux/arch/m32r/lib/ashxdi3.S
4 *
5 * Copyright (C) 2001,2002 Hiroyuki Kondo, and Hirokazu Takata
6 *
7 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]8
9;
10; input (r0,r1) src
11; input r2 shift val
12; r3 scratch
13; output (r0,r1)
14;
15
16#ifdef CONFIG_ISA_DUAL_ISSUE
17
18#ifndef __LITTLE_ENDIAN__
19
20 .text
21 .align 4
22 .globl __ashrdi3
23__ashrdi3:
24 cmpz r2 || ldi r3, #32
25 jc r14 || cmpu r2, r3
26 bc 1f
27 ; case 32 =< shift
28 mv r1, r0 || srai r0, #31
29 addi r2, #-32
30 sra r1, r2
31 jmp r14
32 .fillinsn
331: ; case shift <32
34 mv r3, r0 || srl r1, r2
35 sra r0, r2 || neg r2, r2
36 sll r3, r2
37 or r1, r3 || jmp r14
38
39 .align 4
40 .globl __ashldi3
41 .globl __lshldi3
42__ashldi3:
43__lshldi3:
44 cmpz r2 || ldi r3, #32
45 jc r14 || cmpu r2, r3
46 bc 1f
47 ; case 32 =< shift
48 mv r0, r1 || addi r2, #-32
49 sll r0, r2 || ldi r1, #0
50 jmp r14
51 .fillinsn
521: ; case shift <32
53 mv r3, r1 || sll r0, r2
54 sll r1, r2 || neg r2, r2
55 srl r3, r2
56 or r0, r3 || jmp r14
57
58 .align 4
59 .globl __lshrdi3
60__lshrdi3:
61 cmpz r2 || ldi r3, #32
62 jc r14 || cmpu r2, r3
63 bc 1f
64 ; case 32 =< shift
65 mv r1, r0 || addi r2, #-32
66 ldi r0, #0 || srl r1, r2
67 jmp r14
68 .fillinsn
691: ; case shift <32
70 mv r3, r0 || srl r1, r2
71 srl r0, r2 || neg r2, r2
72 sll r3, r2
73 or r1, r3 || jmp r14
74
75#else /* LITTLE_ENDIAN */
76
77 .text
78 .align 4
79 .globl __ashrdi3
80__ashrdi3:
81 cmpz r2 || ldi r3, #32
82 jc r14 || cmpu r2, r3
83 bc 1f
84 ; case 32 =< shift
85 mv r0, r1 || srai r1, #31
86 addi r2, #-32
87 sra r0, r2
88 jmp r14
89 .fillinsn
901: ; case shift <32
91 mv r3, r1 || srl r0, r2
92 sra r1, r2 || neg r2, r2
93 sll r3, r2
94 or r0, r3 || jmp r14
95
96 .align 4
97 .globl __ashldi3
98 .globl __lshldi3
99__ashldi3:
100__lshldi3:
101 cmpz r2 || ldi r3, #32
102 jc r14 || cmpu r2, r3
103 bc 1f
104 ; case 32 =< shift
105 mv r1, r0 || addi r2, #-32
106 sll r1, r2 || ldi r0, #0
107 jmp r14
108 .fillinsn
1091: ; case shift <32
110 mv r3, r0 || sll r1, r2
111 sll r0, r2 || neg r2, r2
112 srl r3, r2
113 or r1, r3 || jmp r14
114
115 .align 4
116 .globl __lshrdi3
117__lshrdi3:
118 cmpz r2 || ldi r3, #32
119 jc r14 || cmpu r2, r3
120 bc 1f
121 ; case 32 =< shift
122 mv r0, r1 || addi r2, #-32
123 ldi r1, #0 || srl r0, r2
124 jmp r14
125 .fillinsn
1261: ; case shift <32
127 mv r3, r1 || srl r0, r2
128 srl r1, r2 || neg r2, r2
129 sll r3, r2
130 or r0, r3 || jmp r14
131
132#endif
133
134#else /* not CONFIG_ISA_DUAL_ISSUE */
135
136#ifndef __LITTLE_ENDIAN__
137
138 .text
139 .align 4
140 .globl __ashrdi3
141__ashrdi3:
142 beqz r2, 2f
143 cmpui r2, #32
144 bc 1f
145 ; case 32 =< shift
146 mv r1, r0
147 srai r0, #31
148 addi r2, #-32
149 sra r1, r2
150 jmp r14
151 .fillinsn
1521: ; case shift <32
153 mv r3, r0
154 srl r1, r2
155 sra r0, r2
156 neg r2, r2
157 sll r3, r2
158 or r1, r3
159 .fillinsn
1602:
161 jmp r14
162
163 .align 4
164 .globl __ashldi3
165 .globl __lshldi3
166__ashldi3:
167__lshldi3:
168 beqz r2, 2f
169 cmpui r2, #32
170 bc 1f
171 ; case 32 =< shift
172 mv r0, r1
173 addi r2, #-32
174 sll r0, r2
175 ldi r1, #0
176 jmp r14
177 .fillinsn
1781: ; case shift <32
179 mv r3, r1
180 sll r0, r2
181 sll r1, r2
182 neg r2, r2
183 srl r3, r2
184 or r0, r3
185 .fillinsn
1862:
187 jmp r14
188
189 .align 4
190 .globl __lshrdi3
191__lshrdi3:
192 beqz r2, 2f
193 cmpui r2, #32
194 bc 1f
195 ; case 32 =< shift
196 mv r1, r0
197 ldi r0, #0
198 addi r2, #-32
199 srl r1, r2
200 jmp r14
201 .fillinsn
2021: ; case shift <32
203 mv r3, r0
204 srl r1, r2
205 srl r0, r2
206 neg r2, r2
207 sll r3, r2
208 or r1, r3
209 .fillinsn
2102:
211 jmp r14
212
213#else
214
215 .text
216 .align 4
217 .globl __ashrdi3
218__ashrdi3:
219 beqz r2, 2f
220 cmpui r2, #32
221 bc 1f
222 ; case 32 =< shift
223 mv r0, r1
224 srai r1, #31
225 addi r2, #-32
226 sra r0, r2
227 jmp r14
228 .fillinsn
2291: ; case shift <32
230 mv r3, r1
231 srl r0, r2
232 sra r1, r2
233 neg r2, r2
234 sll r3, r2
235 or r0, r3
236 .fillinsn
2372:
238 jmp r14
239
240 .align 4
241 .globl __ashldi3
242 .globl __lshldi3
243__ashldi3:
244__lshldi3:
245 beqz r2, 2f
246 cmpui r2, #32
247 bc 1f
248 ; case 32 =< shift
249 mv r1, r0
250 addi r2, #-32
251 sll r1, r2
252 ldi r0, #0
253 jmp r14
254 .fillinsn
2551: ; case shift <32
256 mv r3, r0
257 sll r1, r2
258 sll r0, r2
259 neg r2, r2
260 srl r3, r2
261 or r1, r3
262 .fillinsn
2632:
264 jmp r14
265
266 .align 4
267 .globl __lshrdi3
268__lshrdi3:
269 beqz r2, 2f
270 cmpui r2, #32
271 bc 1f
272 ; case 32 =< shift
273 mv r0, r1
274 ldi r1, #0
275 addi r2, #-32
276 srl r0, r2
277 jmp r14
278 .fillinsn
2791: ; case shift <32
280 mv r3, r1
281 srl r0, r2
282 srl r1, r2
283 neg r2, r2
284 sll r3, r2
285 or r0, r3
286 .fillinsn
2872:
288 jmp r14
289
290#endif
291
292#endif /* not CONFIG_ISA_DUAL_ISSUE */
293
294 .end