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gerrit-public.fairphone.software / kernel / msm-5.4 / ae25eceab616d16a07bcaa434b84463d58a3bdc3 / . / drivers / gpu / drm / i915 / i915_oa_chv.c
blob: aa6bece7e75fcf47faa813f7976f5b590300c3f8 [file] [log] [blame]
Robert Bragg5182f642017-06-13 12:23:02 +0100[diff] [blame]1/*
2 * Autogenerated file by GPU Top : https://github.com/rib/gputop
3 * DO NOT EDIT manually!
4 *
5 *
6 * Copyright (c) 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 *
27 */
28
29#include <linux/sysfs.h>
30
31#include "i915_drv.h"
32#include "i915_oa_chv.h"
33
34enum metric_set_id {
35 METRIC_SET_ID_RENDER_BASIC = 1,
Robert Braggfc599212017-06-13 12:23:04 +0100[diff] [blame]36 METRIC_SET_ID_COMPUTE_BASIC,
37 METRIC_SET_ID_RENDER_PIPE_PROFILE,
38 METRIC_SET_ID_HDC_AND_SF,
39 METRIC_SET_ID_L3_1,
40 METRIC_SET_ID_L3_2,
41 METRIC_SET_ID_L3_3,
42 METRIC_SET_ID_L3_4,
43 METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
44 METRIC_SET_ID_SAMPLER_1,
45 METRIC_SET_ID_SAMPLER_2,
46 METRIC_SET_ID_TDL_1,
47 METRIC_SET_ID_TDL_2,
48 METRIC_SET_ID_TEST_OA,
Robert Bragg5182f642017-06-13 12:23:02 +0100[diff] [blame]49};
50
Robert Braggfc599212017-06-13 12:23:04 +0100[diff] [blame]51int i915_oa_n_builtin_metric_sets_chv = 14;
Robert Bragg5182f642017-06-13 12:23:02 +0100[diff] [blame]52
53static const struct i915_oa_reg b_counter_config_render_basic[] = {
54 { _MMIO(0x2740), 0x00000000 },
55 { _MMIO(0x2710), 0x00000000 },
56 { _MMIO(0x2714), 0x00800000 },
57 { _MMIO(0x2720), 0x00000000 },
58 { _MMIO(0x2724), 0x00800000 },
59};
60
61static const struct i915_oa_reg flex_eu_config_render_basic[] = {
62 { _MMIO(0xe458), 0x00005004 },
63 { _MMIO(0xe558), 0x00010003 },
64 { _MMIO(0xe658), 0x00012011 },
65 { _MMIO(0xe758), 0x00015014 },
66 { _MMIO(0xe45c), 0x00051050 },
67 { _MMIO(0xe55c), 0x00053052 },
68 { _MMIO(0xe65c), 0x00055054 },
69};
70
71static const struct i915_oa_reg mux_config_render_basic[] = {
72 { _MMIO(0x9888), 0x59800000 },
73 { _MMIO(0x9888), 0x59800001 },
74 { _MMIO(0x9888), 0x285a0006 },
75 { _MMIO(0x9888), 0x2c110014 },
76 { _MMIO(0x9888), 0x2e110000 },
77 { _MMIO(0x9888), 0x2c310014 },
78 { _MMIO(0x9888), 0x2e310000 },
79 { _MMIO(0x9888), 0x2b8303df },
80 { _MMIO(0x9888), 0x3580024f },
81 { _MMIO(0x9888), 0x00580888 },
82 { _MMIO(0x9888), 0x1e5a0015 },
83 { _MMIO(0x9888), 0x205a0014 },
84 { _MMIO(0x9888), 0x045a0000 },
85 { _MMIO(0x9888), 0x025a0000 },
86 { _MMIO(0x9888), 0x02180500 },
87 { _MMIO(0x9888), 0x00190555 },
88 { _MMIO(0x9888), 0x021d0500 },
89 { _MMIO(0x9888), 0x021f0a00 },
90 { _MMIO(0x9888), 0x00380444 },
91 { _MMIO(0x9888), 0x02390500 },
92 { _MMIO(0x9888), 0x003a0666 },
93 { _MMIO(0x9888), 0x00100111 },
94 { _MMIO(0x9888), 0x06110030 },
95 { _MMIO(0x9888), 0x0a110031 },
96 { _MMIO(0x9888), 0x0e110046 },
97 { _MMIO(0x9888), 0x04110000 },
98 { _MMIO(0x9888), 0x00110000 },
99 { _MMIO(0x9888), 0x00130111 },
100 { _MMIO(0x9888), 0x00300444 },
101 { _MMIO(0x9888), 0x08310030 },
102 { _MMIO(0x9888), 0x0c310031 },
103 { _MMIO(0x9888), 0x10310046 },
104 { _MMIO(0x9888), 0x04310000 },
105 { _MMIO(0x9888), 0x00310000 },
106 { _MMIO(0x9888), 0x00330444 },
107 { _MMIO(0x9888), 0x038a0a00 },
108 { _MMIO(0x9888), 0x018b0fff },
109 { _MMIO(0x9888), 0x038b0a00 },
110 { _MMIO(0x9888), 0x01855000 },
111 { _MMIO(0x9888), 0x03850055 },
112 { _MMIO(0x9888), 0x13830021 },
113 { _MMIO(0x9888), 0x15830020 },
114 { _MMIO(0x9888), 0x1783002f },
115 { _MMIO(0x9888), 0x1983002e },
116 { _MMIO(0x9888), 0x1b83002d },
117 { _MMIO(0x9888), 0x1d83002c },
118 { _MMIO(0x9888), 0x05830000 },
119 { _MMIO(0x9888), 0x01840555 },
120 { _MMIO(0x9888), 0x03840500 },
121 { _MMIO(0x9888), 0x23800074 },
122 { _MMIO(0x9888), 0x2580007d },
123 { _MMIO(0x9888), 0x05800000 },
124 { _MMIO(0x9888), 0x01805000 },
125 { _MMIO(0x9888), 0x03800055 },
126 { _MMIO(0x9888), 0x01865000 },
127 { _MMIO(0x9888), 0x03860055 },
128 { _MMIO(0x9888), 0x01875000 },
129 { _MMIO(0x9888), 0x03870055 },
130 { _MMIO(0x9888), 0x418000aa },
131 { _MMIO(0x9888), 0x4380000a },
132 { _MMIO(0x9888), 0x45800000 },
133 { _MMIO(0x9888), 0x4780000a },
134 { _MMIO(0x9888), 0x49800000 },
135 { _MMIO(0x9888), 0x4b800000 },
136 { _MMIO(0x9888), 0x4d800000 },
137 { _MMIO(0x9888), 0x4f800000 },
138 { _MMIO(0x9888), 0x51800000 },
139 { _MMIO(0x9888), 0x53800000 },
140 { _MMIO(0x9888), 0x55800000 },
141 { _MMIO(0x9888), 0x57800000 },
142 { _MMIO(0x9888), 0x59800000 },
143};
144
145static int
146get_render_basic_mux_config(struct drm_i915_private *dev_priv,
147 const struct i915_oa_reg **regs,
148 int *lens)
149{
150 int n = 0;
151
152 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
153 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
154
155 regs[n] = mux_config_render_basic;
156 lens[n] = ARRAY_SIZE(mux_config_render_basic);
157 n++;
158
159 return n;
160}
161
Robert Braggfc599212017-06-13 12:23:04 +0100[diff] [blame]162static const struct i915_oa_reg b_counter_config_compute_basic[] = {
163 { _MMIO(0x2710), 0x00000000 },
164 { _MMIO(0x2714), 0x00800000 },
165 { _MMIO(0x2720), 0x00000000 },
166 { _MMIO(0x2724), 0x00800000 },
167};
168
169static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
170 { _MMIO(0xe458), 0x00005004 },
171 { _MMIO(0xe558), 0x00000003 },
172 { _MMIO(0xe658), 0x00002001 },
173 { _MMIO(0xe758), 0x00778008 },
174 { _MMIO(0xe45c), 0x00088078 },
175 { _MMIO(0xe55c), 0x00808708 },
176 { _MMIO(0xe65c), 0x00a08908 },
177};
178
179static const struct i915_oa_reg mux_config_compute_basic[] = {
180 { _MMIO(0x9888), 0x59800000 },
181 { _MMIO(0x9888), 0x59800001 },
182 { _MMIO(0x9888), 0x2e5800e0 },
183 { _MMIO(0x9888), 0x2e3800e0 },
184 { _MMIO(0x9888), 0x3580024f },
185 { _MMIO(0x9888), 0x3d800140 },
186 { _MMIO(0x9888), 0x08580042 },
187 { _MMIO(0x9888), 0x0c580040 },
188 { _MMIO(0x9888), 0x1058004c },
189 { _MMIO(0x9888), 0x1458004b },
190 { _MMIO(0x9888), 0x04580000 },
191 { _MMIO(0x9888), 0x00580000 },
192 { _MMIO(0x9888), 0x00195555 },
193 { _MMIO(0x9888), 0x06380042 },
194 { _MMIO(0x9888), 0x0a380040 },
195 { _MMIO(0x9888), 0x0e38004c },
196 { _MMIO(0x9888), 0x1238004b },
197 { _MMIO(0x9888), 0x04380000 },
198 { _MMIO(0x9888), 0x00384444 },
199 { _MMIO(0x9888), 0x003a5555 },
200 { _MMIO(0x9888), 0x018bffff },
201 { _MMIO(0x9888), 0x01845555 },
202 { _MMIO(0x9888), 0x17800074 },
203 { _MMIO(0x9888), 0x1980007d },
204 { _MMIO(0x9888), 0x1b80007c },
205 { _MMIO(0x9888), 0x1d8000b6 },
206 { _MMIO(0x9888), 0x1f8000b7 },
207 { _MMIO(0x9888), 0x05800000 },
208 { _MMIO(0x9888), 0x03800000 },
209 { _MMIO(0x9888), 0x418000aa },
210 { _MMIO(0x9888), 0x438000aa },
211 { _MMIO(0x9888), 0x45800000 },
212 { _MMIO(0x9888), 0x47800000 },
213 { _MMIO(0x9888), 0x4980012a },
214 { _MMIO(0x9888), 0x4b80012a },
215 { _MMIO(0x9888), 0x4d80012a },
216 { _MMIO(0x9888), 0x4f80012a },
217 { _MMIO(0x9888), 0x518001ce },
218 { _MMIO(0x9888), 0x538001ce },
219 { _MMIO(0x9888), 0x5580000e },
220 { _MMIO(0x9888), 0x59800000 },
221};
222
223static int
224get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
225 const struct i915_oa_reg **regs,
226 int *lens)
227{
228 int n = 0;
229
230 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
231 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
232
233 regs[n] = mux_config_compute_basic;
234 lens[n] = ARRAY_SIZE(mux_config_compute_basic);
235 n++;
236
237 return n;
238}
239
240static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
241 { _MMIO(0x2724), 0xf0800000 },
242 { _MMIO(0x2720), 0x00000000 },
243 { _MMIO(0x2714), 0xf0800000 },
244 { _MMIO(0x2710), 0x00000000 },
245 { _MMIO(0x2770), 0x0007ffea },
246 { _MMIO(0x2774), 0x00007ffc },
247 { _MMIO(0x2778), 0x0007affa },
248 { _MMIO(0x277c), 0x0000f5fd },
249 { _MMIO(0x2780), 0x00079ffa },
250 { _MMIO(0x2784), 0x0000f3fb },
251 { _MMIO(0x2788), 0x0007bf7a },
252 { _MMIO(0x278c), 0x0000f7e7 },
253 { _MMIO(0x2790), 0x0007fefa },
254 { _MMIO(0x2794), 0x0000f7cf },
255 { _MMIO(0x2798), 0x00077ffa },
256 { _MMIO(0x279c), 0x0000efdf },
257 { _MMIO(0x27a0), 0x0006fffa },
258 { _MMIO(0x27a4), 0x0000cfbf },
259 { _MMIO(0x27a8), 0x0003fffa },
260 { _MMIO(0x27ac), 0x00005f7f },
261};
262
263static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
264 { _MMIO(0xe458), 0x00005004 },
265 { _MMIO(0xe558), 0x00015014 },
266 { _MMIO(0xe658), 0x00025024 },
267 { _MMIO(0xe758), 0x00035034 },
268 { _MMIO(0xe45c), 0x00045044 },
269 { _MMIO(0xe55c), 0x00055054 },
270 { _MMIO(0xe65c), 0x00065064 },
271};
272
273static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
274 { _MMIO(0x9888), 0x59800000 },
275 { _MMIO(0x9888), 0x59800001 },
276 { _MMIO(0x9888), 0x261e0000 },
277 { _MMIO(0x9888), 0x281f000f },
278 { _MMIO(0x9888), 0x2817001a },
279 { _MMIO(0x9888), 0x2791001f },
280 { _MMIO(0x9888), 0x27880019 },
281 { _MMIO(0x9888), 0x2d890000 },
282 { _MMIO(0x9888), 0x278a0007 },
283 { _MMIO(0x9888), 0x298d001f },
284 { _MMIO(0x9888), 0x278e0020 },
285 { _MMIO(0x9888), 0x2b8f0012 },
286 { _MMIO(0x9888), 0x29900000 },
287 { _MMIO(0x9888), 0x00184000 },
288 { _MMIO(0x9888), 0x02181000 },
289 { _MMIO(0x9888), 0x02194000 },
290 { _MMIO(0x9888), 0x141e0002 },
291 { _MMIO(0x9888), 0x041e0000 },
292 { _MMIO(0x9888), 0x001e0000 },
293 { _MMIO(0x9888), 0x221f0015 },
294 { _MMIO(0x9888), 0x041f0000 },
295 { _MMIO(0x9888), 0x001f4000 },
296 { _MMIO(0x9888), 0x021f0000 },
297 { _MMIO(0x9888), 0x023a8000 },
298 { _MMIO(0x9888), 0x0213c000 },
299 { _MMIO(0x9888), 0x02164000 },
300 { _MMIO(0x9888), 0x24170012 },
301 { _MMIO(0x9888), 0x04170000 },
302 { _MMIO(0x9888), 0x07910005 },
303 { _MMIO(0x9888), 0x05910000 },
304 { _MMIO(0x9888), 0x01911500 },
305 { _MMIO(0x9888), 0x03910501 },
306 { _MMIO(0x9888), 0x0d880002 },
307 { _MMIO(0x9888), 0x1d880003 },
308 { _MMIO(0x9888), 0x05880000 },
309 { _MMIO(0x9888), 0x0b890032 },
310 { _MMIO(0x9888), 0x1b890031 },
311 { _MMIO(0x9888), 0x05890000 },
312 { _MMIO(0x9888), 0x01890040 },
313 { _MMIO(0x9888), 0x03890040 },
314 { _MMIO(0x9888), 0x098a0000 },
315 { _MMIO(0x9888), 0x198a0004 },
316 { _MMIO(0x9888), 0x058a0000 },
317 { _MMIO(0x9888), 0x018a8050 },
318 { _MMIO(0x9888), 0x038a2050 },
319 { _MMIO(0x9888), 0x018b95a9 },
320 { _MMIO(0x9888), 0x038be5a9 },
321 { _MMIO(0x9888), 0x018c1500 },
322 { _MMIO(0x9888), 0x038c0501 },
323 { _MMIO(0x9888), 0x178d0015 },
324 { _MMIO(0x9888), 0x058d0000 },
325 { _MMIO(0x9888), 0x138e0004 },
326 { _MMIO(0x9888), 0x218e000c },
327 { _MMIO(0x9888), 0x058e0000 },
328 { _MMIO(0x9888), 0x018e0500 },
329 { _MMIO(0x9888), 0x038e0101 },
330 { _MMIO(0x9888), 0x0f8f0027 },
331 { _MMIO(0x9888), 0x058f0000 },
332 { _MMIO(0x9888), 0x018f0000 },
333 { _MMIO(0x9888), 0x038f0001 },
334 { _MMIO(0x9888), 0x11900013 },
335 { _MMIO(0x9888), 0x1f900017 },
336 { _MMIO(0x9888), 0x05900000 },
337 { _MMIO(0x9888), 0x01900100 },
338 { _MMIO(0x9888), 0x03900001 },
339 { _MMIO(0x9888), 0x01845555 },
340 { _MMIO(0x9888), 0x03845555 },
341 { _MMIO(0x9888), 0x418000aa },
342 { _MMIO(0x9888), 0x438000aa },
343 { _MMIO(0x9888), 0x458000aa },
344 { _MMIO(0x9888), 0x478000aa },
345 { _MMIO(0x9888), 0x4980018c },
346 { _MMIO(0x9888), 0x4b80014b },
347 { _MMIO(0x9888), 0x4d800128 },
348 { _MMIO(0x9888), 0x4f80012a },
349 { _MMIO(0x9888), 0x51800187 },
350 { _MMIO(0x9888), 0x5380014b },
351 { _MMIO(0x9888), 0x55800149 },
352 { _MMIO(0x9888), 0x5780010a },
353 { _MMIO(0x9888), 0x59800000 },
354};
355
356static int
357get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
358 const struct i915_oa_reg **regs,
359 int *lens)
360{
361 int n = 0;
362
363 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
364 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
365
366 regs[n] = mux_config_render_pipe_profile;
367 lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
368 n++;
369
370 return n;
371}
372
373static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
374 { _MMIO(0x2740), 0x00000000 },
375 { _MMIO(0x2744), 0x00800000 },
376 { _MMIO(0x2710), 0x00000000 },
377 { _MMIO(0x2714), 0x10800000 },
378 { _MMIO(0x2720), 0x00000000 },
379 { _MMIO(0x2724), 0x00800000 },
380 { _MMIO(0x2770), 0x00000002 },
381 { _MMIO(0x2774), 0x0000fff7 },
382};
383
384static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
385 { _MMIO(0xe458), 0x00005004 },
386 { _MMIO(0xe558), 0x00010003 },
387 { _MMIO(0xe658), 0x00012011 },
388 { _MMIO(0xe758), 0x00015014 },
389 { _MMIO(0xe45c), 0x00051050 },
390 { _MMIO(0xe55c), 0x00053052 },
391 { _MMIO(0xe65c), 0x00055054 },
392};
393
394static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
395 { _MMIO(0x9888), 0x105c0232 },
396 { _MMIO(0x9888), 0x10580232 },
397 { _MMIO(0x9888), 0x10380232 },
398 { _MMIO(0x9888), 0x10dc0232 },
399 { _MMIO(0x9888), 0x10d80232 },
400 { _MMIO(0x9888), 0x10b80232 },
401 { _MMIO(0x9888), 0x118e4400 },
402 { _MMIO(0x9888), 0x025c6080 },
403 { _MMIO(0x9888), 0x045c004b },
404 { _MMIO(0x9888), 0x005c8000 },
405 { _MMIO(0x9888), 0x00582080 },
406 { _MMIO(0x9888), 0x0258004b },
407 { _MMIO(0x9888), 0x025b4000 },
408 { _MMIO(0x9888), 0x045b4000 },
409 { _MMIO(0x9888), 0x0c1fa000 },
410 { _MMIO(0x9888), 0x0e1f00aa },
411 { _MMIO(0x9888), 0x04386080 },
412 { _MMIO(0x9888), 0x0638404b },
413 { _MMIO(0x9888), 0x02384000 },
414 { _MMIO(0x9888), 0x08384000 },
415 { _MMIO(0x9888), 0x0a380000 },
416 { _MMIO(0x9888), 0x0c380000 },
417 { _MMIO(0x9888), 0x00398000 },
418 { _MMIO(0x9888), 0x0239a000 },
419 { _MMIO(0x9888), 0x0439a000 },
420 { _MMIO(0x9888), 0x06392000 },
421 { _MMIO(0x9888), 0x0cdc25c1 },
422 { _MMIO(0x9888), 0x0adcc000 },
423 { _MMIO(0x9888), 0x0ad825c1 },
424 { _MMIO(0x9888), 0x18db4000 },
425 { _MMIO(0x9888), 0x1adb0001 },
426 { _MMIO(0x9888), 0x0e9f8000 },
427 { _MMIO(0x9888), 0x109f02aa },
428 { _MMIO(0x9888), 0x0eb825c1 },
429 { _MMIO(0x9888), 0x18b80154 },
430 { _MMIO(0x9888), 0x0ab9a000 },
431 { _MMIO(0x9888), 0x0cb9a000 },
432 { _MMIO(0x9888), 0x0eb9a000 },
433 { _MMIO(0x9888), 0x0d88c000 },
434 { _MMIO(0x9888), 0x0f88000f },
435 { _MMIO(0x9888), 0x038a8000 },
436 { _MMIO(0x9888), 0x058a8000 },
437 { _MMIO(0x9888), 0x078a8000 },
438 { _MMIO(0x9888), 0x098a8000 },
439 { _MMIO(0x9888), 0x0b8a8000 },
440 { _MMIO(0x9888), 0x0d8a8000 },
441 { _MMIO(0x9888), 0x258baa05 },
442 { _MMIO(0x9888), 0x278b002a },
443 { _MMIO(0x9888), 0x238b2a80 },
444 { _MMIO(0x9888), 0x198c5400 },
445 { _MMIO(0x9888), 0x1b8c0015 },
446 { _MMIO(0x9888), 0x098dc000 },
447 { _MMIO(0x9888), 0x0b8da000 },
448 { _MMIO(0x9888), 0x0d8da000 },
449 { _MMIO(0x9888), 0x0f8da000 },
450 { _MMIO(0x9888), 0x098e05c0 },
451 { _MMIO(0x9888), 0x058e0000 },
452 { _MMIO(0x9888), 0x198f0020 },
453 { _MMIO(0x9888), 0x2185aa0a },
454 { _MMIO(0x9888), 0x2385002a },
455 { _MMIO(0x9888), 0x1f85aa00 },
456 { _MMIO(0x9888), 0x19835000 },
457 { _MMIO(0x9888), 0x1b830155 },
458 { _MMIO(0x9888), 0x03834000 },
459 { _MMIO(0x9888), 0x05834000 },
460 { _MMIO(0x9888), 0x07834000 },
461 { _MMIO(0x9888), 0x09834000 },
462 { _MMIO(0x9888), 0x0b834000 },
463 { _MMIO(0x9888), 0x0d834000 },
464 { _MMIO(0x9888), 0x09848000 },
465 { _MMIO(0x9888), 0x0b84c000 },
466 { _MMIO(0x9888), 0x0d84c000 },
467 { _MMIO(0x9888), 0x0f84c000 },
468 { _MMIO(0x9888), 0x01848000 },
469 { _MMIO(0x9888), 0x0384c000 },
470 { _MMIO(0x9888), 0x0584c000 },
471 { _MMIO(0x9888), 0x07844000 },
472 { _MMIO(0x9888), 0x19808000 },
473 { _MMIO(0x9888), 0x1b80c000 },
474 { _MMIO(0x9888), 0x1d80c000 },
475 { _MMIO(0x9888), 0x1f80c000 },
476 { _MMIO(0x9888), 0x11808000 },
477 { _MMIO(0x9888), 0x1380c000 },
478 { _MMIO(0x9888), 0x1580c000 },
479 { _MMIO(0x9888), 0x17804000 },
480 { _MMIO(0x9888), 0x51800040 },
481 { _MMIO(0x9888), 0x43800400 },
482 { _MMIO(0x9888), 0x45800800 },
483 { _MMIO(0x9888), 0x53800000 },
484 { _MMIO(0x9888), 0x47800c62 },
485 { _MMIO(0x9888), 0x21800000 },
486 { _MMIO(0x9888), 0x31800000 },
487 { _MMIO(0x9888), 0x4d800000 },
488 { _MMIO(0x9888), 0x3f801042 },
489 { _MMIO(0x9888), 0x4f800000 },
490 { _MMIO(0x9888), 0x418014a4 },
491};
492
493static int
494get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
495 const struct i915_oa_reg **regs,
496 int *lens)
497{
498 int n = 0;
499
500 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
501 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
502
503 regs[n] = mux_config_hdc_and_sf;
504 lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
505 n++;
506
507 return n;
508}
509
510static const struct i915_oa_reg b_counter_config_l3_1[] = {
511 { _MMIO(0x2740), 0x00000000 },
512 { _MMIO(0x2744), 0x00800000 },
513 { _MMIO(0x2710), 0x00000000 },
514 { _MMIO(0x2714), 0xf0800000 },
515 { _MMIO(0x2720), 0x00000000 },
516 { _MMIO(0x2724), 0xf0800000 },
517 { _MMIO(0x2770), 0x00100070 },
518 { _MMIO(0x2774), 0x0000fff1 },
519 { _MMIO(0x2778), 0x00014002 },
520 { _MMIO(0x277c), 0x0000c3ff },
521 { _MMIO(0x2780), 0x00010002 },
522 { _MMIO(0x2784), 0x0000c7ff },
523 { _MMIO(0x2788), 0x00004002 },
524 { _MMIO(0x278c), 0x0000d3ff },
525 { _MMIO(0x2790), 0x00100700 },
526 { _MMIO(0x2794), 0x0000ff1f },
527 { _MMIO(0x2798), 0x00001402 },
528 { _MMIO(0x279c), 0x0000fc3f },
529 { _MMIO(0x27a0), 0x00001002 },
530 { _MMIO(0x27a4), 0x0000fc7f },
531 { _MMIO(0x27a8), 0x00000402 },
532 { _MMIO(0x27ac), 0x0000fd3f },
533};
534
535static const struct i915_oa_reg flex_eu_config_l3_1[] = {
536 { _MMIO(0xe458), 0x00005004 },
537 { _MMIO(0xe558), 0x00010003 },
538 { _MMIO(0xe658), 0x00012011 },
539 { _MMIO(0xe758), 0x00015014 },
540 { _MMIO(0xe45c), 0x00051050 },
541 { _MMIO(0xe55c), 0x00053052 },
542 { _MMIO(0xe65c), 0x00055054 },
543};
544
545static const struct i915_oa_reg mux_config_l3_1[] = {
546 { _MMIO(0x9888), 0x10bf03da },
547 { _MMIO(0x9888), 0x14bf0001 },
548 { _MMIO(0x9888), 0x12980340 },
549 { _MMIO(0x9888), 0x12990340 },
550 { _MMIO(0x9888), 0x0cbf1187 },
551 { _MMIO(0x9888), 0x0ebf1205 },
552 { _MMIO(0x9888), 0x00bf0500 },
553 { _MMIO(0x9888), 0x02bf042b },
554 { _MMIO(0x9888), 0x04bf002c },
555 { _MMIO(0x9888), 0x0cdac000 },
556 { _MMIO(0x9888), 0x0edac000 },
557 { _MMIO(0x9888), 0x00da8000 },
558 { _MMIO(0x9888), 0x02dac000 },
559 { _MMIO(0x9888), 0x04da4000 },
560 { _MMIO(0x9888), 0x04983400 },
561 { _MMIO(0x9888), 0x10980000 },
562 { _MMIO(0x9888), 0x06990034 },
563 { _MMIO(0x9888), 0x10990000 },
564 { _MMIO(0x9888), 0x0c9dc000 },
565 { _MMIO(0x9888), 0x0e9dc000 },
566 { _MMIO(0x9888), 0x009d8000 },
567 { _MMIO(0x9888), 0x029dc000 },
568 { _MMIO(0x9888), 0x049d4000 },
569 { _MMIO(0x9888), 0x109f02a8 },
570 { _MMIO(0x9888), 0x0c9fa000 },
571 { _MMIO(0x9888), 0x0e9f00ba },
572 { _MMIO(0x9888), 0x0cb88000 },
573 { _MMIO(0x9888), 0x0cb95000 },
574 { _MMIO(0x9888), 0x0eb95000 },
575 { _MMIO(0x9888), 0x00b94000 },
576 { _MMIO(0x9888), 0x02b95000 },
577 { _MMIO(0x9888), 0x04b91000 },
578 { _MMIO(0x9888), 0x06b92000 },
579 { _MMIO(0x9888), 0x0cba4000 },
580 { _MMIO(0x9888), 0x0f88000f },
581 { _MMIO(0x9888), 0x03888000 },
582 { _MMIO(0x9888), 0x05888000 },
583 { _MMIO(0x9888), 0x07888000 },
584 { _MMIO(0x9888), 0x09888000 },
585 { _MMIO(0x9888), 0x0b888000 },
586 { _MMIO(0x9888), 0x0d880400 },
587 { _MMIO(0x9888), 0x258b800a },
588 { _MMIO(0x9888), 0x278b002a },
589 { _MMIO(0x9888), 0x238b5500 },
590 { _MMIO(0x9888), 0x198c4000 },
591 { _MMIO(0x9888), 0x1b8c0015 },
592 { _MMIO(0x9888), 0x038c4000 },
593 { _MMIO(0x9888), 0x058c4000 },
594 { _MMIO(0x9888), 0x078c4000 },
595 { _MMIO(0x9888), 0x098c4000 },
596 { _MMIO(0x9888), 0x0b8c4000 },
597 { _MMIO(0x9888), 0x0d8c4000 },
598 { _MMIO(0x9888), 0x0d8da000 },
599 { _MMIO(0x9888), 0x0f8da000 },
600 { _MMIO(0x9888), 0x018d8000 },
601 { _MMIO(0x9888), 0x038da000 },
602 { _MMIO(0x9888), 0x058da000 },
603 { _MMIO(0x9888), 0x078d2000 },
604 { _MMIO(0x9888), 0x2185800a },
605 { _MMIO(0x9888), 0x2385002a },
606 { _MMIO(0x9888), 0x1f85aa00 },
607 { _MMIO(0x9888), 0x1b830154 },
608 { _MMIO(0x9888), 0x03834000 },
609 { _MMIO(0x9888), 0x05834000 },
610 { _MMIO(0x9888), 0x07834000 },
611 { _MMIO(0x9888), 0x09834000 },
612 { _MMIO(0x9888), 0x0b834000 },
613 { _MMIO(0x9888), 0x0d834000 },
614 { _MMIO(0x9888), 0x0d84c000 },
615 { _MMIO(0x9888), 0x0f84c000 },
616 { _MMIO(0x9888), 0x01848000 },
617 { _MMIO(0x9888), 0x0384c000 },
618 { _MMIO(0x9888), 0x0584c000 },
619 { _MMIO(0x9888), 0x07844000 },
620 { _MMIO(0x9888), 0x1d80c000 },
621 { _MMIO(0x9888), 0x1f80c000 },
622 { _MMIO(0x9888), 0x11808000 },
623 { _MMIO(0x9888), 0x1380c000 },
624 { _MMIO(0x9888), 0x1580c000 },
625 { _MMIO(0x9888), 0x17804000 },
626 { _MMIO(0x9888), 0x53800000 },
627 { _MMIO(0x9888), 0x45800000 },
628 { _MMIO(0x9888), 0x47800000 },
629 { _MMIO(0x9888), 0x21800000 },
630 { _MMIO(0x9888), 0x31800000 },
631 { _MMIO(0x9888), 0x4d800000 },
632 { _MMIO(0x9888), 0x3f800000 },
633 { _MMIO(0x9888), 0x4f800000 },
634 { _MMIO(0x9888), 0x41800060 },
635};
636
637static int
638get_l3_1_mux_config(struct drm_i915_private *dev_priv,
639 const struct i915_oa_reg **regs,
640 int *lens)
641{
642 int n = 0;
643
644 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
645 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
646
647 regs[n] = mux_config_l3_1;
648 lens[n] = ARRAY_SIZE(mux_config_l3_1);
649 n++;
650
651 return n;
652}
653
654static const struct i915_oa_reg b_counter_config_l3_2[] = {
655 { _MMIO(0x2740), 0x00000000 },
656 { _MMIO(0x2744), 0x00800000 },
657 { _MMIO(0x2710), 0x00000000 },
658 { _MMIO(0x2714), 0xf0800000 },
659 { _MMIO(0x2720), 0x00000000 },
660 { _MMIO(0x2724), 0xf0800000 },
661 { _MMIO(0x2770), 0x00100070 },
662 { _MMIO(0x2774), 0x0000fff1 },
663 { _MMIO(0x2778), 0x00014002 },
664 { _MMIO(0x277c), 0x0000c3ff },
665 { _MMIO(0x2780), 0x00010002 },
666 { _MMIO(0x2784), 0x0000c7ff },
667 { _MMIO(0x2788), 0x00004002 },
668 { _MMIO(0x278c), 0x0000d3ff },
669 { _MMIO(0x2790), 0x00100700 },
670 { _MMIO(0x2794), 0x0000ff1f },
671 { _MMIO(0x2798), 0x00001402 },
672 { _MMIO(0x279c), 0x0000fc3f },
673 { _MMIO(0x27a0), 0x00001002 },
674 { _MMIO(0x27a4), 0x0000fc7f },
675 { _MMIO(0x27a8), 0x00000402 },
676 { _MMIO(0x27ac), 0x0000fd3f },
677};
678
679static const struct i915_oa_reg flex_eu_config_l3_2[] = {
680 { _MMIO(0xe458), 0x00005004 },
681 { _MMIO(0xe558), 0x00010003 },
682 { _MMIO(0xe658), 0x00012011 },
683 { _MMIO(0xe758), 0x00015014 },
684 { _MMIO(0xe45c), 0x00051050 },
685 { _MMIO(0xe55c), 0x00053052 },
686 { _MMIO(0xe65c), 0x00055054 },
687};
688
689static const struct i915_oa_reg mux_config_l3_2[] = {
690 { _MMIO(0x9888), 0x103f03da },
691 { _MMIO(0x9888), 0x143f0001 },
692 { _MMIO(0x9888), 0x12180340 },
693 { _MMIO(0x9888), 0x12190340 },
694 { _MMIO(0x9888), 0x0c3f1187 },
695 { _MMIO(0x9888), 0x0e3f1205 },
696 { _MMIO(0x9888), 0x003f0500 },
697 { _MMIO(0x9888), 0x023f042b },
698 { _MMIO(0x9888), 0x043f002c },
699 { _MMIO(0x9888), 0x0c5ac000 },
700 { _MMIO(0x9888), 0x0e5ac000 },
701 { _MMIO(0x9888), 0x005a8000 },
702 { _MMIO(0x9888), 0x025ac000 },
703 { _MMIO(0x9888), 0x045a4000 },
704 { _MMIO(0x9888), 0x04183400 },
705 { _MMIO(0x9888), 0x10180000 },
706 { _MMIO(0x9888), 0x06190034 },
707 { _MMIO(0x9888), 0x10190000 },
708 { _MMIO(0x9888), 0x0c1dc000 },
709 { _MMIO(0x9888), 0x0e1dc000 },
710 { _MMIO(0x9888), 0x001d8000 },
711 { _MMIO(0x9888), 0x021dc000 },
712 { _MMIO(0x9888), 0x041d4000 },
713 { _MMIO(0x9888), 0x101f02a8 },
714 { _MMIO(0x9888), 0x0c1fa000 },
715 { _MMIO(0x9888), 0x0e1f00ba },
716 { _MMIO(0x9888), 0x0c388000 },
717 { _MMIO(0x9888), 0x0c395000 },
718 { _MMIO(0x9888), 0x0e395000 },
719 { _MMIO(0x9888), 0x00394000 },
720 { _MMIO(0x9888), 0x02395000 },
721 { _MMIO(0x9888), 0x04391000 },
722 { _MMIO(0x9888), 0x06392000 },
723 { _MMIO(0x9888), 0x0c3a4000 },
724 { _MMIO(0x9888), 0x1b8aa800 },
725 { _MMIO(0x9888), 0x1d8a0002 },
726 { _MMIO(0x9888), 0x038a8000 },
727 { _MMIO(0x9888), 0x058a8000 },
728 { _MMIO(0x9888), 0x078a8000 },
729 { _MMIO(0x9888), 0x098a8000 },
730 { _MMIO(0x9888), 0x0b8a8000 },
731 { _MMIO(0x9888), 0x0d8a8000 },
732 { _MMIO(0x9888), 0x258b4005 },
733 { _MMIO(0x9888), 0x278b0015 },
734 { _MMIO(0x9888), 0x238b2a80 },
735 { _MMIO(0x9888), 0x2185800a },
736 { _MMIO(0x9888), 0x2385002a },
737 { _MMIO(0x9888), 0x1f85aa00 },
738 { _MMIO(0x9888), 0x1b830154 },
739 { _MMIO(0x9888), 0x03834000 },
740 { _MMIO(0x9888), 0x05834000 },
741 { _MMIO(0x9888), 0x07834000 },
742 { _MMIO(0x9888), 0x09834000 },
743 { _MMIO(0x9888), 0x0b834000 },
744 { _MMIO(0x9888), 0x0d834000 },
745 { _MMIO(0x9888), 0x0d84c000 },
746 { _MMIO(0x9888), 0x0f84c000 },
747 { _MMIO(0x9888), 0x01848000 },
748 { _MMIO(0x9888), 0x0384c000 },
749 { _MMIO(0x9888), 0x0584c000 },
750 { _MMIO(0x9888), 0x07844000 },
751 { _MMIO(0x9888), 0x1d80c000 },
752 { _MMIO(0x9888), 0x1f80c000 },
753 { _MMIO(0x9888), 0x11808000 },
754 { _MMIO(0x9888), 0x1380c000 },
755 { _MMIO(0x9888), 0x1580c000 },
756 { _MMIO(0x9888), 0x17804000 },
757 { _MMIO(0x9888), 0x53800000 },
758 { _MMIO(0x9888), 0x45800000 },
759 { _MMIO(0x9888), 0x47800000 },
760 { _MMIO(0x9888), 0x21800000 },
761 { _MMIO(0x9888), 0x31800000 },
762 { _MMIO(0x9888), 0x4d800000 },
763 { _MMIO(0x9888), 0x3f800000 },
764 { _MMIO(0x9888), 0x4f800000 },
765 { _MMIO(0x9888), 0x41800060 },
766};
767
768static int
769get_l3_2_mux_config(struct drm_i915_private *dev_priv,
770 const struct i915_oa_reg **regs,
771 int *lens)
772{
773 int n = 0;
774
775 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
776 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
777
778 regs[n] = mux_config_l3_2;
779 lens[n] = ARRAY_SIZE(mux_config_l3_2);
780 n++;
781
782 return n;
783}
784
785static const struct i915_oa_reg b_counter_config_l3_3[] = {
786 { _MMIO(0x2740), 0x00000000 },
787 { _MMIO(0x2744), 0x00800000 },
788 { _MMIO(0x2710), 0x00000000 },
789 { _MMIO(0x2714), 0xf0800000 },
790 { _MMIO(0x2720), 0x00000000 },
791 { _MMIO(0x2724), 0xf0800000 },
792 { _MMIO(0x2770), 0x00100070 },
793 { _MMIO(0x2774), 0x0000fff1 },
794 { _MMIO(0x2778), 0x00014002 },
795 { _MMIO(0x277c), 0x0000c3ff },
796 { _MMIO(0x2780), 0x00010002 },
797 { _MMIO(0x2784), 0x0000c7ff },
798 { _MMIO(0x2788), 0x00004002 },
799 { _MMIO(0x278c), 0x0000d3ff },
800 { _MMIO(0x2790), 0x00100700 },
801 { _MMIO(0x2794), 0x0000ff1f },
802 { _MMIO(0x2798), 0x00001402 },
803 { _MMIO(0x279c), 0x0000fc3f },
804 { _MMIO(0x27a0), 0x00001002 },
805 { _MMIO(0x27a4), 0x0000fc7f },
806 { _MMIO(0x27a8), 0x00000402 },
807 { _MMIO(0x27ac), 0x0000fd3f },
808};
809
810static const struct i915_oa_reg flex_eu_config_l3_3[] = {
811 { _MMIO(0xe458), 0x00005004 },
812 { _MMIO(0xe558), 0x00010003 },
813 { _MMIO(0xe658), 0x00012011 },
814 { _MMIO(0xe758), 0x00015014 },
815 { _MMIO(0xe45c), 0x00051050 },
816 { _MMIO(0xe55c), 0x00053052 },
817 { _MMIO(0xe65c), 0x00055054 },
818};
819
820static const struct i915_oa_reg mux_config_l3_3[] = {
821 { _MMIO(0x9888), 0x121b0340 },
822 { _MMIO(0x9888), 0x103f0274 },
823 { _MMIO(0x9888), 0x123f0000 },
824 { _MMIO(0x9888), 0x129b0340 },
825 { _MMIO(0x9888), 0x10bf0274 },
826 { _MMIO(0x9888), 0x12bf0000 },
827 { _MMIO(0x9888), 0x041b3400 },
828 { _MMIO(0x9888), 0x101b0000 },
829 { _MMIO(0x9888), 0x045c8000 },
830 { _MMIO(0x9888), 0x0a3d4000 },
831 { _MMIO(0x9888), 0x003f0080 },
832 { _MMIO(0x9888), 0x023f0793 },
833 { _MMIO(0x9888), 0x043f0014 },
834 { _MMIO(0x9888), 0x04588000 },
835 { _MMIO(0x9888), 0x005a8000 },
836 { _MMIO(0x9888), 0x025ac000 },
837 { _MMIO(0x9888), 0x045a4000 },
838 { _MMIO(0x9888), 0x0a5b4000 },
839 { _MMIO(0x9888), 0x001d8000 },
840 { _MMIO(0x9888), 0x021dc000 },
841 { _MMIO(0x9888), 0x041d4000 },
842 { _MMIO(0x9888), 0x0c1fa000 },
843 { _MMIO(0x9888), 0x0e1f002a },
844 { _MMIO(0x9888), 0x0a384000 },
845 { _MMIO(0x9888), 0x00394000 },
846 { _MMIO(0x9888), 0x02395000 },
847 { _MMIO(0x9888), 0x04399000 },
848 { _MMIO(0x9888), 0x069b0034 },
849 { _MMIO(0x9888), 0x109b0000 },
850 { _MMIO(0x9888), 0x06dc4000 },
851 { _MMIO(0x9888), 0x0cbd4000 },
852 { _MMIO(0x9888), 0x0cbf0981 },
853 { _MMIO(0x9888), 0x0ebf0a0f },
854 { _MMIO(0x9888), 0x06d84000 },
855 { _MMIO(0x9888), 0x0cdac000 },
856 { _MMIO(0x9888), 0x0edac000 },
857 { _MMIO(0x9888), 0x0cdb4000 },
858 { _MMIO(0x9888), 0x0c9dc000 },
859 { _MMIO(0x9888), 0x0e9dc000 },
860 { _MMIO(0x9888), 0x109f02a8 },
861 { _MMIO(0x9888), 0x0e9f0080 },
862 { _MMIO(0x9888), 0x0cb84000 },
863 { _MMIO(0x9888), 0x0cb95000 },
864 { _MMIO(0x9888), 0x0eb95000 },
865 { _MMIO(0x9888), 0x06b92000 },
866 { _MMIO(0x9888), 0x0f88000f },
867 { _MMIO(0x9888), 0x0d880400 },
868 { _MMIO(0x9888), 0x038a8000 },
869 { _MMIO(0x9888), 0x058a8000 },
870 { _MMIO(0x9888), 0x078a8000 },
871 { _MMIO(0x9888), 0x098a8000 },
872 { _MMIO(0x9888), 0x0b8a8000 },
873 { _MMIO(0x9888), 0x258b8009 },
874 { _MMIO(0x9888), 0x278b002a },
875 { _MMIO(0x9888), 0x238b2a80 },
876 { _MMIO(0x9888), 0x198c4000 },
877 { _MMIO(0x9888), 0x1b8c0015 },
878 { _MMIO(0x9888), 0x0d8c4000 },
879 { _MMIO(0x9888), 0x0d8da000 },
880 { _MMIO(0x9888), 0x0f8da000 },
881 { _MMIO(0x9888), 0x078d2000 },
882 { _MMIO(0x9888), 0x2185800a },
883 { _MMIO(0x9888), 0x2385002a },
884 { _MMIO(0x9888), 0x1f85aa00 },
885 { _MMIO(0x9888), 0x1b830154 },
886 { _MMIO(0x9888), 0x03834000 },
887 { _MMIO(0x9888), 0x05834000 },
888 { _MMIO(0x9888), 0x07834000 },
889 { _MMIO(0x9888), 0x09834000 },
890 { _MMIO(0x9888), 0x0b834000 },
891 { _MMIO(0x9888), 0x0d834000 },
892 { _MMIO(0x9888), 0x0d84c000 },
893 { _MMIO(0x9888), 0x0f84c000 },
894 { _MMIO(0x9888), 0x01848000 },
895 { _MMIO(0x9888), 0x0384c000 },
896 { _MMIO(0x9888), 0x0584c000 },
897 { _MMIO(0x9888), 0x07844000 },
898 { _MMIO(0x9888), 0x1d80c000 },
899 { _MMIO(0x9888), 0x1f80c000 },
900 { _MMIO(0x9888), 0x11808000 },
901 { _MMIO(0x9888), 0x1380c000 },
902 { _MMIO(0x9888), 0x1580c000 },
903 { _MMIO(0x9888), 0x17804000 },
904 { _MMIO(0x9888), 0x53800000 },
905 { _MMIO(0x9888), 0x45800c00 },
906 { _MMIO(0x9888), 0x47800c63 },
907 { _MMIO(0x9888), 0x21800000 },
908 { _MMIO(0x9888), 0x31800000 },
909 { _MMIO(0x9888), 0x4d800000 },
910 { _MMIO(0x9888), 0x3f8014a5 },
911 { _MMIO(0x9888), 0x4f800000 },
912 { _MMIO(0x9888), 0x41800045 },
913};
914
915static int
916get_l3_3_mux_config(struct drm_i915_private *dev_priv,
917 const struct i915_oa_reg **regs,
918 int *lens)
919{
920 int n = 0;
921
922 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
923 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
924
925 regs[n] = mux_config_l3_3;
926 lens[n] = ARRAY_SIZE(mux_config_l3_3);
927 n++;
928
929 return n;
930}
931
932static const struct i915_oa_reg b_counter_config_l3_4[] = {
933 { _MMIO(0x2740), 0x00000000 },
934 { _MMIO(0x2744), 0x00800000 },
935 { _MMIO(0x2710), 0x00000000 },
936 { _MMIO(0x2714), 0xf0800000 },
937 { _MMIO(0x2720), 0x00000000 },
938 { _MMIO(0x2724), 0xf0800000 },
939 { _MMIO(0x2770), 0x00100070 },
940 { _MMIO(0x2774), 0x0000fff1 },
941 { _MMIO(0x2778), 0x00014002 },
942 { _MMIO(0x277c), 0x0000c3ff },
943 { _MMIO(0x2780), 0x00010002 },
944 { _MMIO(0x2784), 0x0000c7ff },
945 { _MMIO(0x2788), 0x00004002 },
946 { _MMIO(0x278c), 0x0000d3ff },
947 { _MMIO(0x2790), 0x00100700 },
948 { _MMIO(0x2794), 0x0000ff1f },
949 { _MMIO(0x2798), 0x00001402 },
950 { _MMIO(0x279c), 0x0000fc3f },
951 { _MMIO(0x27a0), 0x00001002 },
952 { _MMIO(0x27a4), 0x0000fc7f },
953 { _MMIO(0x27a8), 0x00000402 },
954 { _MMIO(0x27ac), 0x0000fd3f },
955};
956
957static const struct i915_oa_reg flex_eu_config_l3_4[] = {
958 { _MMIO(0xe458), 0x00005004 },
959 { _MMIO(0xe558), 0x00010003 },
960 { _MMIO(0xe658), 0x00012011 },
961 { _MMIO(0xe758), 0x00015014 },
962 { _MMIO(0xe45c), 0x00051050 },
963 { _MMIO(0xe55c), 0x00053052 },
964 { _MMIO(0xe65c), 0x00055054 },
965};
966
967static const struct i915_oa_reg mux_config_l3_4[] = {
968 { _MMIO(0x9888), 0x121a0340 },
969 { _MMIO(0x9888), 0x103f0017 },
970 { _MMIO(0x9888), 0x123f0020 },
971 { _MMIO(0x9888), 0x129a0340 },
972 { _MMIO(0x9888), 0x10bf0017 },
973 { _MMIO(0x9888), 0x12bf0020 },
974 { _MMIO(0x9888), 0x041a3400 },
975 { _MMIO(0x9888), 0x101a0000 },
976 { _MMIO(0x9888), 0x043b8000 },
977 { _MMIO(0x9888), 0x0a3e0010 },
978 { _MMIO(0x9888), 0x003f0200 },
979 { _MMIO(0x9888), 0x023f0113 },
980 { _MMIO(0x9888), 0x043f0014 },
981 { _MMIO(0x9888), 0x02592000 },
982 { _MMIO(0x9888), 0x005a8000 },
983 { _MMIO(0x9888), 0x025ac000 },
984 { _MMIO(0x9888), 0x045a4000 },
985 { _MMIO(0x9888), 0x0a1c8000 },
986 { _MMIO(0x9888), 0x001d8000 },
987 { _MMIO(0x9888), 0x021dc000 },
988 { _MMIO(0x9888), 0x041d4000 },
989 { _MMIO(0x9888), 0x0a1e8000 },
990 { _MMIO(0x9888), 0x0c1fa000 },
991 { _MMIO(0x9888), 0x0e1f001a },
992 { _MMIO(0x9888), 0x00394000 },
993 { _MMIO(0x9888), 0x02395000 },
994 { _MMIO(0x9888), 0x04391000 },
995 { _MMIO(0x9888), 0x069a0034 },
996 { _MMIO(0x9888), 0x109a0000 },
997 { _MMIO(0x9888), 0x06bb4000 },
998 { _MMIO(0x9888), 0x0abe0040 },
999 { _MMIO(0x9888), 0x0cbf0984 },
1000 { _MMIO(0x9888), 0x0ebf0a02 },
1001 { _MMIO(0x9888), 0x02d94000 },
1002 { _MMIO(0x9888), 0x0cdac000 },
1003 { _MMIO(0x9888), 0x0edac000 },
1004 { _MMIO(0x9888), 0x0c9c0400 },
1005 { _MMIO(0x9888), 0x0c9dc000 },
1006 { _MMIO(0x9888), 0x0e9dc000 },
1007 { _MMIO(0x9888), 0x0c9e0400 },
1008 { _MMIO(0x9888), 0x109f02a8 },
1009 { _MMIO(0x9888), 0x0e9f0040 },
1010 { _MMIO(0x9888), 0x0cb95000 },
1011 { _MMIO(0x9888), 0x0eb95000 },
1012 { _MMIO(0x9888), 0x0f88000f },
1013 { _MMIO(0x9888), 0x0d880400 },
1014 { _MMIO(0x9888), 0x038a8000 },
1015 { _MMIO(0x9888), 0x058a8000 },
1016 { _MMIO(0x9888), 0x078a8000 },
1017 { _MMIO(0x9888), 0x098a8000 },
1018 { _MMIO(0x9888), 0x0b8a8000 },
1019 { _MMIO(0x9888), 0x258b8009 },
1020 { _MMIO(0x9888), 0x278b002a },
1021 { _MMIO(0x9888), 0x238b2a80 },
1022 { _MMIO(0x9888), 0x198c4000 },
1023 { _MMIO(0x9888), 0x1b8c0015 },
1024 { _MMIO(0x9888), 0x0d8c4000 },
1025 { _MMIO(0x9888), 0x0d8da000 },
1026 { _MMIO(0x9888), 0x0f8da000 },
1027 { _MMIO(0x9888), 0x078d2000 },
1028 { _MMIO(0x9888), 0x2185800a },
1029 { _MMIO(0x9888), 0x2385002a },
1030 { _MMIO(0x9888), 0x1f85aa00 },
1031 { _MMIO(0x9888), 0x1b830154 },
1032 { _MMIO(0x9888), 0x03834000 },
1033 { _MMIO(0x9888), 0x05834000 },
1034 { _MMIO(0x9888), 0x07834000 },
1035 { _MMIO(0x9888), 0x09834000 },
1036 { _MMIO(0x9888), 0x0b834000 },
1037 { _MMIO(0x9888), 0x0d834000 },
1038 { _MMIO(0x9888), 0x0d84c000 },
1039 { _MMIO(0x9888), 0x0f84c000 },
1040 { _MMIO(0x9888), 0x01848000 },
1041 { _MMIO(0x9888), 0x0384c000 },
1042 { _MMIO(0x9888), 0x0584c000 },
1043 { _MMIO(0x9888), 0x07844000 },
1044 { _MMIO(0x9888), 0x1d80c000 },
1045 { _MMIO(0x9888), 0x1f80c000 },
1046 { _MMIO(0x9888), 0x11808000 },
1047 { _MMIO(0x9888), 0x1380c000 },
1048 { _MMIO(0x9888), 0x1580c000 },
1049 { _MMIO(0x9888), 0x17804000 },
1050 { _MMIO(0x9888), 0x53800000 },
1051 { _MMIO(0x9888), 0x45800800 },
1052 { _MMIO(0x9888), 0x47800842 },
1053 { _MMIO(0x9888), 0x21800000 },
1054 { _MMIO(0x9888), 0x31800000 },
1055 { _MMIO(0x9888), 0x4d800000 },
1056 { _MMIO(0x9888), 0x3f801084 },
1057 { _MMIO(0x9888), 0x4f800000 },
1058 { _MMIO(0x9888), 0x41800044 },
1059};
1060
1061static int
1062get_l3_4_mux_config(struct drm_i915_private *dev_priv,
1063 const struct i915_oa_reg **regs,
1064 int *lens)
1065{
1066 int n = 0;
1067
1068 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1069 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1070
1071 regs[n] = mux_config_l3_4;
1072 lens[n] = ARRAY_SIZE(mux_config_l3_4);
1073 n++;
1074
1075 return n;
1076}
1077
1078static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
1079 { _MMIO(0x2740), 0x00000000 },
1080 { _MMIO(0x2744), 0x00800000 },
1081 { _MMIO(0x2710), 0x00000000 },
1082 { _MMIO(0x2714), 0xf0800000 },
1083 { _MMIO(0x2720), 0x00000000 },
1084 { _MMIO(0x2724), 0x30800000 },
1085 { _MMIO(0x2770), 0x00006000 },
1086 { _MMIO(0x2774), 0x0000f3ff },
1087 { _MMIO(0x2778), 0x00001800 },
1088 { _MMIO(0x277c), 0x0000fcff },
1089 { _MMIO(0x2780), 0x00000600 },
1090 { _MMIO(0x2784), 0x0000ff3f },
1091 { _MMIO(0x2788), 0x00000180 },
1092 { _MMIO(0x278c), 0x0000ffcf },
1093 { _MMIO(0x2790), 0x00000060 },
1094 { _MMIO(0x2794), 0x0000fff3 },
1095 { _MMIO(0x2798), 0x00000018 },
1096 { _MMIO(0x279c), 0x0000fffc },
1097};
1098
1099static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
1100 { _MMIO(0xe458), 0x00005004 },
1101 { _MMIO(0xe558), 0x00010003 },
1102 { _MMIO(0xe658), 0x00012011 },
1103 { _MMIO(0xe758), 0x00015014 },
1104 { _MMIO(0xe45c), 0x00051050 },
1105 { _MMIO(0xe55c), 0x00053052 },
1106 { _MMIO(0xe65c), 0x00055054 },
1107};
1108
1109static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
1110 { _MMIO(0x9888), 0x143b000e },
1111 { _MMIO(0x9888), 0x043c55c0 },
1112 { _MMIO(0x9888), 0x0a1e0280 },
1113 { _MMIO(0x9888), 0x0c1e0408 },
1114 { _MMIO(0x9888), 0x10390000 },
1115 { _MMIO(0x9888), 0x12397a1f },
1116 { _MMIO(0x9888), 0x14bb000e },
1117 { _MMIO(0x9888), 0x04bc5000 },
1118 { _MMIO(0x9888), 0x0a9e0296 },
1119 { _MMIO(0x9888), 0x0c9e0008 },
1120 { _MMIO(0x9888), 0x10b90000 },
1121 { _MMIO(0x9888), 0x12b97a1f },
1122 { _MMIO(0x9888), 0x063b0042 },
1123 { _MMIO(0x9888), 0x103b0000 },
1124 { _MMIO(0x9888), 0x083c0000 },
1125 { _MMIO(0x9888), 0x0a3e0040 },
1126 { _MMIO(0x9888), 0x043f8000 },
1127 { _MMIO(0x9888), 0x02594000 },
1128 { _MMIO(0x9888), 0x045a8000 },
1129 { _MMIO(0x9888), 0x0c1c0400 },
1130 { _MMIO(0x9888), 0x041d8000 },
1131 { _MMIO(0x9888), 0x081e02c0 },
1132 { _MMIO(0x9888), 0x0e1e0000 },
1133 { _MMIO(0x9888), 0x0c1fa800 },
1134 { _MMIO(0x9888), 0x0e1f0260 },
1135 { _MMIO(0x9888), 0x101f0014 },
1136 { _MMIO(0x9888), 0x003905e0 },
1137 { _MMIO(0x9888), 0x06390bc0 },
1138 { _MMIO(0x9888), 0x02390018 },
1139 { _MMIO(0x9888), 0x04394000 },
1140 { _MMIO(0x9888), 0x04bb0042 },
1141 { _MMIO(0x9888), 0x10bb0000 },
1142 { _MMIO(0x9888), 0x02bc05c0 },
1143 { _MMIO(0x9888), 0x08bc0000 },
1144 { _MMIO(0x9888), 0x0abe0004 },
1145 { _MMIO(0x9888), 0x02bf8000 },
1146 { _MMIO(0x9888), 0x02d91000 },
1147 { _MMIO(0x9888), 0x02da8000 },
1148 { _MMIO(0x9888), 0x089c8000 },
1149 { _MMIO(0x9888), 0x029d8000 },
1150 { _MMIO(0x9888), 0x089e8000 },
1151 { _MMIO(0x9888), 0x0e9e0000 },
1152 { _MMIO(0x9888), 0x0e9fa806 },
1153 { _MMIO(0x9888), 0x109f0142 },
1154 { _MMIO(0x9888), 0x08b90617 },
1155 { _MMIO(0x9888), 0x0ab90be0 },
1156 { _MMIO(0x9888), 0x02b94000 },
1157 { _MMIO(0x9888), 0x0d88f000 },
1158 { _MMIO(0x9888), 0x0f88000c },
1159 { _MMIO(0x9888), 0x07888000 },
1160 { _MMIO(0x9888), 0x09888000 },
1161 { _MMIO(0x9888), 0x018a8000 },
1162 { _MMIO(0x9888), 0x0f8a8000 },
1163 { _MMIO(0x9888), 0x1b8a2800 },
1164 { _MMIO(0x9888), 0x038a8000 },
1165 { _MMIO(0x9888), 0x058a8000 },
1166 { _MMIO(0x9888), 0x0b8a8000 },
1167 { _MMIO(0x9888), 0x0d8a8000 },
1168 { _MMIO(0x9888), 0x238b52a0 },
1169 { _MMIO(0x9888), 0x258b6a95 },
1170 { _MMIO(0x9888), 0x278b0029 },
1171 { _MMIO(0x9888), 0x178c2000 },
1172 { _MMIO(0x9888), 0x198c1500 },
1173 { _MMIO(0x9888), 0x1b8c0014 },
1174 { _MMIO(0x9888), 0x078c4000 },
1175 { _MMIO(0x9888), 0x098c4000 },
1176 { _MMIO(0x9888), 0x098da000 },
1177 { _MMIO(0x9888), 0x0b8da000 },
1178 { _MMIO(0x9888), 0x0f8da000 },
1179 { _MMIO(0x9888), 0x038d8000 },
1180 { _MMIO(0x9888), 0x058d2000 },
1181 { _MMIO(0x9888), 0x1f85aa80 },
1182 { _MMIO(0x9888), 0x2185aaaa },
1183 { _MMIO(0x9888), 0x2385002a },
1184 { _MMIO(0x9888), 0x01834000 },
1185 { _MMIO(0x9888), 0x0f834000 },
1186 { _MMIO(0x9888), 0x19835400 },
1187 { _MMIO(0x9888), 0x1b830155 },
1188 { _MMIO(0x9888), 0x03834000 },
1189 { _MMIO(0x9888), 0x05834000 },
1190 { _MMIO(0x9888), 0x07834000 },
1191 { _MMIO(0x9888), 0x09834000 },
1192 { _MMIO(0x9888), 0x0b834000 },
1193 { _MMIO(0x9888), 0x0d834000 },
1194 { _MMIO(0x9888), 0x0184c000 },
1195 { _MMIO(0x9888), 0x0784c000 },
1196 { _MMIO(0x9888), 0x0984c000 },
1197 { _MMIO(0x9888), 0x0b84c000 },
1198 { _MMIO(0x9888), 0x0d84c000 },
1199 { _MMIO(0x9888), 0x0f84c000 },
1200 { _MMIO(0x9888), 0x0384c000 },
1201 { _MMIO(0x9888), 0x0584c000 },
1202 { _MMIO(0x9888), 0x1180c000 },
1203 { _MMIO(0x9888), 0x1780c000 },
1204 { _MMIO(0x9888), 0x1980c000 },
1205 { _MMIO(0x9888), 0x1b80c000 },
1206 { _MMIO(0x9888), 0x1d80c000 },
1207 { _MMIO(0x9888), 0x1f80c000 },
1208 { _MMIO(0x9888), 0x1380c000 },
1209 { _MMIO(0x9888), 0x1580c000 },
1210 { _MMIO(0x9888), 0x4d800444 },
1211 { _MMIO(0x9888), 0x3d800000 },
1212 { _MMIO(0x9888), 0x4f804000 },
1213 { _MMIO(0x9888), 0x43801080 },
1214 { _MMIO(0x9888), 0x51800000 },
1215 { _MMIO(0x9888), 0x45800084 },
1216 { _MMIO(0x9888), 0x53800044 },
1217 { _MMIO(0x9888), 0x47801080 },
1218 { _MMIO(0x9888), 0x21800000 },
1219 { _MMIO(0x9888), 0x31800000 },
1220 { _MMIO(0x9888), 0x3f800000 },
1221 { _MMIO(0x9888), 0x41800840 },
1222};
1223
1224static int
1225get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
1226 const struct i915_oa_reg **regs,
1227 int *lens)
1228{
1229 int n = 0;
1230
1231 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1232 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1233
1234 regs[n] = mux_config_rasterizer_and_pixel_backend;
1235 lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
1236 n++;
1237
1238 return n;
1239}
1240
1241static const struct i915_oa_reg b_counter_config_sampler_1[] = {
1242 { _MMIO(0x2740), 0x00000000 },
1243 { _MMIO(0x2744), 0x00800000 },
1244 { _MMIO(0x2710), 0x00000000 },
1245 { _MMIO(0x2714), 0x70800000 },
1246 { _MMIO(0x2720), 0x00000000 },
1247 { _MMIO(0x2724), 0x00800000 },
1248 { _MMIO(0x2770), 0x0000c000 },
1249 { _MMIO(0x2774), 0x0000e7ff },
1250 { _MMIO(0x2778), 0x00003000 },
1251 { _MMIO(0x277c), 0x0000f9ff },
1252 { _MMIO(0x2780), 0x00000c00 },
1253 { _MMIO(0x2784), 0x0000fe7f },
1254};
1255
1256static const struct i915_oa_reg flex_eu_config_sampler_1[] = {
1257 { _MMIO(0xe458), 0x00005004 },
1258 { _MMIO(0xe558), 0x00010003 },
1259 { _MMIO(0xe658), 0x00012011 },
1260 { _MMIO(0xe758), 0x00015014 },
1261 { _MMIO(0xe45c), 0x00051050 },
1262 { _MMIO(0xe55c), 0x00053052 },
1263 { _MMIO(0xe65c), 0x00055054 },
1264};
1265
1266static const struct i915_oa_reg mux_config_sampler_1[] = {
1267 { _MMIO(0x9888), 0x18921400 },
1268 { _MMIO(0x9888), 0x149500ab },
1269 { _MMIO(0x9888), 0x18b21400 },
1270 { _MMIO(0x9888), 0x14b500ab },
1271 { _MMIO(0x9888), 0x18d21400 },
1272 { _MMIO(0x9888), 0x14d500ab },
1273 { _MMIO(0x9888), 0x0cdc8000 },
1274 { _MMIO(0x9888), 0x0edc4000 },
1275 { _MMIO(0x9888), 0x02dcc000 },
1276 { _MMIO(0x9888), 0x04dcc000 },
1277 { _MMIO(0x9888), 0x1abd00a0 },
1278 { _MMIO(0x9888), 0x0abd8000 },
1279 { _MMIO(0x9888), 0x0cd88000 },
1280 { _MMIO(0x9888), 0x0ed84000 },
1281 { _MMIO(0x9888), 0x04d88000 },
1282 { _MMIO(0x9888), 0x1adb0050 },
1283 { _MMIO(0x9888), 0x04db8000 },
1284 { _MMIO(0x9888), 0x06db8000 },
1285 { _MMIO(0x9888), 0x08db8000 },
1286 { _MMIO(0x9888), 0x0adb4000 },
1287 { _MMIO(0x9888), 0x109f02a0 },
1288 { _MMIO(0x9888), 0x0c9fa000 },
1289 { _MMIO(0x9888), 0x0e9f00aa },
1290 { _MMIO(0x9888), 0x18b82500 },
1291 { _MMIO(0x9888), 0x02b88000 },
1292 { _MMIO(0x9888), 0x04b84000 },
1293 { _MMIO(0x9888), 0x06b84000 },
1294 { _MMIO(0x9888), 0x08b84000 },
1295 { _MMIO(0x9888), 0x0ab84000 },
1296 { _MMIO(0x9888), 0x0cb88000 },
1297 { _MMIO(0x9888), 0x0cb98000 },
1298 { _MMIO(0x9888), 0x0eb9a000 },
1299 { _MMIO(0x9888), 0x00b98000 },
1300 { _MMIO(0x9888), 0x02b9a000 },
1301 { _MMIO(0x9888), 0x04b9a000 },
1302 { _MMIO(0x9888), 0x06b92000 },
1303 { _MMIO(0x9888), 0x1aba0200 },
1304 { _MMIO(0x9888), 0x02ba8000 },
1305 { _MMIO(0x9888), 0x0cba8000 },
1306 { _MMIO(0x9888), 0x04908000 },
1307 { _MMIO(0x9888), 0x04918000 },
1308 { _MMIO(0x9888), 0x04927300 },
1309 { _MMIO(0x9888), 0x10920000 },
1310 { _MMIO(0x9888), 0x1893000a },
1311 { _MMIO(0x9888), 0x0a934000 },
1312 { _MMIO(0x9888), 0x0a946000 },
1313 { _MMIO(0x9888), 0x0c959000 },
1314 { _MMIO(0x9888), 0x0e950098 },
1315 { _MMIO(0x9888), 0x10950000 },
1316 { _MMIO(0x9888), 0x04b04000 },
1317 { _MMIO(0x9888), 0x04b14000 },
1318 { _MMIO(0x9888), 0x04b20073 },
1319 { _MMIO(0x9888), 0x10b20000 },
1320 { _MMIO(0x9888), 0x04b38000 },
1321 { _MMIO(0x9888), 0x06b38000 },
1322 { _MMIO(0x9888), 0x08b34000 },
1323 { _MMIO(0x9888), 0x04b4c000 },
1324 { _MMIO(0x9888), 0x02b59890 },
1325 { _MMIO(0x9888), 0x10b50000 },
1326 { _MMIO(0x9888), 0x06d04000 },
1327 { _MMIO(0x9888), 0x06d14000 },
1328 { _MMIO(0x9888), 0x06d20073 },
1329 { _MMIO(0x9888), 0x10d20000 },
1330 { _MMIO(0x9888), 0x18d30020 },
1331 { _MMIO(0x9888), 0x02d38000 },
1332 { _MMIO(0x9888), 0x0cd34000 },
1333 { _MMIO(0x9888), 0x0ad48000 },
1334 { _MMIO(0x9888), 0x04d42000 },
1335 { _MMIO(0x9888), 0x0ed59000 },
1336 { _MMIO(0x9888), 0x00d59800 },
1337 { _MMIO(0x9888), 0x10d50000 },
1338 { _MMIO(0x9888), 0x0f88000e },
1339 { _MMIO(0x9888), 0x03888000 },
1340 { _MMIO(0x9888), 0x05888000 },
1341 { _MMIO(0x9888), 0x07888000 },
1342 { _MMIO(0x9888), 0x09888000 },
1343 { _MMIO(0x9888), 0x0b888000 },
1344 { _MMIO(0x9888), 0x0d880400 },
1345 { _MMIO(0x9888), 0x278b002a },
1346 { _MMIO(0x9888), 0x238b5500 },
1347 { _MMIO(0x9888), 0x258b000a },
1348 { _MMIO(0x9888), 0x1b8c0015 },
1349 { _MMIO(0x9888), 0x038c4000 },
1350 { _MMIO(0x9888), 0x058c4000 },
1351 { _MMIO(0x9888), 0x078c4000 },
1352 { _MMIO(0x9888), 0x098c4000 },
1353 { _MMIO(0x9888), 0x0b8c4000 },
1354 { _MMIO(0x9888), 0x0d8c4000 },
1355 { _MMIO(0x9888), 0x0d8d8000 },
1356 { _MMIO(0x9888), 0x0f8da000 },
1357 { _MMIO(0x9888), 0x018d8000 },
1358 { _MMIO(0x9888), 0x038da000 },
1359 { _MMIO(0x9888), 0x058da000 },
1360 { _MMIO(0x9888), 0x078d2000 },
1361 { _MMIO(0x9888), 0x2385002a },
1362 { _MMIO(0x9888), 0x1f85aa00 },
1363 { _MMIO(0x9888), 0x2185000a },
1364 { _MMIO(0x9888), 0x1b830150 },
1365 { _MMIO(0x9888), 0x03834000 },
1366 { _MMIO(0x9888), 0x05834000 },
1367 { _MMIO(0x9888), 0x07834000 },
1368 { _MMIO(0x9888), 0x09834000 },
1369 { _MMIO(0x9888), 0x0b834000 },
1370 { _MMIO(0x9888), 0x0d834000 },
1371 { _MMIO(0x9888), 0x0d848000 },
1372 { _MMIO(0x9888), 0x0f84c000 },
1373 { _MMIO(0x9888), 0x01848000 },
1374 { _MMIO(0x9888), 0x0384c000 },
1375 { _MMIO(0x9888), 0x0584c000 },
1376 { _MMIO(0x9888), 0x07844000 },
1377 { _MMIO(0x9888), 0x1d808000 },
1378 { _MMIO(0x9888), 0x1f80c000 },
1379 { _MMIO(0x9888), 0x11808000 },
1380 { _MMIO(0x9888), 0x1380c000 },
1381 { _MMIO(0x9888), 0x1580c000 },
1382 { _MMIO(0x9888), 0x17804000 },
1383 { _MMIO(0x9888), 0x53800000 },
1384 { _MMIO(0x9888), 0x47801021 },
1385 { _MMIO(0x9888), 0x21800000 },
1386 { _MMIO(0x9888), 0x31800000 },
1387 { _MMIO(0x9888), 0x4d800000 },
1388 { _MMIO(0x9888), 0x3f800c64 },
1389 { _MMIO(0x9888), 0x4f800000 },
1390 { _MMIO(0x9888), 0x41800c02 },
1391};
1392
1393static int
1394get_sampler_1_mux_config(struct drm_i915_private *dev_priv,
1395 const struct i915_oa_reg **regs,
1396 int *lens)
1397{
1398 int n = 0;
1399
1400 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1401 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1402
1403 regs[n] = mux_config_sampler_1;
1404 lens[n] = ARRAY_SIZE(mux_config_sampler_1);
1405 n++;
1406
1407 return n;
1408}
1409
1410static const struct i915_oa_reg b_counter_config_sampler_2[] = {
1411 { _MMIO(0x2740), 0x00000000 },
1412 { _MMIO(0x2744), 0x00800000 },
1413 { _MMIO(0x2710), 0x00000000 },
1414 { _MMIO(0x2714), 0x70800000 },
1415 { _MMIO(0x2720), 0x00000000 },
1416 { _MMIO(0x2724), 0x00800000 },
1417 { _MMIO(0x2770), 0x0000c000 },
1418 { _MMIO(0x2774), 0x0000e7ff },
1419 { _MMIO(0x2778), 0x00003000 },
1420 { _MMIO(0x277c), 0x0000f9ff },
1421 { _MMIO(0x2780), 0x00000c00 },
1422 { _MMIO(0x2784), 0x0000fe7f },
1423};
1424
1425static const struct i915_oa_reg flex_eu_config_sampler_2[] = {
1426 { _MMIO(0xe458), 0x00005004 },
1427 { _MMIO(0xe558), 0x00010003 },
1428 { _MMIO(0xe658), 0x00012011 },
1429 { _MMIO(0xe758), 0x00015014 },
1430 { _MMIO(0xe45c), 0x00051050 },
1431 { _MMIO(0xe55c), 0x00053052 },
1432 { _MMIO(0xe65c), 0x00055054 },
1433};
1434
1435static const struct i915_oa_reg mux_config_sampler_2[] = {
1436 { _MMIO(0x9888), 0x18121400 },
1437 { _MMIO(0x9888), 0x141500ab },
1438 { _MMIO(0x9888), 0x18321400 },
1439 { _MMIO(0x9888), 0x143500ab },
1440 { _MMIO(0x9888), 0x18521400 },
1441 { _MMIO(0x9888), 0x145500ab },
1442 { _MMIO(0x9888), 0x0c5c8000 },
1443 { _MMIO(0x9888), 0x0e5c4000 },
1444 { _MMIO(0x9888), 0x025cc000 },
1445 { _MMIO(0x9888), 0x045cc000 },
1446 { _MMIO(0x9888), 0x1a3d00a0 },
1447 { _MMIO(0x9888), 0x0a3d8000 },
1448 { _MMIO(0x9888), 0x0c588000 },
1449 { _MMIO(0x9888), 0x0e584000 },
1450 { _MMIO(0x9888), 0x04588000 },
1451 { _MMIO(0x9888), 0x1a5b0050 },
1452 { _MMIO(0x9888), 0x045b8000 },
1453 { _MMIO(0x9888), 0x065b8000 },
1454 { _MMIO(0x9888), 0x085b8000 },
1455 { _MMIO(0x9888), 0x0a5b4000 },
1456 { _MMIO(0x9888), 0x101f02a0 },
1457 { _MMIO(0x9888), 0x0c1fa000 },
1458 { _MMIO(0x9888), 0x0e1f00aa },
1459 { _MMIO(0x9888), 0x18382500 },
1460 { _MMIO(0x9888), 0x02388000 },
1461 { _MMIO(0x9888), 0x04384000 },
1462 { _MMIO(0x9888), 0x06384000 },
1463 { _MMIO(0x9888), 0x08384000 },
1464 { _MMIO(0x9888), 0x0a384000 },
1465 { _MMIO(0x9888), 0x0c388000 },
1466 { _MMIO(0x9888), 0x0c398000 },
1467 { _MMIO(0x9888), 0x0e39a000 },
1468 { _MMIO(0x9888), 0x00398000 },
1469 { _MMIO(0x9888), 0x0239a000 },
1470 { _MMIO(0x9888), 0x0439a000 },
1471 { _MMIO(0x9888), 0x06392000 },
1472 { _MMIO(0x9888), 0x1a3a0200 },
1473 { _MMIO(0x9888), 0x023a8000 },
1474 { _MMIO(0x9888), 0x0c3a8000 },
1475 { _MMIO(0x9888), 0x04108000 },
1476 { _MMIO(0x9888), 0x04118000 },
1477 { _MMIO(0x9888), 0x04127300 },
1478 { _MMIO(0x9888), 0x10120000 },
1479 { _MMIO(0x9888), 0x1813000a },
1480 { _MMIO(0x9888), 0x0a134000 },
1481 { _MMIO(0x9888), 0x0a146000 },
1482 { _MMIO(0x9888), 0x0c159000 },
1483 { _MMIO(0x9888), 0x0e150098 },
1484 { _MMIO(0x9888), 0x10150000 },
1485 { _MMIO(0x9888), 0x04304000 },
1486 { _MMIO(0x9888), 0x04314000 },
1487 { _MMIO(0x9888), 0x04320073 },
1488 { _MMIO(0x9888), 0x10320000 },
1489 { _MMIO(0x9888), 0x04338000 },
1490 { _MMIO(0x9888), 0x06338000 },
1491 { _MMIO(0x9888), 0x08334000 },
1492 { _MMIO(0x9888), 0x0434c000 },
1493 { _MMIO(0x9888), 0x02359890 },
1494 { _MMIO(0x9888), 0x10350000 },
1495 { _MMIO(0x9888), 0x06504000 },
1496 { _MMIO(0x9888), 0x06514000 },
1497 { _MMIO(0x9888), 0x06520073 },
1498 { _MMIO(0x9888), 0x10520000 },
1499 { _MMIO(0x9888), 0x18530020 },
1500 { _MMIO(0x9888), 0x02538000 },
1501 { _MMIO(0x9888), 0x0c534000 },
1502 { _MMIO(0x9888), 0x0a548000 },
1503 { _MMIO(0x9888), 0x04542000 },
1504 { _MMIO(0x9888), 0x0e559000 },
1505 { _MMIO(0x9888), 0x00559800 },
1506 { _MMIO(0x9888), 0x10550000 },
1507 { _MMIO(0x9888), 0x1b8aa000 },
1508 { _MMIO(0x9888), 0x1d8a0002 },
1509 { _MMIO(0x9888), 0x038a8000 },
1510 { _MMIO(0x9888), 0x058a8000 },
1511 { _MMIO(0x9888), 0x078a8000 },
1512 { _MMIO(0x9888), 0x098a8000 },
1513 { _MMIO(0x9888), 0x0b8a8000 },
1514 { _MMIO(0x9888), 0x0d8a8000 },
1515 { _MMIO(0x9888), 0x278b0015 },
1516 { _MMIO(0x9888), 0x238b2a80 },
1517 { _MMIO(0x9888), 0x258b0005 },
1518 { _MMIO(0x9888), 0x2385002a },
1519 { _MMIO(0x9888), 0x1f85aa00 },
1520 { _MMIO(0x9888), 0x2185000a },
1521 { _MMIO(0x9888), 0x1b830150 },
1522 { _MMIO(0x9888), 0x03834000 },
1523 { _MMIO(0x9888), 0x05834000 },
1524 { _MMIO(0x9888), 0x07834000 },
1525 { _MMIO(0x9888), 0x09834000 },
1526 { _MMIO(0x9888), 0x0b834000 },
1527 { _MMIO(0x9888), 0x0d834000 },
1528 { _MMIO(0x9888), 0x0d848000 },
1529 { _MMIO(0x9888), 0x0f84c000 },
1530 { _MMIO(0x9888), 0x01848000 },
1531 { _MMIO(0x9888), 0x0384c000 },
1532 { _MMIO(0x9888), 0x0584c000 },
1533 { _MMIO(0x9888), 0x07844000 },
1534 { _MMIO(0x9888), 0x1d808000 },
1535 { _MMIO(0x9888), 0x1f80c000 },
1536 { _MMIO(0x9888), 0x11808000 },
1537 { _MMIO(0x9888), 0x1380c000 },
1538 { _MMIO(0x9888), 0x1580c000 },
1539 { _MMIO(0x9888), 0x17804000 },
1540 { _MMIO(0x9888), 0x53800000 },
1541 { _MMIO(0x9888), 0x47801021 },
1542 { _MMIO(0x9888), 0x21800000 },
1543 { _MMIO(0x9888), 0x31800000 },
1544 { _MMIO(0x9888), 0x4d800000 },
1545 { _MMIO(0x9888), 0x3f800c64 },
1546 { _MMIO(0x9888), 0x4f800000 },
1547 { _MMIO(0x9888), 0x41800c02 },
1548};
1549
1550static int
1551get_sampler_2_mux_config(struct drm_i915_private *dev_priv,
1552 const struct i915_oa_reg **regs,
1553 int *lens)
1554{
1555 int n = 0;
1556
1557 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1558 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1559
1560 regs[n] = mux_config_sampler_2;
1561 lens[n] = ARRAY_SIZE(mux_config_sampler_2);
1562 n++;
1563
1564 return n;
1565}
1566
1567static const struct i915_oa_reg b_counter_config_tdl_1[] = {
1568 { _MMIO(0x2740), 0x00000000 },
1569 { _MMIO(0x2744), 0x00800000 },
1570 { _MMIO(0x2710), 0x00000000 },
1571 { _MMIO(0x2714), 0xf0800000 },
1572 { _MMIO(0x2720), 0x00000000 },
1573 { _MMIO(0x2724), 0x30800000 },
1574 { _MMIO(0x2770), 0x00000002 },
1575 { _MMIO(0x2774), 0x0000fdff },
1576 { _MMIO(0x2778), 0x00000000 },
1577 { _MMIO(0x277c), 0x0000fe7f },
1578 { _MMIO(0x2780), 0x00000002 },
1579 { _MMIO(0x2784), 0x0000ffbf },
1580 { _MMIO(0x2788), 0x00000000 },
1581 { _MMIO(0x278c), 0x0000ffcf },
1582 { _MMIO(0x2790), 0x00000002 },
1583 { _MMIO(0x2794), 0x0000fff7 },
1584 { _MMIO(0x2798), 0x00000000 },
1585 { _MMIO(0x279c), 0x0000fff9 },
1586};
1587
1588static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
1589 { _MMIO(0xe458), 0x00005004 },
1590 { _MMIO(0xe558), 0x00010003 },
1591 { _MMIO(0xe658), 0x00012011 },
1592 { _MMIO(0xe758), 0x00015014 },
1593 { _MMIO(0xe45c), 0x00051050 },
1594 { _MMIO(0xe55c), 0x00053052 },
1595 { _MMIO(0xe65c), 0x00055054 },
1596};
1597
1598static const struct i915_oa_reg mux_config_tdl_1[] = {
1599 { _MMIO(0x9888), 0x16154d60 },
1600 { _MMIO(0x9888), 0x16352e60 },
1601 { _MMIO(0x9888), 0x16554d60 },
1602 { _MMIO(0x9888), 0x16950000 },
1603 { _MMIO(0x9888), 0x16b50000 },
1604 { _MMIO(0x9888), 0x16d50000 },
1605 { _MMIO(0x9888), 0x005c8000 },
1606 { _MMIO(0x9888), 0x045cc000 },
1607 { _MMIO(0x9888), 0x065c4000 },
1608 { _MMIO(0x9888), 0x083d8000 },
1609 { _MMIO(0x9888), 0x0a3d8000 },
1610 { _MMIO(0x9888), 0x0458c000 },
1611 { _MMIO(0x9888), 0x025b8000 },
1612 { _MMIO(0x9888), 0x085b4000 },
1613 { _MMIO(0x9888), 0x0a5b4000 },
1614 { _MMIO(0x9888), 0x0c5b8000 },
1615 { _MMIO(0x9888), 0x0c1fa000 },
1616 { _MMIO(0x9888), 0x0e1f00aa },
1617 { _MMIO(0x9888), 0x02384000 },
1618 { _MMIO(0x9888), 0x04388000 },
1619 { _MMIO(0x9888), 0x06388000 },
1620 { _MMIO(0x9888), 0x08384000 },
1621 { _MMIO(0x9888), 0x0a384000 },
1622 { _MMIO(0x9888), 0x0c384000 },
1623 { _MMIO(0x9888), 0x00398000 },
1624 { _MMIO(0x9888), 0x0239a000 },
1625 { _MMIO(0x9888), 0x0439a000 },
1626 { _MMIO(0x9888), 0x06392000 },
1627 { _MMIO(0x9888), 0x043a8000 },
1628 { _MMIO(0x9888), 0x063a8000 },
1629 { _MMIO(0x9888), 0x08138000 },
1630 { _MMIO(0x9888), 0x0a138000 },
1631 { _MMIO(0x9888), 0x06143000 },
1632 { _MMIO(0x9888), 0x0415cfc7 },
1633 { _MMIO(0x9888), 0x10150000 },
1634 { _MMIO(0x9888), 0x02338000 },
1635 { _MMIO(0x9888), 0x0c338000 },
1636 { _MMIO(0x9888), 0x04342000 },
1637 { _MMIO(0x9888), 0x06344000 },
1638 { _MMIO(0x9888), 0x0035c700 },
1639 { _MMIO(0x9888), 0x063500cf },
1640 { _MMIO(0x9888), 0x10350000 },
1641 { _MMIO(0x9888), 0x04538000 },
1642 { _MMIO(0x9888), 0x06538000 },
1643 { _MMIO(0x9888), 0x0454c000 },
1644 { _MMIO(0x9888), 0x0255cfc7 },
1645 { _MMIO(0x9888), 0x10550000 },
1646 { _MMIO(0x9888), 0x06dc8000 },
1647 { _MMIO(0x9888), 0x08dc4000 },
1648 { _MMIO(0x9888), 0x0cdcc000 },
1649 { _MMIO(0x9888), 0x0edcc000 },
1650 { _MMIO(0x9888), 0x1abd00a8 },
1651 { _MMIO(0x9888), 0x0cd8c000 },
1652 { _MMIO(0x9888), 0x0ed84000 },
1653 { _MMIO(0x9888), 0x0edb8000 },
1654 { _MMIO(0x9888), 0x18db0800 },
1655 { _MMIO(0x9888), 0x1adb0254 },
1656 { _MMIO(0x9888), 0x0e9faa00 },
1657 { _MMIO(0x9888), 0x109f02aa },
1658 { _MMIO(0x9888), 0x0eb84000 },
1659 { _MMIO(0x9888), 0x16b84000 },
1660 { _MMIO(0x9888), 0x18b8156a },
1661 { _MMIO(0x9888), 0x06b98000 },
1662 { _MMIO(0x9888), 0x08b9a000 },
1663 { _MMIO(0x9888), 0x0ab9a000 },
1664 { _MMIO(0x9888), 0x0cb9a000 },
1665 { _MMIO(0x9888), 0x0eb9a000 },
1666 { _MMIO(0x9888), 0x18baa000 },
1667 { _MMIO(0x9888), 0x1aba0002 },
1668 { _MMIO(0x9888), 0x16934000 },
1669 { _MMIO(0x9888), 0x1893000a },
1670 { _MMIO(0x9888), 0x0a947000 },
1671 { _MMIO(0x9888), 0x0c95c5c1 },
1672 { _MMIO(0x9888), 0x0e9500c3 },
1673 { _MMIO(0x9888), 0x10950000 },
1674 { _MMIO(0x9888), 0x0eb38000 },
1675 { _MMIO(0x9888), 0x16b30040 },
1676 { _MMIO(0x9888), 0x18b30020 },
1677 { _MMIO(0x9888), 0x06b48000 },
1678 { _MMIO(0x9888), 0x08b41000 },
1679 { _MMIO(0x9888), 0x0ab48000 },
1680 { _MMIO(0x9888), 0x06b5c500 },
1681 { _MMIO(0x9888), 0x08b500c3 },
1682 { _MMIO(0x9888), 0x0eb5c100 },
1683 { _MMIO(0x9888), 0x10b50000 },
1684 { _MMIO(0x9888), 0x16d31500 },
1685 { _MMIO(0x9888), 0x08d4e000 },
1686 { _MMIO(0x9888), 0x08d5c100 },
1687 { _MMIO(0x9888), 0x0ad5c3c5 },
1688 { _MMIO(0x9888), 0x10d50000 },
1689 { _MMIO(0x9888), 0x0d88f800 },
1690 { _MMIO(0x9888), 0x0f88000f },
1691 { _MMIO(0x9888), 0x038a8000 },
1692 { _MMIO(0x9888), 0x058a8000 },
1693 { _MMIO(0x9888), 0x078a8000 },
1694 { _MMIO(0x9888), 0x098a8000 },
1695 { _MMIO(0x9888), 0x0b8a8000 },
1696 { _MMIO(0x9888), 0x0d8a8000 },
1697 { _MMIO(0x9888), 0x258baaa5 },
1698 { _MMIO(0x9888), 0x278b002a },
1699 { _MMIO(0x9888), 0x238b2a80 },
1700 { _MMIO(0x9888), 0x0f8c4000 },
1701 { _MMIO(0x9888), 0x178c2000 },
1702 { _MMIO(0x9888), 0x198c5500 },
1703 { _MMIO(0x9888), 0x1b8c0015 },
1704 { _MMIO(0x9888), 0x078d8000 },
1705 { _MMIO(0x9888), 0x098da000 },
1706 { _MMIO(0x9888), 0x0b8da000 },
1707 { _MMIO(0x9888), 0x0d8da000 },
1708 { _MMIO(0x9888), 0x0f8da000 },
1709 { _MMIO(0x9888), 0x2185aaaa },
1710 { _MMIO(0x9888), 0x2385002a },
1711 { _MMIO(0x9888), 0x1f85aa00 },
1712 { _MMIO(0x9888), 0x0f834000 },
1713 { _MMIO(0x9888), 0x19835400 },
1714 { _MMIO(0x9888), 0x1b830155 },
1715 { _MMIO(0x9888), 0x03834000 },
1716 { _MMIO(0x9888), 0x05834000 },
1717 { _MMIO(0x9888), 0x07834000 },
1718 { _MMIO(0x9888), 0x09834000 },
1719 { _MMIO(0x9888), 0x0b834000 },
1720 { _MMIO(0x9888), 0x0d834000 },
1721 { _MMIO(0x9888), 0x0784c000 },
1722 { _MMIO(0x9888), 0x0984c000 },
1723 { _MMIO(0x9888), 0x0b84c000 },
1724 { _MMIO(0x9888), 0x0d84c000 },
1725 { _MMIO(0x9888), 0x0f84c000 },
1726 { _MMIO(0x9888), 0x01848000 },
1727 { _MMIO(0x9888), 0x0384c000 },
1728 { _MMIO(0x9888), 0x0584c000 },
1729 { _MMIO(0x9888), 0x1780c000 },
1730 { _MMIO(0x9888), 0x1980c000 },
1731 { _MMIO(0x9888), 0x1b80c000 },
1732 { _MMIO(0x9888), 0x1d80c000 },
1733 { _MMIO(0x9888), 0x1f80c000 },
1734 { _MMIO(0x9888), 0x11808000 },
1735 { _MMIO(0x9888), 0x1380c000 },
1736 { _MMIO(0x9888), 0x1580c000 },
1737 { _MMIO(0x9888), 0x4f800000 },
1738 { _MMIO(0x9888), 0x43800c42 },
1739 { _MMIO(0x9888), 0x51800000 },
1740 { _MMIO(0x9888), 0x45800063 },
1741 { _MMIO(0x9888), 0x53800000 },
1742 { _MMIO(0x9888), 0x47800800 },
1743 { _MMIO(0x9888), 0x21800000 },
1744 { _MMIO(0x9888), 0x31800000 },
1745 { _MMIO(0x9888), 0x4d800000 },
1746 { _MMIO(0x9888), 0x3f8014a4 },
1747 { _MMIO(0x9888), 0x41801042 },
1748};
1749
1750static int
1751get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
1752 const struct i915_oa_reg **regs,
1753 int *lens)
1754{
1755 int n = 0;
1756
1757 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1758 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1759
1760 regs[n] = mux_config_tdl_1;
1761 lens[n] = ARRAY_SIZE(mux_config_tdl_1);
1762 n++;
1763
1764 return n;
1765}
1766
1767static const struct i915_oa_reg b_counter_config_tdl_2[] = {
1768 { _MMIO(0x2740), 0x00000000 },
1769 { _MMIO(0x2744), 0x00800000 },
1770 { _MMIO(0x2710), 0x00000000 },
1771 { _MMIO(0x2714), 0xf0800000 },
1772 { _MMIO(0x2720), 0x00000000 },
1773 { _MMIO(0x2724), 0x30800000 },
1774 { _MMIO(0x2770), 0x00000002 },
1775 { _MMIO(0x2774), 0x0000fdff },
1776 { _MMIO(0x2778), 0x00000000 },
1777 { _MMIO(0x277c), 0x0000fe7f },
1778 { _MMIO(0x2780), 0x00000000 },
1779 { _MMIO(0x2784), 0x0000ff9f },
1780 { _MMIO(0x2788), 0x00000000 },
1781 { _MMIO(0x278c), 0x0000ffe7 },
1782 { _MMIO(0x2790), 0x00000002 },
1783 { _MMIO(0x2794), 0x0000fffb },
1784 { _MMIO(0x2798), 0x00000002 },
1785 { _MMIO(0x279c), 0x0000fffd },
1786};
1787
1788static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
1789 { _MMIO(0xe458), 0x00005004 },
1790 { _MMIO(0xe558), 0x00010003 },
1791 { _MMIO(0xe658), 0x00012011 },
1792 { _MMIO(0xe758), 0x00015014 },
1793 { _MMIO(0xe45c), 0x00051050 },
1794 { _MMIO(0xe55c), 0x00053052 },
1795 { _MMIO(0xe65c), 0x00055054 },
1796};
1797
1798static const struct i915_oa_reg mux_config_tdl_2[] = {
1799 { _MMIO(0x9888), 0x16150000 },
1800 { _MMIO(0x9888), 0x16350000 },
1801 { _MMIO(0x9888), 0x16550000 },
1802 { _MMIO(0x9888), 0x16952e60 },
1803 { _MMIO(0x9888), 0x16b54d60 },
1804 { _MMIO(0x9888), 0x16d52e60 },
1805 { _MMIO(0x9888), 0x065c8000 },
1806 { _MMIO(0x9888), 0x085cc000 },
1807 { _MMIO(0x9888), 0x0a5cc000 },
1808 { _MMIO(0x9888), 0x0c5c4000 },
1809 { _MMIO(0x9888), 0x0e3d8000 },
1810 { _MMIO(0x9888), 0x183da000 },
1811 { _MMIO(0x9888), 0x06588000 },
1812 { _MMIO(0x9888), 0x08588000 },
1813 { _MMIO(0x9888), 0x0a584000 },
1814 { _MMIO(0x9888), 0x0e5b4000 },
1815 { _MMIO(0x9888), 0x185b5800 },
1816 { _MMIO(0x9888), 0x1a5b000a },
1817 { _MMIO(0x9888), 0x0e1faa00 },
1818 { _MMIO(0x9888), 0x101f02aa },
1819 { _MMIO(0x9888), 0x0e384000 },
1820 { _MMIO(0x9888), 0x16384000 },
1821 { _MMIO(0x9888), 0x18382a55 },
1822 { _MMIO(0x9888), 0x06398000 },
1823 { _MMIO(0x9888), 0x0839a000 },
1824 { _MMIO(0x9888), 0x0a39a000 },
1825 { _MMIO(0x9888), 0x0c39a000 },
1826 { _MMIO(0x9888), 0x0e39a000 },
1827 { _MMIO(0x9888), 0x1a3a02a0 },
1828 { _MMIO(0x9888), 0x0e138000 },
1829 { _MMIO(0x9888), 0x16130500 },
1830 { _MMIO(0x9888), 0x06148000 },
1831 { _MMIO(0x9888), 0x08146000 },
1832 { _MMIO(0x9888), 0x0615c100 },
1833 { _MMIO(0x9888), 0x0815c500 },
1834 { _MMIO(0x9888), 0x0a1500c3 },
1835 { _MMIO(0x9888), 0x10150000 },
1836 { _MMIO(0x9888), 0x16335040 },
1837 { _MMIO(0x9888), 0x08349000 },
1838 { _MMIO(0x9888), 0x0a341000 },
1839 { _MMIO(0x9888), 0x083500c1 },
1840 { _MMIO(0x9888), 0x0a35c500 },
1841 { _MMIO(0x9888), 0x0c3500c3 },
1842 { _MMIO(0x9888), 0x10350000 },
1843 { _MMIO(0x9888), 0x1853002a },
1844 { _MMIO(0x9888), 0x0a54e000 },
1845 { _MMIO(0x9888), 0x0c55c500 },
1846 { _MMIO(0x9888), 0x0e55c1c3 },
1847 { _MMIO(0x9888), 0x10550000 },
1848 { _MMIO(0x9888), 0x00dc8000 },
1849 { _MMIO(0x9888), 0x02dcc000 },
1850 { _MMIO(0x9888), 0x04dc4000 },
1851 { _MMIO(0x9888), 0x04bd8000 },
1852 { _MMIO(0x9888), 0x06bd8000 },
1853 { _MMIO(0x9888), 0x02d8c000 },
1854 { _MMIO(0x9888), 0x02db8000 },
1855 { _MMIO(0x9888), 0x04db4000 },
1856 { _MMIO(0x9888), 0x06db4000 },
1857 { _MMIO(0x9888), 0x08db8000 },
1858 { _MMIO(0x9888), 0x0c9fa000 },
1859 { _MMIO(0x9888), 0x0e9f00aa },
1860 { _MMIO(0x9888), 0x02b84000 },
1861 { _MMIO(0x9888), 0x04b84000 },
1862 { _MMIO(0x9888), 0x06b84000 },
1863 { _MMIO(0x9888), 0x08b84000 },
1864 { _MMIO(0x9888), 0x0ab88000 },
1865 { _MMIO(0x9888), 0x0cb88000 },
1866 { _MMIO(0x9888), 0x00b98000 },
1867 { _MMIO(0x9888), 0x02b9a000 },
1868 { _MMIO(0x9888), 0x04b9a000 },
1869 { _MMIO(0x9888), 0x06b92000 },
1870 { _MMIO(0x9888), 0x0aba8000 },
1871 { _MMIO(0x9888), 0x0cba8000 },
1872 { _MMIO(0x9888), 0x04938000 },
1873 { _MMIO(0x9888), 0x06938000 },
1874 { _MMIO(0x9888), 0x0494c000 },
1875 { _MMIO(0x9888), 0x0295cfc7 },
1876 { _MMIO(0x9888), 0x10950000 },
1877 { _MMIO(0x9888), 0x02b38000 },
1878 { _MMIO(0x9888), 0x08b38000 },
1879 { _MMIO(0x9888), 0x04b42000 },
1880 { _MMIO(0x9888), 0x06b41000 },
1881 { _MMIO(0x9888), 0x00b5c700 },
1882 { _MMIO(0x9888), 0x04b500cf },
1883 { _MMIO(0x9888), 0x10b50000 },
1884 { _MMIO(0x9888), 0x0ad38000 },
1885 { _MMIO(0x9888), 0x0cd38000 },
1886 { _MMIO(0x9888), 0x06d46000 },
1887 { _MMIO(0x9888), 0x04d5c700 },
1888 { _MMIO(0x9888), 0x06d500cf },
1889 { _MMIO(0x9888), 0x10d50000 },
1890 { _MMIO(0x9888), 0x03888000 },
1891 { _MMIO(0x9888), 0x05888000 },
1892 { _MMIO(0x9888), 0x07888000 },
1893 { _MMIO(0x9888), 0x09888000 },
1894 { _MMIO(0x9888), 0x0b888000 },
1895 { _MMIO(0x9888), 0x0d880400 },
1896 { _MMIO(0x9888), 0x0f8a8000 },
1897 { _MMIO(0x9888), 0x198a8000 },
1898 { _MMIO(0x9888), 0x1b8aaaa0 },
1899 { _MMIO(0x9888), 0x1d8a0002 },
1900 { _MMIO(0x9888), 0x258b555a },
1901 { _MMIO(0x9888), 0x278b0015 },
1902 { _MMIO(0x9888), 0x238b5500 },
1903 { _MMIO(0x9888), 0x038c4000 },
1904 { _MMIO(0x9888), 0x058c4000 },
1905 { _MMIO(0x9888), 0x078c4000 },
1906 { _MMIO(0x9888), 0x098c4000 },
1907 { _MMIO(0x9888), 0x0b8c4000 },
1908 { _MMIO(0x9888), 0x0d8c4000 },
1909 { _MMIO(0x9888), 0x018d8000 },
1910 { _MMIO(0x9888), 0x038da000 },
1911 { _MMIO(0x9888), 0x058da000 },
1912 { _MMIO(0x9888), 0x078d2000 },
1913 { _MMIO(0x9888), 0x2185aaaa },
1914 { _MMIO(0x9888), 0x2385002a },
1915 { _MMIO(0x9888), 0x1f85aa00 },
1916 { _MMIO(0x9888), 0x0f834000 },
1917 { _MMIO(0x9888), 0x19835400 },
1918 { _MMIO(0x9888), 0x1b830155 },
1919 { _MMIO(0x9888), 0x03834000 },
1920 { _MMIO(0x9888), 0x05834000 },
1921 { _MMIO(0x9888), 0x07834000 },
1922 { _MMIO(0x9888), 0x09834000 },
1923 { _MMIO(0x9888), 0x0b834000 },
1924 { _MMIO(0x9888), 0x0d834000 },
1925 { _MMIO(0x9888), 0x0784c000 },
1926 { _MMIO(0x9888), 0x0984c000 },
1927 { _MMIO(0x9888), 0x0b84c000 },
1928 { _MMIO(0x9888), 0x0d84c000 },
1929 { _MMIO(0x9888), 0x0f84c000 },
1930 { _MMIO(0x9888), 0x01848000 },
1931 { _MMIO(0x9888), 0x0384c000 },
1932 { _MMIO(0x9888), 0x0584c000 },
1933 { _MMIO(0x9888), 0x1780c000 },
1934 { _MMIO(0x9888), 0x1980c000 },
1935 { _MMIO(0x9888), 0x1b80c000 },
1936 { _MMIO(0x9888), 0x1d80c000 },
1937 { _MMIO(0x9888), 0x1f80c000 },
1938 { _MMIO(0x9888), 0x11808000 },
1939 { _MMIO(0x9888), 0x1380c000 },
1940 { _MMIO(0x9888), 0x1580c000 },
1941 { _MMIO(0x9888), 0x4f800000 },
1942 { _MMIO(0x9888), 0x43800882 },
1943 { _MMIO(0x9888), 0x51800000 },
1944 { _MMIO(0x9888), 0x45801082 },
1945 { _MMIO(0x9888), 0x53800000 },
1946 { _MMIO(0x9888), 0x478014a5 },
1947 { _MMIO(0x9888), 0x21800000 },
1948 { _MMIO(0x9888), 0x31800000 },
1949 { _MMIO(0x9888), 0x4d800000 },
1950 { _MMIO(0x9888), 0x3f800002 },
1951 { _MMIO(0x9888), 0x41800c62 },
1952};
1953
1954static int
1955get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
1956 const struct i915_oa_reg **regs,
1957 int *lens)
1958{
1959 int n = 0;
1960
1961 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1962 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1963
1964 regs[n] = mux_config_tdl_2;
1965 lens[n] = ARRAY_SIZE(mux_config_tdl_2);
1966 n++;
1967
1968 return n;
1969}
1970
1971static const struct i915_oa_reg b_counter_config_test_oa[] = {
1972 { _MMIO(0x2740), 0x00000000 },
1973 { _MMIO(0x2744), 0x00800000 },
1974 { _MMIO(0x2714), 0xf0800000 },
1975 { _MMIO(0x2710), 0x00000000 },
1976 { _MMIO(0x2724), 0xf0800000 },
1977 { _MMIO(0x2720), 0x00000000 },
1978 { _MMIO(0x2770), 0x00000004 },
1979 { _MMIO(0x2774), 0x00000000 },
1980 { _MMIO(0x2778), 0x00000003 },
1981 { _MMIO(0x277c), 0x00000000 },
1982 { _MMIO(0x2780), 0x00000007 },
1983 { _MMIO(0x2784), 0x00000000 },
1984 { _MMIO(0x2788), 0x00100002 },
1985 { _MMIO(0x278c), 0x0000fff7 },
1986 { _MMIO(0x2790), 0x00100002 },
1987 { _MMIO(0x2794), 0x0000ffcf },
1988 { _MMIO(0x2798), 0x00100082 },
1989 { _MMIO(0x279c), 0x0000ffef },
1990 { _MMIO(0x27a0), 0x001000c2 },
1991 { _MMIO(0x27a4), 0x0000ffe7 },
1992 { _MMIO(0x27a8), 0x00100001 },
1993 { _MMIO(0x27ac), 0x0000ffe7 },
1994};
1995
1996static const struct i915_oa_reg flex_eu_config_test_oa[] = {
1997};
1998
1999static const struct i915_oa_reg mux_config_test_oa[] = {
2000 { _MMIO(0x9888), 0x59800000 },
2001 { _MMIO(0x9888), 0x59800001 },
2002 { _MMIO(0x9888), 0x338b0000 },
2003 { _MMIO(0x9888), 0x258b0066 },
2004 { _MMIO(0x9888), 0x058b0000 },
2005 { _MMIO(0x9888), 0x038b0000 },
2006 { _MMIO(0x9888), 0x03844000 },
2007 { _MMIO(0x9888), 0x47800080 },
2008 { _MMIO(0x9888), 0x57800000 },
2009 { _MMIO(0x1823a4), 0x00000000 },
2010 { _MMIO(0x9888), 0x59800000 },
2011};
2012
2013static int
2014get_test_oa_mux_config(struct drm_i915_private *dev_priv,
2015 const struct i915_oa_reg **regs,
2016 int *lens)
2017{
2018 int n = 0;
2019
2020 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
2021 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
2022
2023 regs[n] = mux_config_test_oa;
2024 lens[n] = ARRAY_SIZE(mux_config_test_oa);
2025 n++;
2026
2027 return n;
2028}
2029
Robert Bragg5182f642017-06-13 12:23:02 +0100[diff] [blame]2030int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv)
2031{
2032 dev_priv->perf.oa.n_mux_configs = 0;
2033 dev_priv->perf.oa.b_counter_regs = NULL;
2034 dev_priv->perf.oa.b_counter_regs_len = 0;
2035 dev_priv->perf.oa.flex_regs = NULL;
2036 dev_priv->perf.oa.flex_regs_len = 0;
2037
2038 switch (dev_priv->perf.oa.metrics_set) {
2039 case METRIC_SET_ID_RENDER_BASIC:
2040 dev_priv->perf.oa.n_mux_configs =
2041 get_render_basic_mux_config(dev_priv,
2042 dev_priv->perf.oa.mux_regs,
2043 dev_priv->perf.oa.mux_regs_lens);
2044 if (dev_priv->perf.oa.n_mux_configs == 0) {
2045 DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
2046
2047 /* EINVAL because *_register_sysfs already checked this
2048 * and so it wouldn't have been advertised to userspace and
2049 * so shouldn't have been requested
2050 */
2051 return -EINVAL;
2052 }
2053
2054 dev_priv->perf.oa.b_counter_regs =
2055 b_counter_config_render_basic;
2056 dev_priv->perf.oa.b_counter_regs_len =
2057 ARRAY_SIZE(b_counter_config_render_basic);
2058
2059 dev_priv->perf.oa.flex_regs =
2060 flex_eu_config_render_basic;
2061 dev_priv->perf.oa.flex_regs_len =
2062 ARRAY_SIZE(flex_eu_config_render_basic);
2063
2064 return 0;
Robert Braggfc599212017-06-13 12:23:04 +0100[diff] [blame]2065 case METRIC_SET_ID_COMPUTE_BASIC:
2066 dev_priv->perf.oa.n_mux_configs =
2067 get_compute_basic_mux_config(dev_priv,
2068 dev_priv->perf.oa.mux_regs,
2069 dev_priv->perf.oa.mux_regs_lens);
2070 if (dev_priv->perf.oa.n_mux_configs == 0) {
2071 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
2072
2073 /* EINVAL because *_register_sysfs already checked this
2074 * and so it wouldn't have been advertised to userspace and
2075 * so shouldn't have been requested
2076 */
2077 return -EINVAL;
2078 }
2079
2080 dev_priv->perf.oa.b_counter_regs =
2081 b_counter_config_compute_basic;
2082 dev_priv->perf.oa.b_counter_regs_len =
2083 ARRAY_SIZE(b_counter_config_compute_basic);
2084
2085 dev_priv->perf.oa.flex_regs =
2086 flex_eu_config_compute_basic;
2087 dev_priv->perf.oa.flex_regs_len =
2088 ARRAY_SIZE(flex_eu_config_compute_basic);
2089
2090 return 0;
2091 case METRIC_SET_ID_RENDER_PIPE_PROFILE:
2092 dev_priv->perf.oa.n_mux_configs =
2093 get_render_pipe_profile_mux_config(dev_priv,
2094 dev_priv->perf.oa.mux_regs,
2095 dev_priv->perf.oa.mux_regs_lens);
2096 if (dev_priv->perf.oa.n_mux_configs == 0) {
2097 DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
2098
2099 /* EINVAL because *_register_sysfs already checked this
2100 * and so it wouldn't have been advertised to userspace and
2101 * so shouldn't have been requested
2102 */
2103 return -EINVAL;
2104 }
2105
2106 dev_priv->perf.oa.b_counter_regs =
2107 b_counter_config_render_pipe_profile;
2108 dev_priv->perf.oa.b_counter_regs_len =
2109 ARRAY_SIZE(b_counter_config_render_pipe_profile);
2110
2111 dev_priv->perf.oa.flex_regs =
2112 flex_eu_config_render_pipe_profile;
2113 dev_priv->perf.oa.flex_regs_len =
2114 ARRAY_SIZE(flex_eu_config_render_pipe_profile);
2115
2116 return 0;
2117 case METRIC_SET_ID_HDC_AND_SF:
2118 dev_priv->perf.oa.n_mux_configs =
2119 get_hdc_and_sf_mux_config(dev_priv,
2120 dev_priv->perf.oa.mux_regs,
2121 dev_priv->perf.oa.mux_regs_lens);
2122 if (dev_priv->perf.oa.n_mux_configs == 0) {
2123 DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
2124
2125 /* EINVAL because *_register_sysfs already checked this
2126 * and so it wouldn't have been advertised to userspace and
2127 * so shouldn't have been requested
2128 */
2129 return -EINVAL;
2130 }
2131
2132 dev_priv->perf.oa.b_counter_regs =
2133 b_counter_config_hdc_and_sf;
2134 dev_priv->perf.oa.b_counter_regs_len =
2135 ARRAY_SIZE(b_counter_config_hdc_and_sf);
2136
2137 dev_priv->perf.oa.flex_regs =
2138 flex_eu_config_hdc_and_sf;
2139 dev_priv->perf.oa.flex_regs_len =
2140 ARRAY_SIZE(flex_eu_config_hdc_and_sf);
2141
2142 return 0;
2143 case METRIC_SET_ID_L3_1:
2144 dev_priv->perf.oa.n_mux_configs =
2145 get_l3_1_mux_config(dev_priv,
2146 dev_priv->perf.oa.mux_regs,
2147 dev_priv->perf.oa.mux_regs_lens);
2148 if (dev_priv->perf.oa.n_mux_configs == 0) {
2149 DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
2150
2151 /* EINVAL because *_register_sysfs already checked this
2152 * and so it wouldn't have been advertised to userspace and
2153 * so shouldn't have been requested
2154 */
2155 return -EINVAL;
2156 }
2157
2158 dev_priv->perf.oa.b_counter_regs =
2159 b_counter_config_l3_1;
2160 dev_priv->perf.oa.b_counter_regs_len =
2161 ARRAY_SIZE(b_counter_config_l3_1);
2162
2163 dev_priv->perf.oa.flex_regs =
2164 flex_eu_config_l3_1;
2165 dev_priv->perf.oa.flex_regs_len =
2166 ARRAY_SIZE(flex_eu_config_l3_1);
2167
2168 return 0;
2169 case METRIC_SET_ID_L3_2:
2170 dev_priv->perf.oa.n_mux_configs =
2171 get_l3_2_mux_config(dev_priv,
2172 dev_priv->perf.oa.mux_regs,
2173 dev_priv->perf.oa.mux_regs_lens);
2174 if (dev_priv->perf.oa.n_mux_configs == 0) {
2175 DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
2176
2177 /* EINVAL because *_register_sysfs already checked this
2178 * and so it wouldn't have been advertised to userspace and
2179 * so shouldn't have been requested
2180 */
2181 return -EINVAL;
2182 }
2183
2184 dev_priv->perf.oa.b_counter_regs =
2185 b_counter_config_l3_2;
2186 dev_priv->perf.oa.b_counter_regs_len =
2187 ARRAY_SIZE(b_counter_config_l3_2);
2188
2189 dev_priv->perf.oa.flex_regs =
2190 flex_eu_config_l3_2;
2191 dev_priv->perf.oa.flex_regs_len =
2192 ARRAY_SIZE(flex_eu_config_l3_2);
2193
2194 return 0;
2195 case METRIC_SET_ID_L3_3:
2196 dev_priv->perf.oa.n_mux_configs =
2197 get_l3_3_mux_config(dev_priv,
2198 dev_priv->perf.oa.mux_regs,
2199 dev_priv->perf.oa.mux_regs_lens);
2200 if (dev_priv->perf.oa.n_mux_configs == 0) {
2201 DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
2202
2203 /* EINVAL because *_register_sysfs already checked this
2204 * and so it wouldn't have been advertised to userspace and
2205 * so shouldn't have been requested
2206 */
2207 return -EINVAL;
2208 }
2209
2210 dev_priv->perf.oa.b_counter_regs =
2211 b_counter_config_l3_3;
2212 dev_priv->perf.oa.b_counter_regs_len =
2213 ARRAY_SIZE(b_counter_config_l3_3);
2214
2215 dev_priv->perf.oa.flex_regs =
2216 flex_eu_config_l3_3;
2217 dev_priv->perf.oa.flex_regs_len =
2218 ARRAY_SIZE(flex_eu_config_l3_3);
2219
2220 return 0;
2221 case METRIC_SET_ID_L3_4:
2222 dev_priv->perf.oa.n_mux_configs =
2223 get_l3_4_mux_config(dev_priv,
2224 dev_priv->perf.oa.mux_regs,
2225 dev_priv->perf.oa.mux_regs_lens);
2226 if (dev_priv->perf.oa.n_mux_configs == 0) {
2227 DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set\n");
2228
2229 /* EINVAL because *_register_sysfs already checked this
2230 * and so it wouldn't have been advertised to userspace and
2231 * so shouldn't have been requested
2232 */
2233 return -EINVAL;
2234 }
2235
2236 dev_priv->perf.oa.b_counter_regs =
2237 b_counter_config_l3_4;
2238 dev_priv->perf.oa.b_counter_regs_len =
2239 ARRAY_SIZE(b_counter_config_l3_4);
2240
2241 dev_priv->perf.oa.flex_regs =
2242 flex_eu_config_l3_4;
2243 dev_priv->perf.oa.flex_regs_len =
2244 ARRAY_SIZE(flex_eu_config_l3_4);
2245
2246 return 0;
2247 case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
2248 dev_priv->perf.oa.n_mux_configs =
2249 get_rasterizer_and_pixel_backend_mux_config(dev_priv,
2250 dev_priv->perf.oa.mux_regs,
2251 dev_priv->perf.oa.mux_regs_lens);
2252 if (dev_priv->perf.oa.n_mux_configs == 0) {
2253 DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
2254
2255 /* EINVAL because *_register_sysfs already checked this
2256 * and so it wouldn't have been advertised to userspace and
2257 * so shouldn't have been requested
2258 */
2259 return -EINVAL;
2260 }
2261
2262 dev_priv->perf.oa.b_counter_regs =
2263 b_counter_config_rasterizer_and_pixel_backend;
2264 dev_priv->perf.oa.b_counter_regs_len =
2265 ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
2266
2267 dev_priv->perf.oa.flex_regs =
2268 flex_eu_config_rasterizer_and_pixel_backend;
2269 dev_priv->perf.oa.flex_regs_len =
2270 ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
2271
2272 return 0;
2273 case METRIC_SET_ID_SAMPLER_1:
2274 dev_priv->perf.oa.n_mux_configs =
2275 get_sampler_1_mux_config(dev_priv,
2276 dev_priv->perf.oa.mux_regs,
2277 dev_priv->perf.oa.mux_regs_lens);
2278 if (dev_priv->perf.oa.n_mux_configs == 0) {
2279 DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set\n");
2280
2281 /* EINVAL because *_register_sysfs already checked this
2282 * and so it wouldn't have been advertised to userspace and
2283 * so shouldn't have been requested
2284 */
2285 return -EINVAL;
2286 }
2287
2288 dev_priv->perf.oa.b_counter_regs =
2289 b_counter_config_sampler_1;
2290 dev_priv->perf.oa.b_counter_regs_len =
2291 ARRAY_SIZE(b_counter_config_sampler_1);
2292
2293 dev_priv->perf.oa.flex_regs =
2294 flex_eu_config_sampler_1;
2295 dev_priv->perf.oa.flex_regs_len =
2296 ARRAY_SIZE(flex_eu_config_sampler_1);
2297
2298 return 0;
2299 case METRIC_SET_ID_SAMPLER_2:
2300 dev_priv->perf.oa.n_mux_configs =
2301 get_sampler_2_mux_config(dev_priv,
2302 dev_priv->perf.oa.mux_regs,
2303 dev_priv->perf.oa.mux_regs_lens);
2304 if (dev_priv->perf.oa.n_mux_configs == 0) {
2305 DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set\n");
2306
2307 /* EINVAL because *_register_sysfs already checked this
2308 * and so it wouldn't have been advertised to userspace and
2309 * so shouldn't have been requested
2310 */
2311 return -EINVAL;
2312 }
2313
2314 dev_priv->perf.oa.b_counter_regs =
2315 b_counter_config_sampler_2;
2316 dev_priv->perf.oa.b_counter_regs_len =
2317 ARRAY_SIZE(b_counter_config_sampler_2);
2318
2319 dev_priv->perf.oa.flex_regs =
2320 flex_eu_config_sampler_2;
2321 dev_priv->perf.oa.flex_regs_len =
2322 ARRAY_SIZE(flex_eu_config_sampler_2);
2323
2324 return 0;
2325 case METRIC_SET_ID_TDL_1:
2326 dev_priv->perf.oa.n_mux_configs =
2327 get_tdl_1_mux_config(dev_priv,
2328 dev_priv->perf.oa.mux_regs,
2329 dev_priv->perf.oa.mux_regs_lens);
2330 if (dev_priv->perf.oa.n_mux_configs == 0) {
2331 DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
2332
2333 /* EINVAL because *_register_sysfs already checked this
2334 * and so it wouldn't have been advertised to userspace and
2335 * so shouldn't have been requested
2336 */
2337 return -EINVAL;
2338 }
2339
2340 dev_priv->perf.oa.b_counter_regs =
2341 b_counter_config_tdl_1;
2342 dev_priv->perf.oa.b_counter_regs_len =
2343 ARRAY_SIZE(b_counter_config_tdl_1);
2344
2345 dev_priv->perf.oa.flex_regs =
2346 flex_eu_config_tdl_1;
2347 dev_priv->perf.oa.flex_regs_len =
2348 ARRAY_SIZE(flex_eu_config_tdl_1);
2349
2350 return 0;
2351 case METRIC_SET_ID_TDL_2:
2352 dev_priv->perf.oa.n_mux_configs =
2353 get_tdl_2_mux_config(dev_priv,
2354 dev_priv->perf.oa.mux_regs,
2355 dev_priv->perf.oa.mux_regs_lens);
2356 if (dev_priv->perf.oa.n_mux_configs == 0) {
2357 DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
2358
2359 /* EINVAL because *_register_sysfs already checked this
2360 * and so it wouldn't have been advertised to userspace and
2361 * so shouldn't have been requested
2362 */
2363 return -EINVAL;
2364 }
2365
2366 dev_priv->perf.oa.b_counter_regs =
2367 b_counter_config_tdl_2;
2368 dev_priv->perf.oa.b_counter_regs_len =
2369 ARRAY_SIZE(b_counter_config_tdl_2);
2370
2371 dev_priv->perf.oa.flex_regs =
2372 flex_eu_config_tdl_2;
2373 dev_priv->perf.oa.flex_regs_len =
2374 ARRAY_SIZE(flex_eu_config_tdl_2);
2375
2376 return 0;
2377 case METRIC_SET_ID_TEST_OA:
2378 dev_priv->perf.oa.n_mux_configs =
2379 get_test_oa_mux_config(dev_priv,
2380 dev_priv->perf.oa.mux_regs,
2381 dev_priv->perf.oa.mux_regs_lens);
2382 if (dev_priv->perf.oa.n_mux_configs == 0) {
2383 DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
2384
2385 /* EINVAL because *_register_sysfs already checked this
2386 * and so it wouldn't have been advertised to userspace and
2387 * so shouldn't have been requested
2388 */
2389 return -EINVAL;
2390 }
2391
2392 dev_priv->perf.oa.b_counter_regs =
2393 b_counter_config_test_oa;
2394 dev_priv->perf.oa.b_counter_regs_len =
2395 ARRAY_SIZE(b_counter_config_test_oa);
2396
2397 dev_priv->perf.oa.flex_regs =
2398 flex_eu_config_test_oa;
2399 dev_priv->perf.oa.flex_regs_len =
2400 ARRAY_SIZE(flex_eu_config_test_oa);
2401
2402 return 0;
Robert Bragg5182f642017-06-13 12:23:02 +0100[diff] [blame]2403 default:
2404 return -ENODEV;
2405 }
2406}
2407
2408static ssize_t
2409show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2410{
2411 return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
2412}
2413
2414static struct device_attribute dev_attr_render_basic_id = {
2415 .attr = { .name = "id", .mode = 0444 },
2416 .show = show_render_basic_id,
2417 .store = NULL,
2418};
2419
2420static struct attribute *attrs_render_basic[] = {
2421 &dev_attr_render_basic_id.attr,
2422 NULL,
2423};
2424
2425static struct attribute_group group_render_basic = {
2426 .name = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb",
2427 .attrs = attrs_render_basic,
2428};
2429
Robert Braggfc599212017-06-13 12:23:04 +0100[diff] [blame]2430static ssize_t
2431show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2432{
2433 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
2434}
2435
2436static struct device_attribute dev_attr_compute_basic_id = {
2437 .attr = { .name = "id", .mode = 0444 },
2438 .show = show_compute_basic_id,
2439 .store = NULL,
2440};
2441
2442static struct attribute *attrs_compute_basic[] = {
2443 &dev_attr_compute_basic_id.attr,
2444 NULL,
2445};
2446
2447static struct attribute_group group_compute_basic = {
2448 .name = "f522a89c-ecd1-4522-8331-3383c54af5f5",
2449 .attrs = attrs_compute_basic,
2450};
2451
2452static ssize_t
2453show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
2454{
2455 return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
2456}
2457
2458static struct device_attribute dev_attr_render_pipe_profile_id = {
2459 .attr = { .name = "id", .mode = 0444 },
2460 .show = show_render_pipe_profile_id,
2461 .store = NULL,
2462};
2463
2464static struct attribute *attrs_render_pipe_profile[] = {
2465 &dev_attr_render_pipe_profile_id.attr,
2466 NULL,
2467};
2468
2469static struct attribute_group group_render_pipe_profile = {
2470 .name = "a9ccc03d-a943-4e6b-9cd6-13e063075927",
2471 .attrs = attrs_render_pipe_profile,
2472};
2473
2474static ssize_t
2475show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
2476{
2477 return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
2478}
2479
2480static struct device_attribute dev_attr_hdc_and_sf_id = {
2481 .attr = { .name = "id", .mode = 0444 },
2482 .show = show_hdc_and_sf_id,
2483 .store = NULL,
2484};
2485
2486static struct attribute *attrs_hdc_and_sf[] = {
2487 &dev_attr_hdc_and_sf_id.attr,
2488 NULL,
2489};
2490
2491static struct attribute_group group_hdc_and_sf = {
2492 .name = "2cf0c064-68df-4fac-9b3f-57f51ca8a069",
2493 .attrs = attrs_hdc_and_sf,
2494};
2495
2496static ssize_t
2497show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2498{
2499 return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
2500}
2501
2502static struct device_attribute dev_attr_l3_1_id = {
2503 .attr = { .name = "id", .mode = 0444 },
2504 .show = show_l3_1_id,
2505 .store = NULL,
2506};
2507
2508static struct attribute *attrs_l3_1[] = {
2509 &dev_attr_l3_1_id.attr,
2510 NULL,
2511};
2512
2513static struct attribute_group group_l3_1 = {
2514 .name = "78a87ff9-543a-49ce-95ea-26d86071ea93",
2515 .attrs = attrs_l3_1,
2516};
2517
2518static ssize_t
2519show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
2520{
2521 return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
2522}
2523
2524static struct device_attribute dev_attr_l3_2_id = {
2525 .attr = { .name = "id", .mode = 0444 },
2526 .show = show_l3_2_id,
2527 .store = NULL,
2528};
2529
2530static struct attribute *attrs_l3_2[] = {
2531 &dev_attr_l3_2_id.attr,
2532 NULL,
2533};
2534
2535static struct attribute_group group_l3_2 = {
2536 .name = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5",
2537 .attrs = attrs_l3_2,
2538};
2539
2540static ssize_t
2541show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
2542{
2543 return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
2544}
2545
2546static struct device_attribute dev_attr_l3_3_id = {
2547 .attr = { .name = "id", .mode = 0444 },
2548 .show = show_l3_3_id,
2549 .store = NULL,
2550};
2551
2552static struct attribute *attrs_l3_3[] = {
2553 &dev_attr_l3_3_id.attr,
2554 NULL,
2555};
2556
2557static struct attribute_group group_l3_3 = {
2558 .name = "d890ef38-d309-47e4-b8b5-aa779bb19ab0",
2559 .attrs = attrs_l3_3,
2560};
2561
2562static ssize_t
2563show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf)
2564{
2565 return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4);
2566}
2567
2568static struct device_attribute dev_attr_l3_4_id = {
2569 .attr = { .name = "id", .mode = 0444 },
2570 .show = show_l3_4_id,
2571 .store = NULL,
2572};
2573
2574static struct attribute *attrs_l3_4[] = {
2575 &dev_attr_l3_4_id.attr,
2576 NULL,
2577};
2578
2579static struct attribute_group group_l3_4 = {
2580 .name = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4",
2581 .attrs = attrs_l3_4,
2582};
2583
2584static ssize_t
2585show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
2586{
2587 return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
2588}
2589
2590static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
2591 .attr = { .name = "id", .mode = 0444 },
2592 .show = show_rasterizer_and_pixel_backend_id,
2593 .store = NULL,
2594};
2595
2596static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
2597 &dev_attr_rasterizer_and_pixel_backend_id.attr,
2598 NULL,
2599};
2600
2601static struct attribute_group group_rasterizer_and_pixel_backend = {
2602 .name = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa",
2603 .attrs = attrs_rasterizer_and_pixel_backend,
2604};
2605
2606static ssize_t
2607show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2608{
2609 return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1);
2610}
2611
2612static struct device_attribute dev_attr_sampler_1_id = {
2613 .attr = { .name = "id", .mode = 0444 },
2614 .show = show_sampler_1_id,
2615 .store = NULL,
2616};
2617
2618static struct attribute *attrs_sampler_1[] = {
2619 &dev_attr_sampler_1_id.attr,
2620 NULL,
2621};
2622
2623static struct attribute_group group_sampler_1 = {
2624 .name = "71148d78-baf5-474f-878a-e23158d0265d",
2625 .attrs = attrs_sampler_1,
2626};
2627
2628static ssize_t
2629show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
2630{
2631 return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2);
2632}
2633
2634static struct device_attribute dev_attr_sampler_2_id = {
2635 .attr = { .name = "id", .mode = 0444 },
2636 .show = show_sampler_2_id,
2637 .store = NULL,
2638};
2639
2640static struct attribute *attrs_sampler_2[] = {
2641 &dev_attr_sampler_2_id.attr,
2642 NULL,
2643};
2644
2645static struct attribute_group group_sampler_2 = {
2646 .name = "b996a2b7-c59c-492d-877a-8cd54fd6df84",
2647 .attrs = attrs_sampler_2,
2648};
2649
2650static ssize_t
2651show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2652{
2653 return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
2654}
2655
2656static struct device_attribute dev_attr_tdl_1_id = {
2657 .attr = { .name = "id", .mode = 0444 },
2658 .show = show_tdl_1_id,
2659 .store = NULL,
2660};
2661
2662static struct attribute *attrs_tdl_1[] = {
2663 &dev_attr_tdl_1_id.attr,
2664 NULL,
2665};
2666
2667static struct attribute_group group_tdl_1 = {
2668 .name = "eb2fecba-b431-42e7-8261-fe9429a6e67a",
2669 .attrs = attrs_tdl_1,
2670};
2671
2672static ssize_t
2673show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
2674{
2675 return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
2676}
2677
2678static struct device_attribute dev_attr_tdl_2_id = {
2679 .attr = { .name = "id", .mode = 0444 },
2680 .show = show_tdl_2_id,
2681 .store = NULL,
2682};
2683
2684static struct attribute *attrs_tdl_2[] = {
2685 &dev_attr_tdl_2_id.attr,
2686 NULL,
2687};
2688
2689static struct attribute_group group_tdl_2 = {
2690 .name = "60749470-a648-4a4b-9f10-dbfe1e36e44d",
2691 .attrs = attrs_tdl_2,
2692};
2693
2694static ssize_t
2695show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
2696{
2697 return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
2698}
2699
2700static struct device_attribute dev_attr_test_oa_id = {
2701 .attr = { .name = "id", .mode = 0444 },
2702 .show = show_test_oa_id,
2703 .store = NULL,
2704};
2705
2706static struct attribute *attrs_test_oa[] = {
2707 &dev_attr_test_oa_id.attr,
2708 NULL,
2709};
2710
2711static struct attribute_group group_test_oa = {
2712 .name = "4a534b07-cba3-414d-8d60-874830e883aa",
2713 .attrs = attrs_test_oa,
2714};
2715
Robert Bragg5182f642017-06-13 12:23:02 +0100[diff] [blame]2716int
2717i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv)
2718{
2719 const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
2720 int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
2721 int ret = 0;
2722
2723 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2724 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2725 if (ret)
2726 goto error_render_basic;
2727 }
Robert Braggfc599212017-06-13 12:23:04 +0100[diff] [blame]2728 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2729 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2730 if (ret)
2731 goto error_compute_basic;
2732 }
2733 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
2734 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2735 if (ret)
2736 goto error_render_pipe_profile;
2737 }
2738 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
2739 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2740 if (ret)
2741 goto error_hdc_and_sf;
2742 }
2743 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2744 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2745 if (ret)
2746 goto error_l3_1;
2747 }
2748 if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
2749 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
2750 if (ret)
2751 goto error_l3_2;
2752 }
2753 if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
2754 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
2755 if (ret)
2756 goto error_l3_3;
2757 }
2758 if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) {
2759 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4);
2760 if (ret)
2761 goto error_l3_4;
2762 }
2763 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
2764 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2765 if (ret)
2766 goto error_rasterizer_and_pixel_backend;
2767 }
2768 if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2769 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
2770 if (ret)
2771 goto error_sampler_1;
2772 }
2773 if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) {
2774 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
2775 if (ret)
2776 goto error_sampler_2;
2777 }
2778 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2779 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2780 if (ret)
2781 goto error_tdl_1;
2782 }
2783 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
2784 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2785 if (ret)
2786 goto error_tdl_2;
2787 }
2788 if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
2789 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
2790 if (ret)
2791 goto error_test_oa;
2792 }
Robert Bragg5182f642017-06-13 12:23:02 +0100[diff] [blame]2793
2794 return 0;
2795
Robert Braggfc599212017-06-13 12:23:04 +0100[diff] [blame]2796error_test_oa:
2797 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
2798 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2799error_tdl_2:
2800 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
2801 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2802error_tdl_1:
2803 if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens))
2804 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
2805error_sampler_2:
2806 if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens))
2807 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
2808error_sampler_1:
2809 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
2810 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2811error_rasterizer_and_pixel_backend:
2812 if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens))
2813 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
2814error_l3_4:
2815 if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
2816 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
2817error_l3_3:
2818 if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
2819 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
2820error_l3_2:
2821 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
2822 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2823error_l3_1:
2824 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
2825 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2826error_hdc_and_sf:
2827 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
2828 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2829error_render_pipe_profile:
2830 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
2831 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2832error_compute_basic:
2833 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
2834 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
Robert Bragg5182f642017-06-13 12:23:02 +0100[diff] [blame]2835error_render_basic:
2836 return ret;
2837}
2838
2839void
2840i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv)
2841{
2842 const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
2843 int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
2844
2845 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
2846 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
Robert Braggfc599212017-06-13 12:23:04 +0100[diff] [blame]2847 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
2848 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2849 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
2850 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2851 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
2852 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2853 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
2854 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2855 if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
2856 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
2857 if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
2858 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
2859 if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens))
2860 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
2861 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
2862 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2863 if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens))
2864 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
2865 if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens))
2866 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
2867 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
2868 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2869 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
2870 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2871 if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
2872 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
Robert Bragg5182f642017-06-13 12:23:02 +0100[diff] [blame]2873}