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Catalin Marinas4b172442007-02-14 19:20:28 +01001#ifndef __ASMARM_ARCH_SCU_H
2#define __ASMARM_ARCH_SCU_H
3
Russell King292ec422011-02-04 10:36:39 +00004#define SCU_PM_NORMAL 0
5#define SCU_PM_DORMANT 2
6#define SCU_PM_POWEROFF 3
7
8#ifndef __ASSEMBLER__
Hiroshi Doyue9d6b3352013-01-22 07:52:01 +02009
10#include <asm/cputype.h>
11
12static inline bool scu_a9_has_base(void)
13{
Russell Kingaf040ff2014-06-24 19:43:15 +010014 return read_cpuid_part() == ARM_CPU_PART_CORTEX_A9;
Hiroshi Doyue9d6b3352013-01-22 07:52:01 +020015}
16
17static inline unsigned long scu_a9_get_base(void)
18{
19 unsigned long pa;
20
21 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
22
23 return pa;
24}
25
Nishanth Menon2abc75a2013-06-26 09:39:47 -050026#ifdef CONFIG_HAVE_ARM_SCU
Russell Kinga8cbcd92009-05-16 11:51:14 +010027unsigned int scu_get_core_count(void __iomem *);
Russell King292ec422011-02-04 10:36:39 +000028int scu_power_mode(void __iomem *, unsigned int);
Nishanth Menon2abc75a2013-06-26 09:39:47 -050029#else
30static inline unsigned int scu_get_core_count(void __iomem *scu_base)
31{
32 return 0;
33}
34static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode)
35{
36 return -EINVAL;
37}
38#endif
Rob Herringeed88122013-01-31 09:26:06 -060039
Nishanth Menon2abc75a2013-06-26 09:39:47 -050040#if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)
Rob Herringeed88122013-01-31 09:26:06 -060041void scu_enable(void __iomem *scu_base);
42#else
43static inline void scu_enable(void __iomem *scu_base) {}
44#endif
45
Russell King292ec422011-02-04 10:36:39 +000046#endif
Catalin Marinas4b172442007-02-14 19:20:28 +010047
48#endif