blob: 9063a4434d6a59b26e3bac76e24f1643bc6121e8 [file] [log] [blame]
Magnus Damm3d5de272012-05-16 15:45:54 +09001/*
2 * Device Tree Source for the EMEV2 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,emev2";
15 interrupt-parent = <&gic>;
16
Magnus Damm12d035b2013-07-02 18:27:57 +090017 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
23 };
24
Magnus Damm3d5de272012-05-16 15:45:54 +090025 cpus {
Simon Hormanfe681d22013-01-28 09:41:40 +090026 #address-cells = <1>;
27 #size-cells = <0>;
28
Magnus Damm3d5de272012-05-16 15:45:54 +090029 cpu@0 {
Simon Hormanfe681d22013-01-28 09:41:40 +090030 device_type = "cpu";
Magnus Damm3d5de272012-05-16 15:45:54 +090031 compatible = "arm,cortex-a9";
Simon Hormanfe681d22013-01-28 09:41:40 +090032 reg = <0>;
Magnus Damm3d5de272012-05-16 15:45:54 +090033 };
34 cpu@1 {
Simon Hormanfe681d22013-01-28 09:41:40 +090035 device_type = "cpu";
Magnus Damm3d5de272012-05-16 15:45:54 +090036 compatible = "arm,cortex-a9";
Simon Hormanfe681d22013-01-28 09:41:40 +090037 reg = <1>;
Magnus Damm3d5de272012-05-16 15:45:54 +090038 };
39 };
40
41 gic: interrupt-controller@e0020000 {
42 compatible = "arm,cortex-a9-gic";
43 interrupt-controller;
44 #interrupt-cells = <3>;
45 reg = <0xe0028000 0x1000>,
46 <0xe0020000 0x0100>;
47 };
48
Magnus Dammc95ebbb2013-07-24 12:42:40 +090049 pmu {
50 compatible = "arm,cortex-a9-pmu";
51 interrupts = <0 120 4>,
52 <0 121 4>;
53 };
54
Magnus Damm3d5de272012-05-16 15:45:54 +090055 sti@e0180000 {
56 compatible = "renesas,em-sti";
57 reg = <0xe0180000 0x54>;
58 interrupts = <0 125 0>;
59 };
60
61 uart@e1020000 {
62 compatible = "renesas,em-uart";
63 reg = <0xe1020000 0x38>;
64 interrupts = <0 8 0>;
65 };
66
67 uart@e1030000 {
68 compatible = "renesas,em-uart";
69 reg = <0xe1030000 0x38>;
70 interrupts = <0 9 0>;
71 };
72
73 uart@e1040000 {
74 compatible = "renesas,em-uart";
75 reg = <0xe1040000 0x38>;
76 interrupts = <0 10 0>;
77 };
78
79 uart@e1050000 {
80 compatible = "renesas,em-uart";
81 reg = <0xe1050000 0x38>;
82 interrupts = <0 11 0>;
83 };
Magnus Damm12d035b2013-07-02 18:27:57 +090084
85 gpio0: gpio@e0050000 {
86 compatible = "renesas,em-gio";
87 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
88 interrupts = <0 67 0>, <0 68 0>;
89 gpio-controller;
90 #gpio-cells = <2>;
91 ngpios = <32>;
92 interrupt-controller;
93 #interrupt-cells = <2>;
94 };
95 gpio1: gpio@e0050080 {
96 compatible = "renesas,em-gio";
97 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
98 interrupts = <0 69 0>, <0 70 0>;
99 gpio-controller;
100 #gpio-cells = <2>;
101 ngpios = <32>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
104 };
105 gpio2: gpio@e0050100 {
106 compatible = "renesas,em-gio";
107 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
108 interrupts = <0 71 0>, <0 72 0>;
109 gpio-controller;
110 #gpio-cells = <2>;
111 ngpios = <32>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
114 };
115 gpio3: gpio@e0050180 {
116 compatible = "renesas,em-gio";
117 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
118 interrupts = <0 73 0>, <0 74 0>;
119 gpio-controller;
120 #gpio-cells = <2>;
121 ngpios = <32>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 };
125 gpio4: gpio@e0050200 {
126 compatible = "renesas,em-gio";
127 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
128 interrupts = <0 75 0>, <0 76 0>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 ngpios = <31>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
134 };
Magnus Damm3d5de272012-05-16 15:45:54 +0900135};