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gerrit-public.fairphone.software / kernel / msm-5.4 / aefc7c7512455c26574ae7118429920dc3de60ae / . / arch / arm / mach-rockchip / pm.h
blob: 91a542df579177e76432c92217630e8412b1ddf4 [file] [log] [blame]
Chris Zhong9c1ec8e2014-12-01 16:52:17 +0800[diff] [blame]1/*
2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Tony Xie <tony.xie@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __MACH_ROCKCHIP_PM_H
16#define __MACH_ROCKCHIP_PM_H
17
18extern unsigned long rkpm_bootdata_cpusp;
19extern unsigned long rkpm_bootdata_cpu_code;
20extern unsigned long rkpm_bootdata_l2ctlr_f;
21extern unsigned long rkpm_bootdata_l2ctlr;
22extern unsigned long rkpm_bootdata_ddr_code;
23extern unsigned long rkpm_bootdata_ddr_data;
24extern unsigned long rk3288_bootram_sz;
25
26void rockchip_slp_cpu_resume(void);
Arnd Bergmannc8823e72015-01-27 21:26:36 +0100[diff] [blame]27#ifdef CONFIG_PM_SLEEP
Chris Zhong9c1ec8e2014-12-01 16:52:17 +0800[diff] [blame]28void __init rockchip_suspend_init(void);
Arnd Bergmannc8823e72015-01-27 21:26:36 +0100[diff] [blame]29#else
30static inline void rockchip_suspend_init(void)
31{
32}
33#endif
Chris Zhong9c1ec8e2014-12-01 16:52:17 +0800[diff] [blame]34
35/****** following is rk3288 defined **********/
36#define RK3288_PMU_WAKEUP_CFG0 0x00
37#define RK3288_PMU_WAKEUP_CFG1 0x04
38#define RK3288_PMU_PWRMODE_CON 0x18
39#define RK3288_PMU_OSC_CNT 0x20
40#define RK3288_PMU_PLL_CNT 0x24
41#define RK3288_PMU_STABL_CNT 0x28
42#define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
43#define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
44#define RK3288_PMU_CORE_PWRDWN_CNT 0x34
45#define RK3288_PMU_CORE_PWRUP_CNT 0x38
46#define RK3288_PMU_GPU_PWRDWN_CNT 0x3c
47#define RK3288_PMU_GPU_PWRUP_CNT 0x40
48#define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
49#define RK3288_PMU_PWRMODE_CON1 0x90
50
51#define RK3288_SGRF_SOC_CON0 (0x0000)
52#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
53#define SGRF_FAST_BOOT_EN BIT(8)
54#define SGRF_FAST_BOOT_EN_WRITE BIT(24)
55
56#define RK3288_CRU_MODE_CON 0x50
57#define RK3288_CRU_SEL0_CON 0x60
58#define RK3288_CRU_SEL1_CON 0x64
59#define RK3288_CRU_SEL10_CON 0x88
60#define RK3288_CRU_SEL33_CON 0xe4
61#define RK3288_CRU_SEL37_CON 0xf4
62
63/* PMU_WAKEUP_CFG1 bits */
64#define PMU_ARMINT_WAKEUP_EN BIT(0)
65
Chris Zhongaefc7c72015-02-09 21:12:22 +0800[diff] [blame^]66/* wait 30ms for OSC stable and 30ms for pmic stable */
67#define OSC_STABL_CNT_THRESH (32 * 30)
68#define PMU_STABL_CNT_THRESH (32 * 30)
69
Chris Zhong9c1ec8e2014-12-01 16:52:17 +0800[diff] [blame]70enum rk3288_pwr_mode_con {
71 PMU_PWR_MODE_EN = 0,
72 PMU_CLK_CORE_SRC_GATE_EN,
73 PMU_GLOBAL_INT_DISABLE,
74 PMU_L2FLUSH_EN,
75 PMU_BUS_PD_EN,
76 PMU_A12_0_PD_EN,
77 PMU_SCU_EN,
78 PMU_PLL_PD_EN,
79 PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */
80 PMU_PWROFF_COMB,
81 PMU_ALIVE_USE_LF,
82 PMU_PMU_USE_LF,
83 PMU_OSC_24M_DIS,
84 PMU_INPUT_CLAMP_EN,
85 PMU_WAKEUP_RESET_EN,
86 PMU_SREF0_ENTER_EN,
87 PMU_SREF1_ENTER_EN,
88 PMU_DDR0IO_RET_EN,
89 PMU_DDR1IO_RET_EN,
90 PMU_DDR0_GATING_EN,
91 PMU_DDR1_GATING_EN,
92 PMU_DDR0IO_RET_DE_REQ,
93 PMU_DDR1IO_RET_DE_REQ
94};
95
96enum rk3288_pwr_mode_con1 {
97 PMU_CLR_BUS = 0,
98 PMU_CLR_CORE,
99 PMU_CLR_CPUP,
100 PMU_CLR_ALIVE,
101 PMU_CLR_DMA,
102 PMU_CLR_PERI,
103 PMU_CLR_GPU,
104 PMU_CLR_VIDEO,
105 PMU_CLR_HEVC,
106 PMU_CLR_VIO,
107};
108
109#endif /* __MACH_ROCKCHIP_PM_H */