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Mikael Petterssone589ed22008-08-20 09:36:07 +01001#ifndef _ASM_ARM_FUTEX_H
2#define _ASM_ARM_FUTEX_H
3
4#ifdef __KERNEL__
5
Will Deaconc1b0db52011-04-28 18:43:01 +01006#if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP)
7/* ARM doesn't provide unprivileged exclusive memory accessors */
8#include <asm-generic/futex.h>
9#else
10
11#include <linux/futex.h>
12#include <linux/uaccess.h>
13#include <asm/errno.h>
14
15#define __futex_atomic_ex_table(err_reg) \
16 "3:\n" \
17 " .pushsection __ex_table,\"a\"\n" \
18 " .align 3\n" \
19 " .long 1b, 4f, 2b, 4f\n" \
20 " .popsection\n" \
21 " .pushsection .fixup,\"ax\"\n" \
Will Deacon667d1b42012-06-15 16:49:58 +010022 " .align 2\n" \
Will Deaconc1b0db52011-04-28 18:43:01 +010023 "4: mov %0, " err_reg "\n" \
24 " b 3b\n" \
25 " .popsection"
26
Mikael Petterssone589ed22008-08-20 09:36:07 +010027#ifdef CONFIG_SMP
Jakub Jelinek4732efb2005-09-06 15:16:25 -070028
Will Deacondf77abc2011-09-23 14:34:12 +010029#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
Will Deaconc1b0db52011-04-28 18:43:01 +010030 smp_mb(); \
31 __asm__ __volatile__( \
Will Deacondf77abc2011-09-23 14:34:12 +010032 "1: ldrex %1, [%3]\n" \
Will Deaconc1b0db52011-04-28 18:43:01 +010033 " " insn "\n" \
Will Deacondf77abc2011-09-23 14:34:12 +010034 "2: strex %2, %0, [%3]\n" \
35 " teq %2, #0\n" \
Will Deaconc1b0db52011-04-28 18:43:01 +010036 " bne 1b\n" \
37 " mov %0, #0\n" \
Will Deacondf77abc2011-09-23 14:34:12 +010038 __futex_atomic_ex_table("%5") \
39 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
Will Deaconc1b0db52011-04-28 18:43:01 +010040 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
41 : "cc", "memory")
42
43static inline int
44futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
45 u32 oldval, u32 newval)
46{
47 int ret;
48 u32 val;
49
50 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
51 return -EFAULT;
52
53 smp_mb();
54 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
55 "1: ldrex %1, [%4]\n"
56 " teq %1, %2\n"
57 " ite eq @ explicit IT needed for the 2b label\n"
58 "2: strexeq %0, %3, [%4]\n"
59 " movne %0, #0\n"
60 " teq %0, #0\n"
61 " bne 1b\n"
62 __futex_atomic_ex_table("%5")
63 : "=&r" (ret), "=&r" (val)
64 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
65 : "cc", "memory");
66 smp_mb();
67
68 *uval = val;
69 return ret;
70}
Jakub Jelinek4732efb2005-09-06 15:16:25 -070071
Mikael Petterssone589ed22008-08-20 09:36:07 +010072#else /* !SMP, we can work around lack of atomic ops by disabling preemption */
73
Mikael Petterssone589ed22008-08-20 09:36:07 +010074#include <linux/preempt.h>
Catalin Marinas247055a2010-09-13 16:03:21 +010075#include <asm/domain.h>
Mikael Petterssone589ed22008-08-20 09:36:07 +010076
Will Deacondf77abc2011-09-23 14:34:12 +010077#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
Mikael Petterssone589ed22008-08-20 09:36:07 +010078 __asm__ __volatile__( \
Catalin Marinas4e7682d2012-01-25 11:38:13 +010079 "1: " TUSER(ldr) " %1, [%3]\n" \
Mikael Petterssone589ed22008-08-20 09:36:07 +010080 " " insn "\n" \
Catalin Marinas4e7682d2012-01-25 11:38:13 +010081 "2: " TUSER(str) " %0, [%3]\n" \
Mikael Petterssone589ed22008-08-20 09:36:07 +010082 " mov %0, #0\n" \
Will Deacondf77abc2011-09-23 14:34:12 +010083 __futex_atomic_ex_table("%5") \
84 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
Mikael Petterssone589ed22008-08-20 09:36:07 +010085 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
86 : "cc", "memory")
87
88static inline int
Will Deaconc1b0db52011-04-28 18:43:01 +010089futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
90 u32 oldval, u32 newval)
91{
92 int ret = 0;
93 u32 val;
94
95 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
96 return -EFAULT;
97
98 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
Catalin Marinas4e7682d2012-01-25 11:38:13 +010099 "1: " TUSER(ldr) " %1, [%4]\n"
Will Deaconc1b0db52011-04-28 18:43:01 +0100100 " teq %1, %2\n"
101 " it eq @ explicit IT needed for the 2b label\n"
Catalin Marinas4e7682d2012-01-25 11:38:13 +0100102 "2: " TUSER(streq) " %3, [%4]\n"
Will Deaconc1b0db52011-04-28 18:43:01 +0100103 __futex_atomic_ex_table("%5")
104 : "+r" (ret), "=&r" (val)
105 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
106 : "cc", "memory");
107
108 *uval = val;
109 return ret;
110}
111
112#endif /* !SMP */
113
114static inline int
Michel Lespinasse8d7718a2011-03-10 18:50:58 -0800115futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
Mikael Petterssone589ed22008-08-20 09:36:07 +0100116{
117 int op = (encoded_op >> 28) & 7;
118 int cmp = (encoded_op >> 24) & 15;
119 int oparg = (encoded_op << 8) >> 20;
120 int cmparg = (encoded_op << 20) >> 20;
Will Deacondf77abc2011-09-23 14:34:12 +0100121 int oldval = 0, ret, tmp;
Mikael Petterssone589ed22008-08-20 09:36:07 +0100122
123 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
124 oparg = 1 << oparg;
125
Michel Lespinasse8d7718a2011-03-10 18:50:58 -0800126 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
Mikael Petterssone589ed22008-08-20 09:36:07 +0100127 return -EFAULT;
128
129 pagefault_disable(); /* implies preempt_disable() */
130
131 switch (op) {
132 case FUTEX_OP_SET:
Will Deacondf77abc2011-09-23 14:34:12 +0100133 __futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
Mikael Petterssone589ed22008-08-20 09:36:07 +0100134 break;
135 case FUTEX_OP_ADD:
Will Deacondf77abc2011-09-23 14:34:12 +0100136 __futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
Mikael Petterssone589ed22008-08-20 09:36:07 +0100137 break;
138 case FUTEX_OP_OR:
Will Deacondf77abc2011-09-23 14:34:12 +0100139 __futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
Mikael Petterssone589ed22008-08-20 09:36:07 +0100140 break;
141 case FUTEX_OP_ANDN:
Will Deacondf77abc2011-09-23 14:34:12 +0100142 __futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
Mikael Petterssone589ed22008-08-20 09:36:07 +0100143 break;
144 case FUTEX_OP_XOR:
Will Deacondf77abc2011-09-23 14:34:12 +0100145 __futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
Mikael Petterssone589ed22008-08-20 09:36:07 +0100146 break;
147 default:
148 ret = -ENOSYS;
149 }
150
151 pagefault_enable(); /* subsumes preempt_enable() */
152
153 if (!ret) {
154 switch (cmp) {
155 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
156 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
157 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
158 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
159 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
160 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
161 default: ret = -ENOSYS;
162 }
163 }
164 return ret;
165}
166
Will Deaconc1b0db52011-04-28 18:43:01 +0100167#endif /* !(CPU_USE_DOMAINS && SMP) */
Mikael Petterssone589ed22008-08-20 09:36:07 +0100168#endif /* __KERNEL__ */
169#endif /* _ASM_ARM_FUTEX_H */