blob: 67eab56699bd49f66925b66ed4c5b8d5922de037 [file] [log] [blame]
Peter De Schrijver364c7c3f2012-01-26 18:22:01 +02001/*
2 * arch/arm/mach-tegra/flowctrl.h
3 *
4 * functions and macros to control the flowcontroller
5 *
6 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __MACH_TEGRA_FLOWCTRL_H
22#define __MACH_TEGRA_FLOWCTRL_H
23
24#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
25#define FLOW_CTRL_WAITEVENT (2 << 29)
26#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
27#define FLOW_CTRL_JTAG_RESUME (1 << 28)
28#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
29#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
30#define FLOW_CTRL_CPU0_CSR 0x8
31#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
32#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
33#define FLOW_CTRL_CSR_ENABLE (1 << 0)
34#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
35#define FLOW_CTRL_CPU1_CSR 0x18
36
Joseph Loafec5812013-01-15 22:11:01 +000037#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
38#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
39#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0
40
Joseph Lo01459c62012-10-31 17:41:20 +080041#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
42#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
43#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
44
Peter De Schrijver26fe6812012-02-10 01:47:44 +020045#ifndef __ASSEMBLY__
Joseph Lo01459c62012-10-31 17:41:20 +080046u32 flowctrl_read_cpu_csr(unsigned int cpuid);
Peter De Schrijver26fe6812012-02-10 01:47:44 +020047void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
48void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
Joseph Lo01459c62012-10-31 17:41:20 +080049
50void flowctrl_cpu_suspend_enter(unsigned int cpuid);
51void flowctrl_cpu_suspend_exit(unsigned int cpuid);
Peter De Schrijver26fe6812012-02-10 01:47:44 +020052#endif
53
Peter De Schrijver364c7c3f2012-01-26 18:22:01 +020054#endif