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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon"
Dave Airliec0beb2a2008-05-28 13:52:28 +100041#define DRIVER_DATE "20080528"
Linus Torvalds1da177e2005-04-16 15:20:36 -070042
43/* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
Dave Airlieb5e89ed2005-09-25 14:28:13 +100071 * clients use to tell the DRM where they think the framebuffer is
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
Dave Airlied985c102006-01-02 21:32:48 +110076 * (No 3D support yet - just microcode loading).
Linus Torvalds1da177e2005-04-16 15:20:36 -070077 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
Dave Airlie414ed532005-08-16 20:43:16 +100085 * 1.17- Add initial support for R300 (3D).
Dave Airlie9d176012005-09-11 19:55:53 +100086 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
Dave Airlieea98a922005-09-11 20:28:11 +100090 * 1.19- Add support for gart table in FB memory and PCIE r300
Dave Airlied985c102006-01-02 21:32:48 +110091 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
Dave Airlie4e5e2e22006-02-18 15:51:35 +110093 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
Dave Airlied5ea7022006-03-19 19:37:55 +110094 * 1.23- Add new radeon memory map work from benh
Dave Airlieee4621f2006-03-19 19:45:26 +110095 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
Dave Airlied6fece02006-06-24 17:04:07 +100096 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
Dave Airlief2b04cd2007-05-08 15:19:23 +100098 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
Dave Airlieddbee332007-07-11 12:16:01 +1000100 * 1.28- Add support for VBL on CRTC2
Dave Airliec0beb2a2008-05-28 13:52:28 +1000101 * 1.29- R500 3D cmd buffer support
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102 */
103#define DRIVER_MAJOR 1
Dave Airliec0beb2a2008-05-28 13:52:28 +1000104#define DRIVER_MINOR 29
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105#define DRIVER_PATCHLEVEL 0
106
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107/*
108 * Radeon chip families
109 */
110enum radeon_family {
111 CHIP_R100,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 CHIP_RV100,
Dave Airliedfab1152006-03-19 20:01:37 +1100113 CHIP_RS100,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 CHIP_RV200,
115 CHIP_RS200,
Dave Airliedfab1152006-03-19 20:01:37 +1100116 CHIP_R200,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117 CHIP_RV250,
Dave Airliedfab1152006-03-19 20:01:37 +1100118 CHIP_RS300,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119 CHIP_RV280,
120 CHIP_R300,
Dave Airlie414ed532005-08-16 20:43:16 +1000121 CHIP_R350,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 CHIP_RV350,
Dave Airliedfab1152006-03-19 20:01:37 +1100123 CHIP_RV380,
Dave Airlie414ed532005-08-16 20:43:16 +1000124 CHIP_R420,
Alex Deucheredc6f382008-10-17 09:21:45 +1000125 CHIP_R423,
Dave Airliedfab1152006-03-19 20:01:37 +1100126 CHIP_RV410,
Alex Deucherb2ceddf2008-10-17 09:19:33 +1000127 CHIP_RS400,
Alex Deucher45e51902008-05-28 13:28:59 +1000128 CHIP_RS480,
Maciej Cencora60f92682008-02-19 21:32:45 +1000129 CHIP_RS690,
Alex Deucherf0738e92008-10-16 17:12:02 +1000130 CHIP_RS740,
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000131 CHIP_RV515,
132 CHIP_R520,
133 CHIP_RV530,
134 CHIP_RV560,
135 CHIP_RV570,
136 CHIP_R580,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137 CHIP_LAST,
138};
139
140enum radeon_cp_microcode_version {
141 UCODE_R100,
142 UCODE_R200,
143 UCODE_R300,
144};
145
146/*
147 * Chip flags
148 */
149enum radeon_chip_flags {
Dave Airlie54a56ac2006-09-22 04:25:09 +1000150 RADEON_FAMILY_MASK = 0x0000ffffUL,
151 RADEON_FLAGS_MASK = 0xffff0000UL,
152 RADEON_IS_MOBILITY = 0x00010000UL,
153 RADEON_IS_IGP = 0x00020000UL,
154 RADEON_SINGLE_CRTC = 0x00040000UL,
155 RADEON_IS_AGP = 0x00080000UL,
156 RADEON_HAS_HIERZ = 0x00100000UL,
157 RADEON_IS_PCIE = 0x00200000UL,
158 RADEON_NEW_MEMMAP = 0x00400000UL,
159 RADEON_IS_PCI = 0x00800000UL,
Dave Airlief2b04cd2007-05-08 15:19:23 +1000160 RADEON_IS_IGPGART = 0x01000000UL,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161};
162
163typedef struct drm_radeon_freelist {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000164 unsigned int age;
Dave Airlie056219e2007-07-11 16:17:42 +1000165 struct drm_buf *buf;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000166 struct drm_radeon_freelist *next;
167 struct drm_radeon_freelist *prev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168} drm_radeon_freelist_t;
169
170typedef struct drm_radeon_ring_buffer {
171 u32 *start;
172 u32 *end;
173 int size;
174 int size_l2qw;
175
Roland Scheidegger576cc452008-02-07 14:59:24 +1000176 int rptr_update; /* Double Words */
177 int rptr_update_l2qw; /* log2 Quad Words */
178
179 int fetch_size; /* Double Words */
180 int fetch_size_l2ow; /* log2 Oct Words */
181
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 u32 tail;
183 u32 tail_mask;
184 int space;
185
186 int high_mark;
187} drm_radeon_ring_buffer_t;
188
189typedef struct drm_radeon_depth_clear_t {
190 u32 rb3d_cntl;
191 u32 rb3d_zstencilcntl;
192 u32 se_cntl;
193} drm_radeon_depth_clear_t;
194
195struct drm_radeon_driver_file_fields {
196 int64_t radeon_fb_delta;
197};
198
199struct mem_block {
200 struct mem_block *next;
201 struct mem_block *prev;
202 int start;
203 int size;
Eric Anholt6c340ea2007-08-25 20:23:09 +1000204 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205};
206
207struct radeon_surface {
208 int refcount;
209 u32 lower;
210 u32 upper;
211 u32 flags;
212};
213
214struct radeon_virt_surface {
215 int surface_index;
216 u32 lower;
217 u32 upper;
218 u32 flags;
Eric Anholt6c340ea2007-08-25 20:23:09 +1000219 struct drm_file *file_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220};
221
Jerome Glisse54f961a2008-08-13 09:46:31 +1000222#define RADEON_FLUSH_EMITED (1 < 0)
223#define RADEON_PURGE_EMITED (1 < 1)
224
Dave Airlie7c1c2872008-11-28 14:22:24 +1000225struct drm_radeon_master_private {
226 drm_local_map_t *sarea;
227 drm_radeon_sarea_t *sarea_priv;
228};
229
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230typedef struct drm_radeon_private {
231 drm_radeon_ring_buffer_t ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232
233 u32 fb_location;
Dave Airlied5ea7022006-03-19 19:37:55 +1100234 u32 fb_size;
235 int new_memmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236
237 int gart_size;
238 u32 gart_vm_start;
239 unsigned long gart_buffers_offset;
240
241 int cp_mode;
242 int cp_running;
243
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000244 drm_radeon_freelist_t *head;
245 drm_radeon_freelist_t *tail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 int last_buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247 int writeback_works;
248
249 int usec_timeout;
250
251 int microcode_version;
252
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 struct {
254 u32 boxes;
255 int freelist_timeouts;
256 int freelist_loops;
257 int requested_bufs;
258 int last_frame_reads;
259 int last_clear_reads;
260 int clears;
261 int texture_uploads;
262 } stats;
263
264 int do_boxes;
265 int page_flipping;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266
267 u32 color_fmt;
268 unsigned int front_offset;
269 unsigned int front_pitch;
270 unsigned int back_offset;
271 unsigned int back_pitch;
272
273 u32 depth_fmt;
274 unsigned int depth_offset;
275 unsigned int depth_pitch;
276
277 u32 front_pitch_offset;
278 u32 back_pitch_offset;
279 u32 depth_pitch_offset;
280
281 drm_radeon_depth_clear_t depth_clear;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000282
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283 unsigned long ring_offset;
284 unsigned long ring_rptr_offset;
285 unsigned long buffers_offset;
286 unsigned long gart_textures_offset;
287
288 drm_local_map_t *sarea;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 drm_local_map_t *cp_ring;
290 drm_local_map_t *ring_rptr;
291 drm_local_map_t *gart_textures;
292
293 struct mem_block *gart_heap;
294 struct mem_block *fb_heap;
295
296 /* SW interrupt */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000297 wait_queue_head_t swi_queue;
298 atomic_t swi_emitted;
Dave Airlieddbee332007-07-11 12:16:01 +1000299 int vblank_crtc;
300 uint32_t irq_enable_reg;
Dave Airliec0beb2a2008-05-28 13:52:28 +1000301 uint32_t r500_disp_irq_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302
303 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000304 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000306 unsigned long pcigart_offset;
Dave Airlief2b04cd2007-05-08 15:19:23 +1000307 unsigned int pcigart_offset_set;
Dave Airlie55910512007-07-11 16:53:40 +1000308 struct drm_ati_pcigart_info gart_info;
Dave Airlieea98a922005-09-11 20:28:11 +1000309
Dave Airlieee4621f2006-03-19 19:45:26 +1100310 u32 scratch_ages[5];
311
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 /* starting from here on, data is preserved accross an open */
313 uint32_t flags; /* see radeon_chip_flags */
Benjamin Herrenschmidtd883f7f2009-02-02 16:55:45 +1100314 resource_size_t fb_aper_offset;
Alex Deucher5b92c402008-05-28 11:57:40 +1000315
316 int num_gb_pipes;
Jerome Glisse54f961a2008-08-13 09:46:31 +1000317 int track_flush;
Dave Airlie78538bf2008-11-11 17:56:16 +1000318 drm_local_map_t *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319} drm_radeon_private_t;
320
321typedef struct drm_radeon_buf_priv {
322 u32 age;
323} drm_radeon_buf_priv_t;
324
Dave Airlieb3a83632005-09-30 18:37:36 +1000325typedef struct drm_radeon_kcmd_buffer {
326 int bufsz;
327 char *buf;
328 int nbox;
Dave Airliec60ce622007-07-11 15:27:12 +1000329 struct drm_clip_rect __user *boxes;
Dave Airlieb3a83632005-09-30 18:37:36 +1000330} drm_radeon_kcmd_buffer_t;
331
Dave Airlie689b9d72005-09-30 17:09:07 +1000332extern int radeon_no_wb;
Eric Anholtc153f452007-09-03 12:06:45 +1000333extern struct drm_ioctl_desc radeon_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +1000334extern int radeon_max_ioctl;
335
David Millerb07fa022009-02-12 02:15:37 -0800336extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
337extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
338
339#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
340#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
341
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +1100342/* Check whether the given hardware address is inside the framebuffer or the
343 * GART area.
344 */
345static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
346 u64 off)
347{
348 u32 fb_start = dev_priv->fb_location;
349 u32 fb_end = fb_start + dev_priv->fb_size - 1;
350 u32 gart_start = dev_priv->gart_vm_start;
351 u32 gart_end = gart_start + dev_priv->gart_size - 1;
352
353 return ((off >= fb_start && off <= fb_end) ||
354 (off >= gart_start && off <= gart_end));
355}
356
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 /* radeon_cp.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000358extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
359extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
360extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
361extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
362extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
363extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
364extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
365extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
366extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000367extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368
Dave Airlie84b1fd12007-07-11 15:53:27 +1000369extern void radeon_freelist_reset(struct drm_device * dev);
Dave Airlie056219e2007-07-11 16:17:42 +1000370extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000372extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000374extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375
376extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
Dave Airlie836cf042005-07-10 19:27:04 +1000377extern int radeon_presetup(struct drm_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378extern int radeon_driver_postcleanup(struct drm_device *dev);
379
Eric Anholtc153f452007-09-03 12:06:45 +1000380extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
381extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
382extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000383extern void radeon_mem_takedown(struct mem_block **heap);
Eric Anholt6c340ea2007-08-25 20:23:09 +1000384extern void radeon_mem_release(struct drm_file *file_priv,
385 struct mem_block *heap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386
387 /* radeon_irq.c */
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700388extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
Eric Anholtc153f452007-09-03 12:06:45 +1000389extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
390extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391
Dave Airlie84b1fd12007-07-11 15:53:27 +1000392extern void radeon_do_release(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700393extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
394extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
395extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000396extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000397extern void radeon_driver_irq_preinstall(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700398extern int radeon_driver_irq_postinstall(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000399extern void radeon_driver_irq_uninstall(struct drm_device * dev);
Dennis Kasprzyk7ecabc52008-06-19 12:36:55 +1000400extern void radeon_enable_interrupt(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000401extern int radeon_vblank_crtc_get(struct drm_device *dev);
402extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403
Dave Airlie22eae942005-11-10 22:16:34 +1100404extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
405extern int radeon_driver_unload(struct drm_device *dev);
406extern int radeon_driver_firstopen(struct drm_device *dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700407extern void radeon_driver_preclose(struct drm_device *dev,
408 struct drm_file *file_priv);
409extern void radeon_driver_postclose(struct drm_device *dev,
410 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000411extern void radeon_driver_lastclose(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700412extern int radeon_driver_open(struct drm_device *dev,
413 struct drm_file *file_priv);
Dave Airlie9a186642005-06-23 21:29:18 +1000414extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
415 unsigned long arg);
416
Dave Airlie7c1c2872008-11-28 14:22:24 +1000417extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
418extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
419extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master);
Dave Airlie414ed532005-08-16 20:43:16 +1000420/* r300_cmdbuf.c */
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000421extern void r300_init_reg_flags(struct drm_device *dev);
Dave Airlie414ed532005-08-16 20:43:16 +1000422
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700423extern int r300_do_cp_cmdbuf(struct drm_device *dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000424 struct drm_file *file_priv,
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700425 drm_radeon_kcmd_buffer_t *cmdbuf);
Dave Airlie414ed532005-08-16 20:43:16 +1000426
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427/* Flags for stats.boxes
428 */
429#define RADEON_BOX_DMA_IDLE 0x1
430#define RADEON_BOX_RING_FULL 0x2
431#define RADEON_BOX_FLIP 0x4
432#define RADEON_BOX_WAIT_IDLE 0x8
433#define RADEON_BOX_TEXTURE_LOAD 0x10
434
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435/* Register definitions, register access macros and drmAddMap constants
436 * for Radeon kernel driver.
437 */
438
439#define RADEON_AGP_COMMAND 0x0f60
Dave Airlied985c102006-01-02 21:32:48 +1100440#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
441# define RADEON_AGP_ENABLE (1<<8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442#define RADEON_AUX_SCISSOR_CNTL 0x26f0
443# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
444# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
445# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
446# define RADEON_SCISSOR_0_ENABLE (1 << 28)
447# define RADEON_SCISSOR_1_ENABLE (1 << 29)
448# define RADEON_SCISSOR_2_ENABLE (1 << 30)
449
Alex Deucheredc6f382008-10-17 09:21:45 +1000450/*
451 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
452 * don't have an explicit bus mastering disable bit. It's handled
453 * by the PCI D-states. PMI_BM_DIS disables D-state bus master
454 * handling, not bus mastering itself.
455 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456#define RADEON_BUS_CNTL 0x0030
Alex Deucher4e270e92008-10-28 07:48:34 +1000457/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458# define RADEON_BUS_MASTER_DIS (1 << 6)
Alex Deucher4e270e92008-10-28 07:48:34 +1000459/* rs600/rs690/rs740 */
460# define RS600_BUS_MASTER_DIS (1 << 14)
461# define RS600_MSI_REARM (1 << 20)
462/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
Alex Deucheredc6f382008-10-17 09:21:45 +1000463
464#define RADEON_BUS_CNTL1 0x0034
465# define RADEON_PMI_BM_DIS (1 << 2)
466# define RADEON_PMI_INT_DIS (1 << 3)
467
468#define RV370_BUS_CNTL 0x004c
469# define RV370_PMI_BM_DIS (1 << 5)
470# define RV370_PMI_INT_DIS (1 << 6)
471
472#define RADEON_MSI_REARM_EN 0x0160
473/* rv370/rv380, rv410, r423/r430/r480, r5xx */
474# define RV370_MSI_REARM_EN (1 << 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475
476#define RADEON_CLOCK_CNTL_DATA 0x000c
477# define RADEON_PLL_WR_EN (1 << 7)
478#define RADEON_CLOCK_CNTL_INDEX 0x0008
479#define RADEON_CONFIG_APER_SIZE 0x0108
Dave Airlied985c102006-01-02 21:32:48 +1100480#define RADEON_CONFIG_MEMSIZE 0x00f8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481#define RADEON_CRTC_OFFSET 0x0224
482#define RADEON_CRTC_OFFSET_CNTL 0x0228
483# define RADEON_CRTC_TILE_EN (1 << 15)
484# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
485#define RADEON_CRTC2_OFFSET 0x0324
486#define RADEON_CRTC2_OFFSET_CNTL 0x0328
487
Dave Airlieea98a922005-09-11 20:28:11 +1000488#define RADEON_PCIE_INDEX 0x0030
489#define RADEON_PCIE_DATA 0x0034
490#define RADEON_PCIE_TX_GART_CNTL 0x10
Dave Airliebc5f4522007-11-05 12:50:58 +1000491# define RADEON_PCIE_TX_GART_EN (1 << 0)
Alex Deucher27359772008-05-28 12:54:16 +1000492# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
493# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
494# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
495# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
496# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
497# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
498# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
Dave Airlieea98a922005-09-11 20:28:11 +1000499#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
500#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
Dave Airliebc5f4522007-11-05 12:50:58 +1000501#define RADEON_PCIE_TX_GART_BASE 0x13
Dave Airlieea98a922005-09-11 20:28:11 +1000502#define RADEON_PCIE_TX_GART_START_LO 0x14
503#define RADEON_PCIE_TX_GART_START_HI 0x15
504#define RADEON_PCIE_TX_GART_END_LO 0x16
505#define RADEON_PCIE_TX_GART_END_HI 0x17
506
Alex Deucher45e51902008-05-28 13:28:59 +1000507#define RS480_NB_MC_INDEX 0x168
508# define RS480_NB_MC_IND_WR_EN (1 << 8)
509#define RS480_NB_MC_DATA 0x16c
Dave Airlief2b04cd2007-05-08 15:19:23 +1000510
Maciej Cencora60f92682008-02-19 21:32:45 +1000511#define RS690_MC_INDEX 0x78
512# define RS690_MC_INDEX_MASK 0x1ff
513# define RS690_MC_INDEX_WR_EN (1 << 9)
514# define RS690_MC_INDEX_WR_ACK 0x7f
515#define RS690_MC_DATA 0x7c
516
Alex Deucher27359772008-05-28 12:54:16 +1000517/* MC indirect registers */
Alex Deucher45e51902008-05-28 13:28:59 +1000518#define RS480_MC_MISC_CNTL 0x18
519# define RS480_DISABLE_GTW (1 << 1)
Alex Deucher27359772008-05-28 12:54:16 +1000520/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
Alex Deucher45e51902008-05-28 13:28:59 +1000521# define RS480_GART_INDEX_REG_EN (1 << 12)
Alex Deucher27359772008-05-28 12:54:16 +1000522# define RS690_BLOCK_GFX_D3_EN (1 << 14)
Alex Deucher45e51902008-05-28 13:28:59 +1000523#define RS480_K8_FB_LOCATION 0x1e
524#define RS480_GART_FEATURE_ID 0x2b
525# define RS480_HANG_EN (1 << 11)
526# define RS480_TLB_ENABLE (1 << 18)
527# define RS480_P2P_ENABLE (1 << 19)
528# define RS480_GTW_LAC_EN (1 << 25)
529# define RS480_2LEVEL_GART (0 << 30)
530# define RS480_1LEVEL_GART (1 << 30)
531# define RS480_PDC_EN (1 << 31)
532#define RS480_GART_BASE 0x2c
533#define RS480_GART_CACHE_CNTRL 0x2e
534# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
535#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
536# define RS480_GART_EN (1 << 0)
537# define RS480_VA_SIZE_32MB (0 << 1)
538# define RS480_VA_SIZE_64MB (1 << 1)
539# define RS480_VA_SIZE_128MB (2 << 1)
540# define RS480_VA_SIZE_256MB (3 << 1)
541# define RS480_VA_SIZE_512MB (4 << 1)
542# define RS480_VA_SIZE_1GB (5 << 1)
543# define RS480_VA_SIZE_2GB (6 << 1)
544#define RS480_AGP_MODE_CNTL 0x39
545# define RS480_POST_GART_Q_SIZE (1 << 18)
546# define RS480_NONGART_SNOOP (1 << 19)
547# define RS480_AGP_RD_BUF_SIZE (1 << 20)
548# define RS480_REQ_TYPE_SNOOP_SHIFT 22
549# define RS480_REQ_TYPE_SNOOP_MASK 0x3
550# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
551#define RS480_MC_MISC_UMA_CNTL 0x5f
552#define RS480_MC_MCLK_CNTL 0x7a
553#define RS480_MC_UMA_DUALCH_CNTL 0x86
Alex Deucher27359772008-05-28 12:54:16 +1000554
Maciej Cencora60f92682008-02-19 21:32:45 +1000555#define RS690_MC_FB_LOCATION 0x100
556#define RS690_MC_AGP_LOCATION 0x101
557#define RS690_MC_AGP_BASE 0x102
Dave Airlie3722bfc2008-05-28 11:28:27 +1000558#define RS690_MC_AGP_BASE_2 0x103
Maciej Cencora60f92682008-02-19 21:32:45 +1000559
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000560#define R520_MC_IND_INDEX 0x70
Alex Deucher27359772008-05-28 12:54:16 +1000561#define R520_MC_IND_WR_EN (1 << 24)
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000562#define R520_MC_IND_DATA 0x74
563
564#define RV515_MC_FB_LOCATION 0x01
565#define RV515_MC_AGP_LOCATION 0x02
Dave Airlie70b13d52008-06-19 11:40:44 +1000566#define RV515_MC_AGP_BASE 0x03
567#define RV515_MC_AGP_BASE_2 0x04
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000568
569#define R520_MC_FB_LOCATION 0x04
570#define R520_MC_AGP_LOCATION 0x05
Dave Airlie70b13d52008-06-19 11:40:44 +1000571#define R520_MC_AGP_BASE 0x06
572#define R520_MC_AGP_BASE_2 0x07
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000573
Dave Airlie414ed532005-08-16 20:43:16 +1000574#define RADEON_MPP_TB_CONFIG 0x01c0
575#define RADEON_MEM_CNTL 0x0140
576#define RADEON_MEM_SDRAM_MODE_REG 0x0158
Alex Deucher45e51902008-05-28 13:28:59 +1000577#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
578#define RS480_AGP_BASE_2 0x0164
Dave Airlie414ed532005-08-16 20:43:16 +1000579#define RADEON_AGP_BASE 0x0170
580
Alex Deucher5b92c402008-05-28 11:57:40 +1000581/* pipe config regs */
582#define R400_GB_PIPE_SELECT 0x402c
583#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
584#define R500_SU_REG_DEST 0x42c8
585#define R300_GB_TILE_CONFIG 0x4018
586# define R300_ENABLE_TILING (1 << 0)
587# define R300_PIPE_COUNT_RV350 (0 << 1)
588# define R300_PIPE_COUNT_R300 (3 << 1)
589# define R300_PIPE_COUNT_R420_3P (6 << 1)
590# define R300_PIPE_COUNT_R420 (7 << 1)
591# define R300_TILE_SIZE_8 (0 << 4)
592# define R300_TILE_SIZE_16 (1 << 4)
593# define R300_TILE_SIZE_32 (2 << 4)
594# define R300_SUBPIXEL_1_12 (0 << 16)
595# define R300_SUBPIXEL_1_16 (1 << 16)
596#define R300_DST_PIPE_CONFIG 0x170c
597# define R300_PIPE_AUTO_CONFIG (1 << 31)
598#define R300_RB2D_DSTCACHE_MODE 0x3428
599# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
600# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
601
Linus Torvalds1da177e2005-04-16 15:20:36 -0700602#define RADEON_RB3D_COLOROFFSET 0x1c40
603#define RADEON_RB3D_COLORPITCH 0x1c48
604
Michel Daenzer3e14a282006-09-22 04:26:35 +1000605#define RADEON_SRC_X_Y 0x1590
606
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607#define RADEON_DP_GUI_MASTER_CNTL 0x146c
608# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
609# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
610# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
611# define RADEON_GMC_BRUSH_NONE (15 << 4)
612# define RADEON_GMC_DST_16BPP (4 << 8)
613# define RADEON_GMC_DST_24BPP (5 << 8)
614# define RADEON_GMC_DST_32BPP (6 << 8)
615# define RADEON_GMC_DST_DATATYPE_SHIFT 8
616# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
617# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
618# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
619# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
620# define RADEON_GMC_WR_MSK_DIS (1 << 30)
621# define RADEON_ROP3_S 0x00cc0000
622# define RADEON_ROP3_P 0x00f00000
623#define RADEON_DP_WRITE_MASK 0x16cc
Michel Daenzer3e14a282006-09-22 04:26:35 +1000624#define RADEON_SRC_PITCH_OFFSET 0x1428
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625#define RADEON_DST_PITCH_OFFSET 0x142c
626#define RADEON_DST_PITCH_OFFSET_C 0x1c80
627# define RADEON_DST_TILE_LINEAR (0 << 30)
628# define RADEON_DST_TILE_MACRO (1 << 30)
629# define RADEON_DST_TILE_MICRO (2 << 30)
630# define RADEON_DST_TILE_BOTH (3 << 30)
631
632#define RADEON_SCRATCH_REG0 0x15e0
633#define RADEON_SCRATCH_REG1 0x15e4
634#define RADEON_SCRATCH_REG2 0x15e8
635#define RADEON_SCRATCH_REG3 0x15ec
636#define RADEON_SCRATCH_REG4 0x15f0
637#define RADEON_SCRATCH_REG5 0x15f4
638#define RADEON_SCRATCH_UMSK 0x0770
639#define RADEON_SCRATCH_ADDR 0x0774
640
641#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
642
David Millerb07fa022009-02-12 02:15:37 -0800643extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
644
645#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647#define RADEON_GEN_INT_CNTL 0x0040
648# define RADEON_CRTC_VBLANK_MASK (1 << 0)
Dave Airlieddbee332007-07-11 12:16:01 +1000649# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
651# define RADEON_SW_INT_ENABLE (1 << 25)
652
653#define RADEON_GEN_INT_STATUS 0x0044
654# define RADEON_CRTC_VBLANK_STAT (1 << 0)
Dave Airliebc5f4522007-11-05 12:50:58 +1000655# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
Dave Airlieddbee332007-07-11 12:16:01 +1000656# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
Dave Airliebc5f4522007-11-05 12:50:58 +1000657# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
659# define RADEON_SW_INT_TEST (1 << 25)
Dave Airliebc5f4522007-11-05 12:50:58 +1000660# define RADEON_SW_INT_TEST_ACK (1 << 25)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661# define RADEON_SW_INT_FIRE (1 << 26)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700662# define R500_DISPLAY_INT_STATUS (1 << 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663
664#define RADEON_HOST_PATH_CNTL 0x0130
665# define RADEON_HDP_SOFT_RESET (1 << 26)
666# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
667# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
668
669#define RADEON_ISYNC_CNTL 0x1724
670# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
671# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
672# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
673# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
674# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
675# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
676
677#define RADEON_RBBM_GUICNTL 0x172c
678# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
679# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
680# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
681# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
682
683#define RADEON_MC_AGP_LOCATION 0x014c
684#define RADEON_MC_FB_LOCATION 0x0148
685#define RADEON_MCLK_CNTL 0x0012
686# define RADEON_FORCEON_MCLKA (1 << 16)
687# define RADEON_FORCEON_MCLKB (1 << 17)
688# define RADEON_FORCEON_YCLKA (1 << 18)
689# define RADEON_FORCEON_YCLKB (1 << 19)
690# define RADEON_FORCEON_MC (1 << 20)
691# define RADEON_FORCEON_AIC (1 << 21)
692
693#define RADEON_PP_BORDER_COLOR_0 0x1d40
694#define RADEON_PP_BORDER_COLOR_1 0x1d44
695#define RADEON_PP_BORDER_COLOR_2 0x1d48
696#define RADEON_PP_CNTL 0x1c38
697# define RADEON_SCISSOR_ENABLE (1 << 1)
698#define RADEON_PP_LUM_MATRIX 0x1d00
699#define RADEON_PP_MISC 0x1c14
700#define RADEON_PP_ROT_MATRIX_0 0x1d58
701#define RADEON_PP_TXFILTER_0 0x1c54
702#define RADEON_PP_TXOFFSET_0 0x1c5c
703#define RADEON_PP_TXFILTER_1 0x1c6c
704#define RADEON_PP_TXFILTER_2 0x1c84
705
Alex Deucher5e35eff2008-06-19 12:39:23 +1000706#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
707#define R300_DSTCACHE_CTLSTAT 0x1714
708# define R300_RB2D_DC_FLUSH (3 << 0)
709# define R300_RB2D_DC_FREE (3 << 2)
710# define R300_RB2D_DC_FLUSH_ALL 0xf
711# define R300_RB2D_DC_BUSY (1 << 31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712#define RADEON_RB3D_CNTL 0x1c3c
713# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
714# define RADEON_PLANE_MASK_ENABLE (1 << 1)
715# define RADEON_DITHER_ENABLE (1 << 2)
716# define RADEON_ROUND_ENABLE (1 << 3)
717# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
718# define RADEON_DITHER_INIT (1 << 5)
719# define RADEON_ROP_ENABLE (1 << 6)
720# define RADEON_STENCIL_ENABLE (1 << 7)
721# define RADEON_Z_ENABLE (1 << 8)
722# define RADEON_ZBLOCK16 (1 << 15)
723#define RADEON_RB3D_DEPTHOFFSET 0x1c24
724#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
725#define RADEON_RB3D_DEPTHPITCH 0x1c28
726#define RADEON_RB3D_PLANEMASK 0x1d84
727#define RADEON_RB3D_STENCILREFMASK 0x1d7c
728#define RADEON_RB3D_ZCACHE_MODE 0x3250
729#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
730# define RADEON_RB3D_ZC_FLUSH (1 << 0)
731# define RADEON_RB3D_ZC_FREE (1 << 2)
732# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
733# define RADEON_RB3D_ZC_BUSY (1 << 31)
Alex Deucher259434a2008-05-28 11:51:12 +1000734#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
735# define R300_ZC_FLUSH (1 << 0)
736# define R300_ZC_FREE (1 << 1)
Alex Deucher259434a2008-05-28 11:51:12 +1000737# define R300_ZC_BUSY (1 << 31)
Michel Dänzerb9b603dd2006-08-07 20:41:53 +1000738#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
739# define RADEON_RB3D_DC_FLUSH (3 << 0)
740# define RADEON_RB3D_DC_FREE (3 << 2)
741# define RADEON_RB3D_DC_FLUSH_ALL 0xf
742# define RADEON_RB3D_DC_BUSY (1 << 31)
Alex Deucher259434a2008-05-28 11:51:12 +1000743#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
Jerome Glisse54f961a2008-08-13 09:46:31 +1000744# define R300_RB3D_DC_FLUSH (2 << 0)
745# define R300_RB3D_DC_FREE (2 << 2)
Alex Deucher259434a2008-05-28 11:51:12 +1000746# define R300_RB3D_DC_FINISH (1 << 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
748# define RADEON_Z_TEST_MASK (7 << 4)
749# define RADEON_Z_TEST_ALWAYS (7 << 4)
750# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
751# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
752# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
753# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
754# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
755# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
756# define RADEON_FORCE_Z_DIRTY (1 << 29)
757# define RADEON_Z_WRITE_ENABLE (1 << 30)
758# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
759#define RADEON_RBBM_SOFT_RESET 0x00f0
760# define RADEON_SOFT_RESET_CP (1 << 0)
761# define RADEON_SOFT_RESET_HI (1 << 1)
762# define RADEON_SOFT_RESET_SE (1 << 2)
763# define RADEON_SOFT_RESET_RE (1 << 3)
764# define RADEON_SOFT_RESET_PP (1 << 4)
765# define RADEON_SOFT_RESET_E2 (1 << 5)
766# define RADEON_SOFT_RESET_RB (1 << 6)
767# define RADEON_SOFT_RESET_HDP (1 << 7)
Roland Scheidegger576cc452008-02-07 14:59:24 +1000768/*
769 * 6:0 Available slots in the FIFO
770 * 8 Host Interface active
771 * 9 CP request active
772 * 10 FIFO request active
773 * 11 Host Interface retry active
774 * 12 CP retry active
775 * 13 FIFO retry active
776 * 14 FIFO pipeline busy
777 * 15 Event engine busy
778 * 16 CP command stream busy
779 * 17 2D engine busy
780 * 18 2D portion of render backend busy
781 * 20 3D setup engine busy
782 * 26 GA engine busy
783 * 27 CBA 2D engine busy
784 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
785 * command stream queue not empty or Ring Buffer not empty
786 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787#define RADEON_RBBM_STATUS 0x0e40
Roland Scheidegger576cc452008-02-07 14:59:24 +1000788/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
789/* #define RADEON_RBBM_STATUS 0x1740 */
790/* bits 6:0 are dword slots available in the cmd fifo */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700791# define RADEON_RBBM_FIFOCNT_MASK 0x007f
Roland Scheidegger576cc452008-02-07 14:59:24 +1000792# define RADEON_HIRQ_ON_RBB (1 << 8)
793# define RADEON_CPRQ_ON_RBB (1 << 9)
794# define RADEON_CFRQ_ON_RBB (1 << 10)
795# define RADEON_HIRQ_IN_RTBUF (1 << 11)
796# define RADEON_CPRQ_IN_RTBUF (1 << 12)
797# define RADEON_CFRQ_IN_RTBUF (1 << 13)
798# define RADEON_PIPE_BUSY (1 << 14)
799# define RADEON_ENG_EV_BUSY (1 << 15)
800# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
801# define RADEON_E2_BUSY (1 << 17)
802# define RADEON_RB2D_BUSY (1 << 18)
803# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
804# define RADEON_VAP_BUSY (1 << 20)
805# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
806# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
807# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
808# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
809# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
810# define RADEON_GA_BUSY (1 << 26)
811# define RADEON_CBA2D_BUSY (1 << 27)
812# define RADEON_RBBM_ACTIVE (1 << 31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813#define RADEON_RE_LINE_PATTERN 0x1cd0
814#define RADEON_RE_MISC 0x26c4
815#define RADEON_RE_TOP_LEFT 0x26c0
816#define RADEON_RE_WIDTH_HEIGHT 0x1c44
817#define RADEON_RE_STIPPLE_ADDR 0x1cc8
818#define RADEON_RE_STIPPLE_DATA 0x1ccc
819
820#define RADEON_SCISSOR_TL_0 0x1cd8
821#define RADEON_SCISSOR_BR_0 0x1cdc
822#define RADEON_SCISSOR_TL_1 0x1ce0
823#define RADEON_SCISSOR_BR_1 0x1ce4
824#define RADEON_SCISSOR_TL_2 0x1ce8
825#define RADEON_SCISSOR_BR_2 0x1cec
826#define RADEON_SE_COORD_FMT 0x1c50
827#define RADEON_SE_CNTL 0x1c4c
828# define RADEON_FFACE_CULL_CW (0 << 0)
829# define RADEON_BFACE_SOLID (3 << 1)
830# define RADEON_FFACE_SOLID (3 << 3)
831# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
832# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
833# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
834# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
835# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
836# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
837# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
838# define RADEON_FOG_SHADE_FLAT (1 << 14)
839# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
840# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
841# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
842# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
843# define RADEON_ROUND_MODE_TRUNC (0 << 28)
844# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
845#define RADEON_SE_CNTL_STATUS 0x2140
846#define RADEON_SE_LINE_WIDTH 0x1db8
847#define RADEON_SE_VPORT_XSCALE 0x1d98
848#define RADEON_SE_ZBIAS_FACTOR 0x1db0
849#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
850#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
851#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
852# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
853# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
854#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
855#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
856# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
857#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
858#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
859#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
860#define RADEON_SURFACE_CNTL 0x0b00
861# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
862# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
863# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
864# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
865# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
866# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
867# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
868# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
869# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
870#define RADEON_SURFACE0_INFO 0x0b0c
871# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
872# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
873# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
874# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
875# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
876# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
877#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
878#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
879# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
880#define RADEON_SURFACE1_INFO 0x0b1c
881#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
882#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
883#define RADEON_SURFACE2_INFO 0x0b2c
884#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
885#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
886#define RADEON_SURFACE3_INFO 0x0b3c
887#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
888#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
889#define RADEON_SURFACE4_INFO 0x0b4c
890#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
891#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
892#define RADEON_SURFACE5_INFO 0x0b5c
893#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
894#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
895#define RADEON_SURFACE6_INFO 0x0b6c
896#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
897#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
898#define RADEON_SURFACE7_INFO 0x0b7c
899#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
900#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
901#define RADEON_SW_SEMAPHORE 0x013c
902
903#define RADEON_WAIT_UNTIL 0x1720
904# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
Dave Airlied985c102006-01-02 21:32:48 +1100905# define RADEON_WAIT_2D_IDLE (1 << 14)
906# define RADEON_WAIT_3D_IDLE (1 << 15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
908# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
909# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
910
911#define RADEON_RB3D_ZMASKOFFSET 0x3234
912#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
913# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
914# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
915
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916/* CP registers */
917#define RADEON_CP_ME_RAM_ADDR 0x07d4
918#define RADEON_CP_ME_RAM_RADDR 0x07d8
919#define RADEON_CP_ME_RAM_DATAH 0x07dc
920#define RADEON_CP_ME_RAM_DATAL 0x07e0
921
922#define RADEON_CP_RB_BASE 0x0700
923#define RADEON_CP_RB_CNTL 0x0704
924# define RADEON_BUF_SWAP_32BIT (2 << 16)
Michel Dänzerae1b1a482006-08-07 20:37:46 +1000925# define RADEON_RB_NO_UPDATE (1 << 27)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700926#define RADEON_CP_RB_RPTR_ADDR 0x070c
927#define RADEON_CP_RB_RPTR 0x0710
928#define RADEON_CP_RB_WPTR 0x0714
929
930#define RADEON_CP_RB_WPTR_DELAY 0x0718
931# define RADEON_PRE_WRITE_TIMER_SHIFT 0
932# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
933
934#define RADEON_CP_IB_BASE 0x0738
935
936#define RADEON_CP_CSQ_CNTL 0x0740
937# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
938# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
939# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
940# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
941# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
942# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
943# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
944
945#define RADEON_AIC_CNTL 0x01d0
946# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
Alex Deucher4e270e92008-10-28 07:48:34 +1000947# define RS400_MSI_REARM (1 << 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948#define RADEON_AIC_STAT 0x01d4
949#define RADEON_AIC_PT_BASE 0x01d8
950#define RADEON_AIC_LO_ADDR 0x01dc
951#define RADEON_AIC_HI_ADDR 0x01e0
952#define RADEON_AIC_TLB_ADDR 0x01e4
953#define RADEON_AIC_TLB_DATA 0x01e8
954
955/* CP command packets */
956#define RADEON_CP_PACKET0 0x00000000
957# define RADEON_ONE_REG_WR (1 << 15)
958#define RADEON_CP_PACKET1 0x40000000
959#define RADEON_CP_PACKET2 0x80000000
960#define RADEON_CP_PACKET3 0xC0000000
Dave Airlie414ed532005-08-16 20:43:16 +1000961# define RADEON_CP_NOP 0x00001000
962# define RADEON_CP_NEXT_CHAR 0x00001900
963# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
964# define RADEON_CP_SET_SCISSORS 0x00001E00
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000965 /* GEN_INDX_PRIM is unsupported starting with R300 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700966# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
967# define RADEON_WAIT_FOR_IDLE 0x00002600
968# define RADEON_3D_DRAW_VBUF 0x00002800
969# define RADEON_3D_DRAW_IMMD 0x00002900
970# define RADEON_3D_DRAW_INDX 0x00002A00
Dave Airlie414ed532005-08-16 20:43:16 +1000971# define RADEON_CP_LOAD_PALETTE 0x00002C00
Linus Torvalds1da177e2005-04-16 15:20:36 -0700972# define RADEON_3D_LOAD_VBPNTR 0x00002F00
973# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
974# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
975# define RADEON_3D_CLEAR_ZMASK 0x00003200
Dave Airlie414ed532005-08-16 20:43:16 +1000976# define RADEON_CP_INDX_BUFFER 0x00003300
977# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
978# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
979# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
Linus Torvalds1da177e2005-04-16 15:20:36 -0700980# define RADEON_3D_CLEAR_HIZ 0x00003700
Dave Airlie414ed532005-08-16 20:43:16 +1000981# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
983# define RADEON_CNTL_PAINT_MULTI 0x00009A00
984# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
985# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
986
987#define RADEON_CP_PACKET_MASK 0xC0000000
988#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
989#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
990#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
991#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
992
993#define RADEON_VTX_Z_PRESENT (1 << 31)
994#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
995
996#define RADEON_PRIM_TYPE_NONE (0 << 0)
997#define RADEON_PRIM_TYPE_POINT (1 << 0)
998#define RADEON_PRIM_TYPE_LINE (2 << 0)
999#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1000#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1001#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1002#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1003#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1004#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1005#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1006#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1007#define RADEON_PRIM_TYPE_MASK 0xf
1008#define RADEON_PRIM_WALK_IND (1 << 4)
1009#define RADEON_PRIM_WALK_LIST (2 << 4)
1010#define RADEON_PRIM_WALK_RING (3 << 4)
1011#define RADEON_COLOR_ORDER_BGRA (0 << 6)
1012#define RADEON_COLOR_ORDER_RGBA (1 << 6)
1013#define RADEON_MAOS_ENABLE (1 << 7)
1014#define RADEON_VTX_FMT_R128_MODE (0 << 8)
1015#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1016#define RADEON_NUM_VERTICES_SHIFT 16
1017
1018#define RADEON_COLOR_FORMAT_CI8 2
1019#define RADEON_COLOR_FORMAT_ARGB1555 3
1020#define RADEON_COLOR_FORMAT_RGB565 4
1021#define RADEON_COLOR_FORMAT_ARGB8888 6
1022#define RADEON_COLOR_FORMAT_RGB332 7
1023#define RADEON_COLOR_FORMAT_RGB8 9
1024#define RADEON_COLOR_FORMAT_ARGB4444 15
1025
1026#define RADEON_TXFORMAT_I8 0
1027#define RADEON_TXFORMAT_AI88 1
1028#define RADEON_TXFORMAT_RGB332 2
1029#define RADEON_TXFORMAT_ARGB1555 3
1030#define RADEON_TXFORMAT_RGB565 4
1031#define RADEON_TXFORMAT_ARGB4444 5
1032#define RADEON_TXFORMAT_ARGB8888 6
1033#define RADEON_TXFORMAT_RGBA8888 7
1034#define RADEON_TXFORMAT_Y8 8
1035#define RADEON_TXFORMAT_VYUY422 10
1036#define RADEON_TXFORMAT_YVYU422 11
1037#define RADEON_TXFORMAT_DXT1 12
1038#define RADEON_TXFORMAT_DXT23 14
1039#define RADEON_TXFORMAT_DXT45 15
1040
1041#define R200_PP_TXCBLEND_0 0x2f00
1042#define R200_PP_TXCBLEND_1 0x2f10
1043#define R200_PP_TXCBLEND_2 0x2f20
1044#define R200_PP_TXCBLEND_3 0x2f30
1045#define R200_PP_TXCBLEND_4 0x2f40
1046#define R200_PP_TXCBLEND_5 0x2f50
1047#define R200_PP_TXCBLEND_6 0x2f60
1048#define R200_PP_TXCBLEND_7 0x2f70
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001049#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050#define R200_PP_TFACTOR_0 0x2ee0
1051#define R200_SE_VTX_FMT_0 0x2088
1052#define R200_SE_VAP_CNTL 0x2080
1053#define R200_SE_TCL_MATRIX_SEL_0 0x2230
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001054#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1055#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1056#define R200_PP_TXFILTER_5 0x2ca0
1057#define R200_PP_TXFILTER_4 0x2c80
1058#define R200_PP_TXFILTER_3 0x2c60
1059#define R200_PP_TXFILTER_2 0x2c40
1060#define R200_PP_TXFILTER_1 0x2c20
1061#define R200_PP_TXFILTER_0 0x2c00
Linus Torvalds1da177e2005-04-16 15:20:36 -07001062#define R200_PP_TXOFFSET_5 0x2d78
1063#define R200_PP_TXOFFSET_4 0x2d60
1064#define R200_PP_TXOFFSET_3 0x2d48
1065#define R200_PP_TXOFFSET_2 0x2d30
1066#define R200_PP_TXOFFSET_1 0x2d18
1067#define R200_PP_TXOFFSET_0 0x2d00
1068
1069#define R200_PP_CUBIC_FACES_0 0x2c18
1070#define R200_PP_CUBIC_FACES_1 0x2c38
1071#define R200_PP_CUBIC_FACES_2 0x2c58
1072#define R200_PP_CUBIC_FACES_3 0x2c78
1073#define R200_PP_CUBIC_FACES_4 0x2c98
1074#define R200_PP_CUBIC_FACES_5 0x2cb8
1075#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1076#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1077#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1078#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1079#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1080#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1081#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1082#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1083#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1084#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1085#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1086#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1087#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1088#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1089#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1090#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1091#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1092#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1093#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1094#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1095#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1096#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1097#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1098#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1099#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1100#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1101#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1102#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1103#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1104#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1105
1106#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1107#define R200_SE_VTE_CNTL 0x20b0
1108#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1109#define R200_PP_TAM_DEBUG3 0x2d9c
1110#define R200_PP_CNTL_X 0x2cc4
1111#define R200_SE_VAP_CNTL_STATUS 0x2140
1112#define R200_RE_SCISSOR_TL_0 0x1cd8
1113#define R200_RE_SCISSOR_TL_1 0x1ce0
1114#define R200_RE_SCISSOR_TL_2 0x1ce8
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001115#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1117#define R200_SE_VTX_STATE_CNTL 0x2180
1118#define R200_RE_POINTSIZE 0x2648
1119#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1120
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001121#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122#define RADEON_PP_TEX_SIZE_1 0x1d0c
1123#define RADEON_PP_TEX_SIZE_2 0x1d14
1124
1125#define RADEON_PP_CUBIC_FACES_0 0x1d24
1126#define RADEON_PP_CUBIC_FACES_1 0x1d28
1127#define RADEON_PP_CUBIC_FACES_2 0x1d2c
1128#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1129#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1130#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1131
Dave Airlief2a22792006-06-24 16:55:34 +10001132#define RADEON_SE_TCL_STATE_FLUSH 0x2284
1133
Linus Torvalds1da177e2005-04-16 15:20:36 -07001134#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1135#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1136#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1137#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1138#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1139#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1140#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1141#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1142#define R200_3D_DRAW_IMMD_2 0xC0003500
1143#define R200_SE_VTX_FMT_1 0x208c
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001144#define R200_RE_CNTL 0x1c50
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145
1146#define R200_RB3D_BLENDCOLOR 0x3218
1147
1148#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1149
1150#define R200_PP_TRI_PERF 0x2cf8
1151
Dave Airlie9d176012005-09-11 19:55:53 +10001152#define R200_PP_AFS_0 0x2f80
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001153#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
Dave Airlie9d176012005-09-11 19:55:53 +10001154
Dave Airlied6fece02006-06-24 17:04:07 +10001155#define R200_VAP_PVS_CNTL_1 0x22D0
1156
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001157#define RADEON_CRTC_CRNT_FRAME 0x0214
1158#define RADEON_CRTC2_CRNT_FRAME 0x0314
1159
Dave Airliec0beb2a2008-05-28 13:52:28 +10001160#define R500_D1CRTC_STATUS 0x609c
1161#define R500_D2CRTC_STATUS 0x689c
1162#define R500_CRTC_V_BLANK (1<<0)
1163
1164#define R500_D1CRTC_FRAME_COUNT 0x60a4
1165#define R500_D2CRTC_FRAME_COUNT 0x68a4
1166
1167#define R500_D1MODE_V_COUNTER 0x6530
1168#define R500_D2MODE_V_COUNTER 0x6d30
1169
1170#define R500_D1MODE_VBLANK_STATUS 0x6534
1171#define R500_D2MODE_VBLANK_STATUS 0x6d34
1172#define R500_VBLANK_OCCURED (1<<0)
1173#define R500_VBLANK_ACK (1<<4)
1174#define R500_VBLANK_STAT (1<<12)
1175#define R500_VBLANK_INT (1<<16)
1176
1177#define R500_DxMODE_INT_MASK 0x6540
1178#define R500_D1MODE_INT_MASK (1<<0)
1179#define R500_D2MODE_INT_MASK (1<<8)
1180
1181#define R500_DISP_INTERRUPT_STATUS 0x7edc
1182#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1183#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1184
Linus Torvalds1da177e2005-04-16 15:20:36 -07001185/* Constants */
1186#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1187
1188#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1189#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1190#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1191#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1192#define RADEON_LAST_DISPATCH 1
1193
1194#define RADEON_MAX_VB_AGE 0x7fffffff
1195#define RADEON_MAX_VB_VERTS (0xffff)
1196
1197#define RADEON_RING_HIGH_MARK 128
1198
Dave Airlieea98a922005-09-11 20:28:11 +10001199#define RADEON_PCIGART_TABLE_SIZE (32*1024)
1200
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1202#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1203#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1204#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1205
Alex Deucher27359772008-05-28 12:54:16 +10001206#define RADEON_WRITE_PLL(addr, val) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207do { \
Alex Deucher27359772008-05-28 12:54:16 +10001208 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001209 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
Alex Deucher27359772008-05-28 12:54:16 +10001210 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211} while (0)
1212
Alex Deucher27359772008-05-28 12:54:16 +10001213#define RADEON_WRITE_PCIE(addr, val) \
Dave Airlieea98a922005-09-11 20:28:11 +10001214do { \
Alex Deucher27359772008-05-28 12:54:16 +10001215 RADEON_WRITE8(RADEON_PCIE_INDEX, \
Dave Airlieea98a922005-09-11 20:28:11 +10001216 ((addr) & 0xff)); \
Alex Deucher27359772008-05-28 12:54:16 +10001217 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
Dave Airlieea98a922005-09-11 20:28:11 +10001218} while (0)
1219
Alex Deucher45e51902008-05-28 13:28:59 +10001220#define R500_WRITE_MCIND(addr, val) \
1221do { \
1222 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1223 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1224 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1225} while (0)
1226
1227#define RS480_WRITE_MCIND(addr, val) \
1228do { \
1229 RADEON_WRITE(RS480_NB_MC_INDEX, \
1230 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1231 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1232 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1233} while (0)
Dave Airlie3d5e2c12008-02-07 15:01:05 +10001234
Alex Deucher27359772008-05-28 12:54:16 +10001235#define RS690_WRITE_MCIND(addr, val) \
Maciej Cencora60f92682008-02-19 21:32:45 +10001236do { \
1237 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1238 RADEON_WRITE(RS690_MC_DATA, val); \
1239 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1240} while (0)
1241
Alex Deucher45e51902008-05-28 13:28:59 +10001242#define IGP_WRITE_MCIND(addr, val) \
1243do { \
Alex Deucherf0738e92008-10-16 17:12:02 +10001244 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1245 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
Alex Deucher45e51902008-05-28 13:28:59 +10001246 RS690_WRITE_MCIND(addr, val); \
1247 else \
1248 RS480_WRITE_MCIND(addr, val); \
1249} while (0)
1250
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251#define CP_PACKET0( reg, n ) \
1252 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1253#define CP_PACKET0_TABLE( reg, n ) \
1254 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1255#define CP_PACKET1( reg0, reg1 ) \
1256 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1257#define CP_PACKET2() \
1258 (RADEON_CP_PACKET2)
1259#define CP_PACKET3( pkt, n ) \
1260 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1261
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262/* ================================================================
1263 * Engine control helper macros
1264 */
1265
1266#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1267 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1268 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1269 RADEON_WAIT_HOST_IDLECLEAN) ); \
1270} while (0)
1271
1272#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1273 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1274 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1275 RADEON_WAIT_HOST_IDLECLEAN) ); \
1276} while (0)
1277
1278#define RADEON_WAIT_UNTIL_IDLE() do { \
1279 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1280 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1281 RADEON_WAIT_3D_IDLECLEAN | \
1282 RADEON_WAIT_HOST_IDLECLEAN) ); \
1283} while (0)
1284
1285#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1286 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1287 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1288} while (0)
1289
1290#define RADEON_FLUSH_CACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +10001291 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1292 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1293 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1294 } else { \
1295 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +10001296 OUT_RING(R300_RB3D_DC_FLUSH); \
Alex Deucher259434a2008-05-28 11:51:12 +10001297 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298} while (0)
1299
1300#define RADEON_PURGE_CACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +10001301 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1302 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +10001303 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +10001304 } else { \
1305 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +10001306 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +10001307 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001308} while (0)
1309
1310#define RADEON_FLUSH_ZCACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +10001311 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1312 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1313 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1314 } else { \
1315 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1316 OUT_RING(R300_ZC_FLUSH); \
1317 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001318} while (0)
1319
1320#define RADEON_PURGE_ZCACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +10001321 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1322 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +10001323 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +10001324 } else { \
Jerome Glisse54f961a2008-08-13 09:46:31 +10001325 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1326 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +10001327 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328} while (0)
1329
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330/* ================================================================
1331 * Misc helper macros
1332 */
1333
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001334/* Perfbox functionality only.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001335 */
1336#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1337do { \
1338 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1339 u32 head = GET_RING_HEAD( dev_priv ); \
1340 if (head == dev_priv->ring.tail) \
1341 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1342 } \
1343} while (0)
1344
1345#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
Dave Airlie7c1c2872008-11-28 14:22:24 +10001346do { \
1347 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
1348 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001349 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1350 int __ret = radeon_do_cp_idle( dev_priv ); \
1351 if ( __ret ) return __ret; \
1352 sarea_priv->last_dispatch = 0; \
1353 radeon_freelist_reset( dev ); \
1354 } \
1355} while (0)
1356
1357#define RADEON_DISPATCH_AGE( age ) do { \
1358 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1359 OUT_RING( age ); \
1360} while (0)
1361
1362#define RADEON_FRAME_AGE( age ) do { \
1363 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1364 OUT_RING( age ); \
1365} while (0)
1366
1367#define RADEON_CLEAR_AGE( age ) do { \
1368 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1369 OUT_RING( age ); \
1370} while (0)
1371
Linus Torvalds1da177e2005-04-16 15:20:36 -07001372/* ================================================================
1373 * Ring control
1374 */
1375
1376#define RADEON_VERBOSE 0
1377
1378#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1379
1380#define BEGIN_RING( n ) do { \
1381 if ( RADEON_VERBOSE ) { \
Márton Németh3e684ea2008-01-24 15:58:57 +10001382 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001383 } \
1384 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1385 COMMIT_RING(); \
1386 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1387 } \
1388 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1389 ring = dev_priv->ring.start; \
1390 write = dev_priv->ring.tail; \
1391 mask = dev_priv->ring.tail_mask; \
1392} while (0)
1393
1394#define ADVANCE_RING() do { \
1395 if ( RADEON_VERBOSE ) { \
1396 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1397 write, dev_priv->ring.tail ); \
1398 } \
1399 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
Dave Airliebc5f4522007-11-05 12:50:58 +10001400 DRM_ERROR( \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001401 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1402 ((dev_priv->ring.tail + _nr) & mask), \
1403 write, __LINE__); \
1404 } else \
1405 dev_priv->ring.tail = write; \
1406} while (0)
1407
1408#define COMMIT_RING() do { \
1409 /* Flush writes to ring */ \
1410 DRM_MEMORYBARRIER(); \
1411 GET_RING_HEAD( dev_priv ); \
1412 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1413 /* read from PCI bus to ensure correct posting */ \
1414 RADEON_READ( RADEON_CP_RB_RPTR ); \
1415} while (0)
1416
1417#define OUT_RING( x ) do { \
1418 if ( RADEON_VERBOSE ) { \
1419 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1420 (unsigned int)(x), write ); \
1421 } \
1422 ring[write++] = (x); \
1423 write &= mask; \
1424} while (0)
1425
1426#define OUT_RING_REG( reg, val ) do { \
1427 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1428 OUT_RING( val ); \
1429} while (0)
1430
Linus Torvalds1da177e2005-04-16 15:20:36 -07001431#define OUT_RING_TABLE( tab, sz ) do { \
1432 int _size = (sz); \
1433 int *_tab = (int *)(tab); \
1434 \
1435 if (write + _size > mask) { \
1436 int _i = (mask+1) - write; \
1437 _size -= _i; \
1438 while (_i > 0 ) { \
1439 *(int *)(ring + write) = *_tab++; \
1440 write++; \
1441 _i--; \
1442 } \
1443 write = 0; \
1444 _tab += _i; \
1445 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001446 while (_size > 0) { \
1447 *(ring + write) = *_tab++; \
1448 write++; \
1449 _size--; \
1450 } \
1451 write &= mask; \
1452} while (0)
1453
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001454#endif /* __RADEON_DRV_H__ */